Re: [PATCH][AArch64] Fix ICE due to store_pair_lanes

[James Greenhalgh <james.greenhalgh@arm.com>]

On Mon, Nov 27, 2017 at 03:20:29PM +0000, Wilco Dijkstra wrote:
> The recently added store_pair_lanes causes ICEs in output_operand.
> This is due to aarch64_classify_address treating it like a 128-bit STR
> rather than a STP. The valid immediate offsets don't fully overlap,
> causing it to return false.  Eg. offset 264 is a valid 8-byte STP offset
> but not a valid 16-byte STR offset since it isn't a multiple of 16.
> 
> The original instruction isn't passed in the printing code, so the context
> is unclear.  The solution is to add a new operand formatting specifier
> which is used for LDP/STP instructions like this.  This, like the Uml
> constraint that applies to store_pair_lanes, uses PARALLEL when calling
> aarch64_classify_address so that it knows it is an STP.
> Also add the 'z' specifier for future use by load/store pair instructions.
> 
> Passes regress, OK for commit? 

OK. But...

> +  if (aarch64_classify_address (&addr, x, mode, op, true))

This interface is not nice, resulting in...

> +/* Print address 'x' of a LDP/STP with mode 'mode'.  */
> +static void
> +aarch64_print_ldpstp_address (FILE *f, machine_mode mode, rtx x)
> +{
> +  aarch64_print_address_internal (f, mode, x, PARALLEL);
> +}
> +
> +/* Print address 'x' of a memory access with mode 'mode'.  */
> +static void
> +aarch64_print_operand_address (FILE *f, machine_mode mode, rtx x)
> +{
> +  aarch64_print_address_internal (f, mode, x, MEM);
> +}

These, which I *really* dislike.

Ideas on how to clean up this interface would be appreciated.

Thanks,
James