From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 74557 invoked by alias); 29 Nov 2017 00:01:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 74298 invoked by uid 89); 29 Nov 2017 00:00:49 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-25.7 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,KB_WAM_FROM_NAME_SINGLEWORD,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=12610, 126,10, Costs X-HELO: mail-pg0-f45.google.com Received: from mail-pg0-f45.google.com (HELO mail-pg0-f45.google.com) (74.125.83.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 29 Nov 2017 00:00:47 +0000 Received: by mail-pg0-f45.google.com with SMTP id e14so665350pgr.9 for ; Tue, 28 Nov 2017 16:00:47 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SB+S6EpjATdb+dJMKhtLrK6wYH3JPXEOITY8ejEFn+4=; b=k9N0GT7v++KJA/dRxr4lniqv+AEnIaxI4Iy1aosziy8Wflj3T2gV1brdEs2plmGeB4 pgG9u1s7XSHvXqsqa58/d52kJcFUHQvg8GMyqbds6RVE5MP52OcX73DGBlPVGYvJ85Dj jZbZptkgp+T/xv3zQ9dlk+JQ3nr2sYP+ahzRv3IBsm1frLVy7aq0Dw7rOHwsmsL/EWl7 G/6iE8BB7/ymIzz5hQkKJxthl4/sXSIaVM/jolMVd7gsqvxJZ2z1/RaqVv9Caws8VTHS lmaQ2S9Uk3suXUoB+kzFJG3FJ0XgfnnHt7jwnDzh4miSyMj/8DzWr8uGDAoFRLYhXNBT rsMA== X-Gm-Message-State: AJaThX77QGZzz+J/zM+Cy1pbHTgj130jn1d9y5pnIQyTXQYH/vEj5F9i rwpkeCuIjlDHpbZ0vd8WakZyJoP+Hk4= X-Google-Smtp-Source: AGs4zMZUMtG/YqZ4bWFh/rT5BygDW+SLTJXhR4KuFG4IxE7w5ckIYVpDtkY+CXQirbKsS86jGS7hUQ== X-Received: by 10.101.101.151 with SMTP id u23mr874933pgv.74.1511913646036; Tue, 28 Nov 2017 16:00:46 -0800 (PST) Received: from rohan.internal.sifive.com ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id y3sm309571pff.122.2017.11.28.16.00.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 28 Nov 2017 16:00:45 -0800 (PST) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH, gcc-7] Add riscv -mstrict-align option. Date: Wed, 29 Nov 2017 04:11:00 -0000 Message-Id: <20171129000043.27048-1-jimw@sifive.com> X-SW-Source: 2017-11/txt/msg02469.txt.bz2 This patch is necessary for proper support of targets that don't directly implement unaligned accesses. Tested with a linux+busybox build and boot, and a gcc testsuite run. There were no regressions. Also tested by hand on some small testcases to verify that it was doing something useful. Committed. gcc/ Backport from mainline 2017-11-04 Andrew Waterman * config/riscv/riscv.c (riscv_option_override): Conditionally set TARGET_STRICT_ALIGN based upon -mtune argument. Backport from mainline 2017-05-04 Andrew Waterman * config/riscv/riscv.opt (mstrict-align): New option. * config/riscv/riscv.h (STRICT_ALIGNMENT): Use it. Update comment. (SLOW_UNALIGNED_ACCESS): Define. (riscv_slow_unaligned_access): Declare. * config/riscv/riscv.c (riscv_tune_info): Add slow_unaligned_access field. (riscv_slow_unaligned_access): New variable. (rocket_tune_info): Set slow_unaligned_access to true. (optimize_size_tune_info): Set slow_unaligned_access to false. (riscv_cpu_info_table): Add entry for optimize_size_tune_info. (riscv_valid_lo_sum_p): Use TARGET_STRICT_ALIGN. (riscv_option_override): Set riscv_slow_unaligned_access. * doc/invoke.texi: Add -mstrict-align to RISC-V. --- gcc/config/riscv/riscv.c | 24 +++++++++++++++++++++--- gcc/config/riscv/riscv.h | 10 ++++++---- gcc/config/riscv/riscv.opt | 4 ++++ gcc/doc/invoke.texi | 6 ++++++ 4 files changed, 37 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 6cb7113..7331271 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -255,6 +255,7 @@ struct riscv_tune_info unsigned short issue_rate; unsigned short branch_cost; unsigned short memory_cost; + bool slow_unaligned_access; }; /* Information about one CPU we know about. */ @@ -268,6 +269,9 @@ struct riscv_cpu_info { /* Global variables for machine-dependent things. */ +/* Whether unaligned accesses execute very slowly. */ +bool riscv_slow_unaligned_access; + /* Which tuning parameters to use. */ static const struct riscv_tune_info *tune_info; @@ -301,7 +305,8 @@ static const struct riscv_tune_info rocket_tune_info = { {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 1, /* issue_rate */ 3, /* branch_cost */ - 5 /* memory_cost */ + 5, /* memory_cost */ + true, /* slow_unaligned_access */ }; /* Costs to use when optimizing for size. */ @@ -313,12 +318,14 @@ static const struct riscv_tune_info optimize_size_tune_info = { {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */ 1, /* issue_rate */ 1, /* branch_cost */ - 2 /* memory_cost */ + 2, /* memory_cost */ + false, /* slow_unaligned_access */ }; /* A table describing all the processors GCC knows about. */ static const struct riscv_cpu_info riscv_cpu_info_table[] = { { "rocket", &rocket_tune_info }, + { "size", &optimize_size_tune_info }, }; /* Return the riscv_cpu_info entry for the given name string. */ @@ -726,7 +733,8 @@ riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, enum machine_mode mode) /* We may need to split multiword moves, so make sure that each word can be accessed without inducing a carry. */ if (GET_MODE_SIZE (mode) > UNITS_PER_WORD - && GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode)) + && (!TARGET_STRICT_ALIGN + || GET_MODE_BITSIZE (mode) > GET_MODE_ALIGNMENT (mode))) return false; return true; @@ -3789,6 +3797,16 @@ riscv_option_override (void) RISCV_TUNE_STRING_DEFAULT); tune_info = optimize_size ? &optimize_size_tune_info : cpu->tune_info; + /* Use -mtune's setting for slow_unaligned_access, even when optimizing + for size. For architectures that trap and emulate unaligned accesses, + the performance cost is too great, even for -Os. Similarly, if + -m[no-]strict-align is left unspecified, heed -mtune's advice. */ + riscv_slow_unaligned_access = (cpu->tune_info->slow_unaligned_access + || TARGET_STRICT_ALIGN); + if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0 + && cpu->tune_info->slow_unaligned_access) + target_flags |= MASK_STRICT_ALIGN; + /* If the user hasn't specified a branch cost, use the processor's default. */ if (riscv_branch_cost == 0) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 8d4c75e..c5d134c 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -126,10 +126,11 @@ along with GCC; see the file COPYING3. If not see /* There is no point aligning anything to a rounder boundary than this. */ #define BIGGEST_ALIGNMENT 128 -/* The user-level ISA permits misaligned accesses, but they may execute - extremely slowly and non-atomically. Some privileged architectures - do not permit them at all. It is best to enforce strict alignment. */ -#define STRICT_ALIGNMENT 1 +/* The user-level ISA permits unaligned accesses, but they are not required + of the privileged architecture. */ +#define STRICT_ALIGNMENT TARGET_STRICT_ALIGN + +#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) riscv_slow_unaligned_access /* Define this if you wish to imitate the way many other C compilers handle alignment of bitfields and the structures that contain @@ -864,6 +865,7 @@ while (0) #ifndef USED_FOR_TARGET extern const enum reg_class riscv_regno_to_class[]; extern bool riscv_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; +extern bool riscv_slow_unaligned_access; #endif #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 0466bb2..cfd0335 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -84,6 +84,10 @@ mcmodel= Target Report RejectNegative Joined Enum(code_model) Var(riscv_cmodel) Init(TARGET_DEFAULT_CMODEL) Specify the code model. +mstrict-align +Target Report Mask(STRICT_ALIGN) Save +Do not generate unaligned memory accesses. + Enum Name(code_model) Type(enum riscv_code_model) Known code models (for use with the -mcmodel= option): diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6d02832..9b1857c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -975,6 +975,7 @@ See RS/6000 and PowerPC Options. -mtune=@var{processor-string} @gol -msmall-data-limit=@var{N-bytes} @gol -msave-restore -mno-save-restore @gol +-mstrict-align -mno-strict-align @gol -mcmodel=@var{code-model} @gol -mexplicit-relocs -mno-explicit-relocs @gol} @@ -20931,6 +20932,11 @@ Put global and static data smaller than @var{n} bytes into a special section @opindex msave-restore Use smaller but slower prologue and epilogue code. +@item -mstrict-align +@itemx -mno-strict-align +@opindex mstrict-align +Do not generate unaligned memory accesses. + @item -mcmodel=@var{code-model} @opindex mcmodel Specify the code model. -- 2.7.4