* RE: [PATCH][i386,AVX] Enable VAES support [3/5]
@ 2017-11-08 12:45 Koval, Julia
2017-12-15 4:05 ` Kirill Yukhin
0 siblings, 1 reply; 3+ messages in thread
From: Koval, Julia @ 2017-11-08 12:45 UTC (permalink / raw)
To: 'GCC Patches'; +Cc: 'Kirill Yukhin'
[-- Attachment #1: Type: text/plain, Size: 1070 bytes --]
Patch attached.
> -----Original Message-----
> From: Koval, Julia
> Sent: Wednesday, November 08, 2017 1:38 PM
> To: 'GCC Patches' <gcc-patches@gcc.gnu.org>
> Cc: 'Kirill Yukhin' <kirill.yukhin@gmail.com>
> Subject: [PATCH][i386,AVX] Enable VAES support [3/5]
>
> Hi, this patch enables VAESDECLAST instruction from VAES isaset, defined here:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> instruction-set-extensions-programming-reference.pdf
>
> Ok for trunk?
> Thanks,
> Julia
>
> gcc/
> * config/i386/i386-builtin.def (__builtin_ia32_vaesdeclast_v16qi,
> __builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi):
> New.
> * config/i386/sse.md (vaesdeclast_<mode>): New pattern.
> * config/i386/vaesintrin.h (_mm256_aesdeclast_epi128,
> _mm512_aesdeclast_epi128, _mm_aesdeclast_epi128): New intrinsics.
>
> gcc/testsuite/
> * gcc.target/i386/avx512f-aesdeclast-2.c: New test.
> * gcc.target/i386/avx512vl-aesdeclast-2.c
> * gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics.
[-- Attachment #2: 0003-VAESDECLAST.PATCH --]
[-- Type: application/octet-stream, Size: 8091 bytes --]
From cda374a6bf4c2697bdedcb48d63d0fa306c105ab Mon Sep 17 00:00:00 2001
From: "julia.koval" <jkoval@gkticlel801.igk.intel.com>
Date: Mon, 27 Feb 2017 22:42:13 +0300
Subject: [PATCH 3/5] VAESDECLAST
---
gcc/config/i386/i386-builtin.def | 3 ++
gcc/config/i386/sse.md | 11 +++++
gcc/config/i386/vaesintrin.h | 24 ++++++++++
.../gcc.target/i386/avx512f-aesdeclast-2.c | 52 ++++++++++++++++++++++
gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c | 7 ++-
.../gcc.target/i386/avx512vl-aesdeclast-2.c | 17 +++++++
6 files changed, 113 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-aesdeclast-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-aesdeclast-2.c
diff --git a/gcc/config/i386/i386-builtin.def b/gcc/config/i386/i386-builtin.def
index 4e76970..2ae1b75 100644
--- a/gcc/config/i386/i386-builtin.def
+++ b/gcc/config/i386/i386-builtin.def
@@ -2601,6 +2601,9 @@ BDESC (OPTION_MASK_ISA_RDPID, CODE_FOR_rdpid, "__builtin_ia32_rdpid", IX86_BUILT
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v16qi, "__builtin_ia32_vaesdec_v16qi", IX86_BUILTIN_VAESDEC16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v32qi, "__builtin_ia32_vaesdec_v32qi", IX86_BUILTIN_VAESDEC32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdec_v64qi, "__builtin_ia32_vaesdec_v64qi", IX86_BUILTIN_VAESDEC64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v16qi, "__builtin_ia32_vaesdeclast_v16qi", IX86_BUILTIN_VAESDECLAST16, UNKNOWN, (int) V16QI_FTYPE_V16QI_V16QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v32qi, "__builtin_ia32_vaesdeclast_v32qi", IX86_BUILTIN_VAESDECLAST32, UNKNOWN, (int) V32QI_FTYPE_V32QI_V32QI)
+BDESC (OPTION_MASK_ISA_VAES, CODE_FOR_vaesdeclast_v64qi, "__builtin_ia32_vaesdeclast_v64qi", IX86_BUILTIN_VAESDECLAST64, UNKNOWN, (int) V64QI_FTYPE_V64QI_V64QI)
BDESC_END (ARGS2, MPX)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9064075..6739b5a 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -161,6 +161,7 @@
;; For VAES support
UNSPEC_VAESDEC
+ UNSPEC_VAESDECLAST
])
(define_c_enum "unspecv" [
@@ -20006,3 +20007,13 @@
"TARGET_VAES"
"vaesdec\t{%2, %1, %0|%0, %1, %2}"
)
+
+(define_insn "vaesdeclast_<mode>"
+ [(set (match_operand:VI1_AVX512VL_F 0 "register_operand" "=v")
+ (unspec:VI1_AVX512VL_F
+ [(match_operand:VI1_AVX512VL_F 1 "register_operand" "v")
+ (match_operand:VI1_AVX512VL_F 2 "vector_operand" "v")]
+ UNSPEC_VAESDECLAST))]
+ "TARGET_VAES"
+ "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
+)
diff --git a/gcc/config/i386/vaesintrin.h b/gcc/config/i386/vaesintrin.h
index 0208cc7..1159922 100644
--- a/gcc/config/i386/vaesintrin.h
+++ b/gcc/config/i386/vaesintrin.h
@@ -14,6 +14,14 @@ _mm256_aesdec_epi128 (__m256i __A, __m256i __B)
return (__m256i)__builtin_ia32_vaesdec_v32qi ((__v32qi) __A, (__v32qi) __B);
}
+extern __inline __m256i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm256_aesdeclast_epi128 (__m256i __A, __m256i __B)
+{
+ return (__m256i)__builtin_ia32_vaesdeclast_v32qi ((__v32qi) __A,
+ (__v32qi) __B);
+}
+
#ifdef __DISABLE_VAES__
#undef __DISABLE_VAES__
#pragma GCC pop_options
@@ -34,6 +42,14 @@ _mm512_aesdec_epi128 (__m512i __A, __m512i __B)
return (__m512i)__builtin_ia32_vaesdec_v64qi ((__v64qi) __A, (__v64qi) __B);
}
+extern __inline __m512i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm512_aesdeclast_epi128 (__m512i __A, __m512i __B)
+{
+ return (__m512i)__builtin_ia32_vaesdeclast_v64qi ((__v64qi) __A,
+ (__v64qi) __B);
+}
+
#ifdef __DISABLE_VAESF__
#undef __DISABLE_VAESF__
#pragma GCC pop_options
@@ -52,6 +68,14 @@ _mm_aesdec_epi128 (__m128i __A, __m128i __B)
return (__m128i)__builtin_ia32_vaesdec_v16qi ((__v16qi) __A, (__v16qi) __B);
}
+extern __inline __m128i
+__attribute__((__gnu_inline__, __always_inline__, __artificial__))
+_mm_aesdeclast_epi128 (__m128i __A, __m128i __B)
+{
+ return (__m128i)__builtin_ia32_vaesdeclast_v16qi ((__v16qi) __A,
+ (__v16qi) __B);
+}
+
#ifdef __DISABLE_VAESVL__
#undef __DISABLE_VAESVL__
#pragma GCC pop_options
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-aesdeclast-2.c b/gcc/testsuite/gcc.target/i386/avx512f-aesdeclast-2.c
new file mode 100644
index 0000000..c318eb2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-aesdeclast-2.c
@@ -0,0 +1,52 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512f -mvaes" } */
+/* { dg-require-effective-target avx512f } */
+/* { dg-require-effective-target avx512vaes } */
+
+#define AVX512F
+
+#define VAES
+#include "avx512f-helper.h"
+
+#define SIZE (AVX512F_LEN / 32)
+
+#include "avx512f-mask-type.h"
+
+static void
+CALC (unsigned int *r)
+{
+ for (int i = 0; i < SIZE; i+=4)
+ {
+ r[i] = 0xa8ba9d0;
+ r[i + 1] = 0x94902ace;
+ r[i + 2] = 0xa7726929;
+ r[i + 3] = 0x654dfb35;
+ }
+}
+
+void
+TEST (void)
+{
+ int i;
+ UNION_TYPE (AVX512F_LEN, i_ud) res1, src1, src2;
+ MASK_TYPE mask = MASK_VALUE;
+ unsigned int res_ref[SIZE];
+
+ for (int i = 0; i < SIZE; i+=4)
+ {
+ src1.a[i] = 0x5d53475d;
+ src1.a[i + 1] = 0x63746f72;
+ src1.a[i + 2] = 0x73745665;
+ src1.a[i + 3] = 0x7b5b5465;
+ src2.a[i] = 0x726f6e5d;
+ src2.a[i + 1] = 0x5b477565;
+ src2.a[i + 2] = 0x68617929;
+ src2.a[i + 3] = 0x48692853;
+ }
+
+ CALC (res_ref);
+ res1.x = INTRINSIC (_aesdeclast_epi128) (src2.x, src1.x);
+
+ if (UNION_CHECK (AVX512F_LEN, i_ud) (res1, res_ref))
+ abort ();
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c b/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
index fc4e6bf..0ff4ce6 100644
--- a/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
+++ b/gcc/testsuite/gcc.target/i386/avx512fvl-vaes-1.c
@@ -1,10 +1,13 @@
/* { dg-do compile } */
/* { dg-options "-mvaes -mavx512f -mavx512vl -O2" } */
/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+\[^\{\n\]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
/* { dg-final { scan-assembler-times "vaesdec\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vaesdeclast\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+\[^\{\n\]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
#include <immintrin.h>
@@ -16,9 +19,11 @@ void extern
avx512f_test (void)
{
x = _mm512_aesdec_epi128 (x, y);
+ x = _mm512_aesdeclast_epi128 (x, y);
x256 = _mm256_aesdec_epi128 (x256, y256);
+ x256 = _mm256_aesdeclast_epi128 (x256, y256);
x128 = _mm_aesdec_epi128 (x128, y128);
-
+ x128 = _mm_aesdeclast_epi128 (x128, y128);
}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-aesdeclast-2.c b/gcc/testsuite/gcc.target/i386/avx512vl-aesdeclast-2.c
new file mode 100644
index 0000000..b2a783a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-aesdeclast-2.c
@@ -0,0 +1,17 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -mavx512bw -mavx512vl -mvaes" } */
+/* { dg-require-effective-target avx512vl } */
+/* { dg-require-effective-target avx512bw } */
+/* { dg-require-effective-target avx512vaes } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512f-aesdeclast-2.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512f-aesdeclast-2.c"
--
2.5.5
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH][i386,AVX] Enable VAES support [3/5]
2017-11-08 12:45 [PATCH][i386,AVX] Enable VAES support [3/5] Koval, Julia
@ 2017-12-15 4:05 ` Kirill Yukhin
0 siblings, 0 replies; 3+ messages in thread
From: Kirill Yukhin @ 2017-12-15 4:05 UTC (permalink / raw)
To: Koval, Julia; +Cc: 'GCC Patches'
Hello Julia,
On 08 Nov 12:38, Koval, Julia wrote:
> Patch attached.
>
> > -----Original Message-----
> > From: Koval, Julia
> > Sent: Wednesday, November 08, 2017 1:38 PM
> > To: 'GCC Patches' <gcc-patches@gcc.gnu.org>
> > Cc: 'Kirill Yukhin' <kirill.yukhin@gmail.com>
> > Subject: [PATCH][i386,AVX] Enable VAES support [3/5]
> >
> > Hi, this patch enables VAESDECLAST instruction from VAES isaset, defined here:
> > https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> > instruction-set-extensions-programming-reference.pdf
> >
> > Ok for trunk?
Your patch is OK for trunk. I've checked it in.
--
Thanks, K
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH][i386,AVX] Enable VAES support [3/5]
@ 2017-11-08 12:42 Koval, Julia
0 siblings, 0 replies; 3+ messages in thread
From: Koval, Julia @ 2017-11-08 12:42 UTC (permalink / raw)
To: 'GCC Patches'; +Cc: 'Kirill Yukhin'
Hi, this patch enables VAESDECLAST instruction from VAES isaset, defined here: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Ok for trunk?
Thanks,
Julia
gcc/
* config/i386/i386-builtin.def (__builtin_ia32_vaesdeclast_v16qi,
__builtin_ia32_vaesdeclast_v32qi, __builtin_ia32_vaesdeclast_v64qi): New.
* config/i386/sse.md (vaesdeclast_<mode>): New pattern.
* config/i386/vaesintrin.h (_mm256_aesdeclast_epi128,
_mm512_aesdeclast_epi128, _mm_aesdeclast_epi128): New intrinsics.
gcc/testsuite/
* gcc.target/i386/avx512f-aesdeclast-2.c: New test.
* gcc.target/i386/avx512vl-aesdeclast-2.c
* gcc.target/i386/avx512fvl-vaes-1.c: Handle new intrinsics.
^ permalink raw reply [flat|nested] 3+ messages in thread
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