* [PATCH] PR rtl-optimization/83565: Fix 32-bit rotate on ia64
@ 2017-12-24 0:32 James Clarke
2017-12-24 0:36 ` [PATCH v2] " James Clarke
0 siblings, 1 reply; 3+ messages in thread
From: James Clarke @ 2017-12-24 0:32 UTC (permalink / raw)
To: gcc-patches; +Cc: James Clarke
From: James Clarke <jrtc27@jrtc27.com>
On ia64, 32-bit rotates are implemented by copying the lower 32 bits of
a register into the upper half, then performing a right shift. However,
depending on the bit pattern in question, this can leave the upper 32
bits as non-zero, despite being only a 32-bit unsigned result. Therefore
add an extra zero_extract to mask these out.
gcc/
PR rtl-optimization/83565
* gcc/config/ia64/ia64.md ("*rotrsi3_internal"): Mask out higher 32
bits from the shift result.
("*rotlsi3_internal"): Likewise
---
gcc/config/ia64/ia64.md | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index b7cd52b..8198b54 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -3329,7 +3329,10 @@
(ior:DI (zero_extend:DI (match_dup 1))
(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
(set (match_dup 3)
- (lshiftrt:DI (match_dup 3) (match_dup 2)))]
+ (lshiftrt:DI (match_dup 3) (match_dup 2)))
+ (set (match_dup 3)
+ (zero_extract:DI (match_dup 3)
+ (const_int 32) (const_int 0)))]
"operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
(define_expand "rotlsi3"
@@ -3358,7 +3361,10 @@
(ior:DI (zero_extend:DI (match_dup 1))
(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
(set (match_dup 3)
- (lshiftrt:DI (match_dup 3) (match_dup 2)))]
+ (lshiftrt:DI (match_dup 3) (match_dup 2)))
+ (set (match_dup 3)
+ (zero_extract:DI (match_dup 3)
+ (const_int 32) (const_int 0)))]
{
operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
--
1.7.10.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH v2] PR rtl-optimization/83565: Fix 32-bit rotate on ia64
2017-12-24 0:32 [PATCH] PR rtl-optimization/83565: Fix 32-bit rotate on ia64 James Clarke
@ 2017-12-24 0:36 ` James Clarke
2017-12-24 5:15 ` Jim Wilson
0 siblings, 1 reply; 3+ messages in thread
From: James Clarke @ 2017-12-24 0:36 UTC (permalink / raw)
To: gcc-patches; +Cc: James Clarke
On ia64, 32-bit rotates are implemented by copying the lower 32 bits of
a register into the upper half, then performing a right shift. However,
depending on the bit pattern in question, this can leave the upper 32
bits as non-zero, despite being only a 32-bit unsigned result. Therefore
add an extra zero_extract to mask these out.
gcc/
PR rtl-optimization/83565
* gcc/config/ia64/ia64.md ("*rotrsi3_internal"): Mask out higher 32
bits from the shift result.
("*rotlsi3_internal"): Likewise
---
[Resent because git send-email messed about with the headers, adding a
second From: with a different email address, presumably since I ran git
send-email from a directory with .git/config containing a user.email
setting...]
gcc/config/ia64/ia64.md | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index b7cd52b..8198b54 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -3329,7 +3329,10 @@
(ior:DI (zero_extend:DI (match_dup 1))
(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
(set (match_dup 3)
- (lshiftrt:DI (match_dup 3) (match_dup 2)))]
+ (lshiftrt:DI (match_dup 3) (match_dup 2)))
+ (set (match_dup 3)
+ (zero_extract:DI (match_dup 3)
+ (const_int 32) (const_int 0)))]
"operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));")
(define_expand "rotlsi3"
@@ -3358,7 +3361,10 @@
(ior:DI (zero_extend:DI (match_dup 1))
(ashift:DI (zero_extend:DI (match_dup 1)) (const_int 32))))
(set (match_dup 3)
- (lshiftrt:DI (match_dup 3) (match_dup 2)))]
+ (lshiftrt:DI (match_dup 3) (match_dup 2)))
+ (set (match_dup 3)
+ (zero_extract:DI (match_dup 3)
+ (const_int 32) (const_int 0)))]
{
operands[3] = gen_rtx_REG (DImode, REGNO (operands[0]));
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
--
1.7.10.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH v2] PR rtl-optimization/83565: Fix 32-bit rotate on ia64
2017-12-24 0:36 ` [PATCH v2] " James Clarke
@ 2017-12-24 5:15 ` Jim Wilson
0 siblings, 0 replies; 3+ messages in thread
From: Jim Wilson @ 2017-12-24 5:15 UTC (permalink / raw)
To: James Clarke, gcc-patches
On 12/23/2017 04:36 PM, James Clarke wrote:
> PR rtl-optimization/83565
> * gcc/config/ia64/ia64.md ("*rotrsi3_internal"): Mask out higher 32
> bits from the shift result.
> ("*rotlsi3_internal"): Likewise
This doesn't look right to me. On ia64, the upper 32-bits of a 32-bit
value in a 64-bit register are garbage bits. So there should be no need
to clear them here after the operation.
Note for instance that lshrsi3 clears the upper 32-bits before shifting
right, because they are garbage bits. And note for instance that
ashlsi3 just shifts left, and doesn't care that it is putting garbage in
the upper 32-bits.
I think either nonzero bits is broken in the SUBREG case, or ia64
perhaps should not be setting WORD_REGISTER_OPERATIONS.
Jim
^ permalink raw reply [flat|nested] 3+ messages in thread
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2017-12-24 0:32 [PATCH] PR rtl-optimization/83565: Fix 32-bit rotate on ia64 James Clarke
2017-12-24 0:36 ` [PATCH v2] " James Clarke
2017-12-24 5:15 ` Jim Wilson
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