From: Jim Wilson <jimw@sifive.com>
To: gcc-patches@gcc.gnu.org
Cc: Jim Wilson <jimw@sifive.com>
Subject: [PATCH] RISC-V: Allow register pairs for 64-bit target.
Date: Sat, 27 Jan 2018 07:43:00 -0000 [thread overview]
Message-ID: <20180127000109.29145-1-jimw@sifive.com> (raw)
This was noticed while looking at some 64-bit libgcc code. Some functions
like negti had a stack frame allocated, but did not use the stack. The 32-bit
equivalent negdi did not have a stack frame allocated. This is because a
128-bit local variable got allocated to the stack and then optimized away.
But we allow register pairs for the 32-bit target, we should allow them for
the 64-bit target too. Fixed by adding a missing definition for
MAX_FIXED_MODE_SIZE.
This was tested by multiple 32-bit and 64-bit newlib and glibc builds and
make checks. There were no regressions. The libgcc code for negti no longer
has a stack frame allocated. libstdc++.so is 3KB smaller with the patch.
Committed.
Jim
gcc/
* config/riscv/riscv.h (MAX_FIXED_MODE_SIZE): New.
---
gcc/config/riscv/riscv.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
index a002bff4480..1c1c3431119 100644
--- a/gcc/config/riscv/riscv.h
+++ b/gcc/config/riscv/riscv.h
@@ -158,6 +158,10 @@ along with GCC; see the file COPYING3. If not see
#define PCC_BITFIELD_TYPE_MATTERS 1
+/* An integer expression for the size in bits of the largest integer machine
+ mode that should actually be used. We allow pairs of registers. */
+#define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode)
+
/* If defined, a C expression to compute the alignment for a static
variable. TYPE is the data type, and ALIGN is the alignment that
the object would ordinarily have. The value of this macro is used
--
2.14.1
reply other threads:[~2018-01-27 0:01 UTC|newest]
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