* [patch][x86] -march=icelake
@ 2017-11-12 7:33 Koval, Julia
2017-11-12 16:34 ` Uros Bizjak
2017-11-12 17:33 ` Sandra Loosemore
0 siblings, 2 replies; 21+ messages in thread
From: Koval, Julia @ 2017-11-12 7:33 UTC (permalink / raw)
To: GCC Patches; +Cc: Uros Bizjak, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 1291 bytes --]
Hi, this patch adds new option -march=icelake. Isasets defined in: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
I didn't add arch code to driver-i386.c, because there is no code available in SDM yet, only for cannonlake (https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Chapter 2).
gcc/
* config.gcc: Add -march=icelake.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
* config/i386/i386.c (processor_costs): Add m_ICELAKE.
(PTA_ICELAKE, PTA2_ICELAKE, PTA2_GFNI, PTA2_AVX512VBMI2, PTA2_VAES,
PTA2_AVX512VNNI, PTA2_VPCLMULQDQ, PTA2_RDPID, PTA2_AVX512BITALG): New.
(processor_target_table): Add icelake.
(ix86_option_override_internal): Add flags2 for new PTA, handle GFNI, RDPID.
(get_builtin_code_for_version): Handle icelake.
(M_INTEL_COREI7_ICELAKE): New.
* config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
* doc/invoke.texi: Add -march=icelake.
gcc/testsuite/
* gcc.target/i386/funcspec-56.inc: Handle new march.
* g++.dg/ext/mv16.C: Ditto.
libgcc/
* config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.
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From a1c0fbf71b581bd32927cf826cade2f66c009983 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Tue, 7 Nov 2017 18:54:46 +0300
Subject: [PATCH] icelake
---
gcc/config.gcc | 2 +-
gcc/config/i386/driver-i386.c | 5 +-
gcc/config/i386/i386-c.c | 7 +
gcc/config/i386/i386.c | 208 +++++++++++++++-----------
gcc/config/i386/i386.h | 2 +
gcc/doc/invoke.texi | 8 +
gcc/testsuite/g++.dg/ext/mv16.C | 6 +
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 +
libgcc/config/i386/cpuinfo.h | 1 +
9 files changed, 149 insertions(+), 91 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 1247702..a6d8518 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -629,7 +629,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
-skylake-avx512 cannonlake x86-64 native"
+skylake-avx512 cannonlake icelake x86-64 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 5b3b5ce..88932af 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -808,8 +808,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
if (arch)
{
/* This is unknown family 0x6 CPU. */
+ /* Assume Ice Lake. */
+ if (has_gfni)
+ cpu = "icelake";
/* Assume Cannon Lake. */
- if (has_avx512vbmi)
+ else if (has_avx512vbmi)
cpu = "cannonlake";
/* Assume Knights Mill. */
else if (has_avx5124vnniw)
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index e7e8f53..750c152 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -188,6 +188,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__cannonlake");
def_or_undef (parse_in, "__cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__icelake");
+ def_or_undef (parse_in, "__icelake__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
@@ -309,6 +313,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_CANNONLAKE:
def_or_undef (parse_in, "__tune_cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__tune_icelake__");
+ break;
case PROCESSOR_LAKEMONT:
def_or_undef (parse_in, "__tune_lakemont__");
break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 5796b4f..41ee88c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -143,6 +143,7 @@ const struct processor_costs *ix86_cost = NULL;
#define m_KNM (1U<<PROCESSOR_KNM)
#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
+#define m_ICELAKE (1U<<PROCESSOR_ICELAKE)
#define m_INTEL (1U<<PROCESSOR_INTEL)
#define m_GEODE (1U<<PROCESSOR_GEODE)
@@ -856,6 +857,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{"knm", &slm_cost, 16, 15, 16, 7, 16},
{"skylake-avx512", &core_cost, 16, 10, 16, 10, 16},
{"cannonlake", &core_cost, 16, 10, 16, 10, 16},
+ {"icelake", &core_cost, 16, 10, 16, 10, 16},
{"intel", &intel_cost, 16, 15, 16, 7, 16},
{"geode", &geode_cost, 0, 0, 0, 0, 0},
{"k6", &k6_cost, 32, 7, 32, 7, 32},
@@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
#define PTA_SGX (HOST_WIDE_INT_1 << 63)
+#define PTA2_GFNI (HOST_WIDE_INT_1 << 0)
+#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1)
+#define PTA2_VAES (HOST_WIDE_INT_1 << 2)
+#define PTA2_AVX512VNNI (HOST_WIDE_INT_1 << 3)
+#define PTA2_VPCLMULQDQ (HOST_WIDE_INT_1 << 4)
+#define PTA2_RDPID (HOST_WIDE_INT_1 << 5)
+#define PTA2_AVX512BITALG (HOST_WIDE_INT_1 << 6)
#define PTA_CORE2 \
(PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
@@ -3449,6 +3458,9 @@ ix86_option_override_internal (bool main_args_p,
| PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU)
#define PTA_CANNONLAKE \
(PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_CLWB)
+#define PTA_ICELAKE (PTA_CANNONLAKE | PTA_AVX512VPOPCNTDQ)
+#define PTA2_ICELAKE (PTA2_GFNI | PTA2_AVX512VBMI2 | PTA2_VAES \
+ | PTA2_AVX512VNNI | PTA2_VPCLMULQDQ | PTA2_RDPID | PTA2_AVX512BITALG)
#define PTA_KNL \
(PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
#define PTA_BONNELL \
@@ -3466,155 +3478,162 @@ ix86_option_override_internal (bool main_args_p,
const enum processor_type processor;
const enum attr_cpu schedule;
const unsigned HOST_WIDE_INT flags;
+ const unsigned HOST_WIDE_INT flags2;
}
const processor_alias_table[] =
{
- {"i386", PROCESSOR_I386, CPU_NONE, 0},
- {"i486", PROCESSOR_I486, CPU_NONE, 0},
- {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
- {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
- {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
- {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+ {"i386", PROCESSOR_I386, CPU_NONE, 0, 0},
+ {"i486", PROCESSOR_I486, CPU_NONE, 0, 0},
+ {"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0},
+ {"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0, 0},
+ {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387, 0},
+ {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX, 0},
+ {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX, 0},
+ {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0},
+ {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0},
+ {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW, 0},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0},
{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0},
{"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0},
{"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
- {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0},
+ {"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0},
+ {"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0, 0},
+ {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+ PTA_MMX | PTA_FXSR, 0},
{"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0},
{"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_FXSR, 0},
{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0},
{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR, 0},
{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR, 0},
{"prescott", PROCESSOR_NOCONA, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0},
{"nocona", PROCESSOR_NOCONA, CPU_NONE,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
- {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
- {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+ | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR, 0},
+ {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2, 0},
+ {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM, 0},
+ {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM, 0},
+ {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE, 0},
{"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ PTA_SANDYBRIDGE, 0},
{"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ PTA_SANDYBRIDGE, 0},
{"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
+ PTA_IVYBRIDGE, 0},
{"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
- {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
- {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE},
- {"skylake-avx512", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE_AVX512},
- {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE},
- {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
- {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
- {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+ PTA_IVYBRIDGE, 0},
+ {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL, 0},
+ {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL, 0},
+ {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL, 0},
+ {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE, 0},
+ {"skylake-avx512", PROCESSOR_HASWELL, CPU_HASWELL,
+ PTA_SKYLAKE_AVX512, 0},
+ {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE, 0},
+ {"icelake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_ICELAKE,
+ PTA2_ICELAKE},
+ {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, 0},
+ {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, 0},
+ {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT, 0},
+ {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT, 0},
+ {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL, 0},
+ {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM, 0},
+ {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM, 0},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
- {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
- {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
- {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0},
+ {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX, 0},
+ {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0},
+ {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW, 0},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE, 0},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR, 0},
{"x86-64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0},
{"eden-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR, 0},
{"nano", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_FXSR, 0},
{"nano-1000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_FXSR, 0},
{"nano-2000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_FXSR, 0},
{"nano-3000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0},
{"nano-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0},
{"eden-x4", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0},
{"nano-x4", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
+ | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR, 0},
{"k8", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0},
{"opteron", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0},
{"athlon64", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR, 0},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR, 0},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
+ 0},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR,
+ 0},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE, 0},
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE, 0},
{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
| PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
| PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT | PTA_FSGSBASE},
+ | PTA_XSAVEOPT | PTA_FSGSBASE, 0},
{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -3622,7 +3641,7 @@ ix86_option_override_internal (bool main_args_p,
| PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
| PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
| PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
- | PTA_MOVBE | PTA_MWAITX},
+ | PTA_MOVBE | PTA_MWAITX, 0},
{"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
@@ -3631,21 +3650,21 @@ ix86_option_override_internal (bool main_args_p,
| PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
| PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
| PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
- | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+ | PTA_SHA | PTA_LZCNT | PTA_POPCNT, 0},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE},
+ | PTA_FXSR | PTA_XSAVE, 0},
{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
| PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
| PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
| PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+ | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT, 0},
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
PTA_64BIT
- | PTA_HLE /* flags are only used for -march switch. */ },
+ | PTA_HLE, 0 /* flags are only used for -march switch. */ },
};
/* -mrecip options. */
@@ -4105,6 +4124,12 @@ ix86_option_override_internal (bool main_args_p,
if (processor_alias_table[i].flags & PTA_SGX
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
+ if (processor_alias_table[i].flags2 & PTA2_RDPID
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
+ if (processor_alias_table[i].flags2 & PTA2_GFNI
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_GFNI))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI;
if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
x86_prefetch_sse = true;
@@ -31116,7 +31141,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
priority = P_PROC_AVX;
break;
case PROCESSOR_HASWELL:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI)
+ if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI)
+ arg_str = "icelake";
+ else if (new_target->x_ix86_isa_flags
+ & OPTION_MASK_ISA_AVX512VBMI)
arg_str = "cannonlake";
else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
arg_str = "skylake-avx512";
@@ -31841,7 +31869,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_INTEL_COREI7_BROADWELL,
M_INTEL_COREI7_SKYLAKE,
M_INTEL_COREI7_SKYLAKE_AVX512,
- M_INTEL_COREI7_CANNONLAKE
+ M_INTEL_COREI7_CANNONLAKE,
+ M_INTEL_COREI7_ICELAKE
};
static struct _arch_names_table
@@ -31866,6 +31895,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
{"skylake", M_INTEL_COREI7_SKYLAKE},
{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
+ {"icelake", M_INTEL_COREI7_ICELAKE},
{"bonnell", M_INTEL_BONNELL},
{"silvermont", M_INTEL_SILVERMONT},
{"knl", M_INTEL_KNL},
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index b7b0e5a..844932f 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -373,6 +373,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
+#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE)
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2248,6 +2249,7 @@ enum processor_type
PROCESSOR_KNM,
PROCESSOR_SKYLAKE_AVX512,
PROCESSOR_CANNONLAKE,
+ PROCESSOR_ICELAKE,
PROCESSOR_INTEL,
PROCESSOR_GEODE,
PROCESSOR_K6,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index bc6e86f..891c283 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25331,6 +25331,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
+@item Icelake
+Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
+AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C
index 1e1ae3d..8fbdb47 100644
--- a/gcc/testsuite/g++.dg/ext/mv16.C
+++ b/gcc/testsuite/g++.dg/ext/mv16.C
@@ -60,6 +60,10 @@ int __attribute__ ((target("arch=cannonlake"))) foo () {
return 16;
}
+int __attribute__ ((target("arch=icelake"))) foo () {
+ return 17;
+}
+
int main ()
{
int val = foo ();
@@ -82,6 +86,8 @@ int main ()
assert (val == 15);
else if (__builtin_cpu_is ("cannonlake"))
assert (val == 16);
+ else if (__builtin_cpu_is ("icelake"))
+ assert (val == 17);
else
assert (val == 0);
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index ed0748b..837cdc3 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -145,6 +145,7 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
+extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake")));
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index 4b2a3c5..67f17ef 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -70,6 +70,7 @@ enum processor_subtypes
INTEL_COREI7_SKYLAKE,
INTEL_COREI7_SKYLAKE_AVX512,
INTEL_COREI7_CANNONLAKE,
+ INTEL_COREI7_ICELAKE,
CPU_SUBTYPE_MAX
};
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2017-11-12 7:33 [patch][x86] -march=icelake Koval, Julia
@ 2017-11-12 16:34 ` Uros Bizjak
2017-12-18 13:42 ` Koval, Julia
2017-11-12 17:33 ` Sandra Loosemore
1 sibling, 1 reply; 21+ messages in thread
From: Uros Bizjak @ 2017-11-12 16:34 UTC (permalink / raw)
To: Koval, Julia; +Cc: GCC Patches, Kirill Yukhin
On Sun, Nov 12, 2017 at 1:04 AM, Koval, Julia <julia.koval@intel.com> wrote:
> Hi, this patch adds new option -march=icelake. Isasets defined in: https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
> I didn't add arch code to driver-i386.c, because there is no code available in SDM yet, only for cannonlake (https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf Chapter 2).
This means the driver will go through generic detection for
-march=native. Perhaps a comment should be added, so we won't forget
to add the model number when one is available.
> gcc/
> * config.gcc: Add -march=icelake.
> * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
> * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
> * config/i386/i386.c (processor_costs): Add m_ICELAKE.
> (PTA_ICELAKE, PTA2_ICELAKE, PTA2_GFNI, PTA2_AVX512VBMI2, PTA2_VAES,
> PTA2_AVX512VNNI, PTA2_VPCLMULQDQ, PTA2_RDPID, PTA2_AVX512BITALG): New.
> (processor_target_table): Add icelake.
> (ix86_option_override_internal): Add flags2 for new PTA, handle GFNI, RDPID.
> (get_builtin_code_for_version): Handle icelake.
> (M_INTEL_COREI7_ICELAKE): New.
> * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
> * doc/invoke.texi: Add -march=icelake.
> gcc/testsuite/
> * gcc.target/i386/funcspec-56.inc: Handle new march.
> * g++.dg/ext/mv16.C: Ditto.
> libgcc/
> * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.
@@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
#define PTA_SGX (HOST_WIDE_INT_1 << 63)
+#define PTA2_GFNI (HOST_WIDE_INT_1 << 0)
+#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1)
+#define PTA2_VAES (HOST_WIDE_INT_1 << 2)
+#define PTA2_AVX512VNNI (HOST_WIDE_INT_1 << 3)
+#define PTA2_VPCLMULQDQ (HOST_WIDE_INT_1 << 4)
+#define PTA2_RDPID (HOST_WIDE_INT_1 << 5)
+#define PTA2_AVX512BITALG (HOST_WIDE_INT_1 << 6)
Please add these options first.
On a related note, there should probably be a better way to extend
various bitmapped flag variables beyond 64bit words. We are constantly
going over 64bit sizes in target option masks, now the number of
processor flags doesn't fit in a word anymore. There are several
places one has to keep in mind in which word some specific flag lives,
and this approach opens several ways to make a hard to detect
mistake. Does C++ offer a more elegant way?
Bellow, please find a suggestion of a couple of cosmetic changes.
Thanks,
Uros.
@@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
#define PTA_SGX (HOST_WIDE_INT_1 << 63)
Please add a comment here, that the folowing belongs to flags2.
+#define PTA2_GFNI (HOST_WIDE_INT_1 << 0)
+#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1)
+#define PTA2_VAES (HOST_WIDE_INT_1 << 2)
@@ -4105,6 +4124,12 @@ ix86_option_override_internal (bool main_args_p,
if (processor_alias_table[i].flags & PTA_SGX
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
Please add vertical space here to visually separate flags and flags2 processing.
+ if (processor_alias_table[i].flags2 & PTA2_RDPID
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2017-11-12 7:33 [patch][x86] -march=icelake Koval, Julia
2017-11-12 16:34 ` Uros Bizjak
@ 2017-11-12 17:33 ` Sandra Loosemore
1 sibling, 0 replies; 21+ messages in thread
From: Sandra Loosemore @ 2017-11-12 17:33 UTC (permalink / raw)
To: Koval, Julia, GCC Patches; +Cc: Uros Bizjak, Kirill Yukhin
On 11/11/2017 05:04 PM, Koval, Julia wrote:
> Hi, this patch adds new option -march=icelake.
> [snip]
>
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index bc6e86f..891c283 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -25331,6 +25331,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> AVX512IFMA, SHA, CLWB and UMIP instruction set support.
>
> +@item Icelake
> +Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
> +SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
> +RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
> +XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
> +AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
> +AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
> +
> @item k6
> AMD K6 CPU with MMX instruction set support.
Since it's -march=icelake (all lower case),
s/@item Icelake/@item icelake/
-Sandra
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2017-11-12 16:34 ` Uros Bizjak
@ 2017-12-18 13:42 ` Koval, Julia
2017-12-19 8:31 ` Uros Bizjak
0 siblings, 1 reply; 21+ messages in thread
From: Koval, Julia @ 2017-12-18 13:42 UTC (permalink / raw)
To: Uros Bizjak; +Cc: GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 4698 bytes --]
Hi, I tried to replace 2 flags variable with c++ bitset(in patch attached). What do you think?
> Please add these options first.
2 options left(they are under Kirill's review currently), I'll add PTAs for them to the patch, as soon as they will be commited.
Thanks,
Julia
> -----Original Message-----
> From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches-
> owner@gcc.gnu.org] On Behalf Of Uros Bizjak
> Sent: Sunday, November 12, 2017 5:30 PM
> To: Koval, Julia <julia.koval@intel.com>
> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> <kirill.yukhin@gmail.com>
> Subject: Re: [patch][x86] -march=icelake
>
> On Sun, Nov 12, 2017 at 1:04 AM, Koval, Julia <julia.koval@intel.com> wrote:
> > Hi, this patch adds new option -march=icelake. Isasets defined in:
> https://software.intel.com/sites/default/files/managed/c5/15/architecture-
> instruction-set-extensions-programming-reference.pdf
> > I didn't add arch code to driver-i386.c, because there is no code available in
> SDM yet, only for cannonlake
> (https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-
> vol-1-2abcd-3abcd.pdf Chapter 2).
>
> This means the driver will go through generic detection for
> -march=native. Perhaps a comment should be added, so we won't forget
> to add the model number when one is available.
>
> > gcc/
> > * config.gcc: Add -march=icelake.
> > * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
> > * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
> > * config/i386/i386.c (processor_costs): Add m_ICELAKE.
> > (PTA_ICELAKE, PTA2_ICELAKE, PTA2_GFNI, PTA2_AVX512VBMI2,
> PTA2_VAES,
> > PTA2_AVX512VNNI, PTA2_VPCLMULQDQ, PTA2_RDPID,
> PTA2_AVX512BITALG): New.
> > (processor_target_table): Add icelake.
> > (ix86_option_override_internal): Add flags2 for new PTA, handle GFNI,
> RDPID.
> > (get_builtin_code_for_version): Handle icelake.
> > (M_INTEL_COREI7_ICELAKE): New.
> > * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
> > * doc/invoke.texi: Add -march=icelake.
> > gcc/testsuite/
> > * gcc.target/i386/funcspec-56.inc: Handle new march.
> > * g++.dg/ext/mv16.C: Ditto.
> > libgcc/
> > * config/i386/cpuinfo.h (processor_subtypes): Add
> INTEL_COREI7_ICELAKE.
>
> @@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
> #define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
> #define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
> #define PTA_SGX (HOST_WIDE_INT_1 << 63)
> +#define PTA2_GFNI (HOST_WIDE_INT_1 << 0)
> +#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1)
> +#define PTA2_VAES (HOST_WIDE_INT_1 << 2)
> +#define PTA2_AVX512VNNI (HOST_WIDE_INT_1 << 3)
> +#define PTA2_VPCLMULQDQ (HOST_WIDE_INT_1 << 4)
> +#define PTA2_RDPID (HOST_WIDE_INT_1 << 5)
> +#define PTA2_AVX512BITALG (HOST_WIDE_INT_1 << 6)
>
> Please add these options first.
>
> On a related note, there should probably be a better way to extend
> various bitmapped flag variables beyond 64bit words. We are constantly
> going over 64bit sizes in target option masks, now the number of
> processor flags doesn't fit in a word anymore. There are several
> places one has to keep in mind in which word some specific flag lives,
> and this approach opens several ways to make a hard to detect
> mistake. Does C++ offer a more elegant way?
>
> Bellow, please find a suggestion of a couple of cosmetic changes.
>
> Thanks,
> Uros.
>
> @@ -3425,6 +3427,13 @@ ix86_option_override_internal (bool main_args_p,
> #define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
> #define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
> #define PTA_SGX (HOST_WIDE_INT_1 << 63)
>
> Please add a comment here, that the folowing belongs to flags2.
>
> +#define PTA2_GFNI (HOST_WIDE_INT_1 << 0)
> +#define PTA2_AVX512VBMI2 (HOST_WIDE_INT_1 << 1)
> +#define PTA2_VAES (HOST_WIDE_INT_1 << 2)
>
>
> @@ -4105,6 +4124,12 @@ ix86_option_override_internal (bool main_args_p,
> if (processor_alias_table[i].flags & PTA_SGX
> && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
> opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
>
> Please add vertical space here to visually separate flags and flags2 processing.
>
> + if (processor_alias_table[i].flags2 & PTA2_RDPID
> + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
> + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
[-- Attachment #2: 0001-icelake.patch --]
[-- Type: application/octet-stream, Size: 52042 bytes --]
From 1b214db5fbd32933f5c1b595a04bf9a8868dec02 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Mon, 4 Dec 2017 13:35:45 +0300
Subject: [PATCH] icelake
---
gcc/config.gcc | 2 +-
gcc/config/i386/driver-i386.c | 5 +-
gcc/config/i386/i386-c.c | 7 +
gcc/config/i386/i386.c | 620 ++++++++++++++------------
gcc/config/i386/i386.h | 2 +
gcc/doc/invoke.texi | 8 +
gcc/testsuite/g++.dg/ext/mv16.C | 6 +
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 +
libgcc/config/i386/cpuinfo.h | 1 +
9 files changed, 354 insertions(+), 298 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index ff870c9..4f2bb89 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -631,7 +631,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
-skylake-avx512 cannonlake x86-64 native"
+skylake-avx512 cannonlake icelake x86-64 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index cfa8bd4..fa206cf 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -813,8 +813,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
if (arch)
{
/* This is unknown family 0x6 CPU. */
+ /* Assume Ice Lake. */
+ if (has_gfni)
+ cpu = "icelake";
/* Assume Cannon Lake. */
- if (has_avx512vbmi)
+ else if (has_avx512vbmi)
cpu = "cannonlake";
/* Assume Knights Mill. */
else if (has_avx5124vnniw)
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index d1d522a..7a53d0d 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -188,6 +188,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__cannonlake");
def_or_undef (parse_in, "__cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__icelake");
+ def_or_undef (parse_in, "__icelake__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
@@ -309,6 +313,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_CANNONLAKE:
def_or_undef (parse_in, "__tune_cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__tune_icelake__");
+ break;
case PROCESSOR_LAKEMONT:
def_or_undef (parse_in, "__tune_lakemont__");
break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index fcf7db1..d29cb12 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -88,6 +88,7 @@ along with GCC; see the file COPYING3. If not see
#include "symbol-summary.h"
#include "ipa-prop.h"
#include "ipa-fnsummary.h"
+#include "bitset"
/* This file should be included last. */
#include "target-def.h"
@@ -143,6 +144,7 @@ const struct processor_costs *ix86_cost = NULL;
#define m_KNM (1U<<PROCESSOR_KNM)
#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
+#define m_ICELAKE (1U<<PROCESSOR_ICELAKE)
#define m_INTEL (1U<<PROCESSOR_INTEL)
#define m_GEODE (1U<<PROCESSOR_GEODE)
@@ -855,7 +857,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{"knl", &slm_cost, 16, 15, 16, 7, 16},
{"knm", &slm_cost, 16, 15, 16, 7, 16},
{"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16},
- {"cannonlake", &core_cost, 16, 10, 16, 10, 16},
+ {"cannonlake", &skylake_cost, 16, 10, 16, 10, 16},
+ {"icelake", &skylake_cost, 16, 10, 16, 10, 16},
{"intel", &intel_cost, 16, 15, 16, 7, 16},
{"geode", &geode_cost, 0, 0, 0, 0, 0},
{"k6", &k6_cost, 32, 7, 32, 7, 32},
@@ -3346,6 +3349,15 @@ ix86_override_options_after_change (void)
ix86_default_align (&global_options);
}
+static const int BITSET_SIZE=128;
+typedef const std::bitset<BITSET_SIZE> bitmask;
+static inline bitmask get_bitmask (int set_bit)
+{
+ std::bitset<BITSET_SIZE> N;
+ N.set (set_bit);
+ return N;
+}
+
/* Override various settings based on options. If MAIN_ARGS_P, the
options are from the command line, otherwise they are from
attributes. Return true if there's an error related to march
@@ -3360,111 +3372,113 @@ ix86_option_override_internal (bool main_args_p,
unsigned int ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
-#define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
-#define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
-#define PTA_64BIT (HOST_WIDE_INT_1 << 2)
-#define PTA_ABM (HOST_WIDE_INT_1 << 3)
-#define PTA_AES (HOST_WIDE_INT_1 << 4)
-#define PTA_AVX (HOST_WIDE_INT_1 << 5)
-#define PTA_BMI (HOST_WIDE_INT_1 << 6)
-#define PTA_CX16 (HOST_WIDE_INT_1 << 7)
-#define PTA_F16C (HOST_WIDE_INT_1 << 8)
-#define PTA_FMA (HOST_WIDE_INT_1 << 9)
-#define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
-#define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
-#define PTA_LWP (HOST_WIDE_INT_1 << 12)
-#define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
-#define PTA_MMX (HOST_WIDE_INT_1 << 14)
-#define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
-#define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
-#define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
-#define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
-#define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
-#define PTA_RDRND (HOST_WIDE_INT_1 << 20)
-#define PTA_SSE (HOST_WIDE_INT_1 << 21)
-#define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
-#define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
-#define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
-#define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
-#define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
-#define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
-#define PTA_TBM (HOST_WIDE_INT_1 << 28)
-#define PTA_XOP (HOST_WIDE_INT_1 << 29)
-#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
-#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
-#define PTA_RTM (HOST_WIDE_INT_1 << 32)
-#define PTA_HLE (HOST_WIDE_INT_1 << 33)
-#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
-#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
-#define PTA_ADX (HOST_WIDE_INT_1 << 36)
-#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
-#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
-#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
-#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
-#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
-#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
-#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
-#define PTA_MPX (HOST_WIDE_INT_1 << 44)
-#define PTA_SHA (HOST_WIDE_INT_1 << 45)
-#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
-#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
-#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
-#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
-#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
-#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
-#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
-#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
-#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
-#define PTA_CLWB (HOST_WIDE_INT_1 << 55)
-#define PTA_MWAITX (HOST_WIDE_INT_1 << 56)
-#define PTA_CLZERO (HOST_WIDE_INT_1 << 57)
-#define PTA_NO_80387 (HOST_WIDE_INT_1 << 58)
-#define PTA_PKU (HOST_WIDE_INT_1 << 59)
-#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
-#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
-#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
-#define PTA_SGX (HOST_WIDE_INT_1 << 63)
-
-#define PTA_CORE2 \
- (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
- | PTA_CX16 | PTA_FXSR)
-#define PTA_NEHALEM \
- (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
-#define PTA_WESTMERE \
- (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
-#define PTA_SANDYBRIDGE \
- (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
-#define PTA_IVYBRIDGE \
- (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
-#define PTA_HASWELL \
- (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
- | PTA_FMA | PTA_MOVBE | PTA_HLE)
-#define PTA_BROADWELL \
- (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
-#define PTA_SKYLAKE \
- (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
-#define PTA_SKYLAKE_AVX512 \
- (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
- | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU)
-#define PTA_CANNONLAKE \
- (PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_CLWB)
-#define PTA_KNL \
- (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
-#define PTA_BONNELL \
- (PTA_CORE2 | PTA_MOVBE)
-#define PTA_SILVERMONT \
- (PTA_WESTMERE | PTA_MOVBE)
-#define PTA_KNM \
- (PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
-
-/* if this reaches 64, need to widen struct pta flags below */
+ bitmask pta_3dnow = get_bitmask (0);
+ bitmask pta_3dnow_a = get_bitmask (1);
+ bitmask pta_64bit = get_bitmask (2);
+ bitmask pta_abm = get_bitmask (3);
+ bitmask pta_aes = get_bitmask (4);
+ bitmask pta_avx = get_bitmask (5);
+ bitmask pta_bmi = get_bitmask (6);
+ bitmask pta_cx16 = get_bitmask (7);
+ bitmask pta_f16c = get_bitmask (8);
+ bitmask pta_fma = get_bitmask (9);
+ bitmask pta_fma4 = get_bitmask (10);
+ bitmask pta_fsgsbase = get_bitmask (11);
+ bitmask pta_lwp = get_bitmask (12);
+ bitmask pta_lzcnt = get_bitmask (13);
+ bitmask pta_mmx = get_bitmask (14);
+ bitmask pta_movbe = get_bitmask (15);
+ bitmask pta_no_sahf = get_bitmask (16);
+ bitmask pta_pclmul = get_bitmask (17);
+ bitmask pta_popcnt = get_bitmask (18);
+ bitmask pta_prefetch_sse = get_bitmask (19);
+ bitmask pta_rdrnd = get_bitmask (20);
+ bitmask pta_sse = get_bitmask (21);
+ bitmask pta_sse2 = get_bitmask (22);
+ bitmask pta_sse3 = get_bitmask (23);
+ bitmask pta_sse4_1 = get_bitmask (24);
+ bitmask pta_sse4_2 = get_bitmask (25);
+ bitmask pta_sse4a = get_bitmask (26);
+ bitmask pta_ssse3 = get_bitmask (27);
+ bitmask pta_tbm = get_bitmask (28);
+ bitmask pta_xop = get_bitmask (29);
+ bitmask pta_avx2 = get_bitmask (30);
+ bitmask pta_bmi2 = get_bitmask (31);
+ bitmask pta_rtm = get_bitmask (32);
+ bitmask pta_hle = get_bitmask (33);
+ bitmask pta_prfchw = get_bitmask (34);
+ bitmask pta_rdseed = get_bitmask (35);
+ bitmask pta_adx = get_bitmask (36);
+ bitmask pta_fxsr = get_bitmask (37);
+ bitmask pta_xsave = get_bitmask (38);
+ bitmask pta_xsaveopt = get_bitmask (39);
+ bitmask pta_avx512f = get_bitmask (40);
+ bitmask pta_avx512er = get_bitmask (41);
+ bitmask pta_avx512pf = get_bitmask (42);
+ bitmask pta_avx512cd = get_bitmask (43);
+ bitmask pta_mpx = get_bitmask (44);
+ bitmask pta_sha = get_bitmask (45);
+ bitmask pta_prefetchwt1 = get_bitmask (46);
+ bitmask pta_clflushopt = get_bitmask (47);
+ bitmask pta_xsavec = get_bitmask (48);
+ bitmask pta_xsaves = get_bitmask (49);
+ bitmask pta_avx512dq = get_bitmask (50);
+ bitmask pta_avx512bw = get_bitmask (51);
+ bitmask pta_avx512vl = get_bitmask (52);
+ bitmask pta_avx512ifma = get_bitmask (53);
+ bitmask pta_avx512vbmi = get_bitmask (54);
+ bitmask pta_clwb = get_bitmask (55);
+ bitmask pta_mwaitx = get_bitmask (56);
+ bitmask pta_clzero = get_bitmask (57);
+ bitmask pta_no_80387 = get_bitmask (58);
+ bitmask pta_pku = get_bitmask (59);
+ bitmask pta_avx5124vnniw = get_bitmask (60);
+ bitmask pta_avx5124fmaps = get_bitmask (61);
+ bitmask pta_avx512vpopcntdq = get_bitmask (62);
+ bitmask pta_sgx = get_bitmask (63);
+ bitmask pta_gfni = get_bitmask (64);
+ bitmask pta_avx512vbmi2 = get_bitmask (65);
+ bitmask pta_vaes = get_bitmask (66);
+ bitmask pta_avx512vnni = get_bitmask (67);
+ bitmask pta_vpclmulqdq = get_bitmask (68);
+ bitmask pta_rdpid = get_bitmask (69);
+ bitmask pta_avx512bitalg = get_bitmask (70);
+
+ bitmask pta_core2 = pta_64bit | pta_mmx | pta_sse | pta_sse2
+ | pta_sse3 | pta_ssse3 | pta_cx16 | pta_fxsr;
+ bitmask pta_nehalem = pta_core2 | pta_sse4_1 | pta_sse4_2
+ | pta_popcnt;
+ bitmask pta_westmere = pta_nehalem | pta_aes | pta_pclmul;
+ bitmask pta_sandybridge = pta_westmere | pta_avx | pta_xsave
+ | pta_xsaveopt;
+ bitmask pta_ivybridge = pta_sandybridge | pta_fsgsbase | pta_rdrnd
+ | pta_f16c;
+ bitmask pta_haswell = pta_ivybridge | pta_avx2 | pta_bmi | pta_bmi2
+ | pta_lzcnt | pta_fma | pta_movbe | pta_hle;
+ bitmask pta_broadwell = pta_haswell | pta_adx | pta_prfchw | pta_rdseed;
+ bitmask pta_skylake = pta_broadwell | pta_clflushopt | pta_xsavec
+ | pta_xsaves;
+ bitmask pta_skylake_avx512 = pta_skylake | pta_avx512f | pta_avx512cd
+ | pta_avx512vl | pta_avx512bw | pta_avx512dq
+ | pta_pku;
+ bitmask pta_cannonlake = pta_skylake_avx512 | pta_avx512vbmi
+ | pta_avx512ifma | pta_sha | pta_clwb;
+ bitmask pta_icelake = pta_cannonlake | pta_avx512vpopcntdq | pta_gfni
+ | pta_avx512vbmi2 | pta_vaes | pta_avx512vnni
+ | pta_vpclmulqdq | pta_rdpid | pta_avx512bitalg;
+ bitmask pta_knl = pta_broadwell | pta_avx512pf | pta_avx512er
+ | pta_avx512f | pta_avx512cd;
+ bitmask pta_bonnell = pta_core2 | pta_movbe;
+ bitmask pta_silvermont = pta_westmere | pta_movbe;
+ bitmask pta_knm = pta_knl | pta_avx5124vnniw | pta_avx5124fmaps
+ | pta_avx512vpopcntdq;
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
const enum attr_cpu schedule;
- const unsigned HOST_WIDE_INT flags;
+ bitmask flags;
}
const processor_alias_table[] =
{
@@ -3472,180 +3486,182 @@ ix86_option_override_internal (bool main_args_p,
{"i486", PROCESSOR_I486, CPU_NONE, 0},
{"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
{"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
- {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
- {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
- {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+ {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, pta_no_80387},
+ {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, pta_mmx},
+ {"winchip-c6", PROCESSOR_I486, CPU_NONE, pta_mmx},
+ {"winchip2", PROCESSOR_I486, CPU_NONE, pta_mmx | pta_3dnow},
+ {"c3", PROCESSOR_I486, CPU_NONE, pta_mmx | pta_3dnow},
+ {"samuel-2", PROCESSOR_I486, CPU_NONE, pta_mmx | pta_3dnow},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_sse | pta_fxsr},
{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_sse | pta_fxsr},
{"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ pta_mmx | pta_sse | pta_sse2 | pta_sse3 | pta_fxsr},
{"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ pta_mmx | pta_sse | pta_sse2 | pta_sse3 | pta_fxsr},
{"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
{"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+ {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+ pta_mmx | pta_fxsr},
{"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_sse | pta_fxsr},
{"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_sse | pta_fxsr},
{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ pta_mmx | pta_sse | pta_sse2 | pta_fxsr},
{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ pta_mmx |pta_sse | pta_sse2 | pta_fxsr},
{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ pta_mmx | pta_sse | pta_sse2 | pta_fxsr},
{"prescott", PROCESSOR_NOCONA, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ pta_mmx | pta_sse | pta_sse2 | pta_sse3 | pta_fxsr},
{"nocona", PROCESSOR_NOCONA, CPU_NONE,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
- {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
- {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_cx16 | pta_no_sahf | pta_fxsr},
+ {"core2", PROCESSOR_CORE2, CPU_CORE2, pta_core2},
+ {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, pta_nehalem},
+ {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, pta_nehalem},
+ {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, pta_westmere},
{"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ pta_sandybridge},
{"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ pta_sandybridge},
{"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
+ pta_ivybridge},
{"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
- {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
- {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE},
+ pta_ivybridge},
+ {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, pta_haswell},
+ {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, pta_haswell},
+ {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, pta_broadwell},
+ {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, pta_skylake},
{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
- PTA_SKYLAKE_AVX512},
- {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE},
- {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
- {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
- {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+ pta_skylake_avx512},
+ {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, pta_cannonlake},
+ {"icelake", PROCESSOR_HASWELL, CPU_HASWELL, pta_icelake},
+ {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, pta_bonnell},
+ {"atom", PROCESSOR_BONNELL, CPU_ATOM, pta_bonnell},
+ {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, pta_silvermont},
+ {"slm", PROCESSOR_SILVERMONT, CPU_SLM, pta_silvermont},
+ {"knl", PROCESSOR_KNL, CPU_SLM, pta_knl},
+ {"knm", PROCESSOR_KNM, CPU_SLM, pta_knm},
+ {"intel", PROCESSOR_INTEL, CPU_SLM, pta_nehalem},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
- {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
- {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
- {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+ pta_mmx | pta_3dnow | pta_3dnow_a | pta_prefetch_sse},
+ {"k6", PROCESSOR_K6, CPU_K6, pta_mmx},
+ {"k6-2", PROCESSOR_K6, CPU_K6, pta_mmx | pta_3dnow},
+ {"k6-3", PROCESSOR_K6, CPU_K6, pta_mmx | pta_3dnow},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ pta_mmx | pta_3dnow | pta_3dnow_a | pta_prefetch_sse},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ pta_mmx | pta_3dnow | pta_3dnow_a | pta_prefetch_sse},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse | pta_fxsr},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse | pta_fxsr},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse | pta_fxsr},
{"x86-64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_no_sahf | pta_fxsr},
{"eden-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3 | pta_fxsr},
{"nano", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_fxsr},
{"nano-1000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_fxsr},
{"nano-2000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_fxsr},
{"nano-3000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_sse4_1 | pta_fxsr},
{"nano-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_sse4_1 | pta_fxsr},
{"eden-x4", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_sse4_1 | pta_fxsr},
{"nano-x4", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_sse4_1 | pta_fxsr},
{"k8", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_no_sahf | pta_fxsr},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_sse3 | pta_no_sahf | pta_fxsr},
{"opteron", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_no_sahf | pta_fxsr},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_sse3 | pta_no_sahf | pta_fxsr},
{"athlon64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_no_sahf | pta_fxsr},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_sse3 | pta_no_sahf | pta_fxsr},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse
+ | pta_sse2 | pta_no_sahf | pta_fxsr},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse | pta_sse2
+ | pta_sse3 | pta_sse4a | pta_cx16 | pta_abm | pta_prfchw | pta_fxsr},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ pta_64bit | pta_mmx | pta_3dnow | pta_3dnow_a | pta_sse | pta_sse2
+ | pta_sse3 | pta_sse4a | pta_cx16 | pta_abm | pta_prfchw | pta_fxsr},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_sse4a | pta_cx16 | pta_abm | pta_ssse3 | pta_sse4_1
+ | pta_sse4_2 | pta_aes | pta_pclmul | pta_avx | pta_fma4
+ | pta_xop | pta_lwp | pta_prfchw | pta_fxsr | pta_xsave},
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_sse4a | pta_cx16 | pta_abm | pta_ssse3 | pta_sse4_1
+ | pta_sse4_2 | pta_aes | pta_pclmul | pta_avx | pta_fma4
+ | pta_xop | pta_lwp | pta_bmi | pta_tbm | pta_f16c
+ | pta_fma | pta_prfchw | pta_fxsr | pta_xsave},
{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT | PTA_FSGSBASE},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_sse4a | pta_cx16 | pta_abm | pta_ssse3 | pta_sse4_1
+ | pta_sse4_2 | pta_aes | pta_pclmul | pta_avx | pta_fma4
+ | pta_xop | pta_lwp | pta_bmi | pta_tbm | pta_f16c
+ | pta_fma | pta_prfchw | pta_fxsr | pta_xsave
+ | pta_xsaveopt | pta_fsgsbase},
{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
- | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
- | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
- | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
- | PTA_MOVBE | PTA_MWAITX},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_sse4a | pta_cx16 | pta_abm | pta_ssse3 | pta_sse4_1
+ | pta_sse4_2 | pta_aes | pta_pclmul | pta_avx | pta_avx2
+ | pta_fma4 | pta_xop | pta_lwp | pta_bmi | pta_bmi2
+ | pta_tbm | pta_f16c | pta_fma | pta_prfchw | pta_fxsr
+ | pta_xsave | pta_xsaveopt | pta_fsgsbase | pta_rdrnd
+ | pta_movbe | pta_mwaitx},
{"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
- | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
- | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
- | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
- | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_sse4a | pta_cx16 | pta_abm | pta_ssse3 | pta_sse4_1
+ | pta_sse4_2 | pta_aes | pta_pclmul | pta_avx | pta_avx2
+ | pta_bmi | pta_bmi2 | pta_f16c | pta_fma | pta_prfchw
+ | pta_fxsr | pta_xsave | pta_xsaveopt | pta_fsgsbase
+ | pta_rdrnd | pta_movbe | pta_mwaitx | pta_adx | pta_rdseed
+ | pta_clzero | pta_clflushopt | pta_xsavec | pta_xsaves
+ | pta_sha | pta_lzcnt | pta_popcnt},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_sse4a |pta_abm | pta_cx16 | pta_prfchw
+ | pta_fxsr | pta_xsave},
{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
- | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+ pta_64bit | pta_mmx | pta_sse | pta_sse2 | pta_sse3
+ | pta_ssse3 | pta_sse4a |pta_abm | pta_cx16 | pta_sse4_1
+ | pta_sse4_2 | pta_aes | pta_pclmul | pta_avx
+ | pta_bmi | pta_f16c | pta_movbe | pta_prfchw
+ | pta_fxsr | pta_xsave | pta_xsaveopt},
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
- PTA_64BIT
- | PTA_HLE /* flags are only used for -march switch. */ },
+ pta_64bit
+ | pta_hle /* flags are only used for -march switch. */ },
};
/* -mrecip options. */
@@ -3914,7 +3930,7 @@ ix86_option_override_internal (bool main_args_p,
}
if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && !(processor_alias_table[i].flags & PTA_64BIT))
+ && (processor_alias_table[i].flags & pta_64bit).none ())
{
error ("CPU you selected does not support x86-64 "
"instruction set");
@@ -3926,192 +3942,199 @@ ix86_option_override_internal (bool main_args_p,
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
+ if ((processor_alias_table[i].flags & pta_mmx).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
+ if ((processor_alias_table[i].flags & pta_3dnow).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
+ if ((processor_alias_table[i].flags & pta_3dnow_a).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
+ if ((processor_alias_table[i].flags & pta_sse).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
+ if ((processor_alias_table[i].flags & pta_sse2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
- if (processor_alias_table[i].flags & PTA_SSE3
+ if ((processor_alias_table[i].flags & pta_sse3).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
- if (processor_alias_table[i].flags & PTA_SSSE3
+ if ((processor_alias_table[i].flags & pta_ssse3).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
- if (processor_alias_table[i].flags & PTA_SSE4_1
+ if ((processor_alias_table[i].flags & pta_sse4_1).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
- if (processor_alias_table[i].flags & PTA_SSE4_2
+ if ((processor_alias_table[i].flags & pta_sse4_2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
- if (processor_alias_table[i].flags & PTA_AVX
+ if ((processor_alias_table[i].flags & pta_avx).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX;
- if (processor_alias_table[i].flags & PTA_AVX2
+ if ((processor_alias_table[i].flags & pta_avx2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
- if (processor_alias_table[i].flags & PTA_FMA
+ if ((processor_alias_table[i].flags & pta_fma).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA;
- if (processor_alias_table[i].flags & PTA_SSE4A
+ if ((processor_alias_table[i].flags & pta_sse4a).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_FMA4
+ if ((processor_alias_table[i].flags & pta_fma4).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
- if (processor_alias_table[i].flags & PTA_XOP
+ if ((processor_alias_table[i].flags & pta_xop).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP;
- if (processor_alias_table[i].flags & PTA_LWP
+ if ((processor_alias_table[i].flags & pta_lwp).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP;
- if (processor_alias_table[i].flags & PTA_ABM
+ if ((processor_alias_table[i].flags & pta_abm).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM;
- if (processor_alias_table[i].flags & PTA_BMI
+ if ((processor_alias_table[i].flags & pta_bmi).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI;
- if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
+ if ((processor_alias_table[i].flags & (pta_lzcnt | pta_abm)).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
- if (processor_alias_table[i].flags & PTA_TBM
+ if ((processor_alias_table[i].flags & pta_tbm).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM;
- if (processor_alias_table[i].flags & PTA_BMI2
+ if ((processor_alias_table[i].flags & pta_bmi2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
- if (processor_alias_table[i].flags & PTA_CX16
+ if ((processor_alias_table[i].flags & pta_cx16).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16;
- if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
+ if ((processor_alias_table[i].flags & (pta_popcnt | pta_abm)).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
if (!(TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && (processor_alias_table[i].flags & PTA_NO_SAHF))
+ && (processor_alias_table[i].flags & pta_no_sahf).any ())
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
- if (processor_alias_table[i].flags & PTA_MOVBE
+ if ((processor_alias_table[i].flags & pta_movbe).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
- if (processor_alias_table[i].flags & PTA_AES
+ if ((processor_alias_table[i].flags & pta_aes).any ()
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
ix86_isa_flags |= OPTION_MASK_ISA_AES;
- if (processor_alias_table[i].flags & PTA_SHA
+ if ((processor_alias_table[i].flags & pta_sha).any ()
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SHA))
ix86_isa_flags |= OPTION_MASK_ISA_SHA;
- if (processor_alias_table[i].flags & PTA_PCLMUL
+ if ((processor_alias_table[i].flags & pta_pclmul).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
- if (processor_alias_table[i].flags & PTA_FSGSBASE
+ if ((processor_alias_table[i].flags & pta_fsgsbase).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
- if (processor_alias_table[i].flags & PTA_RDRND
+ if ((processor_alias_table[i].flags & pta_rdrnd).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
- if (processor_alias_table[i].flags & PTA_F16C
+ if ((processor_alias_table[i].flags & pta_f16c).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C;
- if (processor_alias_table[i].flags & PTA_RTM
+ if ((processor_alias_table[i].flags & pta_rtm).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM;
- if (processor_alias_table[i].flags & PTA_HLE
+ if ((processor_alias_table[i].flags & pta_hle).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_HLE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_HLE;
- if (processor_alias_table[i].flags & PTA_PRFCHW
+ if ((processor_alias_table[i].flags & pta_prfchw).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
- if (processor_alias_table[i].flags & PTA_RDSEED
+ if ((processor_alias_table[i].flags & pta_rdseed).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
- if (processor_alias_table[i].flags & PTA_ADX
+ if ((processor_alias_table[i].flags & pta_adx).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ADX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX;
- if (processor_alias_table[i].flags & PTA_FXSR
+ if ((processor_alias_table[i].flags & pta_fxsr).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FXSR))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR;
- if (processor_alias_table[i].flags & PTA_XSAVE
+ if ((processor_alias_table[i].flags & pta_xsave).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE;
- if (processor_alias_table[i].flags & PTA_XSAVEOPT
+ if ((processor_alias_table[i].flags & pta_xsaveopt).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
- if (processor_alias_table[i].flags & PTA_AVX512F
+ if ((processor_alias_table[i].flags & pta_avx512f).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
- if (processor_alias_table[i].flags & PTA_AVX512ER
+ if ((processor_alias_table[i].flags & pta_avx512er).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
- if (processor_alias_table[i].flags & PTA_AVX512PF
+ if ((processor_alias_table[i].flags & pta_avx512pf).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
- if (processor_alias_table[i].flags & PTA_AVX512CD
+ if ((processor_alias_table[i].flags & pta_avx512cd).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
- if (processor_alias_table[i].flags & PTA_PREFETCHWT1
+ if ((processor_alias_table[i].flags & pta_prefetchwt1).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
- if (processor_alias_table[i].flags & PTA_CLWB
+ if ((processor_alias_table[i].flags & pta_clwb).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
- if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
+ if ((processor_alias_table[i].flags & pta_clflushopt).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
- if (processor_alias_table[i].flags & PTA_CLZERO
+ if ((processor_alias_table[i].flags & pta_clzero).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLZERO))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLZERO;
- if (processor_alias_table[i].flags & PTA_XSAVEC
+ if ((processor_alias_table[i].flags & pta_xsavec).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC;
- if (processor_alias_table[i].flags & PTA_XSAVES
+ if ((processor_alias_table[i].flags & pta_xsaves).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
- if (processor_alias_table[i].flags & PTA_AVX512DQ
+ if ((processor_alias_table[i].flags & pta_avx512dq).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
- if (processor_alias_table[i].flags & PTA_AVX512BW
+ if ((processor_alias_table[i].flags & pta_avx512bw).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
- if (processor_alias_table[i].flags & PTA_AVX512VL
+ if ((processor_alias_table[i].flags & pta_avx512vl).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
- if (processor_alias_table[i].flags & PTA_MPX
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
+ if ((processor_alias_table[i].flags & pta_mpx).any ()
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX;
- if (processor_alias_table[i].flags & PTA_AVX512VBMI
+ if ((processor_alias_table[i].flags & pta_avx512vbmi).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI;
- if (processor_alias_table[i].flags & PTA_AVX512IFMA
+ if ((processor_alias_table[i].flags & pta_avx512ifma).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
- if (processor_alias_table[i].flags & PTA_AVX5124VNNIW
+ if ((processor_alias_table[i].flags & pta_avx5124vnniw).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX5124VNNIW))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW;
- if (processor_alias_table[i].flags & PTA_AVX5124FMAPS
+ if ((processor_alias_table[i].flags & pta_avx5124fmaps).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX5124FMAPS))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS;
- if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
+ if ((processor_alias_table[i].flags & pta_avx512vpopcntdq).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
- if (processor_alias_table[i].flags & PTA_SGX
+ if ((processor_alias_table[i].flags & pta_sgx).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
-
- if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
+ if ((processor_alias_table[i].flags & pta_rdpid).any ()
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
+ if ((processor_alias_table[i].flags & pta_gfni).any ()
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_GFNI))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI;
+
+ if ((processor_alias_table[i].flags
+ & (pta_prefetch_sse | pta_sse)).any ())
x86_prefetch_sse = true;
- if (processor_alias_table[i].flags & PTA_MWAITX
+ if ((processor_alias_table[i].flags & pta_mwaitx).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MWAITX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX;
- if (processor_alias_table[i].flags & PTA_PKU
+ if ((processor_alias_table[i].flags & pta_pku).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
@@ -4120,7 +4143,7 @@ ix86_option_override_internal (bool main_args_p,
if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
&& !(opts_set->x_target_flags & MASK_80387))
{
- if (processor_alias_table[i].flags & PTA_NO_80387)
+ if ((processor_alias_table[i].flags & pta_no_80387).any ())
opts->x_target_flags &= ~MASK_80387;
else
opts->x_target_flags |= MASK_80387;
@@ -4146,7 +4169,7 @@ ix86_option_override_internal (bool main_args_p,
if (strcmp (processor_alias_table[i].name, "generic")
&& strcmp (processor_alias_table[i].name, "intel")
&& (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT)))
+ || ((processor_alias_table[i].flags & pta_64bit).any ())))
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -4179,7 +4202,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_tune = processor_alias_table[i].processor;
if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
{
- if (!(processor_alias_table[i].flags & PTA_64BIT))
+ if ((processor_alias_table[i].flags & pta_64bit).none ())
{
if (ix86_tune_defaulted)
{
@@ -4201,8 +4224,8 @@ ix86_option_override_internal (bool main_args_p,
-mtune (rather than -march) points us to a processor that has them.
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
- if (TARGET_CMOV
- && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
+ if (TARGET_CMOV && (processor_alias_table[i].flags
+ & (pta_prefetch_sse | pta_sse)).any ())
x86_prefetch_sse = true;
break;
}
@@ -4217,7 +4240,7 @@ ix86_option_override_internal (bool main_args_p,
auto_vec <const char *> candidates;
for (i = 0; i < pta_size; i++)
if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT))
+ || (processor_alias_table[i].flags & pta_64bit).any ())
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -31260,7 +31283,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
break;
case PROCESSOR_HASWELL:
case PROCESSOR_SKYLAKE_AVX512:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI)
+ if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI)
+ arg_str = "icelake";
+ else if (new_target->x_ix86_isa_flags
+ & OPTION_MASK_ISA_AVX512VBMI)
arg_str = "cannonlake";
else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
arg_str = "skylake-avx512";
@@ -31985,7 +32011,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_INTEL_COREI7_BROADWELL,
M_INTEL_COREI7_SKYLAKE,
M_INTEL_COREI7_SKYLAKE_AVX512,
- M_INTEL_COREI7_CANNONLAKE
+ M_INTEL_COREI7_CANNONLAKE,
+ M_INTEL_COREI7_ICELAKE
};
static struct _arch_names_table
@@ -32010,6 +32037,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
{"skylake", M_INTEL_COREI7_SKYLAKE},
{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
+ {"icelake", M_INTEL_COREI7_ICELAKE},
{"bonnell", M_INTEL_BONNELL},
{"silvermont", M_INTEL_SILVERMONT},
{"knl", M_INTEL_KNL},
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 638f1f15..49fd694 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -375,6 +375,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
+#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE)
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2257,6 +2258,7 @@ enum processor_type
PROCESSOR_KNM,
PROCESSOR_SKYLAKE_AVX512,
PROCESSOR_CANNONLAKE,
+ PROCESSOR_ICELAKE,
PROCESSOR_INTEL,
PROCESSOR_GEODE,
PROCESSOR_K6,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index b4e0231..353920b 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25322,6 +25322,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
+@item Icelake
+Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
+AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C
index 1e1ae3d..8fbdb47 100644
--- a/gcc/testsuite/g++.dg/ext/mv16.C
+++ b/gcc/testsuite/g++.dg/ext/mv16.C
@@ -60,6 +60,10 @@ int __attribute__ ((target("arch=cannonlake"))) foo () {
return 16;
}
+int __attribute__ ((target("arch=icelake"))) foo () {
+ return 17;
+}
+
int main ()
{
int val = foo ();
@@ -82,6 +86,8 @@ int main ()
assert (val == 15);
else if (__builtin_cpu_is ("cannonlake"))
assert (val == 16);
+ else if (__builtin_cpu_is ("icelake"))
+ assert (val == 17);
else
assert (val == 0);
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index ed0748b..837cdc3 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -145,6 +145,7 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
+extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake")));
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index 4b2a3c5..67f17ef 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -70,6 +70,7 @@ enum processor_subtypes
INTEL_COREI7_SKYLAKE,
INTEL_COREI7_SKYLAKE_AVX512,
INTEL_COREI7_CANNONLAKE,
+ INTEL_COREI7_ICELAKE,
CPU_SUBTYPE_MAX
};
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2017-12-18 13:42 ` Koval, Julia
@ 2017-12-19 8:31 ` Uros Bizjak
2017-12-19 11:55 ` Richard Biener
0 siblings, 1 reply; 21+ messages in thread
From: Uros Bizjak @ 2017-12-19 8:31 UTC (permalink / raw)
To: Koval, Julia; +Cc: GCC Patches, Kirill Yukhin
On Mon, Dec 18, 2017 at 2:42 PM, Koval, Julia <julia.koval@intel.com> wrote:
> Hi, I tried to replace 2 flags variable with c++ bitset(in patch attached). What do you think?
Hm, I'm not a c++ person, but I wonder about overhead and performance
impact of this change. Maybe [] operator could be used instead of a
dynamic handling here. Please discuss with a c++ person to find out
the most appropriate approach.
>> Please add these options first.
> 2 options left(they are under Kirill's review currently), I'll add PTAs for them to the patch, as soon as they will be commited.
Actually, let's wait for these 2 options to be reviewed and committed
first, and after that introduce -march=icelake handling.
Uros.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2017-12-19 8:31 ` Uros Bizjak
@ 2017-12-19 11:55 ` Richard Biener
2017-12-19 12:34 ` Koval, Julia
0 siblings, 1 reply; 21+ messages in thread
From: Richard Biener @ 2017-12-19 11:55 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Koval, Julia, GCC Patches, Kirill Yukhin
On Tue, Dec 19, 2017 at 9:29 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Mon, Dec 18, 2017 at 2:42 PM, Koval, Julia <julia.koval@intel.com> wrote:
>> Hi, I tried to replace 2 flags variable with c++ bitset(in patch attached). What do you think?
>
> Hm, I'm not a c++ person, but I wonder about overhead and performance
> impact of this change. Maybe [] operator could be used instead of a
> dynamic handling here. Please discuss with a c++ person to find out
> the most appropriate approach.
The natural GCC data structure is a sbitmap ... I'd rather not use <bitset>
given we have a GCC variant.
>>> Please add these options first.
>> 2 options left(they are under Kirill's review currently), I'll add PTAs for them to the patch, as soon as they will be commited.
>
> Actually, let's wait for these 2 options to be reviewed and committed
> first, and after that introduce -march=icelake handling.
>
> Uros.
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2017-12-19 11:55 ` Richard Biener
@ 2017-12-19 12:34 ` Koval, Julia
2017-12-19 13:08 ` Richard Biener
2017-12-19 13:49 ` Jakub Jelinek
0 siblings, 2 replies; 21+ messages in thread
From: Koval, Julia @ 2017-12-19 12:34 UTC (permalink / raw)
To: Richard Biener, Uros Bizjak; +Cc: GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 2057 bytes --]
>> Maybe [] operator could be used instead of a dynamic handling here.
I had another solution in mind, with enums, which then addresses elements using its index, please look the patch attached.
>>> The natural GCC data structure is a sbitmap ... I'd rather not use <bitset> given we have a GCC variant.
Sorry for maybe stupid question, but how do we set
bitmask pta_core2 = pta_64bit | pta_mmx | pta_sse | pta_sse2
| pta_sse3 | pta_ssse3 | pta_cx16 | pta_fxsr;
in sbitmap, except chain of bitmap_and_or with third bitmap set to ones(which doesn't look fast)?
Sorry, I think there should be some obvious solution, but can't find a proper function.
Thanks,
Julia
> -----Original Message-----
> From: Richard Biener [mailto:richard.guenther@gmail.com]
> Sent: Tuesday, December 19, 2017 12:56 PM
> To: Uros Bizjak <ubizjak@gmail.com>
> Cc: Koval, Julia <julia.koval@intel.com>; GCC Patches <gcc-
> patches@gcc.gnu.org>; Kirill Yukhin <kirill.yukhin@gmail.com>
> Subject: Re: [patch][x86] -march=icelake
>
> On Tue, Dec 19, 2017 at 9:29 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> > On Mon, Dec 18, 2017 at 2:42 PM, Koval, Julia <julia.koval@intel.com> wrote:
> >> Hi, I tried to replace 2 flags variable with c++ bitset(in patch attached). What
> do you think?
> >
> > Hm, I'm not a c++ person, but I wonder about overhead and performance
> > impact of this change. Maybe [] operator could be used instead of a
> > dynamic handling here. Please discuss with a c++ person to find out
> > the most appropriate approach.
>
> The natural GCC data structure is a sbitmap ... I'd rather not use <bitset>
> given we have a GCC variant.
>
> >>> Please add these options first.
> >> 2 options left(they are under Kirill's review currently), I'll add PTAs for them to
> the patch, as soon as they will be commited.
> >
> > Actually, let's wait for these 2 options to be reviewed and committed
> > first, and after that introduce -march=icelake handling.
> >
> > Uros.
[-- Attachment #2: 0001-icelake.patch_enums --]
[-- Type: application/octet-stream, Size: 51097 bytes --]
From daec2e35cd564d9e9c4659caa9da2bbf79c5916d Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Mon, 4 Dec 2017 13:35:45 +0300
Subject: [PATCH] icelake
---
gcc/config.gcc | 2 +-
gcc/config/i386/driver-i386.c | 5 +-
gcc/config/i386/i386-c.c | 7 +
gcc/config/i386/i386.c | 586 +++++++++++++-------------
gcc/config/i386/i386.h | 2 +
gcc/doc/invoke.texi | 8 +
gcc/testsuite/g++.dg/ext/mv16.C | 6 +
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 +
libgcc/config/i386/cpuinfo.h | 1 +
9 files changed, 320 insertions(+), 298 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e208d00..30bdff2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -633,7 +633,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
-skylake-avx512 cannonlake x86-64 native"
+skylake-avx512 cannonlake icelake x86-64 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 0cc4c4e..a295171 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -816,8 +816,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
if (arch)
{
/* This is unknown family 0x6 CPU. */
+ /* Assume Ice Lake. */
+ if (has_gfni)
+ cpu = "icelake";
/* Assume Cannon Lake. */
- if (has_avx512vbmi)
+ else if (has_avx512vbmi)
cpu = "cannonlake";
/* Assume Knights Mill. */
else if (has_avx5124vnniw)
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 8ccec7b..ffd9d88 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -188,6 +188,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__cannonlake");
def_or_undef (parse_in, "__cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__icelake");
+ def_or_undef (parse_in, "__icelake__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
@@ -309,6 +313,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_CANNONLAKE:
def_or_undef (parse_in, "__tune_cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__tune_icelake__");
+ break;
case PROCESSOR_LAKEMONT:
def_or_undef (parse_in, "__tune_lakemont__");
break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3503743..980cd80 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -88,6 +88,7 @@ along with GCC; see the file COPYING3. If not see
#include "symbol-summary.h"
#include "ipa-prop.h"
#include "ipa-fnsummary.h"
+#include "bitset"
/* This file should be included last. */
#include "target-def.h"
@@ -143,6 +144,7 @@ const struct processor_costs *ix86_cost = NULL;
#define m_KNM (1U<<PROCESSOR_KNM)
#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
+#define m_ICELAKE (1U<<PROCESSOR_ICELAKE)
#define m_INTEL (1U<<PROCESSOR_INTEL)
#define m_GEODE (1U<<PROCESSOR_GEODE)
@@ -856,6 +858,7 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{"knm", &slm_cost, 16, 15, 16, 7, 16},
{"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16},
{"cannonlake", &core_cost, 16, 10, 16, 10, 16},
+ {"icelake", &skylake_cost, 16, 10, 16, 10, 16},
{"intel", &intel_cost, 16, 15, 16, 7, 16},
{"geode", &geode_cost, 0, 0, 0, 0, 0},
{"k6", &k6_cost, 32, 7, 32, 7, 32},
@@ -3352,6 +3355,19 @@ ix86_override_options_after_change (void)
ix86_default_align (&global_options);
}
+static const int BITSET_SIZE=128;
+typedef std::bitset<BITSET_SIZE> bitmask;
+
+/* There is no constructior to create bitset with Nth
+ bit set, this functions replaces it. */
+
+static inline const bitmask get_bitmask (int set_bit)
+{
+ bitmask N;
+ N.set (set_bit);
+ return N;
+}
+
/* Override various settings based on options. If MAIN_ARGS_P, the
options are from the command line, otherwise they are from
attributes. Return true if there's an error related to march
@@ -3366,102 +3382,54 @@ ix86_option_override_internal (bool main_args_p,
unsigned int ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
-#define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
-#define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
-#define PTA_64BIT (HOST_WIDE_INT_1 << 2)
-#define PTA_ABM (HOST_WIDE_INT_1 << 3)
-#define PTA_AES (HOST_WIDE_INT_1 << 4)
-#define PTA_AVX (HOST_WIDE_INT_1 << 5)
-#define PTA_BMI (HOST_WIDE_INT_1 << 6)
-#define PTA_CX16 (HOST_WIDE_INT_1 << 7)
-#define PTA_F16C (HOST_WIDE_INT_1 << 8)
-#define PTA_FMA (HOST_WIDE_INT_1 << 9)
-#define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
-#define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
-#define PTA_LWP (HOST_WIDE_INT_1 << 12)
-#define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
-#define PTA_MMX (HOST_WIDE_INT_1 << 14)
-#define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
-#define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
-#define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
-#define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
-#define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
-#define PTA_RDRND (HOST_WIDE_INT_1 << 20)
-#define PTA_SSE (HOST_WIDE_INT_1 << 21)
-#define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
-#define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
-#define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
-#define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
-#define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
-#define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
-#define PTA_TBM (HOST_WIDE_INT_1 << 28)
-#define PTA_XOP (HOST_WIDE_INT_1 << 29)
-#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
-#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
-#define PTA_RTM (HOST_WIDE_INT_1 << 32)
-#define PTA_HLE (HOST_WIDE_INT_1 << 33)
-#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
-#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
-#define PTA_ADX (HOST_WIDE_INT_1 << 36)
-#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
-#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
-#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
-#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
-#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
-#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
-#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
-#define PTA_MPX (HOST_WIDE_INT_1 << 44)
-#define PTA_SHA (HOST_WIDE_INT_1 << 45)
-#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
-#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
-#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
-#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
-#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
-#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
-#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
-#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
-#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
-#define PTA_CLWB (HOST_WIDE_INT_1 << 55)
-#define PTA_MWAITX (HOST_WIDE_INT_1 << 56)
-#define PTA_CLZERO (HOST_WIDE_INT_1 << 57)
-#define PTA_NO_80387 (HOST_WIDE_INT_1 << 58)
-#define PTA_PKU (HOST_WIDE_INT_1 << 59)
-#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
-#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
-#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
-#define PTA_SGX (HOST_WIDE_INT_1 << 63)
-
-#define PTA_CORE2 \
- (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
- | PTA_CX16 | PTA_FXSR)
-#define PTA_NEHALEM \
- (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
-#define PTA_WESTMERE \
- (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
-#define PTA_SANDYBRIDGE \
- (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
-#define PTA_IVYBRIDGE \
- (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
-#define PTA_HASWELL \
- (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
- | PTA_FMA | PTA_MOVBE | PTA_HLE)
-#define PTA_BROADWELL \
- (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
-#define PTA_SKYLAKE \
- (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
-#define PTA_SKYLAKE_AVX512 \
- (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
- | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB)
-#define PTA_CANNONLAKE \
- (PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA)
-#define PTA_KNL \
- (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
-#define PTA_BONNELL \
- (PTA_CORE2 | PTA_MOVBE)
-#define PTA_SILVERMONT \
- (PTA_WESTMERE | PTA_MOVBE)
-#define PTA_KNM \
- (PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
+ bitmask m[BITSET_SIZE];
+ enum masks { PTA_3DNOW, PTA_3DNOW_A, PTA_64BIT, PTA_ABM, PTA_AES, PTA_AVX,
+ PTA_BMI, PTA_CX16, PTA_F16C, PTA_FMA, PTA_FMA4, PTA_FSGSBASE, PTA_LWP,
+ PTA_LZCNT, PTA_MMX, PTA_MOVBE, PTA_NO_SAHF, PTA_PCLMUL, PTA_POPCNT,
+ PTA_PREFETCH_SSE, PTA_RDRND, PTA_SSE, PTA_SSE2, PTA_SSE3, PTA_SSE4_1,
+ PTA_SSE4_2, PTA_SSE4A, PTA_SSSE3, PTA_TBM, PTA_XOP, PTA_AVX2, PTA_BMI2,
+ PTA_RTM, PTA_HLE, PTA_PRFCHW, PTA_RDSEED, PTA_ADX, PTA_FXSR, PTA_XSAVE,
+ PTA_XSAVEOPT, PTA_AVX512F, PTA_AVX512ER, PTA_AVX512PF, PTA_AVX512CD,
+ PTA_MPX, PTA_SHA, PTA_PREFETCHWT1, PTA_CLFLUSHOPT, PTA_XSAVEC, PTA_XSAVES,
+ PTA_AVX512DQ, PTA_AVX512BW, PTA_AVX512VL, PTA_AVX512IFMA, PTA_AVX512VBMI,
+ PTA_CLWB, PTA_MWAITX, PTA_CLZERO, PTA_NO_80387, PTA_PKU, PTA_AVX5124VNNIW,
+ PTA_AVX5124FMAPS, PTA_AVX512VPOPCNTDQ, PTA_SGX, PTA_GFNI, PTA_AVX512VBMI2,
+ PTA_VAES, PTA_AVX512VNNI, PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG};
+
+ for (i = PTA_3DNOW; i != PTA_AVX512BITALG; i++)
+ {
+ m[i] = get_bitmask (i);
+ }
+
+ const bitmask pta_core2 = m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_SSSE3] | m[PTA_CX16] | m[PTA_FXSR];
+ const bitmask pta_nehalem = pta_core2 | m[PTA_SSE4_1] | m[PTA_SSE4_2]
+ | m[PTA_POPCNT];
+ const bitmask pta_westmere = pta_nehalem | m[PTA_AES] | m[PTA_PCLMUL];
+ const bitmask pta_sandybridge = pta_westmere | m[PTA_AVX] | m[PTA_XSAVE]
+ | m[PTA_XSAVEOPT];
+ const bitmask pta_ivybridge = pta_sandybridge | m[PTA_FSGSBASE]
+ | m[PTA_RDRND] | m[PTA_F16C];
+ const bitmask pta_haswell = pta_ivybridge | m[PTA_AVX2] | m[PTA_BMI]
+ | m[PTA_BMI2] | m[PTA_LZCNT] | m[PTA_FMA] | m[PTA_MOVBE] | m[PTA_HLE];
+ const bitmask pta_broadwell = pta_haswell | m[PTA_ADX] | m[PTA_PRFCHW]
+ | m[PTA_RDSEED];
+ const bitmask pta_skylake = pta_broadwell | m[PTA_CLFLUSHOPT] | m[PTA_XSAVEC]
+ | m[PTA_XSAVES];
+ const bitmask pta_skylake_avx512 = pta_skylake | m[PTA_AVX512F]
+ | m[PTA_AVX512CD] | m[PTA_AVX512VL] | m[PTA_AVX512BW] | m[PTA_AVX512DQ]
+ | m[PTA_PKU] | m[PTA_CLWB];
+ const bitmask pta_cannonlake = pta_skylake_avx512 | m[PTA_AVX512VBMI]
+ | m[PTA_AVX512IFMA] | m[PTA_SHA];
+ const bitmask pta_icelake = pta_cannonlake | m[PTA_AVX512VPOPCNTDQ]
+ | m[PTA_GFNI] | m[PTA_AVX512VBMI2] | m[PTA_VAES] | m[PTA_AVX512VNNI]
+ | m[PTA_VPCLMULQDQ] | m[PTA_RDPID] | m[PTA_AVX512BITALG];
+ const bitmask pta_knl = pta_broadwell | m[PTA_AVX512PF] | m[PTA_AVX512ER]
+ | m[PTA_AVX512F] | m[PTA_AVX512CD];
+ const bitmask pta_bonnell = pta_core2 | m[PTA_MOVBE];
+ const bitmask pta_silvermont = pta_westmere | m[PTA_MOVBE];
+ const bitmask pta_knm = pta_knl | m[PTA_AVX5124VNNIW] | m[PTA_AVX5124FMAPS]
+ | m[PTA_AVX512VPOPCNTDQ];
/* if this reaches 64, need to widen struct pta flags below */
@@ -3470,7 +3438,7 @@ ix86_option_override_internal (bool main_args_p,
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
const enum attr_cpu schedule;
- const unsigned HOST_WIDE_INT flags;
+ const bitmask flags;
}
const processor_alias_table[] =
{
@@ -3478,180 +3446,189 @@ ix86_option_override_internal (bool main_args_p,
{"i486", PROCESSOR_I486, CPU_NONE, 0},
{"i586", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
{"pentium", PROCESSOR_PENTIUM, CPU_PENTIUM, 0},
- {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, PTA_NO_80387},
- {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, PTA_MMX},
- {"winchip-c6", PROCESSOR_I486, CPU_NONE, PTA_MMX},
- {"winchip2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"c3", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
- {"samuel-2", PROCESSOR_I486, CPU_NONE, PTA_MMX | PTA_3DNOW},
+ {"lakemont", PROCESSOR_LAKEMONT, CPU_PENTIUM, m[PTA_NO_80387]},
+ {"pentium-mmx", PROCESSOR_PENTIUM, CPU_PENTIUM, m[PTA_MMX]},
+ {"winchip-c6", PROCESSOR_I486, CPU_NONE, m[PTA_MMX]},
+ {"winchip2", PROCESSOR_I486, CPU_NONE, m[PTA_MMX] | m[PTA_3DNOW]},
+ {"c3", PROCESSOR_I486, CPU_NONE, m[PTA_MMX] | m[PTA_3DNOW]},
+ {"samuel-2", PROCESSOR_I486, CPU_NONE, m[PTA_MMX] | m[PTA_3DNOW]},
{"c3-2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_FXSR]},
{"nehemiah", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_FXSR]},
{"c7", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_FXSR]},
{"esther", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_FXSR]},
{"i686", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
{"pentiumpro", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, 0},
- {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO, PTA_MMX | PTA_FXSR},
+ {"pentium2", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
+ m[PTA_MMX] | m[PTA_FXSR]},
{"pentium3", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_FXSR]},
{"pentium3m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_FXSR]},
{"pentium-m", PROCESSOR_PENTIUMPRO, CPU_PENTIUMPRO,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_FXSR]},
{"pentium4", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX |PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ m[PTA_MMX] |m[PTA_SSE] | m[PTA_SSE2] | m[PTA_FXSR]},
{"pentium4m", PROCESSOR_PENTIUM4, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_FXSR]},
{"prescott", PROCESSOR_NOCONA, CPU_NONE,
- PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_FXSR]},
{"nocona", PROCESSOR_NOCONA, CPU_NONE,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_CX16 | PTA_NO_SAHF | PTA_FXSR},
- {"core2", PROCESSOR_CORE2, CPU_CORE2, PTA_CORE2},
- {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_NEHALEM},
- {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, PTA_WESTMERE},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_CX16] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
+ {"core2", PROCESSOR_CORE2, CPU_CORE2, pta_core2},
+ {"nehalem", PROCESSOR_NEHALEM, CPU_NEHALEM, pta_nehalem},
+ {"corei7", PROCESSOR_NEHALEM, CPU_NEHALEM, pta_nehalem},
+ {"westmere", PROCESSOR_NEHALEM, CPU_NEHALEM, pta_westmere},
{"sandybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ pta_sandybridge},
{"corei7-avx", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_SANDYBRIDGE},
+ pta_sandybridge},
{"ivybridge", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
+ pta_ivybridge},
{"core-avx-i", PROCESSOR_SANDYBRIDGE, CPU_NEHALEM,
- PTA_IVYBRIDGE},
- {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, PTA_HASWELL},
- {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, PTA_BROADWELL},
- {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE},
+ pta_ivybridge},
+ {"haswell", PROCESSOR_HASWELL, CPU_HASWELL, pta_haswell},
+ {"core-avx2", PROCESSOR_HASWELL, CPU_HASWELL, pta_haswell},
+ {"broadwell", PROCESSOR_HASWELL, CPU_HASWELL, pta_broadwell},
+ {"skylake", PROCESSOR_HASWELL, CPU_HASWELL, pta_skylake},
{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
- PTA_SKYLAKE_AVX512},
- {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE},
- {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
- {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"slm", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
- {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL},
- {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM},
- {"intel", PROCESSOR_INTEL, CPU_SLM, PTA_NEHALEM},
+ pta_skylake_avx512},
+ {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, pta_cannonlake},
+ {"icelake", PROCESSOR_HASWELL, CPU_HASWELL, pta_icelake},
+ {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, pta_bonnell},
+ {"atom", PROCESSOR_BONNELL, CPU_ATOM, pta_bonnell},
+ {"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, pta_silvermont},
+ {"slm", PROCESSOR_SILVERMONT, CPU_SLM, pta_silvermont},
+ {"knl", PROCESSOR_KNL, CPU_SLM, pta_knl},
+ {"knm", PROCESSOR_KNM, CPU_SLM, pta_knm},
+ {"intel", PROCESSOR_INTEL, CPU_SLM, pta_nehalem},
{"geode", PROCESSOR_GEODE, CPU_GEODE,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
- {"k6", PROCESSOR_K6, CPU_K6, PTA_MMX},
- {"k6-2", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
- {"k6-3", PROCESSOR_K6, CPU_K6, PTA_MMX | PTA_3DNOW},
+ m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_PREFETCH_SSE]},
+ {"k6", PROCESSOR_K6, CPU_K6, m[PTA_MMX]},
+ {"k6-2", PROCESSOR_K6, CPU_K6, m[PTA_MMX] | m[PTA_3DNOW]},
+ {"k6-3", PROCESSOR_K6, CPU_K6, m[PTA_MMX] | m[PTA_3DNOW]},
{"athlon", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_PREFETCH_SSE]},
{"athlon-tbird", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_PREFETCH_SSE},
+ m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_PREFETCH_SSE]},
{"athlon-4", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE] | m[PTA_FXSR]},
{"athlon-xp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE] | m[PTA_FXSR]},
{"athlon-mp", PROCESSOR_ATHLON, CPU_ATHLON,
- PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_FXSR},
+ m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE] | m[PTA_FXSR]},
{"x86-64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_NO_SAHF]
+ | m[PTA_FXSR]},
{"eden-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_FXSR]},
{"nano", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_FXSR]},
{"nano-1000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_FXSR]},
{"nano-2000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_FXSR]},
{"nano-3000", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_SSE4_1] | m[PTA_FXSR]},
{"nano-x2", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_SSE4_1] | m[PTA_FXSR]},
{"eden-x4", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_SSE4_1] | m[PTA_FXSR]},
{"nano-x4", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4_1 | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_SSE4_1] | m[PTA_FXSR]},
{"k8", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"k8-sse3", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"opteron", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"opteron-sse3", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"athlon64", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"athlon64-sse3", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_SSE3 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"athlon-fx", PROCESSOR_K8, CPU_K8,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE
- | PTA_SSE2 | PTA_NO_SAHF | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_NO_SAHF] | m[PTA_FXSR]},
{"amdfam10", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM]
+ | m[PTA_PRFCHW] | m[PTA_FXSR]},
{"barcelona", PROCESSOR_AMDFAM10, CPU_AMDFAM10,
- PTA_64BIT | PTA_MMX | PTA_3DNOW | PTA_3DNOW_A | PTA_SSE | PTA_SSE2
- | PTA_SSE3 | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_PRFCHW | PTA_FXSR},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_3DNOW] | m[PTA_3DNOW_A] | m[PTA_SSE]
+ | m[PTA_SSE2] | m[PTA_SSE3] | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM]
+ | m[PTA_PRFCHW] | m[PTA_FXSR]},
{"bdver1", PROCESSOR_BDVER1, CPU_BDVER1,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM] | m[PTA_SSSE3]
+ | m[PTA_SSE4_1] | m[PTA_SSE4_2] | m[PTA_AES] | m[PTA_PCLMUL]
+ | m[PTA_AVX] | m[PTA_FMA4] | m[PTA_XOP] | m[PTA_LWP] | m[PTA_PRFCHW]
+ | m[PTA_FXSR] | m[PTA_XSAVE]},
{"bdver2", PROCESSOR_BDVER2, CPU_BDVER2,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM] | m[PTA_SSSE3]
+ | m[PTA_SSE4_1] | m[PTA_SSE4_2] | m[PTA_AES] | m[PTA_PCLMUL]
+ | m[PTA_AVX] | m[PTA_FMA4] | m[PTA_XOP] | m[PTA_LWP] | m[PTA_BMI]
+ | m[PTA_TBM] | m[PTA_F16C] | m[PTA_FMA] | m[PTA_PRFCHW] | m[PTA_FXSR]
+ | m[PTA_XSAVE]},
{"bdver3", PROCESSOR_BDVER3, CPU_BDVER3,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_FMA4
- | PTA_XOP | PTA_LWP | PTA_BMI | PTA_TBM | PTA_F16C
- | PTA_FMA | PTA_PRFCHW | PTA_FXSR | PTA_XSAVE
- | PTA_XSAVEOPT | PTA_FSGSBASE},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM] | m[PTA_SSSE3]
+ | m[PTA_SSE4_1] | m[PTA_SSE4_2] | m[PTA_AES] | m[PTA_PCLMUL]
+ | m[PTA_AVX] | m[PTA_FMA4] | m[PTA_XOP] | m[PTA_LWP] | m[PTA_BMI]
+ | m[PTA_TBM] | m[PTA_F16C] | m[PTA_FMA] | m[PTA_PRFCHW] | m[PTA_FXSR]
+ | m[PTA_XSAVE] | m[PTA_XSAVEOPT] | m[PTA_FSGSBASE]},
{"bdver4", PROCESSOR_BDVER4, CPU_BDVER4,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
- | PTA_FMA4 | PTA_XOP | PTA_LWP | PTA_BMI | PTA_BMI2
- | PTA_TBM | PTA_F16C | PTA_FMA | PTA_PRFCHW | PTA_FXSR
- | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE | PTA_RDRND
- | PTA_MOVBE | PTA_MWAITX},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM] | m[PTA_SSSE3]
+ | m[PTA_SSE4_1] | m[PTA_SSE4_2] | m[PTA_AES] | m[PTA_PCLMUL]
+ | m[PTA_AVX] | m[PTA_AVX2] | m[PTA_FMA4] | m[PTA_XOP] | m[PTA_LWP]
+ | m[PTA_BMI] | m[PTA_BMI2] | m[PTA_TBM] | m[PTA_F16C] | m[PTA_FMA]
+ | m[PTA_PRFCHW] | m[PTA_FXSR] | m[PTA_XSAVE] | m[PTA_XSAVEOPT]
+ | m[PTA_FSGSBASE] | m[PTA_RDRND] | m[PTA_MOVBE] | m[PTA_MWAITX]},
{"znver1", PROCESSOR_ZNVER1, CPU_ZNVER1,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSE4A | PTA_CX16 | PTA_ABM | PTA_SSSE3 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX | PTA_AVX2
- | PTA_BMI | PTA_BMI2 | PTA_F16C | PTA_FMA | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT | PTA_FSGSBASE
- | PTA_RDRND | PTA_MOVBE | PTA_MWAITX | PTA_ADX | PTA_RDSEED
- | PTA_CLZERO | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES
- | PTA_SHA | PTA_LZCNT | PTA_POPCNT},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSE4A] | m[PTA_CX16] | m[PTA_ABM] | m[PTA_SSSE3]
+ | m[PTA_SSE4_1] | m[PTA_SSE4_2] | m[PTA_AES] | m[PTA_PCLMUL]
+ | m[PTA_AVX] | m[PTA_AVX2] | m[PTA_BMI] | m[PTA_BMI2] | m[PTA_F16C]
+ | m[PTA_FMA] | m[PTA_PRFCHW] | m[PTA_FXSR] | m[PTA_XSAVE]
+ | m[PTA_XSAVEOPT] | m[PTA_FSGSBASE] | m[PTA_RDRND] | m[PTA_MOVBE]
+ | m[PTA_MWAITX] | m[PTA_ADX] | m[PTA_RDSEED] | m[PTA_CLZERO]
+ | m[PTA_CLFLUSHOPT] | m[PTA_XSAVEC] | m[PTA_XSAVES] | m[PTA_SHA]
+ | m[PTA_LZCNT] | m[PTA_POPCNT]},
{"btver1", PROCESSOR_BTVER1, CPU_GENERIC,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_SSE4A] |m[PTA_ABM] | m[PTA_CX16] | m[PTA_PRFCHW]
+ | m[PTA_FXSR] | m[PTA_XSAVE]},
{"btver2", PROCESSOR_BTVER2, CPU_BTVER2,
- PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3
- | PTA_SSSE3 | PTA_SSE4A |PTA_ABM | PTA_CX16 | PTA_SSE4_1
- | PTA_SSE4_2 | PTA_AES | PTA_PCLMUL | PTA_AVX
- | PTA_BMI | PTA_F16C | PTA_MOVBE | PTA_PRFCHW
- | PTA_FXSR | PTA_XSAVE | PTA_XSAVEOPT},
+ m[PTA_64BIT] | m[PTA_MMX] | m[PTA_SSE] | m[PTA_SSE2] | m[PTA_SSE3]
+ | m[PTA_SSSE3] | m[PTA_SSE4A] |m[PTA_ABM] | m[PTA_CX16] | m[PTA_SSE4_1]
+ | m[PTA_SSE4_2] | m[PTA_AES] | m[PTA_PCLMUL] | m[PTA_AVX]
+ | m[PTA_BMI] | m[PTA_F16C] | m[PTA_MOVBE] | m[PTA_PRFCHW]
+ | m[PTA_FXSR] | m[PTA_XSAVE] | m[PTA_XSAVEOPT]},
{"generic", PROCESSOR_GENERIC, CPU_GENERIC,
- PTA_64BIT
- | PTA_HLE /* flags are only used for -march switch. */ },
+ m[PTA_64BIT]
+ | m[PTA_HLE] /* flags are only used for -march switch. */ },
};
/* -mrecip options. */
@@ -3920,7 +3897,7 @@ ix86_option_override_internal (bool main_args_p,
}
if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && !(processor_alias_table[i].flags & PTA_64BIT))
+ && !(processor_alias_table[i].flags[PTA_64BIT]))
{
error ("CPU you selected does not support x86-64 "
"instruction set");
@@ -3932,192 +3909,204 @@ ix86_option_override_internal (bool main_args_p,
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
+ if (processor_alias_table[i].flags[PTA_MMX]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
+ if (processor_alias_table[i].flags[PTA_3DNOW]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
+ if (processor_alias_table[i].flags[PTA_3DNOW_A]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
+ if (processor_alias_table[i].flags[PTA_SSE]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
+ if (processor_alias_table[i].flags[PTA_SSE2]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
- if (processor_alias_table[i].flags & PTA_SSE3
+ if (processor_alias_table[i].flags[PTA_SSE3]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
- if (processor_alias_table[i].flags & PTA_SSSE3
+ if (processor_alias_table[i].flags[PTA_SSSE3]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
- if (processor_alias_table[i].flags & PTA_SSE4_1
+ if (processor_alias_table[i].flags[PTA_SSE4_1]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
- if (processor_alias_table[i].flags & PTA_SSE4_2
+ if (processor_alias_table[i].flags[PTA_SSE4_2]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
- if (processor_alias_table[i].flags & PTA_AVX
+ if (processor_alias_table[i].flags[PTA_AVX]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX;
- if (processor_alias_table[i].flags & PTA_AVX2
+ if (processor_alias_table[i].flags[PTA_AVX2]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
- if (processor_alias_table[i].flags & PTA_FMA
+ if (processor_alias_table[i].flags[PTA_FMA]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA;
- if (processor_alias_table[i].flags & PTA_SSE4A
+ if (processor_alias_table[i].flags[PTA_SSE4A]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_FMA4
+ if (processor_alias_table[i].flags[PTA_FMA4]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
- if (processor_alias_table[i].flags & PTA_XOP
+ if (processor_alias_table[i].flags[PTA_XOP]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP;
- if (processor_alias_table[i].flags & PTA_LWP
+ if (processor_alias_table[i].flags[PTA_LWP]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP;
- if (processor_alias_table[i].flags & PTA_ABM
+ if (processor_alias_table[i].flags[PTA_ABM]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM;
- if (processor_alias_table[i].flags & PTA_BMI
+ if (processor_alias_table[i].flags[PTA_BMI]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI;
- if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
+ if ((processor_alias_table[i].flags
+ & (m[PTA_LZCNT] | m[PTA_ABM])).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
- if (processor_alias_table[i].flags & PTA_TBM
+ if (processor_alias_table[i].flags[PTA_TBM]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM;
- if (processor_alias_table[i].flags & PTA_BMI2
+ if (processor_alias_table[i].flags[PTA_BMI2]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
- if (processor_alias_table[i].flags & PTA_CX16
+ if (processor_alias_table[i].flags[PTA_CX16]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CX16))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CX16;
- if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
+ if ((processor_alias_table[i].flags
+ & (m[PTA_POPCNT] | m[PTA_ABM])).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
if (!(TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && (processor_alias_table[i].flags & PTA_NO_SAHF))
+ && processor_alias_table[i].flags[PTA_NO_SAHF])
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
- if (processor_alias_table[i].flags & PTA_MOVBE
+ if (processor_alias_table[i].flags[PTA_MOVBE]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MOVBE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MOVBE;
- if (processor_alias_table[i].flags & PTA_AES
+ if (processor_alias_table[i].flags[PTA_AES]
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
ix86_isa_flags |= OPTION_MASK_ISA_AES;
- if (processor_alias_table[i].flags & PTA_SHA
+ if (processor_alias_table[i].flags[PTA_SHA]
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SHA))
ix86_isa_flags |= OPTION_MASK_ISA_SHA;
- if (processor_alias_table[i].flags & PTA_PCLMUL
+ if (processor_alias_table[i].flags[PTA_PCLMUL]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
- if (processor_alias_table[i].flags & PTA_FSGSBASE
+ if (processor_alias_table[i].flags[PTA_FSGSBASE]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
- if (processor_alias_table[i].flags & PTA_RDRND
+ if (processor_alias_table[i].flags[PTA_RDRND]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
- if (processor_alias_table[i].flags & PTA_F16C
+ if (processor_alias_table[i].flags[PTA_F16C]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C;
- if (processor_alias_table[i].flags & PTA_RTM
+ if (processor_alias_table[i].flags[PTA_RTM]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM;
- if (processor_alias_table[i].flags & PTA_HLE
+ if (processor_alias_table[i].flags[PTA_HLE]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_HLE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_HLE;
- if (processor_alias_table[i].flags & PTA_PRFCHW
+ if (processor_alias_table[i].flags[PTA_PRFCHW]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
- if (processor_alias_table[i].flags & PTA_RDSEED
+ if (processor_alias_table[i].flags[PTA_RDSEED]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
- if (processor_alias_table[i].flags & PTA_ADX
+ if (processor_alias_table[i].flags[PTA_ADX]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ADX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX;
- if (processor_alias_table[i].flags & PTA_FXSR
+ if (processor_alias_table[i].flags[PTA_FXSR]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FXSR))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR;
- if (processor_alias_table[i].flags & PTA_XSAVE
+ if (processor_alias_table[i].flags[PTA_XSAVE]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE;
- if (processor_alias_table[i].flags & PTA_XSAVEOPT
+ if (processor_alias_table[i].flags[PTA_XSAVEOPT]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
- if (processor_alias_table[i].flags & PTA_AVX512F
+ if (processor_alias_table[i].flags[PTA_AVX512F]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
- if (processor_alias_table[i].flags & PTA_AVX512ER
+ if (processor_alias_table[i].flags[PTA_AVX512ER]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
- if (processor_alias_table[i].flags & PTA_AVX512PF
+ if (processor_alias_table[i].flags[PTA_AVX512PF]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
- if (processor_alias_table[i].flags & PTA_AVX512CD
+ if (processor_alias_table[i].flags[PTA_AVX512CD]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
- if (processor_alias_table[i].flags & PTA_PREFETCHWT1
+ if (processor_alias_table[i].flags[PTA_PREFETCHWT1]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
- if (processor_alias_table[i].flags & PTA_CLWB
+ if (processor_alias_table[i].flags[PTA_CLWB]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
- if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
+ if (processor_alias_table[i].flags[PTA_CLFLUSHOPT]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
- if (processor_alias_table[i].flags & PTA_CLZERO
+ if (processor_alias_table[i].flags[PTA_CLZERO]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLZERO))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLZERO;
- if (processor_alias_table[i].flags & PTA_XSAVEC
+ if (processor_alias_table[i].flags[PTA_XSAVEC]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC;
- if (processor_alias_table[i].flags & PTA_XSAVES
+ if (processor_alias_table[i].flags[PTA_XSAVES]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
- if (processor_alias_table[i].flags & PTA_AVX512DQ
+ if (processor_alias_table[i].flags[PTA_AVX512DQ]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
- if (processor_alias_table[i].flags & PTA_AVX512BW
+ if (processor_alias_table[i].flags[PTA_AVX512BW]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
- if (processor_alias_table[i].flags & PTA_AVX512VL
+ if (processor_alias_table[i].flags[PTA_AVX512VL]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
- if (processor_alias_table[i].flags & PTA_MPX
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
+ if (processor_alias_table[i].flags[PTA_MPX]
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX;
- if (processor_alias_table[i].flags & PTA_AVX512VBMI
+ if (processor_alias_table[i].flags[PTA_AVX512VBMI]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI;
- if (processor_alias_table[i].flags & PTA_AVX512IFMA
+ if (processor_alias_table[i].flags[PTA_AVX512IFMA]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
- if (processor_alias_table[i].flags & PTA_AVX5124VNNIW
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX5124VNNIW))
+ if (processor_alias_table[i].flags[PTA_AVX5124VNNIW]
+ && !(opts->x_ix86_isa_flags2_explicit
+ & OPTION_MASK_ISA_AVX5124VNNIW))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW;
- if (processor_alias_table[i].flags & PTA_AVX5124FMAPS
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX5124FMAPS))
+ if (processor_alias_table[i].flags[PTA_AVX5124FMAPS]
+ && !(opts->x_ix86_isa_flags2_explicit
+ & OPTION_MASK_ISA_AVX5124FMAPS))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS;
- if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
- && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_AVX512VPOPCNTDQ))
+ if (processor_alias_table[i].flags[PTA_AVX512VPOPCNTDQ]
+ && !(opts->x_ix86_isa_flags2_explicit
+ & OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
- if (processor_alias_table[i].flags & PTA_SGX
+ if (processor_alias_table[i].flags[PTA_SGX]
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
-
- if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
+ if (processor_alias_table[i].flags[PTA_RDPID]
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
+ if (processor_alias_table[i].flags[PTA_GFNI]
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_GFNI))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI;
+
+ if ((processor_alias_table[i].flags
+ & (m[PTA_PREFETCH_SSE] | m[PTA_SSE])).any ())
x86_prefetch_sse = true;
- if (processor_alias_table[i].flags & PTA_MWAITX
+ if (processor_alias_table[i].flags[PTA_MWAITX]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MWAITX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MWAITX;
- if (processor_alias_table[i].flags & PTA_PKU
+ if (processor_alias_table[i].flags[PTA_PKU]
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
@@ -4126,7 +4115,7 @@ ix86_option_override_internal (bool main_args_p,
if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
&& !(opts_set->x_target_flags & MASK_80387))
{
- if (processor_alias_table[i].flags & PTA_NO_80387)
+ if (processor_alias_table[i].flags[PTA_NO_80387])
opts->x_target_flags &= ~MASK_80387;
else
opts->x_target_flags |= MASK_80387;
@@ -4152,7 +4141,7 @@ ix86_option_override_internal (bool main_args_p,
if (strcmp (processor_alias_table[i].name, "generic")
&& strcmp (processor_alias_table[i].name, "intel")
&& (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT)))
+ || processor_alias_table[i].flags[PTA_64BIT]))
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -4185,7 +4174,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_tune = processor_alias_table[i].processor;
if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
{
- if (!(processor_alias_table[i].flags & PTA_64BIT))
+ if (!processor_alias_table[i].flags[PTA_64BIT])
{
if (ix86_tune_defaulted)
{
@@ -4207,8 +4196,8 @@ ix86_option_override_internal (bool main_args_p,
-mtune (rather than -march) points us to a processor that has them.
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
- if (TARGET_CMOV
- && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
+ if (TARGET_CMOV && (processor_alias_table[i].flags
+ & (m[PTA_PREFETCH_SSE] | m[PTA_SSE])).any ())
x86_prefetch_sse = true;
break;
}
@@ -4223,7 +4212,7 @@ ix86_option_override_internal (bool main_args_p,
auto_vec <const char *> candidates;
for (i = 0; i < pta_size; i++)
if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT))
+ || processor_alias_table[i].flags[PTA_64BIT])
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -31268,7 +31257,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
break;
case PROCESSOR_HASWELL:
case PROCESSOR_SKYLAKE_AVX512:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI)
+ if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI)
+ arg_str = "icelake";
+ else if (new_target->x_ix86_isa_flags
+ & OPTION_MASK_ISA_AVX512VBMI)
arg_str = "cannonlake";
else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
arg_str = "skylake-avx512";
@@ -31993,7 +31985,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_INTEL_COREI7_BROADWELL,
M_INTEL_COREI7_SKYLAKE,
M_INTEL_COREI7_SKYLAKE_AVX512,
- M_INTEL_COREI7_CANNONLAKE
+ M_INTEL_COREI7_CANNONLAKE,
+ M_INTEL_COREI7_ICELAKE
};
static struct _arch_names_table
@@ -32018,6 +32011,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
{"skylake", M_INTEL_COREI7_SKYLAKE},
{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
+ {"icelake", M_INTEL_COREI7_ICELAKE},
{"bonnell", M_INTEL_BONNELL},
{"silvermont", M_INTEL_SILVERMONT},
{"knl", M_INTEL_KNL},
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 01fd6ce..e285cab 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -379,6 +379,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
+#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE)
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2261,6 +2262,7 @@ enum processor_type
PROCESSOR_KNM,
PROCESSOR_SKYLAKE_AVX512,
PROCESSOR_CANNONLAKE,
+ PROCESSOR_ICELAKE,
PROCESSOR_INTEL,
PROCESSOR_GEODE,
PROCESSOR_K6,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 001bbea..5c7e272 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25423,6 +25423,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
+@item Icelake
+Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
+AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C
index 1e1ae3d..8fbdb47 100644
--- a/gcc/testsuite/g++.dg/ext/mv16.C
+++ b/gcc/testsuite/g++.dg/ext/mv16.C
@@ -60,6 +60,10 @@ int __attribute__ ((target("arch=cannonlake"))) foo () {
return 16;
}
+int __attribute__ ((target("arch=icelake"))) foo () {
+ return 17;
+}
+
int main ()
{
int val = foo ();
@@ -82,6 +86,8 @@ int main ()
assert (val == 15);
else if (__builtin_cpu_is ("cannonlake"))
assert (val == 16);
+ else if (__builtin_cpu_is ("icelake"))
+ assert (val == 17);
else
assert (val == 0);
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index ed0748b..837cdc3 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -145,6 +145,7 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
+extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake")));
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index 4b2a3c5..67f17ef 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -70,6 +70,7 @@ enum processor_subtypes
INTEL_COREI7_SKYLAKE,
INTEL_COREI7_SKYLAKE_AVX512,
INTEL_COREI7_CANNONLAKE,
+ INTEL_COREI7_ICELAKE,
CPU_SUBTYPE_MAX
};
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2017-12-19 12:34 ` Koval, Julia
@ 2017-12-19 13:08 ` Richard Biener
2017-12-19 13:49 ` Jakub Jelinek
1 sibling, 0 replies; 21+ messages in thread
From: Richard Biener @ 2017-12-19 13:08 UTC (permalink / raw)
To: Koval, Julia; +Cc: Uros Bizjak, GCC Patches, Kirill Yukhin
On Tue, Dec 19, 2017 at 1:34 PM, Koval, Julia <julia.koval@intel.com> wrote:
>>> Maybe [] operator could be used instead of a dynamic handling here.
> I had another solution in mind, with enums, which then addresses elements using its index, please look the patch attached.
>
>
>>>> The natural GCC data structure is a sbitmap ... I'd rather not use <bitset> given we have a GCC variant.
>
> Sorry for maybe stupid question, but how do we set
>
> bitmask pta_core2 = pta_64bit | pta_mmx | pta_sse | pta_sse2
> | pta_sse3 | pta_ssse3 | pta_cx16 | pta_fxsr;
>
> in sbitmap, except chain of bitmap_and_or with third bitmap set to ones(which doesn't look fast)?
> Sorry, I think there should be some obvious solution, but can't find a proper function.
Chain of bitmap_set_bit () I'd say. Or are the pta_64bit and friends
bitsets themselves?
Richard.
> Thanks,
> Julia
>
>> -----Original Message-----
>> From: Richard Biener [mailto:richard.guenther@gmail.com]
>> Sent: Tuesday, December 19, 2017 12:56 PM
>> To: Uros Bizjak <ubizjak@gmail.com>
>> Cc: Koval, Julia <julia.koval@intel.com>; GCC Patches <gcc-
>> patches@gcc.gnu.org>; Kirill Yukhin <kirill.yukhin@gmail.com>
>> Subject: Re: [patch][x86] -march=icelake
>>
>> On Tue, Dec 19, 2017 at 9:29 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
>> > On Mon, Dec 18, 2017 at 2:42 PM, Koval, Julia <julia.koval@intel.com> wrote:
>> >> Hi, I tried to replace 2 flags variable with c++ bitset(in patch attached). What
>> do you think?
>> >
>> > Hm, I'm not a c++ person, but I wonder about overhead and performance
>> > impact of this change. Maybe [] operator could be used instead of a
>> > dynamic handling here. Please discuss with a c++ person to find out
>> > the most appropriate approach.
>>
>> The natural GCC data structure is a sbitmap ... I'd rather not use <bitset>
>> given we have a GCC variant.
>>
>> >>> Please add these options first.
>> >> 2 options left(they are under Kirill's review currently), I'll add PTAs for them to
>> the patch, as soon as they will be commited.
>> >
>> > Actually, let's wait for these 2 options to be reviewed and committed
>> > first, and after that introduce -march=icelake handling.
>> >
>> > Uros.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2017-12-19 12:34 ` Koval, Julia
2017-12-19 13:08 ` Richard Biener
@ 2017-12-19 13:49 ` Jakub Jelinek
2018-01-22 11:46 ` Koval, Julia
1 sibling, 1 reply; 21+ messages in thread
From: Jakub Jelinek @ 2017-12-19 13:49 UTC (permalink / raw)
To: Koval, Julia; +Cc: Richard Biener, Uros Bizjak, GCC Patches, Kirill Yukhin
On Tue, Dec 19, 2017 at 12:34:03PM +0000, Koval, Julia wrote:
> >> Maybe [] operator could be used instead of a dynamic handling here.
> I had another solution in mind, with enums, which then addresses elements using its index, please look the patch attached.
You can also have a look at the omp_clause_mask class in c-common.h, that is
also something that has been added to handle the case where we run out of
64-bits for a particular bitmask, wanted to keep using pretty much the same
interfaces and be able to handle it fast. Using 2 enums for the two halves
and treating it accordingly is also an option.
I agree sbitmap is too heavy for this.
Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2017-12-19 13:49 ` Jakub Jelinek
@ 2018-01-22 11:46 ` Koval, Julia
2018-01-22 12:12 ` Jakub Jelinek
0 siblings, 1 reply; 21+ messages in thread
From: Koval, Julia @ 2018-01-22 11:46 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Richard Biener, Uros Bizjak, GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 1325 bytes --]
Hi,
I tried omp_clause_mask and it looks ok. But it lacks check if there is any bit or none. With addition of it(as proposed or in some other way it should work. What do you think about this approach(patch attached)?
Thanks,
Julia
> -----Original Message-----
> From: Jakub Jelinek [mailto:jakub@redhat.com]
> Sent: Tuesday, December 19, 2017 2:50 PM
> To: Koval, Julia <julia.koval@intel.com>
> Cc: Richard Biener <richard.guenther@gmail.com>; Uros Bizjak
> <ubizjak@gmail.com>; GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> <kirill.yukhin@gmail.com>
> Subject: Re: [patch][x86] -march=icelake
>
> On Tue, Dec 19, 2017 at 12:34:03PM +0000, Koval, Julia wrote:
> > >> Maybe [] operator could be used instead of a dynamic handling here.
> > I had another solution in mind, with enums, which then addresses elements
> using its index, please look the patch attached.
>
> You can also have a look at the omp_clause_mask class in c-common.h, that is
> also something that has been added to handle the case where we run out of
> 64-bits for a particular bitmask, wanted to keep using pretty much the same
> interfaces and be able to handle it fast. Using 2 enums for the two halves
> and treating it accordingly is also an option.
>
> I agree sbitmap is too heavy for this.
>
> Jakub
[-- Attachment #2: 0001-test.patch --]
[-- Type: application/octet-stream, Size: 28014 bytes --]
From 9074b23a07b5f9949068ed4e7727825994ab0d86 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Thu, 18 Jan 2018 10:00:54 +0300
Subject: [PATCH] test
---
gcc/c-family/c-common.h | 8 ++
gcc/config/i386/i386.c | 329 ++++++++++++++++++++++++------------------------
2 files changed, 170 insertions(+), 167 deletions(-)
diff --git a/gcc/c-family/c-common.h b/gcc/c-family/c-common.h
index d090881..29224b1 100644
--- a/gcc/c-family/c-common.h
+++ b/gcc/c-family/c-common.h
@@ -1125,11 +1125,13 @@ struct omp_clause_mask
inline omp_clause_mask operator << (int);
inline bool operator == (omp_clause_mask) const;
inline bool operator != (omp_clause_mask) const;
+ inline bool any () const;
uint64_t low, high;
};
inline
omp_clause_mask::omp_clause_mask ()
+: low (0), high (0)
{
}
@@ -1232,6 +1234,12 @@ omp_clause_mask::operator != (omp_clause_mask b) const
return low != b.low || high != b.high;
}
+inline bool
+omp_clause_mask::any () const
+{
+ return low || high;
+}
+
#define OMP_CLAUSE_MASK_1 omp_clause_mask (1)
enum c_omp_clause_split
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ea9c462..29c372c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -38,6 +38,7 @@ along with GCC; see the file COPYING3. If not see
#include "emit-rtl.h"
#include "recog.h"
#include "cgraph.h"
+#include "c-family/c-common.h"
#include "diagnostic.h"
#include "cfgbuild.h"
#include "alias.h"
@@ -3381,111 +3382,103 @@ ix86_option_override_internal (bool main_args_p,
unsigned int ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
-#define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
-#define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
-#define PTA_64BIT (HOST_WIDE_INT_1 << 2)
-#define PTA_ABM (HOST_WIDE_INT_1 << 3)
-#define PTA_AES (HOST_WIDE_INT_1 << 4)
-#define PTA_AVX (HOST_WIDE_INT_1 << 5)
-#define PTA_BMI (HOST_WIDE_INT_1 << 6)
-#define PTA_CX16 (HOST_WIDE_INT_1 << 7)
-#define PTA_F16C (HOST_WIDE_INT_1 << 8)
-#define PTA_FMA (HOST_WIDE_INT_1 << 9)
-#define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
-#define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
-#define PTA_LWP (HOST_WIDE_INT_1 << 12)
-#define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
-#define PTA_MMX (HOST_WIDE_INT_1 << 14)
-#define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
-#define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
-#define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
-#define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
-#define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
-#define PTA_RDRND (HOST_WIDE_INT_1 << 20)
-#define PTA_SSE (HOST_WIDE_INT_1 << 21)
-#define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
-#define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
-#define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
-#define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
-#define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
-#define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
-#define PTA_TBM (HOST_WIDE_INT_1 << 28)
-#define PTA_XOP (HOST_WIDE_INT_1 << 29)
-#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
-#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
-#define PTA_RTM (HOST_WIDE_INT_1 << 32)
-#define PTA_HLE (HOST_WIDE_INT_1 << 33)
-#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
-#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
-#define PTA_ADX (HOST_WIDE_INT_1 << 36)
-#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
-#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
-#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
-#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
-#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
-#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
-#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
-#define PTA_MPX (HOST_WIDE_INT_1 << 44)
-#define PTA_SHA (HOST_WIDE_INT_1 << 45)
-#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
-#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
-#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
-#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
-#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
-#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
-#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
-#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
-#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
-#define PTA_CLWB (HOST_WIDE_INT_1 << 55)
-#define PTA_MWAITX (HOST_WIDE_INT_1 << 56)
-#define PTA_CLZERO (HOST_WIDE_INT_1 << 57)
-#define PTA_NO_80387 (HOST_WIDE_INT_1 << 58)
-#define PTA_PKU (HOST_WIDE_INT_1 << 59)
-#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
-#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
-#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
-#define PTA_SGX (HOST_WIDE_INT_1 << 63)
-
-#define PTA_CORE2 \
- (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
- | PTA_CX16 | PTA_FXSR)
-#define PTA_NEHALEM \
- (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
-#define PTA_WESTMERE \
- (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
-#define PTA_SANDYBRIDGE \
- (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
-#define PTA_IVYBRIDGE \
- (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
-#define PTA_HASWELL \
- (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
- | PTA_FMA | PTA_MOVBE | PTA_HLE)
-#define PTA_BROADWELL \
- (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
-#define PTA_SKYLAKE \
- (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
-#define PTA_SKYLAKE_AVX512 \
- (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
- | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB)
-#define PTA_CANNONLAKE \
- (PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA)
-#define PTA_KNL \
- (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
-#define PTA_BONNELL \
- (PTA_CORE2 | PTA_MOVBE)
-#define PTA_SILVERMONT \
- (PTA_WESTMERE | PTA_MOVBE)
-#define PTA_KNM \
- (PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
-
-/* if this reaches 64, need to widen struct pta flags below */
+ omp_clause_mask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+ omp_clause_mask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+ omp_clause_mask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+ omp_clause_mask PTA_ABM (HOST_WIDE_INT_1U << 3);
+ omp_clause_mask PTA_AES (HOST_WIDE_INT_1U << 4);
+ omp_clause_mask PTA_AVX (HOST_WIDE_INT_1U << 5);
+ omp_clause_mask PTA_BMI (HOST_WIDE_INT_1U << 6);
+ omp_clause_mask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+ omp_clause_mask PTA_F16C (HOST_WIDE_INT_1U << 8);
+ omp_clause_mask PTA_FMA (HOST_WIDE_INT_1U << 9);
+ omp_clause_mask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+ omp_clause_mask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+ omp_clause_mask PTA_LWP (HOST_WIDE_INT_1U << 12);
+ omp_clause_mask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+ omp_clause_mask PTA_MMX (HOST_WIDE_INT_1U << 14);
+ omp_clause_mask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+ omp_clause_mask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+ omp_clause_mask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+ omp_clause_mask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+ omp_clause_mask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+ omp_clause_mask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+ omp_clause_mask PTA_SSE (HOST_WIDE_INT_1U << 21);
+ omp_clause_mask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+ omp_clause_mask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+ omp_clause_mask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+ omp_clause_mask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+ omp_clause_mask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+ omp_clause_mask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+ omp_clause_mask PTA_TBM (HOST_WIDE_INT_1U << 28);
+ omp_clause_mask PTA_XOP (HOST_WIDE_INT_1U << 29);
+ omp_clause_mask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+ omp_clause_mask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+ omp_clause_mask PTA_RTM (HOST_WIDE_INT_1U << 32);
+ omp_clause_mask PTA_HLE (HOST_WIDE_INT_1U << 33);
+ omp_clause_mask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+ omp_clause_mask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+ omp_clause_mask PTA_ADX (HOST_WIDE_INT_1U << 36);
+ omp_clause_mask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+ omp_clause_mask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+ omp_clause_mask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+ omp_clause_mask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+ omp_clause_mask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+ omp_clause_mask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+ omp_clause_mask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+ omp_clause_mask PTA_MPX (HOST_WIDE_INT_1U << 44);
+ omp_clause_mask PTA_SHA (HOST_WIDE_INT_1U << 45);
+ omp_clause_mask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+ omp_clause_mask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+ omp_clause_mask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+ omp_clause_mask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+ omp_clause_mask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+ omp_clause_mask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+ omp_clause_mask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+ omp_clause_mask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+ omp_clause_mask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+ omp_clause_mask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+ omp_clause_mask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+ omp_clause_mask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+ omp_clause_mask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+ omp_clause_mask PTA_PKU (HOST_WIDE_INT_1U << 59);
+ omp_clause_mask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+ omp_clause_mask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+ omp_clause_mask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+ omp_clause_mask PTA_SGX (HOST_WIDE_INT_1U << 63);
+
+ omp_clause_mask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+ omp_clause_mask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+ | PTA_POPCNT;
+ omp_clause_mask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+ omp_clause_mask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+ | PTA_XSAVEOPT;
+ omp_clause_mask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND
+ | PTA_F16C;
+ omp_clause_mask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2
+ | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+ omp_clause_mask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+ | PTA_RDSEED;
+ omp_clause_mask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC
+ | PTA_XSAVES;
+ omp_clause_mask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD
+ | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB;
+ omp_clause_mask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
+ | PTA_AVX512IFMA | PTA_SHA;
+ omp_clause_mask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+ | PTA_AVX512F | PTA_AVX512CD;
+ omp_clause_mask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+ omp_clause_mask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE;
+ omp_clause_mask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS
+ | PTA_AVX512VPOPCNTDQ;
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
const enum attr_cpu schedule;
- const unsigned HOST_WIDE_INT flags;
+ const omp_clause_mask flags;
}
const processor_alias_table[] =
{
@@ -3935,7 +3928,7 @@ ix86_option_override_internal (bool main_args_p,
}
if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && !(processor_alias_table[i].flags & PTA_64BIT))
+ && !(processor_alias_table[i].flags & PTA_64BIT).any ())
{
error ("CPU you selected does not support x86-64 "
"instruction set");
@@ -3947,195 +3940,196 @@ ix86_option_override_internal (bool main_args_p,
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
+ if ((processor_alias_table[i].flags & PTA_MMX).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
+ if ((processor_alias_table[i].flags & PTA_3DNOW).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
+ if ((processor_alias_table[i].flags & PTA_3DNOW_A).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
+ if ((processor_alias_table[i].flags & PTA_SSE).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
+ if ((processor_alias_table[i].flags & PTA_SSE2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
- if (processor_alias_table[i].flags & PTA_SSE3
+ if ((processor_alias_table[i].flags & PTA_SSE3).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
- if (processor_alias_table[i].flags & PTA_SSSE3
+ if ((processor_alias_table[i].flags & PTA_SSSE3).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
- if (processor_alias_table[i].flags & PTA_SSE4_1
+ if ((processor_alias_table[i].flags & PTA_SSE4_1).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
- if (processor_alias_table[i].flags & PTA_SSE4_2
+ if ((processor_alias_table[i].flags & PTA_SSE4_2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
- if (processor_alias_table[i].flags & PTA_AVX
+ if ((processor_alias_table[i].flags & PTA_AVX).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX;
- if (processor_alias_table[i].flags & PTA_AVX2
+ if ((processor_alias_table[i].flags & PTA_AVX2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
- if (processor_alias_table[i].flags & PTA_FMA
+ if ((processor_alias_table[i].flags & PTA_FMA).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA;
- if (processor_alias_table[i].flags & PTA_SSE4A
+ if ((processor_alias_table[i].flags & PTA_SSE4A).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_FMA4
+ if ((processor_alias_table[i].flags & PTA_FMA4).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
- if (processor_alias_table[i].flags & PTA_XOP
+ if ((processor_alias_table[i].flags & PTA_XOP).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP;
- if (processor_alias_table[i].flags & PTA_LWP
+ if ((processor_alias_table[i].flags & PTA_LWP).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP;
- if (processor_alias_table[i].flags & PTA_ABM
+ if ((processor_alias_table[i].flags & PTA_ABM).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM;
- if (processor_alias_table[i].flags & PTA_BMI
+ if ((processor_alias_table[i].flags & PTA_BMI).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI;
- if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
+ if ((processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
- if (processor_alias_table[i].flags & PTA_TBM
+ if ((processor_alias_table[i].flags & PTA_TBM).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM;
- if (processor_alias_table[i].flags & PTA_BMI2
+ if ((processor_alias_table[i].flags & PTA_BMI2).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
- if (processor_alias_table[i].flags & PTA_CX16
+ if ((processor_alias_table[i].flags & PTA_CX16).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CX16))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16;
- if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
+ if ((processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
if (!(TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && (processor_alias_table[i].flags & PTA_NO_SAHF))
+ && (processor_alias_table[i].flags & PTA_NO_SAHF).any ())
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
- if (processor_alias_table[i].flags & PTA_MOVBE
+ if ((processor_alias_table[i].flags & PTA_MOVBE).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVBE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE;
- if (processor_alias_table[i].flags & PTA_AES
+ if ((processor_alias_table[i].flags & PTA_AES).any ()
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
ix86_isa_flags |= OPTION_MASK_ISA_AES;
- if (processor_alias_table[i].flags & PTA_SHA
+ if ((processor_alias_table[i].flags & PTA_SHA).any ()
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SHA))
ix86_isa_flags |= OPTION_MASK_ISA_SHA;
- if (processor_alias_table[i].flags & PTA_PCLMUL
+ if ((processor_alias_table[i].flags & PTA_PCLMUL).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
- if (processor_alias_table[i].flags & PTA_FSGSBASE
+ if ((processor_alias_table[i].flags & PTA_FSGSBASE).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
- if (processor_alias_table[i].flags & PTA_RDRND
+ if ((processor_alias_table[i].flags & PTA_RDRND).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
- if (processor_alias_table[i].flags & PTA_F16C
+ if ((processor_alias_table[i].flags & PTA_F16C).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C;
- if (processor_alias_table[i].flags & PTA_RTM
+ if ((processor_alias_table[i].flags & PTA_RTM).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM;
- if (processor_alias_table[i].flags & PTA_HLE
+ if ((processor_alias_table[i].flags & PTA_HLE).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_HLE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_HLE;
- if (processor_alias_table[i].flags & PTA_PRFCHW
+ if ((processor_alias_table[i].flags & PTA_PRFCHW).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
- if (processor_alias_table[i].flags & PTA_RDSEED
+ if ((processor_alias_table[i].flags & PTA_RDSEED).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
- if (processor_alias_table[i].flags & PTA_ADX
+ if ((processor_alias_table[i].flags & PTA_ADX).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ADX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX;
- if (processor_alias_table[i].flags & PTA_FXSR
+ if ((processor_alias_table[i].flags & PTA_FXSR).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FXSR))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR;
- if (processor_alias_table[i].flags & PTA_XSAVE
+ if ((processor_alias_table[i].flags & PTA_XSAVE).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE;
- if (processor_alias_table[i].flags & PTA_XSAVEOPT
+ if ((processor_alias_table[i].flags & PTA_XSAVEOPT).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
- if (processor_alias_table[i].flags & PTA_AVX512F
+ if ((processor_alias_table[i].flags & PTA_AVX512F).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
- if (processor_alias_table[i].flags & PTA_AVX512ER
+ if ((processor_alias_table[i].flags & PTA_AVX512ER).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
- if (processor_alias_table[i].flags & PTA_AVX512PF
+ if ((processor_alias_table[i].flags & PTA_AVX512PF).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
- if (processor_alias_table[i].flags & PTA_AVX512CD
+ if ((processor_alias_table[i].flags & PTA_AVX512CD).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
- if (processor_alias_table[i].flags & PTA_PREFETCHWT1
+ if ((processor_alias_table[i].flags & PTA_PREFETCHWT1).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
- if (processor_alias_table[i].flags & PTA_CLWB
+ if ((processor_alias_table[i].flags & PTA_CLWB).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
- if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
+ if ((processor_alias_table[i].flags & PTA_CLFLUSHOPT).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
- if (processor_alias_table[i].flags & PTA_CLZERO
+ if ((processor_alias_table[i].flags & PTA_CLZERO).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CLZERO))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO;
- if (processor_alias_table[i].flags & PTA_XSAVEC
+ if ((processor_alias_table[i].flags & PTA_XSAVEC).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC;
- if (processor_alias_table[i].flags & PTA_XSAVES
+ if ((processor_alias_table[i].flags & PTA_XSAVES).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
- if (processor_alias_table[i].flags & PTA_AVX512DQ
+ if ((processor_alias_table[i].flags & PTA_AVX512DQ).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
- if (processor_alias_table[i].flags & PTA_AVX512BW
+ if ((processor_alias_table[i].flags & PTA_AVX512BW).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
- if (processor_alias_table[i].flags & PTA_AVX512VL
+ if ((processor_alias_table[i].flags & PTA_AVX512VL).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
- if (processor_alias_table[i].flags & PTA_MPX
+ if ((processor_alias_table[i].flags & PTA_MPX).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX;
- if (processor_alias_table[i].flags & PTA_AVX512VBMI
+ if ((processor_alias_table[i].flags & PTA_AVX512VBMI).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI;
- if (processor_alias_table[i].flags & PTA_AVX512IFMA
+ if ((processor_alias_table[i].flags & PTA_AVX512IFMA).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
- if (processor_alias_table[i].flags & PTA_AVX5124VNNIW
+ if ((processor_alias_table[i].flags & PTA_AVX5124VNNIW).any ()
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124VNNIW))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW;
- if (processor_alias_table[i].flags & PTA_AVX5124FMAPS
+ if ((processor_alias_table[i].flags & PTA_AVX5124FMAPS).any ()
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124FMAPS))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS;
- if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
+ if ((processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ).any ()
&& !(opts->x_ix86_isa_flags_explicit
& OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
- if (processor_alias_table[i].flags & PTA_SGX
+ if ((processor_alias_table[i].flags & PTA_SGX).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
- if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
+ if ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)).any ())
x86_prefetch_sse = true;
- if (processor_alias_table[i].flags & PTA_MWAITX
+ if ((processor_alias_table[i].flags & PTA_MWAITX).any ()
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MWAITX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX;
- if (processor_alias_table[i].flags & PTA_PKU
+ if ((processor_alias_table[i].flags & PTA_PKU).any ()
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
@@ -4144,7 +4138,7 @@ ix86_option_override_internal (bool main_args_p,
if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
&& !(opts_set->x_target_flags & MASK_80387))
{
- if (processor_alias_table[i].flags & PTA_NO_80387)
+ if ((processor_alias_table[i].flags & PTA_NO_80387).any ())
opts->x_target_flags &= ~MASK_80387;
else
opts->x_target_flags |= MASK_80387;
@@ -4170,7 +4164,7 @@ ix86_option_override_internal (bool main_args_p,
if (strcmp (processor_alias_table[i].name, "generic")
&& strcmp (processor_alias_table[i].name, "intel")
&& (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT)))
+ || (processor_alias_table[i].flags & PTA_64BIT).any ()))
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -4203,7 +4197,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_tune = processor_alias_table[i].processor;
if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
{
- if (!(processor_alias_table[i].flags & PTA_64BIT))
+ if (!(processor_alias_table[i].flags & PTA_64BIT).any ())
{
if (ix86_tune_defaulted)
{
@@ -4226,7 +4220,8 @@ ix86_option_override_internal (bool main_args_p,
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
if (TARGET_CMOV
- && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
+ && (processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)).any ())
x86_prefetch_sse = true;
break;
}
@@ -4241,7 +4236,7 @@ ix86_option_override_internal (bool main_args_p,
auto_vec <const char *> candidates;
for (i = 0; i < pta_size; i++)
if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT))
+ || (processor_alias_table[i].flags & PTA_64BIT).any ())
candidates.safe_push (processor_alias_table[i].name);
char *s;
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2018-01-22 11:46 ` Koval, Julia
@ 2018-01-22 12:12 ` Jakub Jelinek
2018-01-22 15:10 ` Koval, Julia
0 siblings, 1 reply; 21+ messages in thread
From: Jakub Jelinek @ 2018-01-22 12:12 UTC (permalink / raw)
To: Koval, Julia; +Cc: Richard Biener, Uros Bizjak, GCC Patches, Kirill Yukhin
On Mon, Jan 22, 2018 at 11:30:10AM +0000, Koval, Julia wrote:
> Hi, I tried omp_clause_mask and it looks ok. But it lacks check if there
> is any bit or none. With addition of it(as proposed or in some other way
> it should work. What do you think about this approach(patch attached)?
Well, I certainly didn't mean to use omp_clause_mask for something
completely unrelated to OpenMP, the reason I've mentioned it is that it is a
class that deals with a similar problem.
So, if you want to use the same class, it would need to be moved to some
generic header, renamed and then c-common.h would typedef that_class
omp_clause_mask.
I'm surprised you need any, doesn't ((mask & (...)) != 0 already handle
that?
Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2018-01-22 12:12 ` Jakub Jelinek
@ 2018-01-22 15:10 ` Koval, Julia
2018-01-24 11:05 ` Uros Bizjak
0 siblings, 1 reply; 21+ messages in thread
From: Koval, Julia @ 2018-01-22 15:10 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Richard Biener, Uros Bizjak, GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 1241 bytes --]
Yes, you are right, any() is not required. Here is the patch.
Thanks,
Julia
> -----Original Message-----
> From: Jakub Jelinek [mailto:jakub@redhat.com]
> Sent: Monday, January 22, 2018 12:36 PM
> To: Koval, Julia <julia.koval@intel.com>
> Cc: Richard Biener <richard.guenther@gmail.com>; Uros Bizjak
> <ubizjak@gmail.com>; GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> <kirill.yukhin@gmail.com>
> Subject: Re: [patch][x86] -march=icelake
>
> On Mon, Jan 22, 2018 at 11:30:10AM +0000, Koval, Julia wrote:
> > Hi, I tried omp_clause_mask and it looks ok. But it lacks check if there
> > is any bit or none. With addition of it(as proposed or in some other way
> > it should work. What do you think about this approach(patch attached)?
>
> Well, I certainly didn't mean to use omp_clause_mask for something
> completely unrelated to OpenMP, the reason I've mentioned it is that it is a
> class that deals with a similar problem.
>
> So, if you want to use the same class, it would need to be moved to some
> generic header, renamed and then c-common.h would typedef that_class
> omp_clause_mask.
>
> I'm surprised you need any, doesn't ((mask & (...)) != 0 already handle
> that?
>
> Jakub
[-- Attachment #2: 0001-test.patch --]
[-- Type: application/octet-stream, Size: 33281 bytes --]
From a81d109786553a45c49d13aab110d31dbd9318f7 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Thu, 18 Jan 2018 10:00:54 +0300
Subject: [PATCH] test
---
gcc/bit-mask.h | 145 +++++++++++++++++++++
gcc/c-family/c-common.h | 122 +-----------------
gcc/config/i386/i386.c | 329 ++++++++++++++++++++++++------------------------
3 files changed, 309 insertions(+), 287 deletions(-)
create mode 100644 gcc/bit-mask.h
diff --git a/gcc/bit-mask.h b/gcc/bit-mask.h
new file mode 100644
index 0000000..60edaac
--- /dev/null
+++ b/gcc/bit-mask.h
@@ -0,0 +1,145 @@
+/* Operation with 128 bit bitmask.
+ Copyright (C) 1987-2018 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_BIT_MASK_H
+#define GCC_BIT_MASK_H
+
+struct bit_mask
+{
+ inline bit_mask ();
+ inline bit_mask (uint64_t l);
+ inline bit_mask (uint64_t l, uint64_t h);
+ inline bit_mask &operator &= (bit_mask);
+ inline bit_mask &operator |= (bit_mask);
+ inline bit_mask operator ~ () const;
+ inline bit_mask operator & (bit_mask) const;
+ inline bit_mask operator | (bit_mask) const;
+ inline bit_mask operator >> (int);
+ inline bit_mask operator << (int);
+ inline bool operator == (bit_mask) const;
+ inline bool operator != (bit_mask) const;
+ uint64_t low, high;
+};
+
+inline
+bit_mask::bit_mask ()
+: low (0), high (0)
+{
+}
+
+inline
+bit_mask::bit_mask (uint64_t l)
+: low (l), high (0)
+{
+}
+
+inline
+bit_mask::bit_mask (uint64_t l, uint64_t h)
+: low (l), high (h)
+{
+}
+
+inline bit_mask &
+bit_mask::operator &= (bit_mask b)
+{
+ low &= b.low;
+ high &= b.high;
+ return *this;
+}
+
+inline bit_mask &
+bit_mask::operator |= (bit_mask b)
+{
+ low |= b.low;
+ high |= b.high;
+ return *this;
+}
+
+inline bit_mask
+bit_mask::operator ~ () const
+{
+ bit_mask ret (~low, ~high);
+ return ret;
+}
+
+inline bit_mask
+bit_mask::operator | (bit_mask b) const
+{
+ bit_mask ret (low | b.low, high | b.high);
+ return ret;
+}
+
+inline bit_mask
+bit_mask::operator & (bit_mask b) const
+{
+ bit_mask ret (low & b.low, high & b.high);
+ return ret;
+}
+
+inline bit_mask
+bit_mask::operator << (int amount)
+{
+ bit_mask ret;
+ if (amount >= 64)
+ {
+ ret.low = 0;
+ ret.high = low << (amount - 64);
+ }
+ else if (amount == 0)
+ ret = *this;
+ else
+ {
+ ret.low = low << amount;
+ ret.high = (low >> (64 - amount)) | (high << amount);
+ }
+ return ret;
+}
+
+inline bit_mask
+bit_mask::operator >> (int amount)
+{
+ bit_mask ret;
+ if (amount >= 64)
+ {
+ ret.low = high >> (amount - 64);
+ ret.high = 0;
+ }
+ else if (amount == 0)
+ ret = *this;
+ else
+ {
+ ret.low = (high << (64 - amount)) | (low >> amount);
+ ret.high = high >> amount;
+ }
+ return ret;
+}
+
+inline bool
+bit_mask::operator == (bit_mask b) const
+{
+ return low == b.low && high == b.high;
+}
+
+inline bool
+bit_mask::operator != (bit_mask b) const
+{
+ return low != b.low || high != b.high;
+}
+
+#endif /* ! GCC_BIT_MASK_H */
diff --git a/gcc/c-family/c-common.h b/gcc/c-family/c-common.h
index d090881..9793d8a 100644
--- a/gcc/c-family/c-common.h
+++ b/gcc/c-family/c-common.h
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see
#include "alias.h"
#include "tree.h"
#include "fold-const.h"
+#include "bit-mask.h"
/* In order for the format checking to accept the C frontend
diagnostic framework extensions, you must include this file before
@@ -1111,126 +1112,7 @@ extern void pp_dir_change (cpp_reader *, const char *);
extern bool check_missing_format_attribute (tree, tree);
/* In c-omp.c */
-struct omp_clause_mask
-{
- inline omp_clause_mask ();
- inline omp_clause_mask (uint64_t l);
- inline omp_clause_mask (uint64_t l, uint64_t h);
- inline omp_clause_mask &operator &= (omp_clause_mask);
- inline omp_clause_mask &operator |= (omp_clause_mask);
- inline omp_clause_mask operator ~ () const;
- inline omp_clause_mask operator & (omp_clause_mask) const;
- inline omp_clause_mask operator | (omp_clause_mask) const;
- inline omp_clause_mask operator >> (int);
- inline omp_clause_mask operator << (int);
- inline bool operator == (omp_clause_mask) const;
- inline bool operator != (omp_clause_mask) const;
- uint64_t low, high;
-};
-
-inline
-omp_clause_mask::omp_clause_mask ()
-{
-}
-
-inline
-omp_clause_mask::omp_clause_mask (uint64_t l)
-: low (l), high (0)
-{
-}
-
-inline
-omp_clause_mask::omp_clause_mask (uint64_t l, uint64_t h)
-: low (l), high (h)
-{
-}
-
-inline omp_clause_mask &
-omp_clause_mask::operator &= (omp_clause_mask b)
-{
- low &= b.low;
- high &= b.high;
- return *this;
-}
-
-inline omp_clause_mask &
-omp_clause_mask::operator |= (omp_clause_mask b)
-{
- low |= b.low;
- high |= b.high;
- return *this;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator ~ () const
-{
- omp_clause_mask ret (~low, ~high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator | (omp_clause_mask b) const
-{
- omp_clause_mask ret (low | b.low, high | b.high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator & (omp_clause_mask b) const
-{
- omp_clause_mask ret (low & b.low, high & b.high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator << (int amount)
-{
- omp_clause_mask ret;
- if (amount >= 64)
- {
- ret.low = 0;
- ret.high = low << (amount - 64);
- }
- else if (amount == 0)
- ret = *this;
- else
- {
- ret.low = low << amount;
- ret.high = (low >> (64 - amount)) | (high << amount);
- }
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator >> (int amount)
-{
- omp_clause_mask ret;
- if (amount >= 64)
- {
- ret.low = high >> (amount - 64);
- ret.high = 0;
- }
- else if (amount == 0)
- ret = *this;
- else
- {
- ret.low = (high << (64 - amount)) | (low >> amount);
- ret.high = high >> amount;
- }
- return ret;
-}
-
-inline bool
-omp_clause_mask::operator == (omp_clause_mask b) const
-{
- return low == b.low && high == b.high;
-}
-
-inline bool
-omp_clause_mask::operator != (omp_clause_mask b) const
-{
- return low != b.low || high != b.high;
-}
+typedef bit_mask omp_clause_mask;
#define OMP_CLAUSE_MASK_1 omp_clause_mask (1)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ea9c462..a5c5ee1 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -90,6 +90,7 @@ along with GCC; see the file COPYING3. If not see
#include "symbol-summary.h"
#include "ipa-prop.h"
#include "ipa-fnsummary.h"
+#include "bit-mask.h"
/* This file should be included last. */
#include "target-def.h"
@@ -3381,111 +3382,103 @@ ix86_option_override_internal (bool main_args_p,
unsigned int ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
-#define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
-#define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
-#define PTA_64BIT (HOST_WIDE_INT_1 << 2)
-#define PTA_ABM (HOST_WIDE_INT_1 << 3)
-#define PTA_AES (HOST_WIDE_INT_1 << 4)
-#define PTA_AVX (HOST_WIDE_INT_1 << 5)
-#define PTA_BMI (HOST_WIDE_INT_1 << 6)
-#define PTA_CX16 (HOST_WIDE_INT_1 << 7)
-#define PTA_F16C (HOST_WIDE_INT_1 << 8)
-#define PTA_FMA (HOST_WIDE_INT_1 << 9)
-#define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
-#define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
-#define PTA_LWP (HOST_WIDE_INT_1 << 12)
-#define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
-#define PTA_MMX (HOST_WIDE_INT_1 << 14)
-#define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
-#define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
-#define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
-#define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
-#define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
-#define PTA_RDRND (HOST_WIDE_INT_1 << 20)
-#define PTA_SSE (HOST_WIDE_INT_1 << 21)
-#define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
-#define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
-#define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
-#define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
-#define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
-#define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
-#define PTA_TBM (HOST_WIDE_INT_1 << 28)
-#define PTA_XOP (HOST_WIDE_INT_1 << 29)
-#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
-#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
-#define PTA_RTM (HOST_WIDE_INT_1 << 32)
-#define PTA_HLE (HOST_WIDE_INT_1 << 33)
-#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
-#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
-#define PTA_ADX (HOST_WIDE_INT_1 << 36)
-#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
-#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
-#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
-#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
-#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
-#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
-#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
-#define PTA_MPX (HOST_WIDE_INT_1 << 44)
-#define PTA_SHA (HOST_WIDE_INT_1 << 45)
-#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
-#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
-#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
-#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
-#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
-#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
-#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
-#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
-#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
-#define PTA_CLWB (HOST_WIDE_INT_1 << 55)
-#define PTA_MWAITX (HOST_WIDE_INT_1 << 56)
-#define PTA_CLZERO (HOST_WIDE_INT_1 << 57)
-#define PTA_NO_80387 (HOST_WIDE_INT_1 << 58)
-#define PTA_PKU (HOST_WIDE_INT_1 << 59)
-#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
-#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
-#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
-#define PTA_SGX (HOST_WIDE_INT_1 << 63)
-
-#define PTA_CORE2 \
- (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
- | PTA_CX16 | PTA_FXSR)
-#define PTA_NEHALEM \
- (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
-#define PTA_WESTMERE \
- (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
-#define PTA_SANDYBRIDGE \
- (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
-#define PTA_IVYBRIDGE \
- (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
-#define PTA_HASWELL \
- (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
- | PTA_FMA | PTA_MOVBE | PTA_HLE)
-#define PTA_BROADWELL \
- (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
-#define PTA_SKYLAKE \
- (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
-#define PTA_SKYLAKE_AVX512 \
- (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
- | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB)
-#define PTA_CANNONLAKE \
- (PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA)
-#define PTA_KNL \
- (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
-#define PTA_BONNELL \
- (PTA_CORE2 | PTA_MOVBE)
-#define PTA_SILVERMONT \
- (PTA_WESTMERE | PTA_MOVBE)
-#define PTA_KNM \
- (PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
-
-/* if this reaches 64, need to widen struct pta flags below */
+ bit_mask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+ bit_mask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+ bit_mask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+ bit_mask PTA_ABM (HOST_WIDE_INT_1U << 3);
+ bit_mask PTA_AES (HOST_WIDE_INT_1U << 4);
+ bit_mask PTA_AVX (HOST_WIDE_INT_1U << 5);
+ bit_mask PTA_BMI (HOST_WIDE_INT_1U << 6);
+ bit_mask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+ bit_mask PTA_F16C (HOST_WIDE_INT_1U << 8);
+ bit_mask PTA_FMA (HOST_WIDE_INT_1U << 9);
+ bit_mask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+ bit_mask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+ bit_mask PTA_LWP (HOST_WIDE_INT_1U << 12);
+ bit_mask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+ bit_mask PTA_MMX (HOST_WIDE_INT_1U << 14);
+ bit_mask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+ bit_mask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+ bit_mask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+ bit_mask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+ bit_mask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+ bit_mask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+ bit_mask PTA_SSE (HOST_WIDE_INT_1U << 21);
+ bit_mask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+ bit_mask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+ bit_mask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+ bit_mask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+ bit_mask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+ bit_mask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+ bit_mask PTA_TBM (HOST_WIDE_INT_1U << 28);
+ bit_mask PTA_XOP (HOST_WIDE_INT_1U << 29);
+ bit_mask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+ bit_mask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+ bit_mask PTA_RTM (HOST_WIDE_INT_1U << 32);
+ bit_mask PTA_HLE (HOST_WIDE_INT_1U << 33);
+ bit_mask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+ bit_mask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+ bit_mask PTA_ADX (HOST_WIDE_INT_1U << 36);
+ bit_mask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+ bit_mask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+ bit_mask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+ bit_mask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+ bit_mask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+ bit_mask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+ bit_mask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+ bit_mask PTA_MPX (HOST_WIDE_INT_1U << 44);
+ bit_mask PTA_SHA (HOST_WIDE_INT_1U << 45);
+ bit_mask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+ bit_mask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+ bit_mask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+ bit_mask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+ bit_mask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+ bit_mask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+ bit_mask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+ bit_mask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+ bit_mask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+ bit_mask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+ bit_mask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+ bit_mask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+ bit_mask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+ bit_mask PTA_PKU (HOST_WIDE_INT_1U << 59);
+ bit_mask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+ bit_mask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+ bit_mask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+ bit_mask PTA_SGX (HOST_WIDE_INT_1U << 63);
+
+ bit_mask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+ bit_mask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+ | PTA_POPCNT;
+ bit_mask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+ bit_mask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+ | PTA_XSAVEOPT;
+ bit_mask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND
+ | PTA_F16C;
+ bit_mask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2
+ | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+ bit_mask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+ | PTA_RDSEED;
+ bit_mask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC
+ | PTA_XSAVES;
+ bit_mask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD
+ | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB;
+ bit_mask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
+ | PTA_AVX512IFMA | PTA_SHA;
+ bit_mask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+ | PTA_AVX512F | PTA_AVX512CD;
+ bit_mask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+ bit_mask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE;
+ bit_mask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS
+ | PTA_AVX512VPOPCNTDQ;
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
const enum attr_cpu schedule;
- const unsigned HOST_WIDE_INT flags;
+ const bit_mask flags;
}
const processor_alias_table[] =
{
@@ -3935,7 +3928,7 @@ ix86_option_override_internal (bool main_args_p,
}
if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && !(processor_alias_table[i].flags & PTA_64BIT))
+ && !((processor_alias_table[i].flags & PTA_64BIT) != 0))
{
error ("CPU you selected does not support x86-64 "
"instruction set");
@@ -3947,195 +3940,196 @@ ix86_option_override_internal (bool main_args_p,
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
+ if (((processor_alias_table[i].flags & PTA_MMX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
+ if (((processor_alias_table[i].flags & PTA_3DNOW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
+ if (((processor_alias_table[i].flags & PTA_3DNOW_A) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
+ if (((processor_alias_table[i].flags & PTA_SSE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
+ if (((processor_alias_table[i].flags & PTA_SSE2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
- if (processor_alias_table[i].flags & PTA_SSE3
+ if (((processor_alias_table[i].flags & PTA_SSE3) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
- if (processor_alias_table[i].flags & PTA_SSSE3
+ if (((processor_alias_table[i].flags & PTA_SSSE3) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
- if (processor_alias_table[i].flags & PTA_SSE4_1
+ if (((processor_alias_table[i].flags & PTA_SSE4_1) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
- if (processor_alias_table[i].flags & PTA_SSE4_2
+ if (((processor_alias_table[i].flags & PTA_SSE4_2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
- if (processor_alias_table[i].flags & PTA_AVX
+ if (((processor_alias_table[i].flags & PTA_AVX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX;
- if (processor_alias_table[i].flags & PTA_AVX2
+ if (((processor_alias_table[i].flags & PTA_AVX2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
- if (processor_alias_table[i].flags & PTA_FMA
+ if (((processor_alias_table[i].flags & PTA_FMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA;
- if (processor_alias_table[i].flags & PTA_SSE4A
+ if (((processor_alias_table[i].flags & PTA_SSE4A) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_FMA4
+ if (((processor_alias_table[i].flags & PTA_FMA4) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
- if (processor_alias_table[i].flags & PTA_XOP
+ if (((processor_alias_table[i].flags & PTA_XOP) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP;
- if (processor_alias_table[i].flags & PTA_LWP
+ if (((processor_alias_table[i].flags & PTA_LWP) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP;
- if (processor_alias_table[i].flags & PTA_ABM
+ if (((processor_alias_table[i].flags & PTA_ABM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM;
- if (processor_alias_table[i].flags & PTA_BMI
+ if (((processor_alias_table[i].flags & PTA_BMI) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI;
- if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
+ if (((processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
- if (processor_alias_table[i].flags & PTA_TBM
+ if (((processor_alias_table[i].flags & PTA_TBM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM;
- if (processor_alias_table[i].flags & PTA_BMI2
+ if (((processor_alias_table[i].flags & PTA_BMI2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
- if (processor_alias_table[i].flags & PTA_CX16
+ if (((processor_alias_table[i].flags & PTA_CX16) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CX16))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16;
- if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
+ if (((processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
if (!(TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && (processor_alias_table[i].flags & PTA_NO_SAHF))
+ && ((processor_alias_table[i].flags & PTA_NO_SAHF) != 0))
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
- if (processor_alias_table[i].flags & PTA_MOVBE
+ if (((processor_alias_table[i].flags & PTA_MOVBE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVBE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE;
- if (processor_alias_table[i].flags & PTA_AES
+ if (((processor_alias_table[i].flags & PTA_AES) != 0)
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
ix86_isa_flags |= OPTION_MASK_ISA_AES;
- if (processor_alias_table[i].flags & PTA_SHA
+ if (((processor_alias_table[i].flags & PTA_SHA) != 0)
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SHA))
ix86_isa_flags |= OPTION_MASK_ISA_SHA;
- if (processor_alias_table[i].flags & PTA_PCLMUL
+ if (((processor_alias_table[i].flags & PTA_PCLMUL) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
- if (processor_alias_table[i].flags & PTA_FSGSBASE
+ if (((processor_alias_table[i].flags & PTA_FSGSBASE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
- if (processor_alias_table[i].flags & PTA_RDRND
+ if (((processor_alias_table[i].flags & PTA_RDRND) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
- if (processor_alias_table[i].flags & PTA_F16C
+ if (((processor_alias_table[i].flags & PTA_F16C) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C;
- if (processor_alias_table[i].flags & PTA_RTM
+ if (((processor_alias_table[i].flags & PTA_RTM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM;
- if (processor_alias_table[i].flags & PTA_HLE
+ if (((processor_alias_table[i].flags & PTA_HLE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_HLE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_HLE;
- if (processor_alias_table[i].flags & PTA_PRFCHW
+ if (((processor_alias_table[i].flags & PTA_PRFCHW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
- if (processor_alias_table[i].flags & PTA_RDSEED
+ if (((processor_alias_table[i].flags & PTA_RDSEED) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
- if (processor_alias_table[i].flags & PTA_ADX
+ if (((processor_alias_table[i].flags & PTA_ADX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ADX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX;
- if (processor_alias_table[i].flags & PTA_FXSR
+ if (((processor_alias_table[i].flags & PTA_FXSR) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FXSR))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR;
- if (processor_alias_table[i].flags & PTA_XSAVE
+ if (((processor_alias_table[i].flags & PTA_XSAVE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE;
- if (processor_alias_table[i].flags & PTA_XSAVEOPT
+ if (((processor_alias_table[i].flags & PTA_XSAVEOPT) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
- if (processor_alias_table[i].flags & PTA_AVX512F
+ if (((processor_alias_table[i].flags & PTA_AVX512F) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
- if (processor_alias_table[i].flags & PTA_AVX512ER
+ if (((processor_alias_table[i].flags & PTA_AVX512ER) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
- if (processor_alias_table[i].flags & PTA_AVX512PF
+ if (((processor_alias_table[i].flags & PTA_AVX512PF) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
- if (processor_alias_table[i].flags & PTA_AVX512CD
+ if (((processor_alias_table[i].flags & PTA_AVX512CD) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
- if (processor_alias_table[i].flags & PTA_PREFETCHWT1
+ if (((processor_alias_table[i].flags & PTA_PREFETCHWT1) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
- if (processor_alias_table[i].flags & PTA_CLWB
+ if (((processor_alias_table[i].flags & PTA_CLWB) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
- if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
+ if (((processor_alias_table[i].flags & PTA_CLFLUSHOPT) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
- if (processor_alias_table[i].flags & PTA_CLZERO
+ if (((processor_alias_table[i].flags & PTA_CLZERO) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CLZERO))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO;
- if (processor_alias_table[i].flags & PTA_XSAVEC
+ if (((processor_alias_table[i].flags & PTA_XSAVEC) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC;
- if (processor_alias_table[i].flags & PTA_XSAVES
+ if (((processor_alias_table[i].flags & PTA_XSAVES) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
- if (processor_alias_table[i].flags & PTA_AVX512DQ
+ if (((processor_alias_table[i].flags & PTA_AVX512DQ) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
- if (processor_alias_table[i].flags & PTA_AVX512BW
+ if (((processor_alias_table[i].flags & PTA_AVX512BW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
- if (processor_alias_table[i].flags & PTA_AVX512VL
+ if (((processor_alias_table[i].flags & PTA_AVX512VL) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
- if (processor_alias_table[i].flags & PTA_MPX
+ if (((processor_alias_table[i].flags & PTA_MPX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX;
- if (processor_alias_table[i].flags & PTA_AVX512VBMI
+ if (((processor_alias_table[i].flags & PTA_AVX512VBMI) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI;
- if (processor_alias_table[i].flags & PTA_AVX512IFMA
+ if (((processor_alias_table[i].flags & PTA_AVX512IFMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
- if (processor_alias_table[i].flags & PTA_AVX5124VNNIW
+ if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124VNNIW))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW;
- if (processor_alias_table[i].flags & PTA_AVX5124FMAPS
+ if (((processor_alias_table[i].flags & PTA_AVX5124FMAPS) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124FMAPS))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS;
- if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
+ if (((processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ) != 0)
&& !(opts->x_ix86_isa_flags_explicit
& OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
- if (processor_alias_table[i].flags & PTA_SGX
+ if (((processor_alias_table[i].flags & PTA_SGX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
- if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
+ if ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
x86_prefetch_sse = true;
- if (processor_alias_table[i].flags & PTA_MWAITX
+ if (((processor_alias_table[i].flags & PTA_MWAITX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MWAITX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX;
- if (processor_alias_table[i].flags & PTA_PKU
+ if (((processor_alias_table[i].flags & PTA_PKU) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
@@ -4144,7 +4138,7 @@ ix86_option_override_internal (bool main_args_p,
if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
&& !(opts_set->x_target_flags & MASK_80387))
{
- if (processor_alias_table[i].flags & PTA_NO_80387)
+ if (((processor_alias_table[i].flags & PTA_NO_80387) != 0))
opts->x_target_flags &= ~MASK_80387;
else
opts->x_target_flags |= MASK_80387;
@@ -4170,7 +4164,7 @@ ix86_option_override_internal (bool main_args_p,
if (strcmp (processor_alias_table[i].name, "generic")
&& strcmp (processor_alias_table[i].name, "intel")
&& (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT)))
+ || ((processor_alias_table[i].flags & PTA_64BIT) != 0)))
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -4203,7 +4197,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_tune = processor_alias_table[i].processor;
if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
{
- if (!(processor_alias_table[i].flags & PTA_64BIT))
+ if (!((processor_alias_table[i].flags & PTA_64BIT) != 0))
{
if (ix86_tune_defaulted)
{
@@ -4226,7 +4220,8 @@ ix86_option_override_internal (bool main_args_p,
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
if (TARGET_CMOV
- && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
+ && ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)) != 0))
x86_prefetch_sse = true;
break;
}
@@ -4241,7 +4236,7 @@ ix86_option_override_internal (bool main_args_p,
auto_vec <const char *> candidates;
for (i = 0; i < pta_size; i++)
if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT))
+ || ((processor_alias_table[i].flags & PTA_64BIT) != 0))
candidates.safe_push (processor_alias_table[i].name);
char *s;
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2018-01-22 15:10 ` Koval, Julia
@ 2018-01-24 11:05 ` Uros Bizjak
2018-01-24 11:18 ` Jakub Jelinek
0 siblings, 1 reply; 21+ messages in thread
From: Uros Bizjak @ 2018-01-24 11:05 UTC (permalink / raw)
To: Koval, Julia; +Cc: Jakub Jelinek, Richard Biener, GCC Patches, Kirill Yukhin
On Mon, Jan 22, 2018 at 3:44 PM, Koval, Julia <julia.koval@intel.com> wrote:
> Yes, you are right, any() is not required. Here is the patch.
Please also attach ChangeLog.
The patch is OK for x86 target, it needs global reviewer approval
(Maybe Jakub, as the patch touches OMP part).
Uros.
> Thanks,
> Julia
>
>> -----Original Message-----
>> From: Jakub Jelinek [mailto:jakub@redhat.com]
>> Sent: Monday, January 22, 2018 12:36 PM
>> To: Koval, Julia <julia.koval@intel.com>
>> Cc: Richard Biener <richard.guenther@gmail.com>; Uros Bizjak
>> <ubizjak@gmail.com>; GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
>> <kirill.yukhin@gmail.com>
>> Subject: Re: [patch][x86] -march=icelake
>>
>> On Mon, Jan 22, 2018 at 11:30:10AM +0000, Koval, Julia wrote:
>> > Hi, I tried omp_clause_mask and it looks ok. But it lacks check if there
>> > is any bit or none. With addition of it(as proposed or in some other way
>> > it should work. What do you think about this approach(patch attached)?
>>
>> Well, I certainly didn't mean to use omp_clause_mask for something
>> completely unrelated to OpenMP, the reason I've mentioned it is that it is a
>> class that deals with a similar problem.
>>
>> So, if you want to use the same class, it would need to be moved to some
>> generic header, renamed and then c-common.h would typedef that_class
>> omp_clause_mask.
>>
>> I'm surprised you need any, doesn't ((mask & (...)) != 0 already handle
>> that?
>>
>> Jakub
>
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2018-01-24 11:05 ` Uros Bizjak
@ 2018-01-24 11:18 ` Jakub Jelinek
2018-01-24 11:24 ` Koval, Julia
0 siblings, 1 reply; 21+ messages in thread
From: Jakub Jelinek @ 2018-01-24 11:18 UTC (permalink / raw)
To: Uros Bizjak, Richard Biener; +Cc: Koval, Julia, GCC Patches, Kirill Yukhin
On Wed, Jan 24, 2018 at 12:00:26PM +0100, Uros Bizjak wrote:
> On Mon, Jan 22, 2018 at 3:44 PM, Koval, Julia <julia.koval@intel.com> wrote:
> > Yes, you are right, any() is not required. Here is the patch.
>
> Please also attach ChangeLog.
>
> The patch is OK for x86 target, it needs global reviewer approval
> (Maybe Jakub, as the patch touches OMP part).
I don't like the new class name nor header name, bit_mask is way too generic
name for something very specialized (double hwi bitmask).
Richard, any suggestions for this?
Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2018-01-24 11:18 ` Jakub Jelinek
@ 2018-01-24 11:24 ` Koval, Julia
2018-01-24 11:31 ` Richard Biener
0 siblings, 1 reply; 21+ messages in thread
From: Koval, Julia @ 2018-01-24 11:24 UTC (permalink / raw)
To: Jakub Jelinek, Uros Bizjak, Richard Biener; +Cc: GCC Patches, Kirill Yukhin
I think we may want to extend it to more than 2 ints someday, when we run out of bits again. It won't break the existing functionality if 3rd int will be zero by default. That's why I tried to avoid "two" in the name.
Julia
> -----Original Message-----
> From: Jakub Jelinek [mailto:jakub@redhat.com]
> Sent: Wednesday, January 24, 2018 12:06 PM
> To: Uros Bizjak <ubizjak@gmail.com>; Richard Biener <rguenther@suse.de>
> Cc: Koval, Julia <julia.koval@intel.com>; GCC Patches <gcc-
> patches@gcc.gnu.org>; Kirill Yukhin <kirill.yukhin@gmail.com>
> Subject: Re: [patch][x86] -march=icelake
>
> On Wed, Jan 24, 2018 at 12:00:26PM +0100, Uros Bizjak wrote:
> > On Mon, Jan 22, 2018 at 3:44 PM, Koval, Julia <julia.koval@intel.com> wrote:
> > > Yes, you are right, any() is not required. Here is the patch.
> >
> > Please also attach ChangeLog.
> >
> > The patch is OK for x86 target, it needs global reviewer approval
> > (Maybe Jakub, as the patch touches OMP part).
>
> I don't like the new class name nor header name, bit_mask is way too generic
> name for something very specialized (double hwi bitmask).
>
> Richard, any suggestions for this?
>
> Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2018-01-24 11:24 ` Koval, Julia
@ 2018-01-24 11:31 ` Richard Biener
2018-01-30 8:53 ` Koval, Julia
0 siblings, 1 reply; 21+ messages in thread
From: Richard Biener @ 2018-01-24 11:31 UTC (permalink / raw)
To: Koval, Julia; +Cc: Jakub Jelinek, Uros Bizjak, GCC Patches, Kirill Yukhin
On Wed, 24 Jan 2018, Koval, Julia wrote:
> I think we may want to extend it to more than 2 ints someday, when we run out of bits again. It won't break the existing functionality if 3rd int will be zero by default. That's why I tried to avoid "two" in the name.
>
> Julia
>
> > -----Original Message-----
> > From: Jakub Jelinek [mailto:jakub@redhat.com]
> > Sent: Wednesday, January 24, 2018 12:06 PM
> > To: Uros Bizjak <ubizjak@gmail.com>; Richard Biener <rguenther@suse.de>
> > Cc: Koval, Julia <julia.koval@intel.com>; GCC Patches <gcc-
> > patches@gcc.gnu.org>; Kirill Yukhin <kirill.yukhin@gmail.com>
> > Subject: Re: [patch][x86] -march=icelake
> >
> > On Wed, Jan 24, 2018 at 12:00:26PM +0100, Uros Bizjak wrote:
> > > On Mon, Jan 22, 2018 at 3:44 PM, Koval, Julia <julia.koval@intel.com> wrote:
> > > > Yes, you are right, any() is not required. Here is the patch.
> > >
> > > Please also attach ChangeLog.
> > >
> > > The patch is OK for x86 target, it needs global reviewer approval
> > > (Maybe Jakub, as the patch touches OMP part).
> >
> > I don't like the new class name nor header name, bit_mask is way too generic
> > name for something very specialized (double hwi bitmask).
> >
> > Richard, any suggestions for this?
Maybe wide_int_bitmask? You could then even use fixed_wide_int <> as
"implementation".
Richard.
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2018-01-24 11:31 ` Richard Biener
@ 2018-01-30 8:53 ` Koval, Julia
2018-01-30 9:56 ` Jakub Jelinek
0 siblings, 1 reply; 21+ messages in thread
From: Koval, Julia @ 2018-01-30 8:53 UTC (permalink / raw)
To: Richard Biener; +Cc: Jakub Jelinek, Uros Bizjak, GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 2080 bytes --]
Renamed it. Ok for trunk?
gcc/c-family/
* c-common.h (omp_clause_mask): Move to wide_int_bitmask.h
gcc/
* config/i386/i386.c (ix86_option_override_internal): Change flags type to
wide_int_bitmask.
* wide-int-bitmask.h: New.
Thanks,
Julia
> -----Original Message-----
> From: Richard Biener [mailto:rguenther@suse.de]
> Sent: Wednesday, January 24, 2018 12:18 PM
> To: Koval, Julia <julia.koval@intel.com>
> Cc: Jakub Jelinek <jakub@redhat.com>; Uros Bizjak <ubizjak@gmail.com>; GCC
> Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin <kirill.yukhin@gmail.com>
> Subject: RE: [patch][x86] -march=icelake
>
> On Wed, 24 Jan 2018, Koval, Julia wrote:
>
> > I think we may want to extend it to more than 2 ints someday, when we run
> out of bits again. It won't break the existing functionality if 3rd int will be zero by
> default. That's why I tried to avoid "two" in the name.
> >
> > Julia
> >
> > > -----Original Message-----
> > > From: Jakub Jelinek [mailto:jakub@redhat.com]
> > > Sent: Wednesday, January 24, 2018 12:06 PM
> > > To: Uros Bizjak <ubizjak@gmail.com>; Richard Biener <rguenther@suse.de>
> > > Cc: Koval, Julia <julia.koval@intel.com>; GCC Patches <gcc-
> > > patches@gcc.gnu.org>; Kirill Yukhin <kirill.yukhin@gmail.com>
> > > Subject: Re: [patch][x86] -march=icelake
> > >
> > > On Wed, Jan 24, 2018 at 12:00:26PM +0100, Uros Bizjak wrote:
> > > > On Mon, Jan 22, 2018 at 3:44 PM, Koval, Julia <julia.koval@intel.com>
> wrote:
> > > > > Yes, you are right, any() is not required. Here is the patch.
> > > >
> > > > Please also attach ChangeLog.
> > > >
> > > > The patch is OK for x86 target, it needs global reviewer approval
> > > > (Maybe Jakub, as the patch touches OMP part).
> > >
> > > I don't like the new class name nor header name, bit_mask is way too
> generic
> > > name for something very specialized (double hwi bitmask).
> > >
> > > Richard, any suggestions for this?
>
> Maybe wide_int_bitmask? You could then even use fixed_wide_int <> as
> "implementation".
>
> Richard.
[-- Attachment #2: 0001-bitmask.patch --]
[-- Type: application/octet-stream, Size: 34396 bytes --]
From d3e8612ae6feca7d577b1ad2e1fbc8cc4583aaa7 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Tue, 30 Jan 2018 10:45:49 +0300
Subject: [PATCH] bitmask
---
gcc/c-family/c-common.h | 122 +-----------------
gcc/config/i386/i386.c | 329 ++++++++++++++++++++++++------------------------
gcc/wide-int-bitmask.h | 145 +++++++++++++++++++++
3 files changed, 309 insertions(+), 287 deletions(-)
create mode 100644 gcc/wide-int-bitmask.h
diff --git a/gcc/c-family/c-common.h b/gcc/c-family/c-common.h
index d090881..aad01fa 100644
--- a/gcc/c-family/c-common.h
+++ b/gcc/c-family/c-common.h
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see
#include "alias.h"
#include "tree.h"
#include "fold-const.h"
+#include "wide-int-bitmask.h"
/* In order for the format checking to accept the C frontend
diagnostic framework extensions, you must include this file before
@@ -1111,126 +1112,7 @@ extern void pp_dir_change (cpp_reader *, const char *);
extern bool check_missing_format_attribute (tree, tree);
/* In c-omp.c */
-struct omp_clause_mask
-{
- inline omp_clause_mask ();
- inline omp_clause_mask (uint64_t l);
- inline omp_clause_mask (uint64_t l, uint64_t h);
- inline omp_clause_mask &operator &= (omp_clause_mask);
- inline omp_clause_mask &operator |= (omp_clause_mask);
- inline omp_clause_mask operator ~ () const;
- inline omp_clause_mask operator & (omp_clause_mask) const;
- inline omp_clause_mask operator | (omp_clause_mask) const;
- inline omp_clause_mask operator >> (int);
- inline omp_clause_mask operator << (int);
- inline bool operator == (omp_clause_mask) const;
- inline bool operator != (omp_clause_mask) const;
- uint64_t low, high;
-};
-
-inline
-omp_clause_mask::omp_clause_mask ()
-{
-}
-
-inline
-omp_clause_mask::omp_clause_mask (uint64_t l)
-: low (l), high (0)
-{
-}
-
-inline
-omp_clause_mask::omp_clause_mask (uint64_t l, uint64_t h)
-: low (l), high (h)
-{
-}
-
-inline omp_clause_mask &
-omp_clause_mask::operator &= (omp_clause_mask b)
-{
- low &= b.low;
- high &= b.high;
- return *this;
-}
-
-inline omp_clause_mask &
-omp_clause_mask::operator |= (omp_clause_mask b)
-{
- low |= b.low;
- high |= b.high;
- return *this;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator ~ () const
-{
- omp_clause_mask ret (~low, ~high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator | (omp_clause_mask b) const
-{
- omp_clause_mask ret (low | b.low, high | b.high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator & (omp_clause_mask b) const
-{
- omp_clause_mask ret (low & b.low, high & b.high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator << (int amount)
-{
- omp_clause_mask ret;
- if (amount >= 64)
- {
- ret.low = 0;
- ret.high = low << (amount - 64);
- }
- else if (amount == 0)
- ret = *this;
- else
- {
- ret.low = low << amount;
- ret.high = (low >> (64 - amount)) | (high << amount);
- }
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator >> (int amount)
-{
- omp_clause_mask ret;
- if (amount >= 64)
- {
- ret.low = high >> (amount - 64);
- ret.high = 0;
- }
- else if (amount == 0)
- ret = *this;
- else
- {
- ret.low = (high << (64 - amount)) | (low >> amount);
- ret.high = high >> amount;
- }
- return ret;
-}
-
-inline bool
-omp_clause_mask::operator == (omp_clause_mask b) const
-{
- return low == b.low && high == b.high;
-}
-
-inline bool
-omp_clause_mask::operator != (omp_clause_mask b) const
-{
- return low != b.low || high != b.high;
-}
+typedef wide_int_bitmask omp_clause_mask;
#define OMP_CLAUSE_MASK_1 omp_clause_mask (1)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3653ddd..469f994 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -90,6 +90,7 @@ along with GCC; see the file COPYING3. If not see
#include "symbol-summary.h"
#include "ipa-prop.h"
#include "ipa-fnsummary.h"
+#include "wide-int-bitmask.h"
/* This file should be included last. */
#include "target-def.h"
@@ -3381,111 +3382,103 @@ ix86_option_override_internal (bool main_args_p,
unsigned int ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
-#define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
-#define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
-#define PTA_64BIT (HOST_WIDE_INT_1 << 2)
-#define PTA_ABM (HOST_WIDE_INT_1 << 3)
-#define PTA_AES (HOST_WIDE_INT_1 << 4)
-#define PTA_AVX (HOST_WIDE_INT_1 << 5)
-#define PTA_BMI (HOST_WIDE_INT_1 << 6)
-#define PTA_CX16 (HOST_WIDE_INT_1 << 7)
-#define PTA_F16C (HOST_WIDE_INT_1 << 8)
-#define PTA_FMA (HOST_WIDE_INT_1 << 9)
-#define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
-#define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
-#define PTA_LWP (HOST_WIDE_INT_1 << 12)
-#define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
-#define PTA_MMX (HOST_WIDE_INT_1 << 14)
-#define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
-#define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
-#define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
-#define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
-#define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
-#define PTA_RDRND (HOST_WIDE_INT_1 << 20)
-#define PTA_SSE (HOST_WIDE_INT_1 << 21)
-#define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
-#define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
-#define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
-#define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
-#define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
-#define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
-#define PTA_TBM (HOST_WIDE_INT_1 << 28)
-#define PTA_XOP (HOST_WIDE_INT_1 << 29)
-#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
-#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
-#define PTA_RTM (HOST_WIDE_INT_1 << 32)
-#define PTA_HLE (HOST_WIDE_INT_1 << 33)
-#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
-#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
-#define PTA_ADX (HOST_WIDE_INT_1 << 36)
-#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
-#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
-#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
-#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
-#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
-#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
-#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
-#define PTA_MPX (HOST_WIDE_INT_1 << 44)
-#define PTA_SHA (HOST_WIDE_INT_1 << 45)
-#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
-#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
-#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
-#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
-#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
-#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
-#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
-#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
-#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
-#define PTA_CLWB (HOST_WIDE_INT_1 << 55)
-#define PTA_MWAITX (HOST_WIDE_INT_1 << 56)
-#define PTA_CLZERO (HOST_WIDE_INT_1 << 57)
-#define PTA_NO_80387 (HOST_WIDE_INT_1 << 58)
-#define PTA_PKU (HOST_WIDE_INT_1 << 59)
-#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
-#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
-#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
-#define PTA_SGX (HOST_WIDE_INT_1 << 63)
-
-#define PTA_CORE2 \
- (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
- | PTA_CX16 | PTA_FXSR)
-#define PTA_NEHALEM \
- (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
-#define PTA_WESTMERE \
- (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
-#define PTA_SANDYBRIDGE \
- (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
-#define PTA_IVYBRIDGE \
- (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
-#define PTA_HASWELL \
- (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
- | PTA_FMA | PTA_MOVBE | PTA_HLE)
-#define PTA_BROADWELL \
- (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
-#define PTA_SKYLAKE \
- (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
-#define PTA_SKYLAKE_AVX512 \
- (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
- | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB)
-#define PTA_CANNONLAKE \
- (PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA)
-#define PTA_KNL \
- (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
-#define PTA_BONNELL \
- (PTA_CORE2 | PTA_MOVBE)
-#define PTA_SILVERMONT \
- (PTA_WESTMERE | PTA_MOVBE | PTA_RDRND)
-#define PTA_KNM \
- (PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
-
-/* if this reaches 64, need to widen struct pta flags below */
+ wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+ wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+ wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+ wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
+ wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
+ wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
+ wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
+ wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+ wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
+ wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
+ wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+ wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+ wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
+ wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+ wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
+ wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+ wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+ wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+ wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+ wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+ wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+ wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
+ wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+ wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+ wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+ wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+ wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+ wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+ wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
+ wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
+ wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+ wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+ wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
+ wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
+ wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+ wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+ wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
+ wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+ wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+ wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+ wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+ wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+ wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+ wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+ wide_int_bitmask PTA_MPX (HOST_WIDE_INT_1U << 44);
+ wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
+ wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+ wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+ wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+ wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+ wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+ wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+ wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+ wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+ wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+ wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+ wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+ wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+ wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+ wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
+ wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+ wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+ wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+ wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+
+ wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+ wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+ | PTA_POPCNT;
+ wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+ wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+ | PTA_XSAVEOPT;
+ wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND
+ | PTA_F16C;
+ wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2
+ | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+ wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+ | PTA_RDSEED;
+ wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC
+ | PTA_XSAVES;
+ wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD
+ | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB;
+ wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
+ | PTA_AVX512IFMA | PTA_SHA;
+ wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+ | PTA_AVX512F | PTA_AVX512CD;
+ wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+ wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+ wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS
+ | PTA_AVX512VPOPCNTDQ;
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
const enum attr_cpu schedule;
- const unsigned HOST_WIDE_INT flags;
+ const wide_int_bitmask flags;
}
const processor_alias_table[] =
{
@@ -3935,7 +3928,7 @@ ix86_option_override_internal (bool main_args_p,
}
if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && !(processor_alias_table[i].flags & PTA_64BIT))
+ && !((processor_alias_table[i].flags & PTA_64BIT) != 0))
{
error ("CPU you selected does not support x86-64 "
"instruction set");
@@ -3947,195 +3940,196 @@ ix86_option_override_internal (bool main_args_p,
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
+ if (((processor_alias_table[i].flags & PTA_MMX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
+ if (((processor_alias_table[i].flags & PTA_3DNOW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
+ if (((processor_alias_table[i].flags & PTA_3DNOW_A) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
+ if (((processor_alias_table[i].flags & PTA_SSE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
+ if (((processor_alias_table[i].flags & PTA_SSE2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
- if (processor_alias_table[i].flags & PTA_SSE3
+ if (((processor_alias_table[i].flags & PTA_SSE3) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
- if (processor_alias_table[i].flags & PTA_SSSE3
+ if (((processor_alias_table[i].flags & PTA_SSSE3) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
- if (processor_alias_table[i].flags & PTA_SSE4_1
+ if (((processor_alias_table[i].flags & PTA_SSE4_1) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
- if (processor_alias_table[i].flags & PTA_SSE4_2
+ if (((processor_alias_table[i].flags & PTA_SSE4_2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
- if (processor_alias_table[i].flags & PTA_AVX
+ if (((processor_alias_table[i].flags & PTA_AVX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX;
- if (processor_alias_table[i].flags & PTA_AVX2
+ if (((processor_alias_table[i].flags & PTA_AVX2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
- if (processor_alias_table[i].flags & PTA_FMA
+ if (((processor_alias_table[i].flags & PTA_FMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA;
- if (processor_alias_table[i].flags & PTA_SSE4A
+ if (((processor_alias_table[i].flags & PTA_SSE4A) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_FMA4
+ if (((processor_alias_table[i].flags & PTA_FMA4) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
- if (processor_alias_table[i].flags & PTA_XOP
+ if (((processor_alias_table[i].flags & PTA_XOP) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP;
- if (processor_alias_table[i].flags & PTA_LWP
+ if (((processor_alias_table[i].flags & PTA_LWP) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP;
- if (processor_alias_table[i].flags & PTA_ABM
+ if (((processor_alias_table[i].flags & PTA_ABM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM;
- if (processor_alias_table[i].flags & PTA_BMI
+ if (((processor_alias_table[i].flags & PTA_BMI) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI;
- if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
+ if (((processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
- if (processor_alias_table[i].flags & PTA_TBM
+ if (((processor_alias_table[i].flags & PTA_TBM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM;
- if (processor_alias_table[i].flags & PTA_BMI2
+ if (((processor_alias_table[i].flags & PTA_BMI2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
- if (processor_alias_table[i].flags & PTA_CX16
+ if (((processor_alias_table[i].flags & PTA_CX16) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CX16))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16;
- if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
+ if (((processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
if (!(TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && (processor_alias_table[i].flags & PTA_NO_SAHF))
+ && ((processor_alias_table[i].flags & PTA_NO_SAHF) != 0))
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
- if (processor_alias_table[i].flags & PTA_MOVBE
+ if (((processor_alias_table[i].flags & PTA_MOVBE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVBE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE;
- if (processor_alias_table[i].flags & PTA_AES
+ if (((processor_alias_table[i].flags & PTA_AES) != 0)
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
ix86_isa_flags |= OPTION_MASK_ISA_AES;
- if (processor_alias_table[i].flags & PTA_SHA
+ if (((processor_alias_table[i].flags & PTA_SHA) != 0)
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SHA))
ix86_isa_flags |= OPTION_MASK_ISA_SHA;
- if (processor_alias_table[i].flags & PTA_PCLMUL
+ if (((processor_alias_table[i].flags & PTA_PCLMUL) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
- if (processor_alias_table[i].flags & PTA_FSGSBASE
+ if (((processor_alias_table[i].flags & PTA_FSGSBASE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
- if (processor_alias_table[i].flags & PTA_RDRND
+ if (((processor_alias_table[i].flags & PTA_RDRND) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
- if (processor_alias_table[i].flags & PTA_F16C
+ if (((processor_alias_table[i].flags & PTA_F16C) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C;
- if (processor_alias_table[i].flags & PTA_RTM
+ if (((processor_alias_table[i].flags & PTA_RTM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM;
- if (processor_alias_table[i].flags & PTA_HLE
+ if (((processor_alias_table[i].flags & PTA_HLE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_HLE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_HLE;
- if (processor_alias_table[i].flags & PTA_PRFCHW
+ if (((processor_alias_table[i].flags & PTA_PRFCHW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
- if (processor_alias_table[i].flags & PTA_RDSEED
+ if (((processor_alias_table[i].flags & PTA_RDSEED) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
- if (processor_alias_table[i].flags & PTA_ADX
+ if (((processor_alias_table[i].flags & PTA_ADX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ADX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX;
- if (processor_alias_table[i].flags & PTA_FXSR
+ if (((processor_alias_table[i].flags & PTA_FXSR) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FXSR))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR;
- if (processor_alias_table[i].flags & PTA_XSAVE
+ if (((processor_alias_table[i].flags & PTA_XSAVE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE;
- if (processor_alias_table[i].flags & PTA_XSAVEOPT
+ if (((processor_alias_table[i].flags & PTA_XSAVEOPT) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
- if (processor_alias_table[i].flags & PTA_AVX512F
+ if (((processor_alias_table[i].flags & PTA_AVX512F) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
- if (processor_alias_table[i].flags & PTA_AVX512ER
+ if (((processor_alias_table[i].flags & PTA_AVX512ER) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
- if (processor_alias_table[i].flags & PTA_AVX512PF
+ if (((processor_alias_table[i].flags & PTA_AVX512PF) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
- if (processor_alias_table[i].flags & PTA_AVX512CD
+ if (((processor_alias_table[i].flags & PTA_AVX512CD) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
- if (processor_alias_table[i].flags & PTA_PREFETCHWT1
+ if (((processor_alias_table[i].flags & PTA_PREFETCHWT1) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
- if (processor_alias_table[i].flags & PTA_CLWB
+ if (((processor_alias_table[i].flags & PTA_CLWB) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
- if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
+ if (((processor_alias_table[i].flags & PTA_CLFLUSHOPT) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
- if (processor_alias_table[i].flags & PTA_CLZERO
+ if (((processor_alias_table[i].flags & PTA_CLZERO) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CLZERO))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO;
- if (processor_alias_table[i].flags & PTA_XSAVEC
+ if (((processor_alias_table[i].flags & PTA_XSAVEC) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC;
- if (processor_alias_table[i].flags & PTA_XSAVES
+ if (((processor_alias_table[i].flags & PTA_XSAVES) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
- if (processor_alias_table[i].flags & PTA_AVX512DQ
+ if (((processor_alias_table[i].flags & PTA_AVX512DQ) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
- if (processor_alias_table[i].flags & PTA_AVX512BW
+ if (((processor_alias_table[i].flags & PTA_AVX512BW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
- if (processor_alias_table[i].flags & PTA_AVX512VL
+ if (((processor_alias_table[i].flags & PTA_AVX512VL) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
- if (processor_alias_table[i].flags & PTA_MPX
+ if (((processor_alias_table[i].flags & PTA_MPX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX;
- if (processor_alias_table[i].flags & PTA_AVX512VBMI
+ if (((processor_alias_table[i].flags & PTA_AVX512VBMI) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI;
- if (processor_alias_table[i].flags & PTA_AVX512IFMA
+ if (((processor_alias_table[i].flags & PTA_AVX512IFMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
- if (processor_alias_table[i].flags & PTA_AVX5124VNNIW
+ if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124VNNIW))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW;
- if (processor_alias_table[i].flags & PTA_AVX5124FMAPS
+ if (((processor_alias_table[i].flags & PTA_AVX5124FMAPS) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124FMAPS))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS;
- if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
+ if (((processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ) != 0)
&& !(opts->x_ix86_isa_flags_explicit
& OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
- if (processor_alias_table[i].flags & PTA_SGX
+ if (((processor_alias_table[i].flags & PTA_SGX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
- if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
+ if ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
x86_prefetch_sse = true;
- if (processor_alias_table[i].flags & PTA_MWAITX
+ if (((processor_alias_table[i].flags & PTA_MWAITX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MWAITX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX;
- if (processor_alias_table[i].flags & PTA_PKU
+ if (((processor_alias_table[i].flags & PTA_PKU) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
@@ -4144,7 +4138,7 @@ ix86_option_override_internal (bool main_args_p,
if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
&& !(opts_set->x_target_flags & MASK_80387))
{
- if (processor_alias_table[i].flags & PTA_NO_80387)
+ if (((processor_alias_table[i].flags & PTA_NO_80387) != 0))
opts->x_target_flags &= ~MASK_80387;
else
opts->x_target_flags |= MASK_80387;
@@ -4170,7 +4164,7 @@ ix86_option_override_internal (bool main_args_p,
if (strcmp (processor_alias_table[i].name, "generic")
&& strcmp (processor_alias_table[i].name, "intel")
&& (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT)))
+ || ((processor_alias_table[i].flags & PTA_64BIT) != 0)))
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -4203,7 +4197,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_tune = processor_alias_table[i].processor;
if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
{
- if (!(processor_alias_table[i].flags & PTA_64BIT))
+ if (!((processor_alias_table[i].flags & PTA_64BIT) != 0))
{
if (ix86_tune_defaulted)
{
@@ -4226,7 +4220,8 @@ ix86_option_override_internal (bool main_args_p,
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
if (TARGET_CMOV
- && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
+ && ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)) != 0))
x86_prefetch_sse = true;
break;
}
@@ -4241,7 +4236,7 @@ ix86_option_override_internal (bool main_args_p,
auto_vec <const char *> candidates;
for (i = 0; i < pta_size; i++)
if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT))
+ || ((processor_alias_table[i].flags & PTA_64BIT) != 0))
candidates.safe_push (processor_alias_table[i].name);
char *s;
diff --git a/gcc/wide-int-bitmask.h b/gcc/wide-int-bitmask.h
new file mode 100644
index 0000000..06f3733
--- /dev/null
+++ b/gcc/wide-int-bitmask.h
@@ -0,0 +1,145 @@
+/* Operation with 128 bit bitmask.
+ Copyright (C) 1987-2018 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_BIT_MASK_H
+#define GCC_BIT_MASK_H
+
+struct wide_int_bitmask
+{
+ inline wide_int_bitmask ();
+ inline wide_int_bitmask (uint64_t l);
+ inline wide_int_bitmask (uint64_t l, uint64_t h);
+ inline wide_int_bitmask &operator &= (wide_int_bitmask);
+ inline wide_int_bitmask &operator |= (wide_int_bitmask);
+ inline wide_int_bitmask operator ~ () const;
+ inline wide_int_bitmask operator & (wide_int_bitmask) const;
+ inline wide_int_bitmask operator | (wide_int_bitmask) const;
+ inline wide_int_bitmask operator >> (int);
+ inline wide_int_bitmask operator << (int);
+ inline bool operator == (wide_int_bitmask) const;
+ inline bool operator != (wide_int_bitmask) const;
+ uint64_t low, high;
+};
+
+inline
+wide_int_bitmask::wide_int_bitmask ()
+: low (0), high (0)
+{
+}
+
+inline
+wide_int_bitmask::wide_int_bitmask (uint64_t l)
+: low (l), high (0)
+{
+}
+
+inline
+wide_int_bitmask::wide_int_bitmask (uint64_t l, uint64_t h)
+: low (l), high (h)
+{
+}
+
+inline wide_int_bitmask &
+wide_int_bitmask::operator &= (wide_int_bitmask b)
+{
+ low &= b.low;
+ high &= b.high;
+ return *this;
+}
+
+inline wide_int_bitmask &
+wide_int_bitmask::operator |= (wide_int_bitmask b)
+{
+ low |= b.low;
+ high |= b.high;
+ return *this;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator ~ () const
+{
+ wide_int_bitmask ret (~low, ~high);
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator | (wide_int_bitmask b) const
+{
+ wide_int_bitmask ret (low | b.low, high | b.high);
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator & (wide_int_bitmask b) const
+{
+ wide_int_bitmask ret (low & b.low, high & b.high);
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator << (int amount)
+{
+ wide_int_bitmask ret;
+ if (amount >= 64)
+ {
+ ret.low = 0;
+ ret.high = low << (amount - 64);
+ }
+ else if (amount == 0)
+ ret = *this;
+ else
+ {
+ ret.low = low << amount;
+ ret.high = (low >> (64 - amount)) | (high << amount);
+ }
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator >> (int amount)
+{
+ wide_int_bitmask ret;
+ if (amount >= 64)
+ {
+ ret.low = high >> (amount - 64);
+ ret.high = 0;
+ }
+ else if (amount == 0)
+ ret = *this;
+ else
+ {
+ ret.low = (high << (64 - amount)) | (low >> amount);
+ ret.high = high >> amount;
+ }
+ return ret;
+}
+
+inline bool
+wide_int_bitmask::operator == (wide_int_bitmask b) const
+{
+ return low == b.low && high == b.high;
+}
+
+inline bool
+wide_int_bitmask::operator != (wide_int_bitmask b) const
+{
+ return low != b.low || high != b.high;
+}
+
+#endif /* ! GCC_BIT_MASK_H */
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2018-01-30 8:53 ` Koval, Julia
@ 2018-01-30 9:56 ` Jakub Jelinek
2018-01-30 12:55 ` Koval, Julia
0 siblings, 1 reply; 21+ messages in thread
From: Jakub Jelinek @ 2018-01-30 9:56 UTC (permalink / raw)
To: Koval, Julia; +Cc: Richard Biener, Uros Bizjak, GCC Patches, Kirill Yukhin
On Tue, Jan 30, 2018 at 08:35:38AM +0000, Koval, Julia wrote:
> * c-common.h (omp_clause_mask): Move to wide_int_bitmask.h
Missing dot ad the end.
+ wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
Can't all these be const wide_int_bitmask instead of just
wide_int_bitmask?
...
+
+ wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+ wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+ | PTA_POPCNT;
+ wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+ wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+ | PTA_XSAVEOPT;
+ wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND
+ | PTA_F16C;
+ wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2
+ | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+ wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+ | PTA_RDSEED;
+ wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC
+ | PTA_XSAVES;
+ wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD
+ | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB;
+ wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
+ | PTA_AVX512IFMA | PTA_SHA;
+ wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+ | PTA_AVX512F | PTA_AVX512CD;
+ wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+ wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+ wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS
+ | PTA_AVX512VPOPCNTDQ;
Likewise for these.
--- /dev/null
+++ b/gcc/wide-int-bitmask.h
@@ -0,0 +1,145 @@
+/* Operation with 128 bit bitmask.
+ Copyright (C) 1987-2018 Free Software Foundation, Inc.
Please use 2013-2018 instead, all the omp_clause_mask stuff was
introduced in 2013.
+
+#ifndef GCC_BIT_MASK_H
+#define GCC_BIT_MASK_H
The macro hasn't been renamed for the header file rename.
+
+#endif /* ! GCC_BIT_MASK_H */
Here as well. Otherwise LGTM.
Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
* RE: [patch][x86] -march=icelake
2018-01-30 9:56 ` Jakub Jelinek
@ 2018-01-30 12:55 ` Koval, Julia
2018-02-01 7:49 ` Uros Bizjak
0 siblings, 1 reply; 21+ messages in thread
From: Koval, Julia @ 2018-01-30 12:55 UTC (permalink / raw)
To: Jakub Jelinek; +Cc: Richard Biener, Uros Bizjak, GCC Patches, Kirill Yukhin
[-- Attachment #1: Type: text/plain, Size: 3984 bytes --]
Thank you for your comments, fixed them and rebased Ice Lake patch on top of it. Ok for trunk?
Bitmask patch changelog:
gcc/c-family/
* c-common.h (omp_clause_mask): Move to wide_int_bitmask.h.
gcc/
* config/i386/i386.c (ix86_option_override_internal): Change flags type to
wide_int_bitmask.
* wide-int-bitmask.h: New.
Icelake patch changelog:
gcc/
* config.gcc: Add -march=icelake.
* config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
* config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
* config/i386/i386.c (processor_costs): Add m_ICELAKE.
(PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2,
PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New.
(processor_target_table): Add icelake.
(ix86_option_override_internal): Handle new PTAs.
(get_builtin_code_for_version): Handle icelake.
(M_INTEL_COREI7_ICELAKE): New.
(fold_builtin_cpu): Handle icelake.
* config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
* doc/invoke.texi: Add -march=icelake.
gcc/testsuite/
* gcc.target/i386/funcspec-56.inc: Handle new march.
* g++.dg/ext/mv16.C: Ditto.
libgcc/
* config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.
Thanks,
Julia
> -----Original Message-----
> From: Jakub Jelinek [mailto:jakub@redhat.com]
> Sent: Tuesday, January 30, 2018 9:47 AM
> To: Koval, Julia <julia.koval@intel.com>
> Cc: Richard Biener <rguenther@suse.de>; Uros Bizjak <ubizjak@gmail.com>;
> GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
> <kirill.yukhin@gmail.com>
> Subject: Re: [patch][x86] -march=icelake
>
> On Tue, Jan 30, 2018 at 08:35:38AM +0000, Koval, Julia wrote:
> > * c-common.h (omp_clause_mask): Move to wide_int_bitmask.h
>
> Missing dot ad the end.
>
> + wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>
> Can't all these be const wide_int_bitmask instead of just
> wide_int_bitmask?
>
> ...
> +
> + wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE |
> PTA_SSE2
> + | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
> + wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
> + | PTA_POPCNT;
> + wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES |
> PTA_PCLMUL;
> + wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX |
> PTA_XSAVE
> + | PTA_XSAVEOPT;
> + wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE |
> PTA_RDRND
> + | PTA_F16C;
> + wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI |
> PTA_BMI2
> + | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
> + wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX |
> PTA_PRFCHW
> + | PTA_RDSEED;
> + wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT |
> PTA_XSAVEC
> + | PTA_XSAVES;
> + wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F |
> PTA_AVX512CD
> + | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU |
> PTA_CLWB;
> + wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 |
> PTA_AVX512VBMI
> + | PTA_AVX512IFMA | PTA_SHA;
> + wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF |
> PTA_AVX512ER
> + | PTA_AVX512F | PTA_AVX512CD;
> + wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> + wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE |
> PTA_RDRND;
> + wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW |
> PTA_AVX5124FMAPS
> + | PTA_AVX512VPOPCNTDQ;
>
> Likewise for these.
>
> --- /dev/null
> +++ b/gcc/wide-int-bitmask.h
> @@ -0,0 +1,145 @@
> +/* Operation with 128 bit bitmask.
> + Copyright (C) 1987-2018 Free Software Foundation, Inc.
>
> Please use 2013-2018 instead, all the omp_clause_mask stuff was
> introduced in 2013.
>
> +
> +#ifndef GCC_BIT_MASK_H
> +#define GCC_BIT_MASK_H
>
> The macro hasn't been renamed for the header file rename.
>
> +
> +#endif /* ! GCC_BIT_MASK_H */
>
> Here as well. Otherwise LGTM.
>
> Jakub
[-- Attachment #2: 0001-bitmask.patch --]
[-- Type: application/octet-stream, Size: 34897 bytes --]
From 6dbd3faf85e3812c1e1348dd4d565295a25e48f6 Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Tue, 30 Jan 2018 10:45:49 +0300
Subject: [PATCH 1/2] bitmask
---
gcc/c-family/c-common.h | 122 +-----------------
gcc/config/i386/i386.c | 330 ++++++++++++++++++++++++------------------------
gcc/wide-int-bitmask.h | 145 +++++++++++++++++++++
3 files changed, 310 insertions(+), 287 deletions(-)
create mode 100644 gcc/wide-int-bitmask.h
diff --git a/gcc/c-family/c-common.h b/gcc/c-family/c-common.h
index d090881..aad01fa 100644
--- a/gcc/c-family/c-common.h
+++ b/gcc/c-family/c-common.h
@@ -25,6 +25,7 @@ along with GCC; see the file COPYING3. If not see
#include "alias.h"
#include "tree.h"
#include "fold-const.h"
+#include "wide-int-bitmask.h"
/* In order for the format checking to accept the C frontend
diagnostic framework extensions, you must include this file before
@@ -1111,126 +1112,7 @@ extern void pp_dir_change (cpp_reader *, const char *);
extern bool check_missing_format_attribute (tree, tree);
/* In c-omp.c */
-struct omp_clause_mask
-{
- inline omp_clause_mask ();
- inline omp_clause_mask (uint64_t l);
- inline omp_clause_mask (uint64_t l, uint64_t h);
- inline omp_clause_mask &operator &= (omp_clause_mask);
- inline omp_clause_mask &operator |= (omp_clause_mask);
- inline omp_clause_mask operator ~ () const;
- inline omp_clause_mask operator & (omp_clause_mask) const;
- inline omp_clause_mask operator | (omp_clause_mask) const;
- inline omp_clause_mask operator >> (int);
- inline omp_clause_mask operator << (int);
- inline bool operator == (omp_clause_mask) const;
- inline bool operator != (omp_clause_mask) const;
- uint64_t low, high;
-};
-
-inline
-omp_clause_mask::omp_clause_mask ()
-{
-}
-
-inline
-omp_clause_mask::omp_clause_mask (uint64_t l)
-: low (l), high (0)
-{
-}
-
-inline
-omp_clause_mask::omp_clause_mask (uint64_t l, uint64_t h)
-: low (l), high (h)
-{
-}
-
-inline omp_clause_mask &
-omp_clause_mask::operator &= (omp_clause_mask b)
-{
- low &= b.low;
- high &= b.high;
- return *this;
-}
-
-inline omp_clause_mask &
-omp_clause_mask::operator |= (omp_clause_mask b)
-{
- low |= b.low;
- high |= b.high;
- return *this;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator ~ () const
-{
- omp_clause_mask ret (~low, ~high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator | (omp_clause_mask b) const
-{
- omp_clause_mask ret (low | b.low, high | b.high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator & (omp_clause_mask b) const
-{
- omp_clause_mask ret (low & b.low, high & b.high);
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator << (int amount)
-{
- omp_clause_mask ret;
- if (amount >= 64)
- {
- ret.low = 0;
- ret.high = low << (amount - 64);
- }
- else if (amount == 0)
- ret = *this;
- else
- {
- ret.low = low << amount;
- ret.high = (low >> (64 - amount)) | (high << amount);
- }
- return ret;
-}
-
-inline omp_clause_mask
-omp_clause_mask::operator >> (int amount)
-{
- omp_clause_mask ret;
- if (amount >= 64)
- {
- ret.low = high >> (amount - 64);
- ret.high = 0;
- }
- else if (amount == 0)
- ret = *this;
- else
- {
- ret.low = (high << (64 - amount)) | (low >> amount);
- ret.high = high >> amount;
- }
- return ret;
-}
-
-inline bool
-omp_clause_mask::operator == (omp_clause_mask b) const
-{
- return low == b.low && high == b.high;
-}
-
-inline bool
-omp_clause_mask::operator != (omp_clause_mask b) const
-{
- return low != b.low || high != b.high;
-}
+typedef wide_int_bitmask omp_clause_mask;
#define OMP_CLAUSE_MASK_1 omp_clause_mask (1)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 3653ddd..769eb03 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -90,6 +90,7 @@ along with GCC; see the file COPYING3. If not see
#include "symbol-summary.h"
#include "ipa-prop.h"
#include "ipa-fnsummary.h"
+#include "wide-int-bitmask.h"
/* This file should be included last. */
#include "target-def.h"
@@ -3381,111 +3382,104 @@ ix86_option_override_internal (bool main_args_p,
unsigned int ix86_arch_mask;
const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL);
-#define PTA_3DNOW (HOST_WIDE_INT_1 << 0)
-#define PTA_3DNOW_A (HOST_WIDE_INT_1 << 1)
-#define PTA_64BIT (HOST_WIDE_INT_1 << 2)
-#define PTA_ABM (HOST_WIDE_INT_1 << 3)
-#define PTA_AES (HOST_WIDE_INT_1 << 4)
-#define PTA_AVX (HOST_WIDE_INT_1 << 5)
-#define PTA_BMI (HOST_WIDE_INT_1 << 6)
-#define PTA_CX16 (HOST_WIDE_INT_1 << 7)
-#define PTA_F16C (HOST_WIDE_INT_1 << 8)
-#define PTA_FMA (HOST_WIDE_INT_1 << 9)
-#define PTA_FMA4 (HOST_WIDE_INT_1 << 10)
-#define PTA_FSGSBASE (HOST_WIDE_INT_1 << 11)
-#define PTA_LWP (HOST_WIDE_INT_1 << 12)
-#define PTA_LZCNT (HOST_WIDE_INT_1 << 13)
-#define PTA_MMX (HOST_WIDE_INT_1 << 14)
-#define PTA_MOVBE (HOST_WIDE_INT_1 << 15)
-#define PTA_NO_SAHF (HOST_WIDE_INT_1 << 16)
-#define PTA_PCLMUL (HOST_WIDE_INT_1 << 17)
-#define PTA_POPCNT (HOST_WIDE_INT_1 << 18)
-#define PTA_PREFETCH_SSE (HOST_WIDE_INT_1 << 19)
-#define PTA_RDRND (HOST_WIDE_INT_1 << 20)
-#define PTA_SSE (HOST_WIDE_INT_1 << 21)
-#define PTA_SSE2 (HOST_WIDE_INT_1 << 22)
-#define PTA_SSE3 (HOST_WIDE_INT_1 << 23)
-#define PTA_SSE4_1 (HOST_WIDE_INT_1 << 24)
-#define PTA_SSE4_2 (HOST_WIDE_INT_1 << 25)
-#define PTA_SSE4A (HOST_WIDE_INT_1 << 26)
-#define PTA_SSSE3 (HOST_WIDE_INT_1 << 27)
-#define PTA_TBM (HOST_WIDE_INT_1 << 28)
-#define PTA_XOP (HOST_WIDE_INT_1 << 29)
-#define PTA_AVX2 (HOST_WIDE_INT_1 << 30)
-#define PTA_BMI2 (HOST_WIDE_INT_1 << 31)
-#define PTA_RTM (HOST_WIDE_INT_1 << 32)
-#define PTA_HLE (HOST_WIDE_INT_1 << 33)
-#define PTA_PRFCHW (HOST_WIDE_INT_1 << 34)
-#define PTA_RDSEED (HOST_WIDE_INT_1 << 35)
-#define PTA_ADX (HOST_WIDE_INT_1 << 36)
-#define PTA_FXSR (HOST_WIDE_INT_1 << 37)
-#define PTA_XSAVE (HOST_WIDE_INT_1 << 38)
-#define PTA_XSAVEOPT (HOST_WIDE_INT_1 << 39)
-#define PTA_AVX512F (HOST_WIDE_INT_1 << 40)
-#define PTA_AVX512ER (HOST_WIDE_INT_1 << 41)
-#define PTA_AVX512PF (HOST_WIDE_INT_1 << 42)
-#define PTA_AVX512CD (HOST_WIDE_INT_1 << 43)
-#define PTA_MPX (HOST_WIDE_INT_1 << 44)
-#define PTA_SHA (HOST_WIDE_INT_1 << 45)
-#define PTA_PREFETCHWT1 (HOST_WIDE_INT_1 << 46)
-#define PTA_CLFLUSHOPT (HOST_WIDE_INT_1 << 47)
-#define PTA_XSAVEC (HOST_WIDE_INT_1 << 48)
-#define PTA_XSAVES (HOST_WIDE_INT_1 << 49)
-#define PTA_AVX512DQ (HOST_WIDE_INT_1 << 50)
-#define PTA_AVX512BW (HOST_WIDE_INT_1 << 51)
-#define PTA_AVX512VL (HOST_WIDE_INT_1 << 52)
-#define PTA_AVX512IFMA (HOST_WIDE_INT_1 << 53)
-#define PTA_AVX512VBMI (HOST_WIDE_INT_1 << 54)
-#define PTA_CLWB (HOST_WIDE_INT_1 << 55)
-#define PTA_MWAITX (HOST_WIDE_INT_1 << 56)
-#define PTA_CLZERO (HOST_WIDE_INT_1 << 57)
-#define PTA_NO_80387 (HOST_WIDE_INT_1 << 58)
-#define PTA_PKU (HOST_WIDE_INT_1 << 59)
-#define PTA_AVX5124VNNIW (HOST_WIDE_INT_1 << 60)
-#define PTA_AVX5124FMAPS (HOST_WIDE_INT_1 << 61)
-#define PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1 << 62)
-#define PTA_SGX (HOST_WIDE_INT_1 << 63)
-
-#define PTA_CORE2 \
- (PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2 | PTA_SSE3 | PTA_SSSE3 \
- | PTA_CX16 | PTA_FXSR)
-#define PTA_NEHALEM \
- (PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2 | PTA_POPCNT)
-#define PTA_WESTMERE \
- (PTA_NEHALEM | PTA_AES | PTA_PCLMUL)
-#define PTA_SANDYBRIDGE \
- (PTA_WESTMERE | PTA_AVX | PTA_XSAVE | PTA_XSAVEOPT)
-#define PTA_IVYBRIDGE \
- (PTA_SANDYBRIDGE | PTA_FSGSBASE | PTA_RDRND | PTA_F16C)
-#define PTA_HASWELL \
- (PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI | PTA_BMI2 | PTA_LZCNT \
- | PTA_FMA | PTA_MOVBE | PTA_HLE)
-#define PTA_BROADWELL \
- (PTA_HASWELL | PTA_ADX | PTA_PRFCHW | PTA_RDSEED)
-#define PTA_SKYLAKE \
- (PTA_BROADWELL | PTA_CLFLUSHOPT | PTA_XSAVEC | PTA_XSAVES)
-#define PTA_SKYLAKE_AVX512 \
- (PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL \
- | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU | PTA_CLWB)
-#define PTA_CANNONLAKE \
- (PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA)
-#define PTA_KNL \
- (PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD)
-#define PTA_BONNELL \
- (PTA_CORE2 | PTA_MOVBE)
-#define PTA_SILVERMONT \
- (PTA_WESTMERE | PTA_MOVBE | PTA_RDRND)
-#define PTA_KNM \
- (PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ)
-
-/* if this reaches 64, need to widen struct pta flags below */
+ const wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
+ const wide_int_bitmask PTA_3DNOW_A (HOST_WIDE_INT_1U << 1);
+ const wide_int_bitmask PTA_64BIT (HOST_WIDE_INT_1U << 2);
+ const wide_int_bitmask PTA_ABM (HOST_WIDE_INT_1U << 3);
+ const wide_int_bitmask PTA_AES (HOST_WIDE_INT_1U << 4);
+ const wide_int_bitmask PTA_AVX (HOST_WIDE_INT_1U << 5);
+ const wide_int_bitmask PTA_BMI (HOST_WIDE_INT_1U << 6);
+ const wide_int_bitmask PTA_CX16 (HOST_WIDE_INT_1U << 7);
+ const wide_int_bitmask PTA_F16C (HOST_WIDE_INT_1U << 8);
+ const wide_int_bitmask PTA_FMA (HOST_WIDE_INT_1U << 9);
+ const wide_int_bitmask PTA_FMA4 (HOST_WIDE_INT_1U << 10);
+ const wide_int_bitmask PTA_FSGSBASE (HOST_WIDE_INT_1U << 11);
+ const wide_int_bitmask PTA_LWP (HOST_WIDE_INT_1U << 12);
+ const wide_int_bitmask PTA_LZCNT (HOST_WIDE_INT_1U << 13);
+ const wide_int_bitmask PTA_MMX (HOST_WIDE_INT_1U << 14);
+ const wide_int_bitmask PTA_MOVBE (HOST_WIDE_INT_1U << 15);
+ const wide_int_bitmask PTA_NO_SAHF (HOST_WIDE_INT_1U << 16);
+ const wide_int_bitmask PTA_PCLMUL (HOST_WIDE_INT_1U << 17);
+ const wide_int_bitmask PTA_POPCNT (HOST_WIDE_INT_1U << 18);
+ const wide_int_bitmask PTA_PREFETCH_SSE (HOST_WIDE_INT_1U << 19);
+ const wide_int_bitmask PTA_RDRND (HOST_WIDE_INT_1U << 20);
+ const wide_int_bitmask PTA_SSE (HOST_WIDE_INT_1U << 21);
+ const wide_int_bitmask PTA_SSE2 (HOST_WIDE_INT_1U << 22);
+ const wide_int_bitmask PTA_SSE3 (HOST_WIDE_INT_1U << 23);
+ const wide_int_bitmask PTA_SSE4_1 (HOST_WIDE_INT_1U << 24);
+ const wide_int_bitmask PTA_SSE4_2 (HOST_WIDE_INT_1U << 25);
+ const wide_int_bitmask PTA_SSE4A (HOST_WIDE_INT_1U << 26);
+ const wide_int_bitmask PTA_SSSE3 (HOST_WIDE_INT_1U << 27);
+ const wide_int_bitmask PTA_TBM (HOST_WIDE_INT_1U << 28);
+ const wide_int_bitmask PTA_XOP (HOST_WIDE_INT_1U << 29);
+ const wide_int_bitmask PTA_AVX2 (HOST_WIDE_INT_1U << 30);
+ const wide_int_bitmask PTA_BMI2 (HOST_WIDE_INT_1U << 31);
+ const wide_int_bitmask PTA_RTM (HOST_WIDE_INT_1U << 32);
+ const wide_int_bitmask PTA_HLE (HOST_WIDE_INT_1U << 33);
+ const wide_int_bitmask PTA_PRFCHW (HOST_WIDE_INT_1U << 34);
+ const wide_int_bitmask PTA_RDSEED (HOST_WIDE_INT_1U << 35);
+ const wide_int_bitmask PTA_ADX (HOST_WIDE_INT_1U << 36);
+ const wide_int_bitmask PTA_FXSR (HOST_WIDE_INT_1U << 37);
+ const wide_int_bitmask PTA_XSAVE (HOST_WIDE_INT_1U << 38);
+ const wide_int_bitmask PTA_XSAVEOPT (HOST_WIDE_INT_1U << 39);
+ const wide_int_bitmask PTA_AVX512F (HOST_WIDE_INT_1U << 40);
+ const wide_int_bitmask PTA_AVX512ER (HOST_WIDE_INT_1U << 41);
+ const wide_int_bitmask PTA_AVX512PF (HOST_WIDE_INT_1U << 42);
+ const wide_int_bitmask PTA_AVX512CD (HOST_WIDE_INT_1U << 43);
+ const wide_int_bitmask PTA_MPX (HOST_WIDE_INT_1U << 44);
+ const wide_int_bitmask PTA_SHA (HOST_WIDE_INT_1U << 45);
+ const wide_int_bitmask PTA_PREFETCHWT1 (HOST_WIDE_INT_1U << 46);
+ const wide_int_bitmask PTA_CLFLUSHOPT (HOST_WIDE_INT_1U << 47);
+ const wide_int_bitmask PTA_XSAVEC (HOST_WIDE_INT_1U << 48);
+ const wide_int_bitmask PTA_XSAVES (HOST_WIDE_INT_1U << 49);
+ const wide_int_bitmask PTA_AVX512DQ (HOST_WIDE_INT_1U << 50);
+ const wide_int_bitmask PTA_AVX512BW (HOST_WIDE_INT_1U << 51);
+ const wide_int_bitmask PTA_AVX512VL (HOST_WIDE_INT_1U << 52);
+ const wide_int_bitmask PTA_AVX512IFMA (HOST_WIDE_INT_1U << 53);
+ const wide_int_bitmask PTA_AVX512VBMI (HOST_WIDE_INT_1U << 54);
+ const wide_int_bitmask PTA_CLWB (HOST_WIDE_INT_1U << 55);
+ const wide_int_bitmask PTA_MWAITX (HOST_WIDE_INT_1U << 56);
+ const wide_int_bitmask PTA_CLZERO (HOST_WIDE_INT_1U << 57);
+ const wide_int_bitmask PTA_NO_80387 (HOST_WIDE_INT_1U << 58);
+ const wide_int_bitmask PTA_PKU (HOST_WIDE_INT_1U << 59);
+ const wide_int_bitmask PTA_AVX5124VNNIW (HOST_WIDE_INT_1U << 60);
+ const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
+ const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
+ const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+
+ const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
+ | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
+ const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
+ | PTA_POPCNT;
+ const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+ const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
+ | PTA_XSAVEOPT;
+ const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
+ | PTA_RDRND | PTA_F16C;
+ const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
+ | PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
+ const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
+ | PTA_RDSEED;
+ const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+ | PTA_XSAVEC | PTA_XSAVES;
+ const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
+ | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
+ | PTA_CLWB;
+ const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
+ | PTA_AVX512IFMA | PTA_SHA;
+ const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
+ | PTA_AVX512F | PTA_AVX512CD;
+ const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
+ const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
+ const wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
+ | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
static struct pta
{
const char *const name; /* processor name or nickname. */
const enum processor_type processor;
const enum attr_cpu schedule;
- const unsigned HOST_WIDE_INT flags;
+ const wide_int_bitmask flags;
}
const processor_alias_table[] =
{
@@ -3935,7 +3929,7 @@ ix86_option_override_internal (bool main_args_p,
}
if (TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && !(processor_alias_table[i].flags & PTA_64BIT))
+ && !((processor_alias_table[i].flags & PTA_64BIT) != 0))
{
error ("CPU you selected does not support x86-64 "
"instruction set");
@@ -3947,195 +3941,196 @@ ix86_option_override_internal (bool main_args_p,
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
- if (processor_alias_table[i].flags & PTA_MMX
+ if (((processor_alias_table[i].flags & PTA_MMX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_MMX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_MMX;
- if (processor_alias_table[i].flags & PTA_3DNOW
+ if (((processor_alias_table[i].flags & PTA_3DNOW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW;
- if (processor_alias_table[i].flags & PTA_3DNOW_A
+ if (((processor_alias_table[i].flags & PTA_3DNOW_A) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_3DNOW_A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_A;
- if (processor_alias_table[i].flags & PTA_SSE
+ if (((processor_alias_table[i].flags & PTA_SSE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE;
- if (processor_alias_table[i].flags & PTA_SSE2
+ if (((processor_alias_table[i].flags & PTA_SSE2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
- if (processor_alias_table[i].flags & PTA_SSE3
+ if (((processor_alias_table[i].flags & PTA_SSE3) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
- if (processor_alias_table[i].flags & PTA_SSSE3
+ if (((processor_alias_table[i].flags & PTA_SSSE3) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSSE3))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
- if (processor_alias_table[i].flags & PTA_SSE4_1
+ if (((processor_alias_table[i].flags & PTA_SSE4_1) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
- if (processor_alias_table[i].flags & PTA_SSE4_2
+ if (((processor_alias_table[i].flags & PTA_SSE4_2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4_2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2;
- if (processor_alias_table[i].flags & PTA_AVX
+ if (((processor_alias_table[i].flags & PTA_AVX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX;
- if (processor_alias_table[i].flags & PTA_AVX2
+ if (((processor_alias_table[i].flags & PTA_AVX2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2;
- if (processor_alias_table[i].flags & PTA_FMA
+ if (((processor_alias_table[i].flags & PTA_FMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA;
- if (processor_alias_table[i].flags & PTA_SSE4A
+ if (((processor_alias_table[i].flags & PTA_SSE4A) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_FMA4
+ if (((processor_alias_table[i].flags & PTA_FMA4) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FMA4))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FMA4;
- if (processor_alias_table[i].flags & PTA_XOP
+ if (((processor_alias_table[i].flags & PTA_XOP) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XOP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XOP;
- if (processor_alias_table[i].flags & PTA_LWP
+ if (((processor_alias_table[i].flags & PTA_LWP) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LWP))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LWP;
- if (processor_alias_table[i].flags & PTA_ABM
+ if (((processor_alias_table[i].flags & PTA_ABM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ABM;
- if (processor_alias_table[i].flags & PTA_BMI
+ if (((processor_alias_table[i].flags & PTA_BMI) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI;
- if (processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)
+ if (((processor_alias_table[i].flags & (PTA_LZCNT | PTA_ABM)) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_LZCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_LZCNT;
- if (processor_alias_table[i].flags & PTA_TBM
+ if (((processor_alias_table[i].flags & PTA_TBM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_TBM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_TBM;
- if (processor_alias_table[i].flags & PTA_BMI2
+ if (((processor_alias_table[i].flags & PTA_BMI2) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_BMI2))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_BMI2;
- if (processor_alias_table[i].flags & PTA_CX16
+ if (((processor_alias_table[i].flags & PTA_CX16) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CX16))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CX16;
- if (processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)
+ if (((processor_alias_table[i].flags & (PTA_POPCNT | PTA_ABM)) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_POPCNT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_POPCNT;
if (!(TARGET_64BIT_P (opts->x_ix86_isa_flags)
- && (processor_alias_table[i].flags & PTA_NO_SAHF))
+ && ((processor_alias_table[i].flags & PTA_NO_SAHF) != 0))
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_SAHF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_SAHF;
- if (processor_alias_table[i].flags & PTA_MOVBE
+ if (((processor_alias_table[i].flags & PTA_MOVBE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MOVBE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MOVBE;
- if (processor_alias_table[i].flags & PTA_AES
+ if (((processor_alias_table[i].flags & PTA_AES) != 0)
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_AES))
ix86_isa_flags |= OPTION_MASK_ISA_AES;
- if (processor_alias_table[i].flags & PTA_SHA
+ if (((processor_alias_table[i].flags & PTA_SHA) != 0)
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SHA))
ix86_isa_flags |= OPTION_MASK_ISA_SHA;
- if (processor_alias_table[i].flags & PTA_PCLMUL
+ if (((processor_alias_table[i].flags & PTA_PCLMUL) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PCLMUL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PCLMUL;
- if (processor_alias_table[i].flags & PTA_FSGSBASE
+ if (((processor_alias_table[i].flags & PTA_FSGSBASE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FSGSBASE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FSGSBASE;
- if (processor_alias_table[i].flags & PTA_RDRND
+ if (((processor_alias_table[i].flags & PTA_RDRND) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDRND))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDRND;
- if (processor_alias_table[i].flags & PTA_F16C
+ if (((processor_alias_table[i].flags & PTA_F16C) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_F16C))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_F16C;
- if (processor_alias_table[i].flags & PTA_RTM
+ if (((processor_alias_table[i].flags & PTA_RTM) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RTM))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RTM;
- if (processor_alias_table[i].flags & PTA_HLE
+ if (((processor_alias_table[i].flags & PTA_HLE) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_HLE))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_HLE;
- if (processor_alias_table[i].flags & PTA_PRFCHW
+ if (((processor_alias_table[i].flags & PTA_PRFCHW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PRFCHW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PRFCHW;
- if (processor_alias_table[i].flags & PTA_RDSEED
+ if (((processor_alias_table[i].flags & PTA_RDSEED) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_RDSEED))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_RDSEED;
- if (processor_alias_table[i].flags & PTA_ADX
+ if (((processor_alias_table[i].flags & PTA_ADX) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_ADX))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_ADX;
- if (processor_alias_table[i].flags & PTA_FXSR
+ if (((processor_alias_table[i].flags & PTA_FXSR) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_FXSR))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_FXSR;
- if (processor_alias_table[i].flags & PTA_XSAVE
+ if (((processor_alias_table[i].flags & PTA_XSAVE) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVE))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVE;
- if (processor_alias_table[i].flags & PTA_XSAVEOPT
+ if (((processor_alias_table[i].flags & PTA_XSAVEOPT) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEOPT;
- if (processor_alias_table[i].flags & PTA_AVX512F
+ if (((processor_alias_table[i].flags & PTA_AVX512F) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512F))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512F;
- if (processor_alias_table[i].flags & PTA_AVX512ER
+ if (((processor_alias_table[i].flags & PTA_AVX512ER) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512ER))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512ER;
- if (processor_alias_table[i].flags & PTA_AVX512PF
+ if (((processor_alias_table[i].flags & PTA_AVX512PF) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512PF))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512PF;
- if (processor_alias_table[i].flags & PTA_AVX512CD
+ if (((processor_alias_table[i].flags & PTA_AVX512CD) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512CD))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512CD;
- if (processor_alias_table[i].flags & PTA_PREFETCHWT1
+ if (((processor_alias_table[i].flags & PTA_PREFETCHWT1) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PREFETCHWT1))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PREFETCHWT1;
- if (processor_alias_table[i].flags & PTA_CLWB
+ if (((processor_alias_table[i].flags & PTA_CLWB) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLWB))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLWB;
- if (processor_alias_table[i].flags & PTA_CLFLUSHOPT
+ if (((processor_alias_table[i].flags & PTA_CLFLUSHOPT) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_CLFLUSHOPT))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_CLFLUSHOPT;
- if (processor_alias_table[i].flags & PTA_CLZERO
+ if (((processor_alias_table[i].flags & PTA_CLZERO) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_CLZERO))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_CLZERO;
- if (processor_alias_table[i].flags & PTA_XSAVEC
+ if (((processor_alias_table[i].flags & PTA_XSAVEC) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVEC))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVEC;
- if (processor_alias_table[i].flags & PTA_XSAVES
+ if (((processor_alias_table[i].flags & PTA_XSAVES) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_XSAVES))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_XSAVES;
- if (processor_alias_table[i].flags & PTA_AVX512DQ
+ if (((processor_alias_table[i].flags & PTA_AVX512DQ) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512DQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512DQ;
- if (processor_alias_table[i].flags & PTA_AVX512BW
+ if (((processor_alias_table[i].flags & PTA_AVX512BW) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512BW))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BW;
- if (processor_alias_table[i].flags & PTA_AVX512VL
+ if (((processor_alias_table[i].flags & PTA_AVX512VL) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VL))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VL;
- if (processor_alias_table[i].flags & PTA_MPX
+ if (((processor_alias_table[i].flags & PTA_MPX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MPX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MPX;
- if (processor_alias_table[i].flags & PTA_AVX512VBMI
+ if (((processor_alias_table[i].flags & PTA_AVX512VBMI) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VBMI))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI;
- if (processor_alias_table[i].flags & PTA_AVX512IFMA
+ if (((processor_alias_table[i].flags & PTA_AVX512IFMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
- if (processor_alias_table[i].flags & PTA_AVX5124VNNIW
+ if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124VNNIW))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124VNNIW;
- if (processor_alias_table[i].flags & PTA_AVX5124FMAPS
+ if (((processor_alias_table[i].flags & PTA_AVX5124FMAPS) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
& OPTION_MASK_ISA_AVX5124FMAPS))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_AVX5124FMAPS;
- if (processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ
+ if (((processor_alias_table[i].flags & PTA_AVX512VPOPCNTDQ) != 0)
&& !(opts->x_ix86_isa_flags_explicit
& OPTION_MASK_ISA_AVX512VPOPCNTDQ))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VPOPCNTDQ;
- if (processor_alias_table[i].flags & PTA_SGX
+ if (((processor_alias_table[i].flags & PTA_SGX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
- if (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE))
+ if ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
x86_prefetch_sse = true;
- if (processor_alias_table[i].flags & PTA_MWAITX
+ if (((processor_alias_table[i].flags & PTA_MWAITX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_MWAITX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_MWAITX;
- if (processor_alias_table[i].flags & PTA_PKU
+ if (((processor_alias_table[i].flags & PTA_PKU) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
@@ -4144,7 +4139,7 @@ ix86_option_override_internal (bool main_args_p,
if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
&& !(opts_set->x_target_flags & MASK_80387))
{
- if (processor_alias_table[i].flags & PTA_NO_80387)
+ if (((processor_alias_table[i].flags & PTA_NO_80387) != 0))
opts->x_target_flags &= ~MASK_80387;
else
opts->x_target_flags |= MASK_80387;
@@ -4170,7 +4165,7 @@ ix86_option_override_internal (bool main_args_p,
if (strcmp (processor_alias_table[i].name, "generic")
&& strcmp (processor_alias_table[i].name, "intel")
&& (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT)))
+ || ((processor_alias_table[i].flags & PTA_64BIT) != 0)))
candidates.safe_push (processor_alias_table[i].name);
char *s;
@@ -4203,7 +4198,7 @@ ix86_option_override_internal (bool main_args_p,
ix86_tune = processor_alias_table[i].processor;
if (TARGET_64BIT_P (opts->x_ix86_isa_flags))
{
- if (!(processor_alias_table[i].flags & PTA_64BIT))
+ if (!((processor_alias_table[i].flags & PTA_64BIT) != 0))
{
if (ix86_tune_defaulted)
{
@@ -4226,7 +4221,8 @@ ix86_option_override_internal (bool main_args_p,
However, the VIA C3 gives a SIGILL, so we only do that for i686 and
higher processors. */
if (TARGET_CMOV
- && (processor_alias_table[i].flags & (PTA_PREFETCH_SSE | PTA_SSE)))
+ && ((processor_alias_table[i].flags
+ & (PTA_PREFETCH_SSE | PTA_SSE)) != 0))
x86_prefetch_sse = true;
break;
}
@@ -4241,7 +4237,7 @@ ix86_option_override_internal (bool main_args_p,
auto_vec <const char *> candidates;
for (i = 0; i < pta_size; i++)
if (!TARGET_64BIT_P (opts->x_ix86_isa_flags)
- || (processor_alias_table[i].flags & PTA_64BIT))
+ || ((processor_alias_table[i].flags & PTA_64BIT) != 0))
candidates.safe_push (processor_alias_table[i].name);
char *s;
diff --git a/gcc/wide-int-bitmask.h b/gcc/wide-int-bitmask.h
new file mode 100644
index 0000000..517bb2a
--- /dev/null
+++ b/gcc/wide-int-bitmask.h
@@ -0,0 +1,145 @@
+/* Operation with 128 bit bitmask.
+ Copyright (C) 2013-2018 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify it under
+the terms of the GNU General Public License as published by the Free
+Software Foundation; either version 3, or (at your option) any later
+version.
+
+GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+WARRANTY; without even the implied warranty of MERCHANTABILITY or
+FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3. If not see
+<http://www.gnu.org/licenses/>. */
+
+#ifndef GCC_WIDE_INT_BITMASK_H
+#define GCC_WIDE_INT_BITMASK_H
+
+struct wide_int_bitmask
+{
+ inline wide_int_bitmask ();
+ inline wide_int_bitmask (uint64_t l);
+ inline wide_int_bitmask (uint64_t l, uint64_t h);
+ inline wide_int_bitmask &operator &= (wide_int_bitmask);
+ inline wide_int_bitmask &operator |= (wide_int_bitmask);
+ inline wide_int_bitmask operator ~ () const;
+ inline wide_int_bitmask operator & (wide_int_bitmask) const;
+ inline wide_int_bitmask operator | (wide_int_bitmask) const;
+ inline wide_int_bitmask operator >> (int);
+ inline wide_int_bitmask operator << (int);
+ inline bool operator == (wide_int_bitmask) const;
+ inline bool operator != (wide_int_bitmask) const;
+ uint64_t low, high;
+};
+
+inline
+wide_int_bitmask::wide_int_bitmask ()
+: low (0), high (0)
+{
+}
+
+inline
+wide_int_bitmask::wide_int_bitmask (uint64_t l)
+: low (l), high (0)
+{
+}
+
+inline
+wide_int_bitmask::wide_int_bitmask (uint64_t l, uint64_t h)
+: low (l), high (h)
+{
+}
+
+inline wide_int_bitmask &
+wide_int_bitmask::operator &= (wide_int_bitmask b)
+{
+ low &= b.low;
+ high &= b.high;
+ return *this;
+}
+
+inline wide_int_bitmask &
+wide_int_bitmask::operator |= (wide_int_bitmask b)
+{
+ low |= b.low;
+ high |= b.high;
+ return *this;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator ~ () const
+{
+ wide_int_bitmask ret (~low, ~high);
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator | (wide_int_bitmask b) const
+{
+ wide_int_bitmask ret (low | b.low, high | b.high);
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator & (wide_int_bitmask b) const
+{
+ wide_int_bitmask ret (low & b.low, high & b.high);
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator << (int amount)
+{
+ wide_int_bitmask ret;
+ if (amount >= 64)
+ {
+ ret.low = 0;
+ ret.high = low << (amount - 64);
+ }
+ else if (amount == 0)
+ ret = *this;
+ else
+ {
+ ret.low = low << amount;
+ ret.high = (low >> (64 - amount)) | (high << amount);
+ }
+ return ret;
+}
+
+inline wide_int_bitmask
+wide_int_bitmask::operator >> (int amount)
+{
+ wide_int_bitmask ret;
+ if (amount >= 64)
+ {
+ ret.low = high >> (amount - 64);
+ ret.high = 0;
+ }
+ else if (amount == 0)
+ ret = *this;
+ else
+ {
+ ret.low = (high << (64 - amount)) | (low >> amount);
+ ret.high = high >> amount;
+ }
+ return ret;
+}
+
+inline bool
+wide_int_bitmask::operator == (wide_int_bitmask b) const
+{
+ return low == b.low && high == b.high;
+}
+
+inline bool
+wide_int_bitmask::operator != (wide_int_bitmask b) const
+{
+ return low != b.low || high != b.high;
+}
+
+#endif /* ! GCC_WIDE_INT_BITMASK_H */
--
2.5.5
[-- Attachment #3: 0002-icelake_rebased.patch --]
[-- Type: application/octet-stream, Size: 12876 bytes --]
From 891868ce8e040ba17d9777d61490160cfb6bc91c Mon Sep 17 00:00:00 2001
From: julia <jkoval@gkticlel801.igk.intel.com>
Date: Tue, 30 Jan 2018 12:27:31 +0300
Subject: [PATCH 2/2] icelake_rebased
---
gcc/config.gcc | 2 +-
gcc/config/i386/driver-i386.c | 5 ++-
gcc/config/i386/i386-c.c | 7 ++++
gcc/config/i386/i386.c | 49 ++++++++++++++++++++++++---
gcc/config/i386/i386.h | 2 ++
gcc/doc/invoke.texi | 8 +++++
gcc/testsuite/g++.dg/ext/mv16.C | 6 ++++
gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 +
libgcc/config/i386/cpuinfo.h | 1 +
9 files changed, 75 insertions(+), 6 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index ec6822b..c52fecf 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -635,7 +635,7 @@ x86_64_archs="amdfam10 athlon64 athlon64-sse3 barcelona bdver1 bdver2 \
bdver3 bdver4 znver1 btver1 btver2 k8 k8-sse3 opteron opteron-sse3 nocona \
core2 corei7 corei7-avx core-avx-i core-avx2 atom slm nehalem westmere \
sandybridge ivybridge haswell broadwell bonnell silvermont knl knm \
-skylake-avx512 cannonlake x86-64 native"
+skylake-avx512 cannonlake icelake x86-64 native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c
index 5b20575..ca1a2e0 100644
--- a/gcc/config/i386/driver-i386.c
+++ b/gcc/config/i386/driver-i386.c
@@ -822,8 +822,11 @@ const char *host_detect_local_cpu (int argc, const char **argv)
if (arch)
{
/* This is unknown family 0x6 CPU. */
+ /* Assume Ice Lake. */
+ if (has_gfni)
+ cpu = "icelake";
/* Assume Cannon Lake. */
- if (has_avx512vbmi)
+ else if (has_avx512vbmi)
cpu = "cannonlake";
/* Assume Knights Mill. */
else if (has_avx5124vnniw)
diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c
index 78dd657..c0b4ffe 100644
--- a/gcc/config/i386/i386-c.c
+++ b/gcc/config/i386/i386-c.c
@@ -190,6 +190,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
def_or_undef (parse_in, "__cannonlake");
def_or_undef (parse_in, "__cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__icelake");
+ def_or_undef (parse_in, "__icelake__");
+ break;
/* use PROCESSOR_max to not set/unset the arch macro. */
case PROCESSOR_max:
break;
@@ -311,6 +315,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag,
case PROCESSOR_CANNONLAKE:
def_or_undef (parse_in, "__tune_cannonlake__");
break;
+ case PROCESSOR_ICELAKE:
+ def_or_undef (parse_in, "__tune_icelake__");
+ break;
case PROCESSOR_LAKEMONT:
def_or_undef (parse_in, "__tune_lakemont__");
break;
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 769eb03..3dc0a55 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -146,6 +146,7 @@ const struct processor_costs *ix86_cost = NULL;
#define m_KNM (1U<<PROCESSOR_KNM)
#define m_SKYLAKE_AVX512 (1U<<PROCESSOR_SKYLAKE_AVX512)
#define m_CANNONLAKE (1U<<PROCESSOR_CANNONLAKE)
+#define m_ICELAKE (1U<<PROCESSOR_ICELAKE)
#define m_INTEL (1U<<PROCESSOR_INTEL)
#define m_GEODE (1U<<PROCESSOR_GEODE)
@@ -858,7 +859,8 @@ static const struct ptt processor_target_table[PROCESSOR_max] =
{"knl", &slm_cost, 16, 15, 16, 7, 16},
{"knm", &slm_cost, 16, 15, 16, 7, 16},
{"skylake-avx512", &skylake_cost, 16, 10, 16, 10, 16},
- {"cannonlake", &core_cost, 16, 10, 16, 10, 16},
+ {"cannonlake", &skylake_cost, 16, 10, 16, 10, 16},
+ {"icelake", &skylake_cost, 16, 10, 16, 10, 16},
{"intel", &intel_cost, 16, 15, 16, 7, 16},
{"geode", &geode_cost, 0, 0, 0, 0, 0},
{"k6", &k6_cost, 32, 7, 32, 7, 32},
@@ -3446,6 +3448,13 @@ ix86_option_override_internal (bool main_args_p,
const wide_int_bitmask PTA_AVX5124FMAPS (HOST_WIDE_INT_1U << 61);
const wide_int_bitmask PTA_AVX512VPOPCNTDQ (HOST_WIDE_INT_1U << 62);
const wide_int_bitmask PTA_SGX (HOST_WIDE_INT_1U << 63);
+ const wide_int_bitmask PTA_AVX512VNNI (0, HOST_WIDE_INT_1U);
+ const wide_int_bitmask PTA_GFNI (0, HOST_WIDE_INT_1U << 1);
+ const wide_int_bitmask PTA_VAES (0, HOST_WIDE_INT_1U << 2);
+ const wide_int_bitmask PTA_AVX512VBMI2 (0, HOST_WIDE_INT_1U << 3);
+ const wide_int_bitmask PTA_VPCLMULQDQ (0, HOST_WIDE_INT_1U << 4);
+ const wide_int_bitmask PTA_AVX512BITALG (0, HOST_WIDE_INT_1U << 5);
+ const wide_int-bitmask PTA_RDPID (0, HOST_WIDE_INT_1U << 6);
const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
@@ -3467,6 +3476,9 @@ ix86_option_override_internal (bool main_args_p,
| PTA_CLWB;
const wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 | PTA_AVX512VBMI
| PTA_AVX512IFMA | PTA_SHA;
+ const wide_int_bitmask PTA_ICELAKE = PTA_CANNONLAKE | PTA_AVX512VNNI
+ | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG
+ | PTA_RDPID;
const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
| PTA_AVX512F | PTA_AVX512CD;
const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
@@ -3537,7 +3549,8 @@ ix86_option_override_internal (bool main_args_p,
{"skylake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_SKYLAKE},
{"skylake-avx512", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL,
PTA_SKYLAKE_AVX512},
- {"cannonlake", PROCESSOR_HASWELL, CPU_HASWELL, PTA_CANNONLAKE},
+ {"cannonlake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_CANNONLAKE},
+ {"icelake", PROCESSOR_SKYLAKE_AVX512, CPU_HASWELL, PTA_ICELAKE},
{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL},
{"silvermont", PROCESSOR_SILVERMONT, CPU_SLM, PTA_SILVERMONT},
@@ -4107,6 +4120,23 @@ ix86_option_override_internal (bool main_args_p,
if (((processor_alias_table[i].flags & PTA_AVX512IFMA) != 0)
&& !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512IFMA))
opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512IFMA;
+ if (((processor_alias_table[i].flags & PTA_AVX512VNNI) != 0)
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_AVX512VNNI))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VNNI;
+ if (((processor_alias_table[i].flags & PTA_GFNI) != 0)
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_GFNI))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_GFNI;
+ if (((processor_alias_table[i].flags & PTA_AVX512VBMI2) != 0)
+ && !(opts->x_ix86_isa_flags_explicit
+ & OPTION_MASK_ISA_AVX512VBMI2))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512VBMI2;
+ if (((processor_alias_table[i].flags & PTA_VPCLMULQDQ) != 0)
+ && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_VPCLMULQDQ))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_VPCLMULQDQ;
+ if (((processor_alias_table[i].flags & PTA_AVX512BITALG) != 0)
+ && !(opts->x_ix86_isa_flags_explicit
+ & OPTION_MASK_ISA_AVX512BITALG))
+ opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX512BITALG;
if (((processor_alias_table[i].flags & PTA_AVX5124VNNIW) != 0)
&& !(opts->x_ix86_isa_flags2_explicit
@@ -4123,6 +4153,12 @@ ix86_option_override_internal (bool main_args_p,
if (((processor_alias_table[i].flags & PTA_SGX) != 0)
&& !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_SGX))
opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_SGX;
+ if (((processor_alias_table[i].flags & PTA_VAES) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_VAES))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_VAES;
+ if (((processor_alias_table[i].flags & PTA_RDPID) != 0)
+ && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA_RDPID))
+ opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA_RDPID;
if ((processor_alias_table[i].flags
& (PTA_PREFETCH_SSE | PTA_SSE)) != 0)
@@ -32063,7 +32099,10 @@ get_builtin_code_for_version (tree decl, tree *predicate_list)
break;
case PROCESSOR_HASWELL:
case PROCESSOR_SKYLAKE_AVX512:
- if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VBMI)
+ if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_GFNI)
+ arg_str = "icelake";
+ else if (new_target->x_ix86_isa_flags
+ & OPTION_MASK_ISA_AVX512VBMI)
arg_str = "cannonlake";
else if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)
arg_str = "skylake-avx512";
@@ -32788,7 +32827,8 @@ fold_builtin_cpu (tree fndecl, tree *args)
M_INTEL_COREI7_BROADWELL,
M_INTEL_COREI7_SKYLAKE,
M_INTEL_COREI7_SKYLAKE_AVX512,
- M_INTEL_COREI7_CANNONLAKE
+ M_INTEL_COREI7_CANNONLAKE,
+ M_INTEL_COREI7_ICELAKE
};
static struct _arch_names_table
@@ -32813,6 +32853,7 @@ fold_builtin_cpu (tree fndecl, tree *args)
{"skylake", M_INTEL_COREI7_SKYLAKE},
{"skylake-avx512", M_INTEL_COREI7_SKYLAKE_AVX512},
{"cannonlake", M_INTEL_COREI7_CANNONLAKE},
+ {"icelake", M_INTEL_COREI7_ICELAKE},
{"bonnell", M_INTEL_BONNELL},
{"silvermont", M_INTEL_SILVERMONT},
{"knl", M_INTEL_KNL},
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 59522cc..9d86450 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -383,6 +383,7 @@ extern const struct processor_costs ix86_size_cost;
#define TARGET_KNM (ix86_tune == PROCESSOR_KNM)
#define TARGET_SKYLAKE_AVX512 (ix86_tune == PROCESSOR_SKYLAKE_AVX512)
#define TARGET_CANNONLAKE (ix86_tune == PROCESSOR_CANNONLAKE)
+#define TARGET_ICELAKE (ix86_tune == PROCESSOR_ICELAKE)
#define TARGET_INTEL (ix86_tune == PROCESSOR_INTEL)
#define TARGET_GENERIC (ix86_tune == PROCESSOR_GENERIC)
#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)
@@ -2263,6 +2264,7 @@ enum processor_type
PROCESSOR_KNM,
PROCESSOR_SKYLAKE_AVX512,
PROCESSOR_CANNONLAKE,
+ PROCESSOR_ICELAKE,
PROCESSOR_INTEL,
PROCESSOR_GEODE,
PROCESSOR_K6,
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index dbc5c47..f3d9336 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -25606,6 +25606,14 @@ RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
AVX512IFMA, SHA, CLWB and UMIP instruction set support.
+@item Icelake
+Intel Icelake Server CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2,
+SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, PKU, AVX, AVX2, AES, PCLMUL, FSGSBASE,
+RDRND, FMA, BMI, BMI2, F16C, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVEC,
+XSAVES, AVX512F, AVX512VL, AVX512BW, AVX512DQ, AVX512CD, AVX512VBMI,
+AVX512IFMA, SHA, CLWB, UMIP, RDPID, GFNI, AVX512VBMI2, AVX512VPOPCNTDQ,
+AVX512BITALG, AVX512VNNI, VPCLMULQDQ, VAES instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
diff --git a/gcc/testsuite/g++.dg/ext/mv16.C b/gcc/testsuite/g++.dg/ext/mv16.C
index 1e1ae3d..8fbdb47 100644
--- a/gcc/testsuite/g++.dg/ext/mv16.C
+++ b/gcc/testsuite/g++.dg/ext/mv16.C
@@ -60,6 +60,10 @@ int __attribute__ ((target("arch=cannonlake"))) foo () {
return 16;
}
+int __attribute__ ((target("arch=icelake"))) foo () {
+ return 17;
+}
+
int main ()
{
int val = foo ();
@@ -82,6 +86,8 @@ int main ()
assert (val == 15);
else if (__builtin_cpu_is ("cannonlake"))
assert (val == 16);
+ else if (__builtin_cpu_is ("icelake"))
+ assert (val == 17);
else
assert (val == 0);
diff --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
index ed0748b..837cdc3 100644
--- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc
+++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc
@@ -145,6 +145,7 @@ extern void test_arch_knl (void) __attribute__((__target__("arch=knl")));
extern void test_arch_knm (void) __attribute__((__target__("arch=knm")));
extern void test_arch_skylake_avx512 (void) __attribute__((__target__("arch=skylake-avx512")));
extern void test_arch_cannonlake (void) __attribute__((__target__("arch=cannonlake")));
+extern void test_arch_icelake (void) __attribute__((__target__("arch=icelake")));
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));
extern void test_arch_opteron (void) __attribute__((__target__("arch=opteron")));
diff --git a/libgcc/config/i386/cpuinfo.h b/libgcc/config/i386/cpuinfo.h
index c43d941..a247072 100644
--- a/libgcc/config/i386/cpuinfo.h
+++ b/libgcc/config/i386/cpuinfo.h
@@ -70,6 +70,7 @@ enum processor_subtypes
INTEL_COREI7_SKYLAKE,
INTEL_COREI7_SKYLAKE_AVX512,
INTEL_COREI7_CANNONLAKE,
+ INTEL_COREI7_ICELAKE,
CPU_SUBTYPE_MAX
};
--
2.5.5
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2018-01-30 12:55 ` Koval, Julia
@ 2018-02-01 7:49 ` Uros Bizjak
2018-02-01 14:02 ` Jakub Jelinek
0 siblings, 1 reply; 21+ messages in thread
From: Uros Bizjak @ 2018-02-01 7:49 UTC (permalink / raw)
To: Koval, Julia; +Cc: Jakub Jelinek, Richard Biener, GCC Patches, Kirill Yukhin
On Tue, Jan 30, 2018 at 12:53 PM, Koval, Julia <julia.koval@intel.com> wrote:
> Thank you for your comments, fixed them and rebased Ice Lake patch on top of it. Ok for trunk?
>
> Bitmask patch changelog:
>
> gcc/c-family/
> * c-common.h (omp_clause_mask): Move to wide_int_bitmask.h.
>
> gcc/
> * config/i386/i386.c (ix86_option_override_internal): Change flags type to
> wide_int_bitmask.
> * wide-int-bitmask.h: New.
>
> Icelake patch changelog:
>
> gcc/
> * config.gcc: Add -march=icelake.
> * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
> * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
> * config/i386/i386.c (processor_costs): Add m_ICELAKE.
> (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2,
> PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New.
> (processor_target_table): Add icelake.
> (ix86_option_override_internal): Handle new PTAs.
> (get_builtin_code_for_version): Handle icelake.
> (M_INTEL_COREI7_ICELAKE): New.
> (fold_builtin_cpu): Handle icelake.
> * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
> * doc/invoke.texi: Add -march=icelake.
> gcc/testsuite/
> * gcc.target/i386/funcspec-56.inc: Handle new march.
> * g++.dg/ext/mv16.C: Ditto.
> libgcc/
> * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.
x86 parts are OK, generic parts need approval from global maintainer.
Thanks,
Uros.
> Thanks,
> Julia
>
>> -----Original Message-----
>> From: Jakub Jelinek [mailto:jakub@redhat.com]
>> Sent: Tuesday, January 30, 2018 9:47 AM
>> To: Koval, Julia <julia.koval@intel.com>
>> Cc: Richard Biener <rguenther@suse.de>; Uros Bizjak <ubizjak@gmail.com>;
>> GCC Patches <gcc-patches@gcc.gnu.org>; Kirill Yukhin
>> <kirill.yukhin@gmail.com>
>> Subject: Re: [patch][x86] -march=icelake
>>
>> On Tue, Jan 30, 2018 at 08:35:38AM +0000, Koval, Julia wrote:
>> > * c-common.h (omp_clause_mask): Move to wide_int_bitmask.h
>>
>> Missing dot ad the end.
>>
>> + wide_int_bitmask PTA_3DNOW (HOST_WIDE_INT_1U << 0);
>>
>> Can't all these be const wide_int_bitmask instead of just
>> wide_int_bitmask?
>>
>> ...
>> +
>> + wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE |
>> PTA_SSE2
>> + | PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
>> + wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
>> + | PTA_POPCNT;
>> + wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES |
>> PTA_PCLMUL;
>> + wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX |
>> PTA_XSAVE
>> + | PTA_XSAVEOPT;
>> + wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE |
>> PTA_RDRND
>> + | PTA_F16C;
>> + wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI |
>> PTA_BMI2
>> + | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
>> + wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX |
>> PTA_PRFCHW
>> + | PTA_RDSEED;
>> + wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT |
>> PTA_XSAVEC
>> + | PTA_XSAVES;
>> + wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F |
>> PTA_AVX512CD
>> + | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU |
>> PTA_CLWB;
>> + wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE_AVX512 |
>> PTA_AVX512VBMI
>> + | PTA_AVX512IFMA | PTA_SHA;
>> + wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF |
>> PTA_AVX512ER
>> + | PTA_AVX512F | PTA_AVX512CD;
>> + wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
>> + wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE |
>> PTA_RDRND;
>> + wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW |
>> PTA_AVX5124FMAPS
>> + | PTA_AVX512VPOPCNTDQ;
>>
>> Likewise for these.
>>
>> --- /dev/null
>> +++ b/gcc/wide-int-bitmask.h
>> @@ -0,0 +1,145 @@
>> +/* Operation with 128 bit bitmask.
>> + Copyright (C) 1987-2018 Free Software Foundation, Inc.
>>
>> Please use 2013-2018 instead, all the omp_clause_mask stuff was
>> introduced in 2013.
>>
>> +
>> +#ifndef GCC_BIT_MASK_H
>> +#define GCC_BIT_MASK_H
>>
>> The macro hasn't been renamed for the header file rename.
>>
>> +
>> +#endif /* ! GCC_BIT_MASK_H */
>>
>> Here as well. Otherwise LGTM.
>>
>> Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [patch][x86] -march=icelake
2018-02-01 7:49 ` Uros Bizjak
@ 2018-02-01 14:02 ` Jakub Jelinek
0 siblings, 0 replies; 21+ messages in thread
From: Jakub Jelinek @ 2018-02-01 14:02 UTC (permalink / raw)
To: Uros Bizjak; +Cc: Koval, Julia, Richard Biener, GCC Patches, Kirill Yukhin
On Thu, Feb 01, 2018 at 08:49:09AM +0100, Uros Bizjak wrote:
> > gcc/c-family/
> > * c-common.h (omp_clause_mask): Move to wide_int_bitmask.h.
> >
> > gcc/
> > * config/i386/i386.c (ix86_option_override_internal): Change flags type to
> > wide_int_bitmask.
> > * wide-int-bitmask.h: New.
> >
> > Icelake patch changelog:
> >
> > gcc/
> > * config.gcc: Add -march=icelake.
> > * config/i386/driver-i386.c (host_detect_local_cpu): Detect icelake.
> > * config/i386/i386-c.c (ix86_target_macros_internal): Handle icelake.
> > * config/i386/i386.c (processor_costs): Add m_ICELAKE.
> > (PTA_ICELAKE, PTA_AVX512VNNI, PTA_GFNI, PTA_VAES, PTA_AVX512VBMI2,
> > PTA_VPCLMULQDQ, PTA_RDPID, PTA_AVX512BITALG): New.
> > (processor_target_table): Add icelake.
> > (ix86_option_override_internal): Handle new PTAs.
> > (get_builtin_code_for_version): Handle icelake.
> > (M_INTEL_COREI7_ICELAKE): New.
> > (fold_builtin_cpu): Handle icelake.
> > * config/i386/i386.h (TARGET_ICELAKE, PROCESSOR_ICELAKE): New.
> > * doc/invoke.texi: Add -march=icelake.
> > gcc/testsuite/
> > * gcc.target/i386/funcspec-56.inc: Handle new march.
> > * g++.dg/ext/mv16.C: Ditto.
> > libgcc/
> > * config/i386/cpuinfo.h (processor_subtypes): Add INTEL_COREI7_ICELAKE.
>
> x86 parts are OK, generic parts need approval from global maintainer.
The generic parts are ok as well.
Jakub
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2018-02-01 14:02 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2017-11-12 7:33 [patch][x86] -march=icelake Koval, Julia
2017-11-12 16:34 ` Uros Bizjak
2017-12-18 13:42 ` Koval, Julia
2017-12-19 8:31 ` Uros Bizjak
2017-12-19 11:55 ` Richard Biener
2017-12-19 12:34 ` Koval, Julia
2017-12-19 13:08 ` Richard Biener
2017-12-19 13:49 ` Jakub Jelinek
2018-01-22 11:46 ` Koval, Julia
2018-01-22 12:12 ` Jakub Jelinek
2018-01-22 15:10 ` Koval, Julia
2018-01-24 11:05 ` Uros Bizjak
2018-01-24 11:18 ` Jakub Jelinek
2018-01-24 11:24 ` Koval, Julia
2018-01-24 11:31 ` Richard Biener
2018-01-30 8:53 ` Koval, Julia
2018-01-30 9:56 ` Jakub Jelinek
2018-01-30 12:55 ` Koval, Julia
2018-02-01 7:49 ` Uros Bizjak
2018-02-01 14:02 ` Jakub Jelinek
2017-11-12 17:33 ` Sandra Loosemore
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