From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 43259 invoked by alias); 5 Feb 2018 22:58:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 43199 invoked by uid 89); 5 Feb 2018 22:58:02 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-10.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,KAM_LAZY_DOMAIN_SECURITY,RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.2 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 05 Feb 2018 22:57:58 +0000 Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w15Mdgpu123922 for ; Mon, 5 Feb 2018 17:57:56 -0500 Received: from e18.ny.us.ibm.com (e18.ny.us.ibm.com [129.33.205.208]) by mx0b-001b2d01.pphosted.com with ESMTP id 2fxvv2066f-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Mon, 05 Feb 2018 17:57:56 -0500 Received: from localhost by e18.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Mon, 5 Feb 2018 17:57:53 -0500 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp23034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w15MvqeX44302560; Mon, 5 Feb 2018 22:57:52 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8A84212404E; Mon, 5 Feb 2018 17:54:39 -0500 (EST) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id 585D612403F; Mon, 5 Feb 2018 17:54:39 -0500 (EST) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id D4AB549636; Mon, 5 Feb 2018 17:57:51 -0500 (EST) Date: Mon, 05 Feb 2018 22:58:00 -0000 From: Michael Meissner To: Segher Boessenkool Cc: Michael Meissner , GCC Patches , David Edelsohn , Bill Schmidt Subject: Re: [PATCH] PowerPC PR target/84154, fix floating point to small integer conversion regression Mail-Followup-To: Michael Meissner , Segher Boessenkool , GCC Patches , David Edelsohn , Bill Schmidt References: <20180201193116.GA15164@ibm-tiger.the-meissners.org> <20180205115724.GQ21977@gate.crashing.org> <20180205125457.GA20319@ibm-tiger.the-meissners.org> <20180205140131.GT21977@gate.crashing.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="M9NhX3UHpAaciwkO" Content-Disposition: inline In-Reply-To: <20180205140131.GT21977@gate.crashing.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 18020522-0044-0000-0000-000003DBFD90 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008479; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000248; SDB=6.00985479; UDB=6.00500038; IPR=6.00764850; BA=6.00005812; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00019387; XFM=3.00000015; UTC=2018-02-05 22:57:54 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18020522-0045-0000-0000-0000080B6C68 Message-Id: <20180205225751.GA11436@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-02-05_05:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1802050279 X-IsSubscribed: yes X-SW-Source: 2018-02/txt/msg00198.txt.bz2 --M9NhX3UHpAaciwkO Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 5181 On Mon, Feb 05, 2018 at 08:01:32AM -0600, Segher Boessenkool wrote: > On Mon, Feb 05, 2018 at 07:54:58AM -0500, Michael Meissner wrote: > > On Mon, Feb 05, 2018 at 05:57:25AM -0600, Segher Boessenkool wrote: > > > On Thu, Feb 01, 2018 at 02:31:17PM -0500, Michael Meissner wrote: > > > > This patch fixes the optimization regression that occurred on GCC 7 where > > > > conversions from the various floating point types to small integers would at > > > > times generate a store and a load. > > > > > > [ snip big explanation; thanks for that! ] > > > > > > Could you merge the signed and unsigned patterns, using any_fix? Or is > > > there a reason that cannot work (other than that unsigned_fix seems > > > buggy, it should say "u")? > > > > Well that's the way the instructions are. For traditional FPR instructions we > > have FCTIWZ vs. FCTIWUZ, while on the VSX side we have XSCVDPSXWS > > vs. XSCVDPUXWS. If you mean the name of the insn, I can change it if desired, > > but originally it was based on the FPR insn name. > > We have > > (define_code_attr su [(sign_extend "s") > (zero_extend "u") > (fix "s") > (unsigned_fix "s") > (float "s") > (unsigned_float "u")]) > > and "s" for unsigned_fix seems like it should be "u". Very surprising > otherwise (if this is needed in some case, it should just write "s" there > instead of ""). > > > > Okay for trunk even without that (but please try). Also okay for 7 after > > > looking for fallout. > > > > In the past, I have found that combining code iterators with two mode iterators > > has a bug where it would use the wrong code iterator, so I just avoided doing > > that. I'll see if it is still a bug. > > Hrm. If you have multiple iterators you often need to use ":" syntax, > and you might want that anyway because the precedence rules are non-obvious; > but you are hitting something else? Please open a PR if so :-) I already do use the : syntax. I found as long as I avoid putting the or in the output template (i.e. use an output statement instead of a template) it works. It only seems to fail in the IEEE128 case, and not in the SFDF case. I will submit a bug report on it after this gets checked in, as it will be simpler to provide a patch that people can test. This patch cleans up all of the {,unsigned_}fix patterns that convert to QImode or HImode. It adds the memory combiner to include SImode to the mix. While I was at it, I combined the IEEE insns to use any_fix. I have checked this patch on both little endian and big endian power8 systems, and I have have hand checked the code for power7 and power9 systems. There were no regressions in the test suite, the new tests were verified to run, and I did bootstrap builds on both systems. The big endian power8 system also 32-bit tests as well as 64-bit tests. Can I apply this patch to the trunk and after a waiting period, apply the patch to the GCC 7 branch? [gcc] 2018-02-05 Michael Meissner PR target/84154 * config/rs6000/rs6000.md (fix_trunc2): Convert from define_expand to be define_insn_and_split. Rework float/double/_Float128 conversions to QI/HI/SImode to work with both ISA 2.07 (power8) or ISA 3.0 (power9). Fix regression where conversions to QI/HImode types did a store and then a load to truncate the value. For conversions to VSX registers, don't split the insn, instead emit the code directly. Use the code iterator any_fix to combine signed and unsigned conversions. (fix_truncsi2_p8): Likewise. (fixuns_trunc2): Likewise. (fix_trunc2): Likewise. (fix_trunc2): Likewise. (fix_di2_hw): Likewise. (fixuns_di2_hw): Likewise. (fix_si2_hw): Likewise. (fixuns_si2_hw): Likewise. (fix_2_hw): Likewise. (fix_trunc2): Likewise. (fctiwz__smallint): Rename fctiwz__smallint to fix_truncsi2_p8. (fix_trunc2_internal): Delete, no longer used. (fixuns_trunc2_internal): Likewise. (fix__mem): Likewise. (fctiwz__mem): Likewise. (fix__mem): Likewise. (fix_trunc2_mem): On ISA 3.0, prevent the register allocator from doing a direct move to the GPRs to do a store, and instead use the ISA 3.0 store byte/half-word from vector register instruction. For IEEE 128-bit floating point, also optimize stores of 32-bit ints. (fix_trunc2_mem): Likewise. [gcc/testsuite] 2018-02-05 Michael Meissner PR target/84154 * gcc.target/powerpc/pr84154-1.c: New tests. * gcc.target/powerpc/pr84154-2.c: Likewise. * gcc.target/powerpc/pr84154-3.c: Likewise. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797 --M9NhX3UHpAaciwkO Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="pr84154.patch02b" Content-length: 16545 Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 257269) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -5700,43 +5700,60 @@ (define_insn "*fix_truncdi2_fctidz xscvdpsxds %x0,%x1" [(set_attr "type" "fp")]) -(define_expand "fix_trunc2" - [(parallel [(set (match_operand: 0 "nonimmediate_operand") - (fix:QHI (match_operand:SFDF 1 "gpc_reg_operand"))) - (clobber (match_scratch:DI 2))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" +;; If have ISA 3.0, QI/HImode values can go in both VSX registers and GPR +;; registers. If we have ISA 2.07, we don't allow QI/HImode values in the +;; vector registers, so we need to do direct moves to the GPRs, but SImode +;; values can go in VSX registers. Keeping the direct move part through +;; register allocation prevents the register allocator from doing a direct move +;; of the SImode value to a GPR, and then a store/load. +(define_insn_and_split "fix_trunc2" + [(set (match_operand: 0 "gpc_reg_operand" "=wJ,wJwK,r") + (any_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand" "wJ,wJwK,wa"))) + (clobber (match_scratch:SI 2 "=X,X,wi"))] + "TARGET_DIRECT_MOVE" + "@ + fctiwz %0,%1 + xscvdpxws %x0,%x1 + #" + "&& reload_completed && int_reg_operand (operands[0], mode)" + [(set (match_dup 2) + (any_fix:SI (match_dup 1))) + (set (match_dup 3) + (match_dup 2))] { - if (MEM_P (operands[0])) - operands[0] = rs6000_address_for_fpconvert (operands[0]); -}) + operands[3] = gen_rtx_REG (SImode, REGNO (operands[0])); +} + [(set_attr "length" "4,4,8") + (set_attr "type" "fp")]) -(define_insn_and_split "*fix_trunc2_internal" - [(set (match_operand: 0 "reg_or_indexed_operand" "=wIwJ,rZ") - (fix:QHI - (match_operand:SFDF 1 "gpc_reg_operand" ","))) - (clobber (match_scratch:DI 2 "=X,wi"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" +(define_insn "*fix_truncsi2_p8" + [(set (match_operand:SI 0 "gpc_reg_operand" "=d,wa") + (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,wa")))] + "TARGET_DIRECT_MOVE" + "@ + fctiwz %0,%1 + xscvdpxws %x0,%x1" + [(set_attr "type" "fp")]) + +;; Keep the convert and store together through register allocation to prevent +;; the register allocator from getting clever and doing a direct move to a GPR +;; and then store for reg+offset stores. +(define_insn_and_split "*fix_trunc2_mem" + [(set (match_operand:QHSI 0 "memory_operand" "=Z") + (any_fix:QHSI (match_operand:SFDF 1 "gpc_reg_operand" "wa"))) + (clobber (match_scratch:SI 2 "=wa"))] + "((mode == SImode && TARGET_P8_VECTOR) + || (mode != SImode && TARGET_P9_VECTOR))" "#" "&& reload_completed" - [(const_int 0)] + [(set (match_dup 2) + (any_fix:SI (match_dup 1))) + (set (match_dup 0) + (match_dup 3))] { - rtx dest = operands[0]; - rtx src = operands[1]; - - if (vsx_register_operand (dest, mode)) - { - rtx di_dest = gen_rtx_REG (DImode, REGNO (dest)); - emit_insn (gen_fix_truncdi2 (di_dest, src)); - } - else - { - rtx tmp = operands[2]; - rtx tmp2 = gen_rtx_REG (mode, REGNO (tmp)); - - emit_insn (gen_fix_truncdi2 (tmp, src)); - emit_move_insn (dest, tmp2); - } - DONE; + operands[3] = (mode == SImode + ? operands[2] + : gen_rtx_REG (mode, REGNO (operands[2]))); }) (define_expand "fixuns_truncsi2" @@ -5803,71 +5820,6 @@ (define_insn "fixuns_truncdi2" xscvdpuxds %x0,%x1" [(set_attr "type" "fp")]) -(define_expand "fixuns_trunc2" - [(parallel [(set (match_operand: 0 "nonimmediate_operand") - (unsigned_fix:QHI (match_operand:SFDF 1 "gpc_reg_operand"))) - (clobber (match_scratch:DI 2))])] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" -{ - if (MEM_P (operands[0])) - operands[0] = rs6000_address_for_fpconvert (operands[0]); -}) - -(define_insn_and_split "*fixuns_trunc2_internal" - [(set (match_operand: 0 "reg_or_indexed_operand" "=wIwJ,rZ") - (unsigned_fix:QHI - (match_operand:SFDF 1 "gpc_reg_operand" ","))) - (clobber (match_scratch:DI 2 "=X,wi"))] - "TARGET_P9_VECTOR && TARGET_DIRECT_MOVE_64BIT" - "#" - "&& reload_completed" - [(const_int 0)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - - if (vsx_register_operand (dest, mode)) - { - rtx di_dest = gen_rtx_REG (DImode, REGNO (dest)); - emit_insn (gen_fixuns_truncdi2 (di_dest, src)); - } - else - { - rtx tmp = operands[2]; - rtx tmp2 = gen_rtx_REG (mode, REGNO (tmp)); - - emit_insn (gen_fixuns_truncdi2 (tmp, src)); - emit_move_insn (dest, tmp2); - } - DONE; -}) - -;; If -mvsx-small-integer, we can represent the FIX operation directly. On -;; older machines, we have to use an UNSPEC to produce a SImode and move it -;; to another location, since SImode is not allowed in vector registers. -(define_insn "*fctiwz__smallint" - [(set (match_operand:SI 0 "vsx_register_operand" "=d,wi") - (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" ",")))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR" - "@ - fctiwz %0,%1 - xscvdpxws %x0,%x1" - [(set_attr "type" "fp")]) - -;; Combiner pattern to prevent moving the result of converting a floating point -;; value to 32-bit integer to GPR in order to save it. -(define_insn_and_split "*fctiwz__mem" - [(set (match_operand:SI 0 "memory_operand" "=Z") - (any_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "wa"))) - (clobber (match_scratch:SI 2 "=wa"))] - "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_P8_VECTOR" - "#" - "&& reload_completed" - [(set (match_dup 2) - (any_fix:SI (match_dup 1))) - (set (match_dup 0) - (match_dup 2))]) - ;; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) ;; rather than (set (subreg:SI (reg)) (fix:SI ...)) ;; because the first makes it clear that operand 0 is not live @@ -14362,49 +14314,61 @@ (define_insn_and_split "truncsf2_h (set_attr "length" "8")]) ;; Conversion between IEEE 128-bit and integer types -(define_insn "fix_di2_hw" - [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpsdz %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "size" "128")]) -(define_insn "fixuns_di2_hw" - [(set (match_operand:DI 0 "altivec_register_operand" "=v") - (unsigned_fix:DI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpudz %0,%1" - [(set_attr "type" "vecfloat") - (set_attr "size" "128")]) - -(define_insn "fix_si2_hw" - [(set (match_operand:SI 0 "altivec_register_operand" "=v") - (fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpswz %0,%1" +;; It would be convenient if we could just use: +;; (define_insn "fix_2_hw" +;; [(set (match_operand:SDI 0 "altivec_register_operand" "=v") +;; (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] +;; "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" +;; "xscvqpz %0,%1" +;; [(set_attr "type" "vecfloat") +;; (set_attr "size" "128")]) +;; +;; However, there is a bug in the expander, such that always expands to "s", +;; when it should expand to "u" for UNSIGNED_FIX and "s" for FIX. +;; +;; The fix function for DImode and SImode was declared earlier as a +;; define_expand. It calls into rs6000_expand_float128_convert if we don't +;; have IEEE 128-bit hardware support. QImode and HImode are not provided +;; unless we have the IEEE 128-bit hardware. +;; +;; Unlike the code for converting SFmode/DFmode to QImode/HImode, we don't have +;; to provide a GPR target that used direct move and a conversion in the GPR +;; which works around QImode/HImode not being allowed in vector registers in +;; ISA 2.07 (power8). +(define_insn "fix_2_hw" + [(set (match_operand:SDI 0 "altivec_register_operand" "=v") + (any_fix:SDI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" +{ + return ( == UNSIGNED_FIX) ? "xscvqpuz %0,%1" : "xscvqpsz %0,%1"; +} [(set_attr "type" "vecfloat") (set_attr "size" "128")]) -(define_insn "fixuns_si2_hw" - [(set (match_operand:SI 0 "altivec_register_operand" "=v") - (unsigned_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v")))] - "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" - "xscvqpuwz %0,%1" +(define_insn "fix_trunc2" + [(set (match_operand:QHI 0 "altivec_register_operand" "=v") + (any_fix:QHI + (match_operand:IEEE128 1 "altivec_register_operand" "v")))] + "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" +{ + return ( == UNSIGNED_FIX) ? "xscvqpuwz %0,%1" : "xscvqpswz %0,%1"; +} [(set_attr "type" "vecfloat") (set_attr "size" "128")]) -;; Combiner pattern to prevent moving the result of converting an IEEE 128-bit -;; floating point value to 32-bit integer to GPR in order to save it. -(define_insn_and_split "*fix__mem" - [(set (match_operand:SI 0 "memory_operand" "=Z") - (any_fix:SI (match_operand:IEEE128 1 "altivec_register_operand" "v"))) - (clobber (match_scratch:SI 2 "=v"))] +;; Combiner patterns to prevent moving the result of converting an IEEE 128-bit +;; floating point value to 8/16/32-bit integer to GPR in order to save it. +(define_insn_and_split "*fix_trunc2_mem" + [(set (match_operand:QHSI 0 "memory_operand" "=Z") + (any_fix:QHSI + (match_operand:IEEE128 1 "altivec_register_operand" "v"))) + (clobber (match_scratch:QHSI 2 "=v"))] "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" "&& reload_completed" [(set (match_dup 2) - (any_fix:SI (match_dup 1))) + (any_fix:QHSI (match_dup 1))) (set (match_dup 0) (match_dup 2))]) Index: gcc/testsuite/gcc.target/powerpc/pr84154-1.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr84154-1.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr84154-1.c (revision 0) @@ -0,0 +1,55 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-options "-mpower8-vector -O2" } */ + +/* PR target/84154. Make sure conversion to char/short does not generate a + store and a load on ISA 2.07 and newer systems. */ + +unsigned char +double_to_uc (double x) +{ + return x; +} + +signed char +double_to_sc (double x) +{ + return x; +} + +unsigned short +double_to_us (double x) +{ + return x; +} + +short +double_to_ss (double x) +{ + return x; +} + +unsigned int +double_to_ui (double x) +{ + return x; +} + +int +double_to_si (double x) +{ + return x; +} + +/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mextsh\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mrlwinm\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbz\M} } } */ +/* { dg-final { scan-assembler-not {\mlhz\M} } } */ +/* { dg-final { scan-assembler-not {\mlha\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ Index: gcc/testsuite/gcc.target/powerpc/pr84154-2.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr84154-2.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr84154-2.c (revision 0) @@ -0,0 +1,58 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p8vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ +/* { dg-options "-mcpu=power8 -O2" } */ + +/* PR target/84154. Make sure on ISA 2.07 (power8) that we store the result of + a conversion to char/short using an offsettable address does not generate + direct moves for storing 32-bit integers, but does do a direct move for + 8/16-bit integers. */ + +void +double_to_uc (double x, unsigned char *p) +{ + p[3] = x; +} + +void +double_to_sc (double x, signed char *p) +{ + p[3] = x; +} + +void +double_to_us (double x, unsigned short *p) +{ + p[3] = x; +} + +void +double_to_ss (double x, short *p) +{ + p[3] = x; +} + +void +double_to_ui (double x, unsigned int *p) +{ + p[3] = x; +} + +void +double_to_si (double x, int *p) +{ + p[3] = x; +} + +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstb\M} 2 } } */ +/* { dg-final { scan-assembler-times {\msth\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbz\M} } } */ +/* { dg-final { scan-assembler-not {\mlhz\M} } } */ +/* { dg-final { scan-assembler-not {\mlha\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ Index: gcc/testsuite/gcc.target/powerpc/pr84154-3.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/pr84154-3.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/pr84154-3.c (revision 0) @@ -0,0 +1,60 @@ +/* { dg-do compile { target { powerpc*-*-* } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ +/* { dg-options "-mcpu=power9 -O2" } */ + +/* PR target/84154. Make sure on ISA 3.0 we store the result of a conversion + to char/short using an offsettable address does not generate direct moves + for storing 8/16/32-bit integers. */ + +void +double_to_uc (double x, unsigned char *p) +{ + p[3] = x; +} + +void +double_to_sc (double x, signed char *p) +{ + p[3] = x; +} + +void +double_to_us (double x, unsigned short *p) +{ + p[3] = x; +} + +void +double_to_ss (double x, short *p) +{ + p[3] = x; +} + +void +double_to_ui (double x, unsigned int *p) +{ + p[3] = x; +} + +void +double_to_si (double x, int *p) +{ + p[3] = x; +} + +/* { dg-final { scan-assembler-times {\maddi\M} 6 } } */ +/* { dg-final { scan-assembler-times {\mfctiwuz\M|\mxscvdpuxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mfctiwz\M|\mxscvdpsxws\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mstfiwx\M|\mstxsiwx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxsibx\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstxsihx\M} 2 } } */ +/* { dg-final { scan-assembler-not {\mlbz\M} } } */ +/* { dg-final { scan-assembler-not {\mlhz\M} } } */ +/* { dg-final { scan-assembler-not {\mlha\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrwz\M} } } */ +/* { dg-final { scan-assembler-not {\mmfvsrd\M} } } */ +/* { dg-final { scan-assembler-not {\mstw\M} } } */ +/* { dg-final { scan-assembler-not {\mstb\M} } } */ +/* { dg-final { scan-assembler-not {\msth\M} } } */ --M9NhX3UHpAaciwkO--