[RFC Patch], PowerPC memory support pre-gcc9, Version 2

[RFC Patch], PowerPC memory support pre-gcc9, Version 2

[Michael Meissner]

I will be submitting reworked patches for the stuff I want to do in GCC 9.  The
initial patches are mostly initial cleanup and slight rework of the support
functions.  These patches will be limited to changing one thing at a time,
instead of larger patches like I did in the first set of patches.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #1

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 1321 bytes --]

This patch renames the mode_supports_vsx_dform_quad function and changes all of
the callers.  I'm thinking about enhancing the addressing parts in the
secondary reload support, and I wanted a more logical naming scheme.  There
will be mode_supports_d_form for offsettable addresses of any form, and
mode_supports_ds_form for addresses where the bottom 2 bits are 0 in the
future.

I have built bootstrap compilers with the first 4 patches including this patch
on both big and little endian power8 systems.  There were no regressions.

2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (mode_supports_dq_form): Rename
	mode_supports_vsx_dform_quad to mode_supports_dq_form.
	(mode_supports_vsx_dform_quad): Likeise.
	(quad_address_p): Likewise.
	(reg_offset_addressing_ok_p): Likewise.
	(offsettable_ok_by_alignment): Likewise.
	(rs6000_legitimate_offset_address_p): Likewise.
	(legitimate_lo_sum_address_p): Likewise.
	(rs6000_legitimize_address): Likewise.
	(rs6000_legitimize_reload_address): Likewise.
	(rs6000_secondary_reload_inner): Likewise.
	(rs6000_preferred_reload_class): Likewise.
	(rs6000_output_move_128bit): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258719)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -649,7 +649,7 @@ mode_supports_vmx_dform (machine_mode mo
    is more limited than normal d-form addressing in that the offset must be
    aligned on a 16-byte boundary.  */
 static inline bool
-mode_supports_vsx_dform_quad (machine_mode mode)
+mode_supports_dq_form (machine_mode mode)
 {
   return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
 	  != 0);
@@ -8107,7 +8107,7 @@ quad_address_p (rtx addr, machine_mode m
   if (legitimate_indirect_address_p (addr, strict))
     return true;
 
-  if (VECTOR_MODE_P (mode) && !mode_supports_vsx_dform_quad (mode))
+  if (VECTOR_MODE_P (mode) && !mode_supports_dq_form (mode))
     return false;
 
   if (GET_CODE (addr) != PLUS)
@@ -8289,7 +8289,7 @@ reg_offset_addressing_ok_p (machine_mode
 	 IEEE 128-bit floating point that is passed in a single vector
 	 register.  */
       if (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode))
-	return mode_supports_vsx_dform_quad (mode);
+	return mode_supports_dq_form (mode);
       break;
 
     case E_V2SImode:
@@ -8356,7 +8356,7 @@ offsettable_ok_by_alignment (rtx op, HOS
 
   /* ISA 3.0 vector d-form addressing is restricted, don't allow
      SYMBOL_REF.  */
-  if (mode_supports_vsx_dform_quad (mode))
+  if (mode_supports_dq_form (mode))
     return false;
 
   dsize = GET_MODE_SIZE (mode);
@@ -8527,7 +8527,7 @@ rs6000_legitimate_offset_address_p (mach
     return false;
   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
     return false;
-  if (mode_supports_vsx_dform_quad (mode))
+  if (mode_supports_dq_form (mode))
     return quad_address_p (x, mode, strict);
   if (!reg_offset_addressing_ok_p (mode))
     return virtual_stack_registers_memory_p (x);
@@ -8645,7 +8645,7 @@ legitimate_lo_sum_address_p (machine_mod
   if (!INT_REG_OK_FOR_BASE_P (XEXP (x, 0), strict))
     return false;
   /* quad word addresses are restricted, and we can't use LO_SUM.  */
-  if (mode_supports_vsx_dform_quad (mode))
+  if (mode_supports_dq_form (mode))
     return false;
   x = XEXP (x, 1);
 
@@ -8710,7 +8710,7 @@ rs6000_legitimize_address (rtx x, rtx ol
   unsigned int extra;
 
   if (!reg_offset_addressing_ok_p (mode)
-      || mode_supports_vsx_dform_quad (mode))
+      || mode_supports_dq_form (mode))
     {
       if (virtual_stack_registers_memory_p (x))
 	return x;
@@ -9454,7 +9454,7 @@ rs6000_legitimize_reload_address (rtx x,
 				  int ind_levels ATTRIBUTE_UNUSED, int *win)
 {
   bool reg_offset_p = reg_offset_addressing_ok_p (mode);
-  bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
+  bool quad_offset_p = mode_supports_dq_form (mode);
 
   /* Nasty hack for vsx_splat_v2df/v2di load from mem, which takes a
      DFmode/DImode MEM.  Ditto for ISA 3.0 vsx_splat_v4sf/v4si.  */
@@ -9742,7 +9742,7 @@ static bool
 rs6000_legitimate_address_p (machine_mode mode, rtx x, bool reg_ok_strict)
 {
   bool reg_offset_p = reg_offset_addressing_ok_p (mode);
-  bool quad_offset_p = mode_supports_vsx_dform_quad (mode);
+  bool quad_offset_p = mode_supports_dq_form (mode);
 
   /* If this is an unaligned stvx/ldvx type address, discard the outer AND.  */
   if (VECTOR_MEM_ALTIVEC_P (mode)
@@ -20409,7 +20409,7 @@ rs6000_secondary_reload_inner (rtx reg, 
 	    }
 	}
 
-      else if (mode_supports_vsx_dform_quad (mode) && CONST_INT_P (op1))
+      else if (mode_supports_dq_form (mode) && CONST_INT_P (op1))
 	{
 	  if (((addr_mask & RELOAD_REG_QUAD_OFFSET) == 0)
 	      || !quad_address_p (addr, mode, false))
@@ -20450,7 +20450,7 @@ rs6000_secondary_reload_inner (rtx reg, 
 	}
 
       /* Quad offsets are restricted and can't handle normal addresses.  */
-      else if (mode_supports_vsx_dform_quad (mode))
+      else if (mode_supports_dq_form (mode))
 	{
 	  emit_insn (gen_rtx_SET (scratch, addr));
 	  new_addr = scratch;
@@ -20645,7 +20645,7 @@ rs6000_preferred_reload_class (rtx x, en
 
       /* D-form addressing can easily reload the value.  */
       if (mode_supports_vmx_dform (mode)
-	  || mode_supports_vsx_dform_quad (mode))
+	  || mode_supports_dq_form (mode))
 	return rclass;
 
       /* If this is a scalar floating point value and we don't have D-form
@@ -21048,7 +21048,7 @@ rs6000_output_move_128bit (rtx operands[
 
       else if (TARGET_VSX && dest_vsx_p)
 	{
-	  if (mode_supports_vsx_dform_quad (mode)
+	  if (mode_supports_dq_form (mode)
 	      && quad_address_p (XEXP (src, 0), mode, true))
 	    return "lxv %x0,%1";
 
@@ -21086,7 +21086,7 @@ rs6000_output_move_128bit (rtx operands[
 
       else if (TARGET_VSX && src_vsx_p)
 	{
-	  if (mode_supports_vsx_dform_quad (mode)
+	  if (mode_supports_dq_form (mode)
 	      && quad_address_p (XEXP (dest, 0), mode, true))
 	    return "stxv %x1,%0";
 

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #2

[Michael Meissner]

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This patch just moves two of the mode_supports_* functions so they are all
together.

I have built bootstrap compilers with the first 4 patches including this patch
on both big and little endian power8 systems.  There were no regressions.

2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (mode_supports_vmx_dform): Move these
	functions to be next to the other mode_supports functions.
	(mode_supports_dq_form): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258724)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -553,6 +553,23 @@ mode_supports_pre_modify_p (machine_mode
 	  != 0);
 }
 
+/* Return true if we have D-form addressing in altivec registers.  */
+static inline bool
+mode_supports_vmx_dform (machine_mode mode)
+{
+  return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
+}
+
+/* Return true if we have D-form addressing in VSX registers.  This addressing
+   is more limited than normal d-form addressing in that the offset must be
+   aligned on a 16-byte boundary.  */
+static inline bool
+mode_supports_dq_form (machine_mode mode)
+{
+  return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
+	  != 0);
+}
+
 /* Given that there exists at least one variable that is set (produced)
    by OUT_INSN and read (consumed) by IN_INSN, return true iff
    IN_INSN represents one or more memory store operations and none of
@@ -638,23 +655,6 @@ rs6000_store_data_bypass_p (rtx_insn *ou
   return store_data_bypass_p (out_insn, in_insn);
 }
 
-/* Return true if we have D-form addressing in altivec registers.  */
-static inline bool
-mode_supports_vmx_dform (machine_mode mode)
-{
-  return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
-}
-
-/* Return true if we have D-form addressing in VSX registers.  This addressing
-   is more limited than normal d-form addressing in that the offset must be
-   aligned on a 16-byte boundary.  */
-static inline bool
-mode_supports_dq_form (machine_mode mode)
-{
-  return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
-	  != 0);
-}
-
 \f
 /* Processor costs (relative to an add) */
 

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #3

[Michael Meissner]

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This match renames the d-form mode support function and makes it more general.
It was originally written to test whether we have the ISA 3.0 new D*-form
instruction, but I believe in the future, I will want to use it also for GPR
and tradiational floating point registers.

I have built bootstrap compilers with the first 4 patches including this patch
on both big and little endian power8 systems.  There were no regressions.

2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (mode_supports_d_form): Rename
	mode_supports_vmx_dform to mode_supports_d_form.  Add an optional
	argument to say which reload register class to use.  Chagne all
	callers to pass in the RELOAD_REG_VMX class explicitly.
	(rs6000_secondary_reload): Likewise.
	(rs6000_preferred_reload_class): Likewise.
	(rs6000_secondary_reload_class): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258725)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -553,11 +553,14 @@ mode_supports_pre_modify_p (machine_mode
 	  != 0);
 }
 
-/* Return true if we have D-form addressing in altivec registers.  */
+/* Return true if we have D-form addressing (register+offset) in either a
+   specific reload register class or whether some reload register class
+   supports d-form addressing.  */
 static inline bool
-mode_supports_vmx_dform (machine_mode mode)
+mode_supports_d_form (machine_mode mode,
+		      enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
 {
-  return ((reg_addr[mode].addr_mask[RELOAD_REG_VMX] & RELOAD_REG_OFFSET) != 0);
+  return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_OFFSET) != 0);
 }
 
 /* Return true if we have D-form addressing in VSX registers.  This addressing
@@ -20081,7 +20084,7 @@ rs6000_secondary_reload (bool in_p,
      point register, unless we have D-form addressing.  Also make sure that
      non-zero constants use a FPR.  */
   if (!done_p && reg_addr[mode].scalar_in_vmx_p
-      && !mode_supports_vmx_dform (mode)
+      && !mode_supports_d_form (mode, RELOAD_REG_VMX)
       && (rclass == VSX_REGS || rclass == ALTIVEC_REGS)
       && (memory_p || (GET_CODE (x) == CONST_DOUBLE)))
     {
@@ -20644,7 +20647,7 @@ rs6000_preferred_reload_class (rtx x, en
 	}
 
       /* D-form addressing can easily reload the value.  */
-      if (mode_supports_vmx_dform (mode)
+      if (mode_supports_d_form (mode, RELOAD_REG_VMX)
 	  || mode_supports_dq_form (mode))
 	return rclass;
 
@@ -20801,7 +20804,7 @@ rs6000_secondary_reload_class (enum reg_
      instead of reloading the secondary memory address for Altivec moves.  */
   if (TARGET_VSX
       && GET_MODE_SIZE (mode) < 16
-      && !mode_supports_vmx_dform (mode)
+      && !mode_supports_d_form (mode, RELOAD_REG_VMX)
       && (((rclass == GENERAL_REGS || rclass == BASE_REGS)
            && (regno >= 0 && ALTIVEC_REGNO_P (regno)))
           || ((rclass == VSX_REGS || rclass == ALTIVEC_REGS)

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #4

[Michael Meissner]

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This patch extends the other mode_supports* function to take an optional
second argument to specificy particular reload register class, and it defaults
to REG_RELOAD_ANY which says some reload register supports the feature.

I have built bootstrap compilers with the first 4 patches including this patch
on both big and little endian power8 systems.  There were no regressions.

2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (mode_supports_pre_incdec_p): Add
	additional argument to specify the reload register class to use,
	defaulting to RELOAD_REG_ANY.
	(mode_supports_pre_modify_p): Likewise.
	(mode_supports_dq_form): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258726)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -537,20 +537,22 @@ struct rs6000_reg_addr {
 
 static struct rs6000_reg_addr reg_addr[NUM_MACHINE_MODES];
 
-/* Helper function to say whether a mode supports PRE_INC or PRE_DEC.  */
+/* Helper function to say whether a mode supports PRE_INC or PRE_DEC in a given
+   reload register class or if some reload register class supports it.  */
 static inline bool
-mode_supports_pre_incdec_p (machine_mode mode)
+mode_supports_pre_incdec_p (machine_mode mode,
+			    enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
 {
-  return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_INCDEC)
-	  != 0);
+  return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_PRE_INCDEC) != 0);
 }
 
-/* Helper function to say whether a mode supports PRE_MODIFY.  */
+/* Helper function to say whether a mode supports PRE_MODIFY in a given
+   reload register class or if some reload register class supports it..  */
 static inline bool
-mode_supports_pre_modify_p (machine_mode mode)
+mode_supports_pre_modify_p (machine_mode mode,
+			    enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
 {
-  return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_PRE_MODIFY)
-	  != 0);
+  return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_PRE_MODIFY) != 0);
 }
 
 /* Return true if we have D-form addressing (register+offset) in either a
@@ -563,14 +565,14 @@ mode_supports_d_form (machine_mode mode,
   return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_OFFSET) != 0);
 }
 
-/* Return true if we have D-form addressing in VSX registers.  This addressing
-   is more limited than normal d-form addressing in that the offset must be
-   aligned on a 16-byte boundary.  */
+/* Return true if we have DQ-form addressing in a given reload register class
+   or if some reload register class supports it.  DQ-form addressing must have
+   the bottom 4 bits set to 0.  */
 static inline bool
-mode_supports_dq_form (machine_mode mode)
+mode_supports_dq_form (machine_mode mode,
+		       enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
 {
-  return ((reg_addr[mode].addr_mask[RELOAD_REG_ANY] & RELOAD_REG_QUAD_OFFSET)
-	  != 0);
+  return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_QUAD_OFFSET) != 0);
 }
 
 /* Given that there exists at least one variable that is set (produced)

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #1

[Segher Boessenkool]

Hi Mike,

On Thu, Mar 22, 2018 at 08:11:52AM -0400, Michael Meissner wrote:
> This patch renames the mode_supports_vsx_dform_quad function and changes all of
> the callers.  I'm thinking about enhancing the addressing parts in the
> secondary reload support, and I wanted a more logical naming scheme.  There
> will be mode_supports_d_form for offsettable addresses of any form, and
> mode_supports_ds_form for addresses where the bottom 2 bits are 0 in the
> future.
> 
> I have built bootstrap compilers with the first 4 patches including this patch
> on both big and little endian power8 systems.  There were no regressions.

I like that new name.  More succinct.

> 2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>
> 
> 	* config/rs6000/rs6000.c (mode_supports_dq_form): Rename
> 	mode_supports_vsx_dform_quad to mode_supports_dq_form.
> 	(mode_supports_vsx_dform_quad): Likeise.

(typo, "likewise").

> 	(quad_address_p): Likewise.
> 	(reg_offset_addressing_ok_p): Likewise.
> 	(offsettable_ok_by_alignment): Likewise.
> 	(rs6000_legitimate_offset_address_p): Likewise.
> 	(legitimate_lo_sum_address_p): Likewise.
> 	(rs6000_legitimize_address): Likewise.
> 	(rs6000_legitimize_reload_address): Likewise.
> 	(rs6000_secondary_reload_inner): Likewise.
> 	(rs6000_preferred_reload_class): Likewise.
> 	(rs6000_output_move_128bit): Likewise.


Segher

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #3

[Segher Boessenkool]

Hi!

On Thu, Mar 22, 2018 at 08:16:36AM -0400, Michael Meissner wrote:
> This match renames the d-form mode support function and makes it more general.
> It was originally written to test whether we have the ISA 3.0 new D*-form
> instruction, but I believe in the future, I will want to use it also for GPR
> and tradiational floating point registers.
> 
> I have built bootstrap compilers with the first 4 patches including this patch
> on both big and little endian power8 systems.  There were no regressions.
> 
> 2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>
> 
> 	* config/rs6000/rs6000.c (mode_supports_d_form): Rename
> 	mode_supports_vmx_dform to mode_supports_d_form.  Add an optional
> 	argument to say which reload register class to use.  Chagne all

(typo, "change").

> 	callers to pass in the RELOAD_REG_VMX class explicitly.
> 	(rs6000_secondary_reload): Likewise.
> 	(rs6000_preferred_reload_class): Likewise.
> 	(rs6000_secondary_reload_class): Likewise.

So it is called "mode_supports_d_form" but it actually returns true for
*any* offset form?

> +mode_supports_d_form (machine_mode mode,
> +		      enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)

Does the default argument make the interface simpler, or more complex?


Segher

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #3

[Michael Meissner]

On Thu, Mar 22, 2018 at 10:03:55AM -0500, Segher Boessenkool wrote:
> Hi!
> 
> On Thu, Mar 22, 2018 at 08:16:36AM -0400, Michael Meissner wrote:
> > This match renames the d-form mode support function and makes it more general.
> > It was originally written to test whether we have the ISA 3.0 new D*-form
> > instruction, but I believe in the future, I will want to use it also for GPR
> > and tradiational floating point registers.
> > 
> > I have built bootstrap compilers with the first 4 patches including this patch
> > on both big and little endian power8 systems.  There were no regressions.
> > 
> > 2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>
> > 
> > 	* config/rs6000/rs6000.c (mode_supports_d_form): Rename
> > 	mode_supports_vmx_dform to mode_supports_d_form.  Add an optional
> > 	argument to say which reload register class to use.  Chagne all
> 
> (typo, "change").

Ok.

> > 	callers to pass in the RELOAD_REG_VMX class explicitly.
> > 	(rs6000_secondary_reload): Likewise.
> > 	(rs6000_preferred_reload_class): Likewise.
> > 	(rs6000_secondary_reload_class): Likewise.
> 
> So it is called "mode_supports_d_form" but it actually returns true for
> *any* offset form?

Yes, the intention is to say whether some form of offset is available.  Other
parts need to know whether the offset is D-form, DS-form, DQ-form, and perhaps
other forms in the future.

> > +mode_supports_d_form (machine_mode mode,
> > +		      enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
> 
> Does the default argument make the interface simpler, or more complex?

The intention is for things like go if legitimate address, where you don't have
context of which register to use, you will use the default second argument.

However, when you are in the middle of secondary reload and friends, and you
are wanting to know what a specific reload register class (GPR, FPR, VMX)
constraints are, you will add the second argument.  It makes it easier to use
the function if you don't need to specify the second argument.  With the 79
character limit, the 2nd argument would often force a line break.

I'm trying to get rid of a lot of tests that say things like:

	if (gpr-register && (mode == DFmode || DImode || ...)) { }

and instead move the tests to reg_addr.  Of course right now, it is just 

For example for DFmode, if you are loading it into a GPR, it uses DS-form, if
you are loading it into a FPR, it uses normal 16-bit D-form, and if you don't
have the ISA 3.0 instruction set, the VMX register doesn't support an
offset load form at all.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #6

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 834 bytes --]

Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together.  These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.

I have done both big and little endian bootstrap builds with all 5 patches
installed.  There were no regressions.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_softfloat32, FMOVE64):
	Reformat alternatives and attributes so it is easier to identify
	which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch06b --]
[-- Type: text/plain, Size: 1388 bytes --]

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258733)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7441,16 +7441,25 @@ (define_insn "*mov<mode>_hardfloat32"
              4,           4,          4,          4,          8,
              8,           8,          8")])
 
+;;           STW      LWZ     MR      G-const H-const F-const
+
 (define_insn "*mov<mode>_softfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")
-	(match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+           "=Y,       r,      r,      r,      r,      r")
+
+	(match_operand:FMOVE64 1 "input_operand"
+            "r,       Y,      r,      G,      H,      F"))]
+
   "! TARGET_POWERPC64 
    && (TARGET_SINGLE_FLOAT || TARGET_SOFT_FLOAT)
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
   "#"
-  [(set_attr "type" "store,load,two,*,*,*")
-   (set_attr "length" "8,8,8,8,12,16")])
+  [(set_attr "type"
+            "store,   load,   two,    *,      *,      *")
+
+   (set_attr "length"
+             "8,      8,      8,      8,      12,     16")])
 
 ; ld/std require word-aligned displacements -> 'Y' constraint.
 ; List Y->r and r->Y before r->r for reload.

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #5

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 834 bytes --]

Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together.  These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.

I have done both big and little endian bootstrap builds with all 5 patches
installed.  There were no regressions.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_hardfloat32, FMOVE64):
	Reformat alternatives and attributes so it is easier to identify
	which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch05b --]
[-- Type: text/plain, Size: 2297 bytes --]

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258719)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7398,9 +7398,21 @@ (define_split
 ;; If we have FPR registers, rs6000_emit_move has moved all constants to memory,
 ;; except for 0.0 which can be created on VSX with an xor instruction.
 
+;;           STFD         LFD         FMR         LXSD        STXSD
+;;           LXSD         STXSD       XXLOR       XXLXOR      GPR<-0
+;;           LWZ          STW         MR
+
 (define_insn "*mov<mode>_hardfloat32"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r")
-	(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+            "=m,          d,          d,          <f64_p9>,   wY,
+              <f64_av>,   Z,          <f64_vsx>,  <f64_vsx>,  !r,
+              Y,          r,          !r")
+
+	(match_operand:FMOVE64 1 "input_operand"
+             "d,          m,          d,          wY,         <f64_p9>,
+              Z,          <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
+              r,          Y,          r"))]
+
   "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT 
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7418,9 +7430,16 @@ (define_insn "*mov<mode>_hardfloat32"
    #
    #
    #"
-  [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,two,store,load,two")
+  [(set_attr "type"
+            "fpstore,     fpload,     fpsimple,   fpload,     fpstore,
+             fpload,      fpstore,    veclogical, veclogical, two,
+             store,       load,       two")
+
    (set_attr "size" "64")
-   (set_attr "length" "4,4,4,4,4,4,4,4,4,8,8,8,8")])
+   (set_attr "length"
+            "4,           4,          4,          4,          4,
+             4,           4,          4,          4,          8,
+             8,           8,          8")])
 
 (define_insn "*mov<mode>_softfloat32"
   [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r")

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #7

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 834 bytes --]

Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together.  These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.

I have done both big and little endian bootstrap builds with all 5 patches
installed.  There were no regressions.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_hardfloat64, FMOVE64):
	Reformat alternatives and attributes so it is easier to identify
	which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch07b --]
[-- Type: text/plain, Size: 2455 bytes --]

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258734)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7463,9 +7463,25 @@ (define_insn "*mov<mode>_softfloat32"
 
 ; ld/std require word-aligned displacements -> 'Y' constraint.
 ; List Y->r and r->Y before r->r for reload.
+
+;;           STFD         LFD         FMR         LXSD        STXSD
+;;           LXSDX        STXSDX      XXLOR       XXLXOR      LI 0
+;;           STD          LD          MR          MT<SPR>     MF<SPR>
+;;           NOP          MFTGPR      MFFGPR      MTVSRD      MFVSRD
+
 (define_insn "*mov<mode>_hardfloat64"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_p9>,wY,<f64_av>,Z,<f64_vsx>,<f64_vsx>,!r,Y,r,!r,*c*l,!r,*h,r,wg,r,<f64_dm>")
-	(match_operand:FMOVE64 1 "input_operand" "d,m,d,wY,<f64_p9>,Z,<f64_av>,<f64_vsx>,<zero_fp>,<zero_fp>,r,Y,r,r,h,0,wg,r,<f64_dm>,r"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+           "=m,           d,          d,          <f64_p9>,   wY,
+             <f64_av>,    Z,          <f64_vsx>,  <f64_vsx>,  !r,
+             Y,           r,          !r,         *c*l,       !r,
+            *h,           r,          wg,         r,          <f64_dm>")
+
+	(match_operand:FMOVE64 1 "input_operand"
+            "d,           m,          d,          wY,         <f64_p9>,
+             Z,           <f64_av>,   <f64_vsx>,  <zero_fp>,  <zero_fp>,
+             r,           Y,          r,          r,          h,
+             0,           wg,         r,          <f64_dm>,   r"))]
+
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7490,7 +7506,12 @@ (define_insn "*mov<mode>_hardfloat64"
    mffgpr %0,%1
    mfvsrd %0,%x1
    mtvsrd %x0,%1"
-  [(set_attr "type" "fpstore,fpload,fpsimple,fpload,fpstore,fpload,fpstore,veclogical,veclogical,integer,store,load,*,mtjmpr,mfjmpr,*,mftgpr,mffgpr,mftgpr,mffgpr")
+  [(set_attr "type"
+            "fpstore,     fpload,     fpsimple,   fpload,     fpstore,
+             fpload,      fpstore,    veclogical, veclogical, integer,
+             store,       load,       *,          mtjmpr,     mfjmpr,
+             *,           mftgpr,     mffgpr,     mftgpr,    mffgpr")
+
    (set_attr "size" "64")
    (set_attr "length" "4")])
 

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #8

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 834 bytes --]

Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together.  These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.

I have done both big and little endian bootstrap builds with all 5 patches
installed.  There were no regressions.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_softfloat64, FMOVE64):
	Reformat alternatives and attributes so it is easier to identify
	which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch08b --]
[-- Type: text/plain, Size: 1560 bytes --]

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258735)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7515,9 +7515,18 @@ (define_insn "*mov<mode>_hardfloat64"
    (set_attr "size" "64")
    (set_attr "length" "4")])
 
+;;           STD      LD       MR      MT<SPR> MF<SPR> G-const
+;;           H-const  F-const  Special
+
 (define_insn "*mov<mode>_softfloat64"
-  [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h")
-	(match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))]
+  [(set (match_operand:FMOVE64 0 "nonimmediate_operand"
+           "=Y,       r,      r,      cl,     r,      r,
+             r,       r,      *h")
+
+	(match_operand:FMOVE64 1 "input_operand"
+            "r,       Y,      r,      r,      h,      G,
+             H,       F,      0"))]
+
   "TARGET_POWERPC64 && TARGET_SOFT_FLOAT
    && (gpc_reg_operand (operands[0], <MODE>mode)
        || gpc_reg_operand (operands[1], <MODE>mode))"
@@ -7531,8 +7540,13 @@ (define_insn "*mov<mode>_softfloat64"
    #
    #
    nop"
-  [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*")
-   (set_attr "length" "4,4,4,4,4,8,12,16,4")])
+  [(set_attr "type"
+            "store,   load,   *,      mtjmpr, mfjmpr, *,
+             *,       *,      *")
+
+   (set_attr "length"
+            "4,       4,      4,      4,      4,      8,
+             12,      16,     4")])
 \f
 (define_expand "mov<mode>"
   [(set (match_operand:FMOVE128 0 "general_operand")

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #9

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 832 bytes --]

Patches #5..8 just add comments and reformat movd{f,d} constraints and
attributes so that it is a lot easier to tell which constraints and attributes
go together.  These do not (or at least should not) change the code generated.
Patch #9 does the same thing for mov{sf,sd} when floating point registers are
not available.

I have done both big and little endian bootstrap builds with all 5 patches
installed.  There were no regressions.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.md (mov<mode>_softfloat, FMOVE32):
	Reformat alternatives and attributes so it is easier to identify
	which constraints/attributes go with which instruction.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch09b --]
[-- Type: text/plain, Size: 1703 bytes --]

Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258737)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -7217,9 +7217,17 @@ (define_insn "movsd_hardfloat"
 	"load,       fpload,    store,     fpstore,   mffgpr,    mftgpr,
 	 fpsimple,   *,         mtjmpr,    mfjmpr,    *")])
 
+;;	MR           MT%0       MF%0       LWZ        STW        LI
+;;	LIS          G-const.   F/n-const  NOP
 (define_insn "*mov<mode>_softfloat"
-  [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h")
-	(match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))]
+  [(set (match_operand:FMOVE32 0 "nonimmediate_operand"
+	"=r,         cl,        r,         r,         m,         r,
+          r,         r,         r,         *h")
+
+	(match_operand:FMOVE32 1 "input_operand"
+	 "r,         r,         h,         m,         r,         I,
+          L,         G,         Fn,        0"))]
+
   "(gpc_reg_operand (operands[0], <MODE>mode)
    || gpc_reg_operand (operands[1], <MODE>mode))
    && TARGET_SOFT_FLOAT"
@@ -7234,8 +7242,13 @@ (define_insn "*mov<mode>_softfloat"
    #
    #
    nop"
-  [(set_attr "type" "*,mtjmpr,mfjmpr,load,store,*,*,*,*,*")
-   (set_attr "length" "4,4,4,4,4,4,4,4,8,4")])
+  [(set_attr "type"
+	"*,          mtjmpr,    mfjmpr,    load,      store,     *,
+         *,          *,         *,         *")
+
+   (set_attr "length"
+	"4,          4,         4,         4,         4,         4,
+         4,          4,         8,         4")])
 
 ;; Like movsf, but adjust a SI value to be used in a SF context, i.e.
 ;; (set (reg:SF ...) (subreg:SF (reg:SI ...) 0))

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #3

[Segher Boessenkool]

On Thu, Mar 22, 2018 at 11:18:05AM -0400, Michael Meissner wrote:
> On Thu, Mar 22, 2018 at 10:03:55AM -0500, Segher Boessenkool wrote:
> > > 	callers to pass in the RELOAD_REG_VMX class explicitly.
> > > 	(rs6000_secondary_reload): Likewise.
> > > 	(rs6000_preferred_reload_class): Likewise.
> > > 	(rs6000_secondary_reload_class): Likewise.
> > 
> > So it is called "mode_supports_d_form" but it actually returns true for
> > *any* offset form?
> 
> Yes, the intention is to say whether some form of offset is available.  Other
> parts need to know whether the offset is D-form, DS-form, DQ-form, and perhaps
> other forms in the future.

So you may want a better name.

> > > +mode_supports_d_form (machine_mode mode,
> > > +		      enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
> > 
> > Does the default argument make the interface simpler, or more complex?
> 
> The intention is for things like go if legitimate address, where you don't have
> context of which register to use, you will use the default second argument.
> 
> However, when you are in the middle of secondary reload and friends, and you
> are wanting to know what a specific reload register class (GPR, FPR, VMX)
> constraints are, you will add the second argument.  It makes it easier to use
> the function if you don't need to specify the second argument.  With the 79
> character limit, the 2nd argument would often force a line break.

Maybe it is better to have two functions then?  One for each behaviour.


Segher

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #3

[Michael Meissner]

On Thu, Mar 22, 2018 at 11:41:48AM -0500, Segher Boessenkool wrote:
> On Thu, Mar 22, 2018 at 11:18:05AM -0400, Michael Meissner wrote:
> > On Thu, Mar 22, 2018 at 10:03:55AM -0500, Segher Boessenkool wrote:
> > > > 	callers to pass in the RELOAD_REG_VMX class explicitly.
> > > > 	(rs6000_secondary_reload): Likewise.
> > > > 	(rs6000_preferred_reload_class): Likewise.
> > > > 	(rs6000_secondary_reload_class): Likewise.
> > > 
> > > So it is called "mode_supports_d_form" but it actually returns true for
> > > *any* offset form?
> > 
> > Yes, the intention is to say whether some form of offset is available.  Other
> > parts need to know whether the offset is D-form, DS-form, DQ-form, and perhaps
> > other forms in the future.
> 
> So you may want a better name.

It all depends on where you are in the compilation process.

> > > > +mode_supports_d_form (machine_mode mode,
> > > > +		      enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
> > > 
> > > Does the default argument make the interface simpler, or more complex?
> > 
> > The intention is for things like go if legitimate address, where you don't have
> > context of which register to use, you will use the default second argument.
> > 
> > However, when you are in the middle of secondary reload and friends, and you
> > are wanting to know what a specific reload register class (GPR, FPR, VMX)
> > constraints are, you will add the second argument.  It makes it easier to use
> > the function if you don't need to specify the second argument.  With the 79
> > character limit, the 2nd argument would often force a line break.
> 
> Maybe it is better to have two functions then?  One for each behaviour.

I don't really see the need, but I can do it if you insist.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #10

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 2741 bytes --]

In preparing to start work on reorganizing the intermediate address support in
PowerPC, I noticed there were some thinkos in the undocumented toc fusion.

There are three problems with toc fusion.  Now, as I start reworking the
address support in general, toc fusion and power9 fusion will likely be moved
into the new address support, but until they go, I'm going add this patch to
fix some of the obvious problems with toc fusion:

1) If you used -mno-power8-fusion -mtoc-fusion or -mno-power8-fusion
-mpower8-fusion-sign, it doesn't clear the toc fusion or sign fusion bits.
Code that only tests TOC fusion or P8 fusion sign bits, might generate code
that isn't enabled because the normal p8 fusion was not set.

2) Toc fusion checks whether code model is medium/large before the Linux
support enables setting code model as medium by default.  Thus if if you use
-mtoc-fusion and don't also use -mcmodel=medium explicitly, the compiler
complains that toc fusion is not compatible with small code model.

3) I suspect that toc fusion is not really appropriate for large code model,
because the TOC might be more than 2**32 away from the PC.  So I limited it to
medium code model.

4) Because toc fusion hasn't been enabled by default due to #2, I removed the
code to enable toc fusion after moving the tests after cmodel is set.

I have checked these patches on both big and little endian systems and there
was no regression.

FWIW, I did a spec 2006 run on a power8 system, enabling toc fusion, and an
additonal run with both toc fusion and power9 fusion.  The cactusADM benchmark
had a 2% drop in performance with toc fusion enabled.  On the other hand, when
I enabled the power9 fusion and toc fusion, cactusADM went back to the same
performance, and povray had a 2% bump.  The power8 systems don't have support
for the advanced fusion forms that were originally planned for power9.

One of my goals with the later work will be to move the addressing support into
the RTL code before register allocation.  This way we can accomidate various
fusion opportunities, and also deal with new addressing forms.  At the moment,
we split the addresses early, and each of the fusion forms then uses peephole2s
to try and glue things back together.

2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_option_override_internal): Move
	toc fusion support after the Linux port has set the default code
	model.  Do not enable it by default.  If either -mtoc-fusion or
	-mpower8-fusion-sign is used with -mno-power8-fusion, clear the
	toc fusion/sign bits.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch10b --]
[-- Type: text/plain, Size: 2674 bytes --]

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258765)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -4471,7 +4471,8 @@ rs6000_option_override_internal (bool gl
 	  if (TARGET_TOC_FUSION)
 	    error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
 
-	  rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+	  rs6000_isa_flags &= ~(OPTION_MASK_P8_FUSION_SIGN
+				| OPTION_MASK_TOC_FUSION);
 	}
       else
 	rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
@@ -4508,28 +4509,6 @@ rs6000_option_override_internal (bool gl
       && optimize >= 3)
     rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
 
-  /* TOC fusion requires 64-bit and medium/large code model.  */
-  if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
-    {
-      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
-      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
-	warning (0, N_("-mtoc-fusion requires 64-bit"));
-    }
-
-  if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
-    {
-      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
-      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
-	warning (0, N_("-mtoc-fusion requires medium/large code model"));
-    }
-
-  /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
-     model.  */
-  if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
-      && (TARGET_CMODEL != CMODEL_SMALL)
-      && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
-    rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
-
   /* ISA 3.0 vector instructions include ISA 2.07.  */
   if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
     {
@@ -4823,6 +4802,24 @@ rs6000_option_override_internal (bool gl
   SUB3TARGET_OVERRIDE_OPTIONS;
 #endif
 
+  /* TOC fusion requires 64-bit and medium code model.  This test has to be
+     after the SUBTARGET_OVERRIDE_OPTIONS, since medium code model is set
+     there.  Large code model can have offsets bigger than ADDIS/ADDI can
+     handle.  */
+  if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
+    {
+      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
+      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
+	warning (0, N_("-mtoc-fusion requires 64-bit"));
+    }
+
+  if (TARGET_TOC_FUSION && (TARGET_CMODEL != CMODEL_MEDIUM))
+    {
+      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
+      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
+	warning (0, N_("-mtoc-fusion requires medium code model"));
+    }
+
   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
     rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);
 

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #11

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 849 bytes --]

This is the last of the infrastructure patches that I have currently done.
This adds a new reg_addr flag to note whether the d-form address is a ds-form
(bottom 2 bits must be 0).  At present, nothing uses this, but I have plans for
it in the future.

2018-03-22  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (addr_mask_type): Grow mask to 16 bits.
	(RELOAD_REG_DS_OFFSET): New mask for DS-form addresses.
	(mode_supports_ds_form): New helper function to return if a reload
	register class uses DS-form addresses.
	(rs6000_debug_addr_mask): Print if we have DS-form addresses.
	(rs6000_setup_reg_addr_masks): Note which reload register classes
	use DS-form addresses.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch11b --]
[-- Type: text/plain, Size: 5199 bytes --]

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258782)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -503,16 +503,17 @@ static const struct reload_reg_map_type 
 /* Mask bits for each register class, indexed per mode.  Historically the
    compiler has been more restrictive which types can do PRE_MODIFY instead of
    PRE_INC and PRE_DEC, so keep track of sepaate bits for these two.  */
-typedef unsigned char addr_mask_type;
+typedef unsigned short addr_mask_type;
 
-#define RELOAD_REG_VALID	0x01	/* Mode valid in register..  */
-#define RELOAD_REG_MULTIPLE	0x02	/* Mode takes multiple registers.  */
-#define RELOAD_REG_INDEXED	0x04	/* Reg+reg addressing.  */
-#define RELOAD_REG_OFFSET	0x08	/* Reg+offset addressing. */
-#define RELOAD_REG_PRE_INCDEC	0x10	/* PRE_INC/PRE_DEC valid.  */
-#define RELOAD_REG_PRE_MODIFY	0x20	/* PRE_MODIFY valid.  */
-#define RELOAD_REG_AND_M16	0x40	/* AND -16 addressing.  */
-#define RELOAD_REG_QUAD_OFFSET	0x80	/* quad offset is limited.  */
+#define RELOAD_REG_VALID	0x001	/* Mode valid in register..  */
+#define RELOAD_REG_MULTIPLE	0x002	/* Mode takes multiple registers.  */
+#define RELOAD_REG_INDEXED	0x004	/* Reg+reg addressing.  */
+#define RELOAD_REG_OFFSET	0x008	/* Reg+offset addressing. */
+#define RELOAD_REG_PRE_INCDEC	0x010	/* PRE_INC/PRE_DEC valid.  */
+#define RELOAD_REG_PRE_MODIFY	0x020	/* PRE_MODIFY valid.  */
+#define RELOAD_REG_AND_M16	0x040	/* AND -16 addressing.  */
+#define RELOAD_REG_QUAD_OFFSET	0x080	/* quad offset is limited.  */
+#define RELOAD_REG_DS_OFFSET	0x100	/* DS-form (bottom 2 bits 0).  */
 
 /* Register type masks based on the type, of valid addressing modes.  */
 struct rs6000_reg_addr {
@@ -565,6 +566,16 @@ mode_supports_d_form (machine_mode mode,
   return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_OFFSET) != 0);
 }
 
+/* Return true if we have DS-form addressing in a given reload register class
+   or if some reload register class supports it.  DS-form addressing must have
+   the bottom 2 bits set to 0.  */
+static inline bool
+mode_supports_ds_form (machine_mode mode,
+		       enum rs6000_reload_reg_type rt = RELOAD_REG_ANY)
+{
+  return ((reg_addr[mode].addr_mask[rt] & RELOAD_REG_DS_OFFSET) != 0);
+}
+
 /* Return true if we have DQ-form addressing in a given reload register class
    or if some reload register class supports it.  DQ-form addressing must have
    the bottom 4 bits set to 0.  */
@@ -2349,6 +2360,8 @@ rs6000_debug_addr_mask (addr_mask_type m
 
   if ((mask & RELOAD_REG_QUAD_OFFSET) != 0)
     *p++ = 'O';
+  else if ((mask & RELOAD_REG_DS_OFFSET) != 0)
+    *p++ = 'O';
   else if ((mask & RELOAD_REG_OFFSET) != 0)
     *p++ = 'o';
   else if (keep_spaces)
@@ -3035,27 +3048,40 @@ rs6000_setup_reg_addr_masks (void)
 
 	  /* GPR and FPR registers can do REG+OFFSET addressing, except
 	     possibly for SDmode.  ISA 3.0 (i.e. power9) adds D-form addressing
-	     for 64-bit scalars and 32-bit SFmode to altivec registers.  */
-	  if ((addr_mask != 0) && !indexed_only_p
-	      && msize <= 8
-	      && (rc == RELOAD_REG_GPR
-		  || ((msize == 8 || m2 == SFmode)
-		      && (rc == RELOAD_REG_FPR
-			  || (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)))))
-	    addr_mask |= RELOAD_REG_OFFSET;
-
-	  /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
-	     instructions are enabled.  The offset for 128-bit VSX registers is
-	     only 12-bits.  While GPRs can handle the full offset range, VSX
-	     registers can only handle the restricted range.  */
-	  else if ((addr_mask != 0) && !indexed_only_p
-		   && msize == 16 && TARGET_P9_VECTOR
-		   && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
-		       || (m2 == TImode && TARGET_VSX)))
-	    {
-	      addr_mask |= RELOAD_REG_OFFSET;
-	      if (rc == RELOAD_REG_FPR || rc == RELOAD_REG_VMX)
-		addr_mask |= RELOAD_REG_QUAD_OFFSET;
+	     for 64-bit scalars and 32-bit SFmode to altivec registers.
+
+	     64-bit GPR and ISA 3.0 D-form use DS-form addressing with the
+	     bottom 2 bits set to 0.  */
+	  if ((addr_mask != 0) && !indexed_only_p)
+	    {
+	      if (msize <= 8 && rc == RELOAD_REG_GPR)
+		{
+		  if (msize == 8)
+		    addr_mask |= RELOAD_REG_OFFSET | RELOAD_REG_DS_OFFSET;
+		  else
+		    addr_mask |= RELOAD_REG_OFFSET;
+		}
+	      else if (msize == 8 || m2 == SFmode)
+		{
+		  if  (rc == RELOAD_REG_FPR)
+		    addr_mask |= RELOAD_REG_OFFSET;
+		  else if (rc == RELOAD_REG_VMX && TARGET_P9_VECTOR)
+		    addr_mask |= RELOAD_REG_OFFSET | RELOAD_REG_DS_OFFSET;
+		}
+
+	      /* VSX registers can do REG+OFFSET addresssing if ISA 3.0
+		 instructions are enabled.  The offset for 128-bit VSX
+		 registers is only 12-bits.  While GPRs use DS offsets for
+		 64-bit, VSX registers can only handle the DQ offsets.  */
+	      else if (msize == 16 && TARGET_P9_VECTOR
+		       && (ALTIVEC_OR_VSX_VECTOR_MODE (m2)
+			   || (m2 == TImode && TARGET_VSX)))
+		{
+		  if (rc == RELOAD_REG_GPR)
+		    addr_mask |= RELOAD_REG_OFFSET | RELOAD_REG_DS_OFFSET;
+		  else
+		    addr_mask |= RELOAD_REG_OFFSET | RELOAD_REG_QUAD_OFFSET;
+		}
 	    }
 
 	  /* VMX registers can do (REG & -16) and ((REG+REG) & -16)

Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #12

[Michael Meissner]

[-- Attachment #1: Type: text/plain, Size: 1410 bytes --]

When I last worked on fusion, I put a bunch of support to save the insn code of
various functions for creating fusion.  I never actually used these functions,
except printing them out with -mdebug=reg.  This patch deletes the generator
functions for the insns, but it does not delete the actual insns themselves.
The current peephole2 for power8 GPR load fusion, and power9 SF/DF load/store
fusion still generate these insns, but it doesn't use the gen_<whatever> to
create the insns.

I have built both little endian and big endian bootstrap compilers and there
were no regressions with these patches.

2018-03-27  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (struct rs6000_reg_addr): Eliminate
	unused insn code fields that were originally meant for adding
	fusion operations.
	(rs6000_debug_print_mode): Likewise.
	(rs6000_init_hard_regno_mode_ok): Likewise.
	* config/rs6000/rs6000.md (fusion_gpr_load_<mode>): Turn off insn
	generator for the fusion functions that are not referenced by name.
	(fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store): Likewise.
	(fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load): Likewise.
	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load): Likewise.
	(fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store): Likewise.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

[-- Attachment #2: ext-addr.rev2-patch12b --]
[-- Type: text/plain, Size: 9421 bytes --]

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258818)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -522,15 +522,6 @@ struct rs6000_reg_addr {
   enum insn_code reload_fpr_gpr;	/* INSN to move from FPR to GPR.  */
   enum insn_code reload_gpr_vsx;	/* INSN to move from GPR to VSX.  */
   enum insn_code reload_vsx_gpr;	/* INSN to move from VSX to GPR.  */
-  enum insn_code fusion_gpr_ld;		/* INSN for fusing gpr ADDIS/loads.  */
-					/* INSNs for fusing addi with loads
-					   or stores for each reg. class.  */					   
-  enum insn_code fusion_addi_ld[(int)N_RELOAD_REG];
-  enum insn_code fusion_addi_st[(int)N_RELOAD_REG];
-					/* INSNs for fusing addis with loads
-					   or stores for each reg. class.  */					   
-  enum insn_code fusion_addis_ld[(int)N_RELOAD_REG];
-  enum insn_code fusion_addis_st[(int)N_RELOAD_REG];
   addr_mask_type addr_mask[(int)N_RELOAD_REG]; /* Valid address masks.  */
   bool scalar_in_vmx_p;			/* Scalar value can go in VMX.  */
   bool fused_toc;			/* Mode supports TOC fusion.  */
@@ -2393,7 +2384,6 @@ rs6000_debug_print_mode (ssize_t m)
 {
   ssize_t rc;
   int spaces = 0;
-  bool fuse_extra_p;
 
   fprintf (stderr, "Mode: %-5s", GET_MODE_NAME (m));
   for (rc = 0; rc < N_RELOAD_REG; rc++)
@@ -2416,82 +2406,6 @@ rs6000_debug_print_mode (ssize_t m)
   else
     spaces += sizeof ("  Upper=y") - 1;
 
-  fuse_extra_p = ((reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
-		  || reg_addr[m].fused_toc);
-  if (!fuse_extra_p)
-    {
-      for (rc = 0; rc < N_RELOAD_REG; rc++)
-	{
-	  if (rc != RELOAD_REG_ANY)
-	    {
-	      if (reg_addr[m].fusion_addi_ld[rc]     != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addi_ld[rc]  != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addi_st[rc]  != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing
-		  || reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
-		{
-		  fuse_extra_p = true;
-		  break;
-		}
-	    }
-	}
-    }
-
-  if (fuse_extra_p)
-    {
-      fprintf (stderr, "%*s  Fuse:", spaces, "");
-      spaces = 0;
-
-      for (rc = 0; rc < N_RELOAD_REG; rc++)
-	{
-	  if (rc != RELOAD_REG_ANY)
-	    {
-	      char load, store;
-
-	      if (reg_addr[m].fusion_addis_ld[rc] != CODE_FOR_nothing)
-		load = 'l';
-	      else if (reg_addr[m].fusion_addi_ld[rc] != CODE_FOR_nothing)
-		load = 'L';
-	      else
-		load = '-';
-
-	      if (reg_addr[m].fusion_addis_st[rc] != CODE_FOR_nothing)
-		store = 's';
-	      else if (reg_addr[m].fusion_addi_st[rc] != CODE_FOR_nothing)
-		store = 'S';
-	      else
-		store = '-';
-
-	      if (load == '-' && store == '-')
-		spaces += 5;
-	      else
-		{
-		  fprintf (stderr, "%*s%c=%c%c", (spaces + 1), "",
-			   reload_reg_map[rc].name[0], load, store);
-		  spaces = 0;
-		}
-	    }
-	}
-
-      if (reg_addr[m].fusion_gpr_ld != CODE_FOR_nothing)
-	{
-	  fprintf (stderr, "%*sP8gpr", (spaces + 1), "");
-	  spaces = 0;
-	}
-      else
-	spaces += sizeof (" P8gpr") - 1;
-
-      if (reg_addr[m].fused_toc)
-	{
-	  fprintf (stderr, "%*sToc", (spaces + 1), "");
-	  spaces = 0;
-	}
-      else
-	spaces += sizeof (" Toc") - 1;
-    }
-  else
-    spaces += sizeof ("  Fuse: G=ls F=ls v=ls P8gpr Toc") - 1;
-
   if (rs6000_vector_unit[m] != VECTOR_NONE
       || rs6000_vector_mem[m] != VECTOR_NONE)
     {
@@ -3580,119 +3494,6 @@ rs6000_init_hard_regno_mode_ok (bool glo
 	}
     }
 
-  /* Setup the fusion operations.  */
-  if (TARGET_P8_FUSION)
-    {
-      reg_addr[QImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_qi;
-      reg_addr[HImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_hi;
-      reg_addr[SImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_si;
-      if (TARGET_64BIT)
-	reg_addr[DImode].fusion_gpr_ld = CODE_FOR_fusion_gpr_load_di;
-    }
-
-  if (TARGET_P9_FUSION)
-    {
-      struct fuse_insns {
-	enum machine_mode mode;			/* mode of the fused type.  */
-	enum machine_mode pmode;		/* pointer mode.  */
-	enum rs6000_reload_reg_type rtype;	/* register type.  */
-	enum insn_code load;			/* load insn.  */
-	enum insn_code store;			/* store insn.  */
-      };
-
-      static const struct fuse_insns addis_insns[] = {
-	{ E_SFmode, E_DImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_di_sf_load,
-	  CODE_FOR_fusion_vsx_di_sf_store },
-
-	{ E_SFmode, E_SImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_si_sf_load,
-	  CODE_FOR_fusion_vsx_si_sf_store },
-
-	{ E_DFmode, E_DImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_di_df_load,
-	  CODE_FOR_fusion_vsx_di_df_store },
-
-	{ E_DFmode, E_SImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_si_df_load,
-	  CODE_FOR_fusion_vsx_si_df_store },
-
-	{ E_DImode, E_DImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_di_di_load,
-	  CODE_FOR_fusion_vsx_di_di_store },
-
-	{ E_DImode, E_SImode, RELOAD_REG_FPR,
-	  CODE_FOR_fusion_vsx_si_di_load,
-	  CODE_FOR_fusion_vsx_si_di_store },
-
-	{ E_QImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_qi_load,
-	  CODE_FOR_fusion_gpr_di_qi_store },
-
-	{ E_QImode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_qi_load,
-	  CODE_FOR_fusion_gpr_si_qi_store },
-
-	{ E_HImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_hi_load,
-	  CODE_FOR_fusion_gpr_di_hi_store },
-
-	{ E_HImode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_hi_load,
-	  CODE_FOR_fusion_gpr_si_hi_store },
-
-	{ E_SImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_si_load,
-	  CODE_FOR_fusion_gpr_di_si_store },
-
-	{ E_SImode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_si_load,
-	  CODE_FOR_fusion_gpr_si_si_store },
-
-	{ E_SFmode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_sf_load,
-	  CODE_FOR_fusion_gpr_di_sf_store },
-
-	{ E_SFmode, E_SImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_si_sf_load,
-	  CODE_FOR_fusion_gpr_si_sf_store },
-
-	{ E_DImode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_di_load,
-	  CODE_FOR_fusion_gpr_di_di_store },
-
-	{ E_DFmode, E_DImode, RELOAD_REG_GPR,
-	  CODE_FOR_fusion_gpr_di_df_load,
-	  CODE_FOR_fusion_gpr_di_df_store },
-      };
-
-      machine_mode cur_pmode = Pmode;
-      size_t i;
-
-      for (i = 0; i < ARRAY_SIZE (addis_insns); i++)
-	{
-	  machine_mode xmode = addis_insns[i].mode;
-	  enum rs6000_reload_reg_type rtype = addis_insns[i].rtype;
-
-	  if (addis_insns[i].pmode != cur_pmode)
-	    continue;
-
-	  if (rtype == RELOAD_REG_FPR && !TARGET_HARD_FLOAT)
-	    continue;
-
-	  reg_addr[xmode].fusion_addis_ld[rtype] = addis_insns[i].load;
-	  reg_addr[xmode].fusion_addis_st[rtype] = addis_insns[i].store;
-
-	  if (rtype == RELOAD_REG_FPR && TARGET_P9_VECTOR)
-	    {
-	      reg_addr[xmode].fusion_addis_ld[RELOAD_REG_VMX]
-		= addis_insns[i].load;
-	      reg_addr[xmode].fusion_addis_st[RELOAD_REG_VMX]
-		= addis_insns[i].store;
-	    }
-	}
-    }
-
   /* Note which types we support fusing TOC setup plus memory insn.  We only do
      fused TOCs for medium/large code models.  */
   if (TARGET_P8_FUSION && TARGET_TOC_FUSION && TARGET_POWERPC64
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md	(revision 258818)
+++ gcc/config/rs6000/rs6000.md	(working copy)
@@ -13692,10 +13692,9 @@ (define_peephole2
   DONE;
 })
 
-;; Fusion insn, created by the define_peephole2 above (and eventually by
-;; reload)
+;; Fusion insn, created by the define_peephole2 above
 
-(define_insn "fusion_gpr_load_<mode>"
+(define_insn "*fusion_gpr_load_<mode>"
   [(set (match_operand:INT1 0 "base_reg_operand" "=b")
 	(unspec:INT1 [(match_operand:INT1 1 "fusion_addis_mem_combo_load" "wF")]
 		     UNSPEC_FUSION_GPR))]
@@ -13764,7 +13763,7 @@ (define_peephole2
 ;; reload).  Because we want to eventually have secondary_reload generate
 ;; these, they have to have a single alternative that gives the register
 ;; classes.  This means we need to have separate gpr/fpr/altivec versions.
-(define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load"
+(define_insn "*fusion_gpr_<P:mode>_<GPR_FUSION:mode>_load"
   [(set (match_operand:GPR_FUSION 0 "int_reg_operand" "=r")
 	(unspec:GPR_FUSION
 	 [(match_operand:GPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")]
@@ -13782,7 +13781,7 @@ (define_insn "fusion_gpr_<P:mode>_<GPR_F
   [(set_attr "type" "load")
    (set_attr "length" "8")])
 
-(define_insn "fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store"
+(define_insn "*fusion_gpr_<P:mode>_<GPR_FUSION:mode>_store"
   [(set (match_operand:GPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF")
 	(unspec:GPR_FUSION
 	 [(match_operand:GPR_FUSION 1 "int_reg_operand" "r")]
@@ -13795,7 +13794,7 @@ (define_insn "fusion_gpr_<P:mode>_<GPR_F
   [(set_attr "type" "store")
    (set_attr "length" "8")])
 
-(define_insn "fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load"
+(define_insn "*fusion_vsx_<P:mode>_<FPR_FUSION:mode>_load"
   [(set (match_operand:FPR_FUSION 0 "vsx_register_operand" "=dwb")
 	(unspec:FPR_FUSION
 	 [(match_operand:FPR_FUSION 1 "fusion_addis_mem_combo_load" "wF")]
@@ -13808,7 +13807,7 @@ (define_insn "fusion_vsx_<P:mode>_<FPR_F
   [(set_attr "type" "fpload")
    (set_attr "length" "8")])
 
-(define_insn "fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store"
+(define_insn "*fusion_vsx_<P:mode>_<FPR_FUSION:mode>_store"
   [(set (match_operand:FPR_FUSION 0 "fusion_addis_mem_combo_store" "=wF")
 	(unspec:FPR_FUSION
 	 [(match_operand:FPR_FUSION 1 "vsx_register_operand" "dwb")]