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Violators will be prosecuted; Thu, 22 Mar 2018 11:34:23 -0400 Received: from b01ledav002.gho.pok.ibm.com (b01ledav002.gho.pok.ibm.com [9.57.199.107]) by b01cxnp22034.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id w2MFYMwa52363480; Thu, 22 Mar 2018 15:34:22 GMT Received: from b01ledav002.gho.pok.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DCDBE124037; Thu, 22 Mar 2018 12:36:31 -0400 (EDT) Received: from ibm-tiger.the-meissners.org (unknown [9.32.77.111]) by b01ledav002.gho.pok.ibm.com (Postfix) with ESMTP id C1F8012404E; Thu, 22 Mar 2018 12:36:31 -0400 (EDT) Received: by ibm-tiger.the-meissners.org (Postfix, from userid 500) id 205994A297; Thu, 22 Mar 2018 11:34:22 -0400 (EDT) Date: Thu, 22 Mar 2018 15:35:00 -0000 From: Michael Meissner To: Michael Meissner , GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt Subject: Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #8 Mail-Followup-To: Michael Meissner , GCC Patches , Segher Boessenkool , David Edelsohn , Bill Schmidt References: <20180322120346.GA7987@ibm-tiger.the-meissners.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="SFyWQ0h3ruR435lw" Content-Disposition: inline In-Reply-To: <20180322120346.GA7987@ibm-tiger.the-meissners.org> User-Agent: Mutt/1.5.20 (2009-12-10) X-TM-AS-GCONF: 00 x-cbid: 18032215-0024-0000-0000-0000033A83F8 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008722; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000255; SDB=6.01006799; UDB=6.00512647; IPR=6.00786087; MB=3.00020181; MTD=3.00000008; XFM=3.00000015; UTC=2018-03-22 15:34:24 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 18032215-0025-0000-0000-000047693B2D Message-Id: <20180322153421.GD24934@ibm-tiger.the-meissners.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2018-03-22_08:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1803220180 X-IsSubscribed: yes X-SW-Source: 2018-03/txt/msg01200.txt.bz2 --SFyWQ0h3ruR435lw Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-length: 834 Patches #5..8 just add comments and reformat movd{f,d} constraints and attributes so that it is a lot easier to tell which constraints and attributes go together. These do not (or at least should not) change the code generated. Patch #9 does the same thing for mov{sf,sd} when floating point registers are not available. I have done both big and little endian bootstrap builds with all 5 patches installed. There were no regressions. 2018-03-22 Michael Meissner * config/rs6000/rs6000.md (mov_softfloat64, FMOVE64): Reformat alternatives and attributes so it is easier to identify which constraints/attributes go with which instruction. -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797 --SFyWQ0h3ruR435lw Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="ext-addr.rev2-patch08b" Content-length: 1560 Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 258735) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -7515,9 +7515,18 @@ (define_insn "*mov_hardfloat64" (set_attr "size" "64") (set_attr "length" "4")]) +;; STD LD MR MT MF G-const +;; H-const F-const Special + (define_insn "*mov_softfloat64" - [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") - (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] + [(set (match_operand:FMOVE64 0 "nonimmediate_operand" + "=Y, r, r, cl, r, r, + r, r, *h") + + (match_operand:FMOVE64 1 "input_operand" + "r, Y, r, r, h, G, + H, F, 0"))] + "TARGET_POWERPC64 && TARGET_SOFT_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -7531,8 +7540,13 @@ (define_insn "*mov_softfloat64" # # nop" - [(set_attr "type" "store,load,*,mtjmpr,mfjmpr,*,*,*,*") - (set_attr "length" "4,4,4,4,4,8,12,16,4")]) + [(set_attr "type" + "store, load, *, mtjmpr, mfjmpr, *, + *, *, *") + + (set_attr "length" + "4, 4, 4, 4, 4, 8, + 12, 16, 4")]) (define_expand "mov" [(set (match_operand:FMOVE128 0 "general_operand") --SFyWQ0h3ruR435lw--