Re: [RFC Patch], PowerPC memory support pre-gcc9, Version 2, Patch #10

[Michael Meissner <meissner@linux.vnet.ibm.com>]

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In preparing to start work on reorganizing the intermediate address support in
PowerPC, I noticed there were some thinkos in the undocumented toc fusion.

There are three problems with toc fusion.  Now, as I start reworking the
address support in general, toc fusion and power9 fusion will likely be moved
into the new address support, but until they go, I'm going add this patch to
fix some of the obvious problems with toc fusion:

1) If you used -mno-power8-fusion -mtoc-fusion or -mno-power8-fusion
-mpower8-fusion-sign, it doesn't clear the toc fusion or sign fusion bits.
Code that only tests TOC fusion or P8 fusion sign bits, might generate code
that isn't enabled because the normal p8 fusion was not set.

2) Toc fusion checks whether code model is medium/large before the Linux
support enables setting code model as medium by default.  Thus if if you use
-mtoc-fusion and don't also use -mcmodel=medium explicitly, the compiler
complains that toc fusion is not compatible with small code model.

3) I suspect that toc fusion is not really appropriate for large code model,
because the TOC might be more than 2**32 away from the PC.  So I limited it to
medium code model.

4) Because toc fusion hasn't been enabled by default due to #2, I removed the
code to enable toc fusion after moving the tests after cmodel is set.

I have checked these patches on both big and little endian systems and there
was no regression.

FWIW, I did a spec 2006 run on a power8 system, enabling toc fusion, and an
additonal run with both toc fusion and power9 fusion.  The cactusADM benchmark
had a 2% drop in performance with toc fusion enabled.  On the other hand, when
I enabled the power9 fusion and toc fusion, cactusADM went back to the same
performance, and povray had a 2% bump.  The power8 systems don't have support
for the advanced fusion forms that were originally planned for power9.

One of my goals with the later work will be to move the addressing support into
the RTL code before register allocation.  This way we can accomidate various
fusion opportunities, and also deal with new addressing forms.  At the moment,
we split the addresses early, and each of the fusion forms then uses peephole2s
to try and glue things back together.

2018-03-21  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/rs6000.c (rs6000_option_override_internal): Move
	toc fusion support after the Linux port has set the default code
	model.  Do not enable it by default.  If either -mtoc-fusion or
	-mpower8-fusion-sign is used with -mno-power8-fusion, clear the
	toc fusion/sign bits.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797

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Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 258765)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -4471,7 +4471,8 @@ rs6000_option_override_internal (bool gl
 	  if (TARGET_TOC_FUSION)
 	    error ("%qs requires %qs", "-mtoc-fusion", "-mpower8-fusion");
 
-	  rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+	  rs6000_isa_flags &= ~(OPTION_MASK_P8_FUSION_SIGN
+				| OPTION_MASK_TOC_FUSION);
 	}
       else
 	rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
@@ -4508,28 +4509,6 @@ rs6000_option_override_internal (bool gl
       && optimize >= 3)
     rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
 
-  /* TOC fusion requires 64-bit and medium/large code model.  */
-  if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
-    {
-      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
-      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
-	warning (0, N_("-mtoc-fusion requires 64-bit"));
-    }
-
-  if (TARGET_TOC_FUSION && (TARGET_CMODEL == CMODEL_SMALL))
-    {
-      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
-      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
-	warning (0, N_("-mtoc-fusion requires medium/large code model"));
-    }
-
-  /* Turn on -mtoc-fusion by default if p8-fusion and 64-bit medium/large code
-     model.  */
-  if (TARGET_P8_FUSION && !TARGET_TOC_FUSION && TARGET_POWERPC64
-      && (TARGET_CMODEL != CMODEL_SMALL)
-      && !(rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION))
-    rs6000_isa_flags |= OPTION_MASK_TOC_FUSION;
-
   /* ISA 3.0 vector instructions include ISA 2.07.  */
   if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
     {
@@ -4823,6 +4802,24 @@ rs6000_option_override_internal (bool gl
   SUB3TARGET_OVERRIDE_OPTIONS;
 #endif
 
+  /* TOC fusion requires 64-bit and medium code model.  This test has to be
+     after the SUBTARGET_OVERRIDE_OPTIONS, since medium code model is set
+     there.  Large code model can have offsets bigger than ADDIS/ADDI can
+     handle.  */
+  if (TARGET_TOC_FUSION && !TARGET_POWERPC64)
+    {
+      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
+      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
+	warning (0, N_("-mtoc-fusion requires 64-bit"));
+    }
+
+  if (TARGET_TOC_FUSION && (TARGET_CMODEL != CMODEL_MEDIUM))
+    {
+      rs6000_isa_flags &= ~OPTION_MASK_TOC_FUSION;
+      if ((rs6000_isa_flags_explicit & OPTION_MASK_TOC_FUSION) != 0)
+	warning (0, N_("-mtoc-fusion requires medium code model"));
+    }
+
   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
     rs6000_print_isa_options (stderr, 0, "after subtarget", rs6000_isa_flags);