From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9841 invoked by alias); 27 Apr 2018 21:27:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 9826 invoked by uid 89); 27 Apr 2018 21:27:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.6 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=opportunities, filling, HX-Received:sk:v12-v6m, 1.9.1 X-HELO: mail-wr0-f169.google.com Received: from mail-wr0-f169.google.com (HELO mail-wr0-f169.google.com) (209.85.128.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Apr 2018 21:27:44 +0000 Received: by mail-wr0-f169.google.com with SMTP id o2-v6so55656wrj.13 for ; Fri, 27 Apr 2018 14:27:43 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=ZOn5KdChARxomZSfaolatx9v/rtstheU8wSP+Lo0ua0=; b=gUbj15BJTlfuX9ayL+0NDM7G3iWefHJ8rO6wkVIhClAS9tAhdxL+QFOM1WPrXK7f21 Ui1odIehtFRYHSeAnTnyusBwWvuKfu5bD9+7Vh3QLtBziszLaiNIi8xVQ/nunUXAvKWQ Jx9fX6R3y3E3fiCT3KxykIaDEJHGg721qy+GtzxfVw5SX5bvruqDhm45jR4qAncSx1sI /P0Fj8jLNETKEob379K5jPkBN6GNsPZETAYM9WyJu0vzR94v22f8Rp/8phWRXpM+hJHe x+RM7yIRGyG9A1VgaSZE7OIK3savN/Yqxr0QVM1eIXdhmdnhrpcncYc0OSuT/ZHGBvyP YVNw== X-Gm-Message-State: ALQs6tDv6Id3MY/DpTxQJ2B7VXIRj1OWqgkAxdyMDO1oO/HeV/QYUWT5 uOPKtEeXG4NZSoeK5K+mD4/U1g== X-Google-Smtp-Source: AB8JxZp6cT5lE34B207jNBYoTXpfweDTW9boYeBpVVgGFGDYHbLmZFlsl1NXq91oDvP9w88HIaVtEw== X-Received: by 2002:adf:e28c:: with SMTP id v12-v6mr1075153wri.188.1524864462091; Fri, 27 Apr 2018 14:27:42 -0700 (PDT) Received: from localhost (host86-135-253-94.range86-135.btcentralplus.com. [86.135.253.94]) by smtp.gmail.com with ESMTPSA id e7-v6sm595373wrn.88.2018.04.27.14.27.41 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 27 Apr 2018 14:27:41 -0700 (PDT) Date: Fri, 27 Apr 2018 21:39:00 -0000 From: Andrew Burgess To: Claudiu Zissulescu Cc: gcc-patches@gcc.gnu.org, Francois.Bedard@synopsys.com, Claudiu Zissulescu Subject: Re: [PATCH 3/5] [ARC] Update movhi and movdi patterns. Message-ID: <20180427212740.GC3375@embecosm.com> References: <1523005214-1611-1-git-send-email-claziss@synopsys.com> <1523005214-1611-4-git-send-email-claziss@synopsys.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1523005214-1611-4-git-send-email-claziss@synopsys.com> X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-04/txt/msg01256.txt.bz2 * Claudiu Zissulescu [2018-04-06 11:00:12 +0200]: > From: Claudiu Zissulescu > > Allow signed 6-bit short immediates into st[d] instructions. > > 2017-10-19 Claudiu Zissulescu > > * config/arc/arc.c (arc_split_move): Allow signed 6-bit constants > as source of std instructions. > * config/arc/arc.md (movsi_insn): Update pattern predicate to > allow 6-bit constants as source for store instructions. > (movdi_insn): Update instruction pattern to allow 6-bit constants > as source for store instructions. > > testsuite/ > 2017-10-19 Claudiu Zissulescu > > * gcc.target/arc/store-merge-1.c: New test. > * gcc.target/arc/add_n-combine.c: Update test. Looks good thanks, Andrew > --- > gcc/config/arc/arc.c | 3 ++- > gcc/config/arc/arc.md | 25 +++++++++++++------------ > gcc/testsuite/gcc.target/arc/add_n-combine.c | 2 +- > gcc/testsuite/gcc.target/arc/store-merge-1.c | 17 +++++++++++++++++ > 4 files changed, 33 insertions(+), 14 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/arc/store-merge-1.c > > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 47d3ba4..2ccdce8 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -9669,7 +9669,8 @@ arc_split_move (rtx *operands) > > if (TARGET_LL64 > && ((memory_operand (operands[0], mode) > - && even_register_operand (operands[1], mode)) > + && (even_register_operand (operands[1], mode) > + || satisfies_constraint_Cm3 (operands[1]))) > || (memory_operand (operands[1], mode) > && even_register_operand (operands[0], mode)))) > { > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index ffd9d5b..0fc7aba 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -740,7 +740,9 @@ archs4x, archs4xd, archs4xd_slow" > /* Don't use a LIMM that we could load with a single insn - we loose > delay-slot filling opportunities. */ > && !satisfies_constraint_I (operands[1]) > - && satisfies_constraint_Usc (operands[0]))" > + && satisfies_constraint_Usc (operands[0])) > + || (satisfies_constraint_Cm3 (operands[1]) > + && memory_operand (operands[0], SImode))" > "@ > mov%? %0,%1%& ;0 > mov%? %0,%1%& ;1 > @@ -1237,10 +1239,12 @@ archs4x, archs4xd, archs4xd_slow" > ") > > (define_insn_and_split "*movdi_insn" > - [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r,m") > - (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,c"))] > + [(set (match_operand:DI 0 "move_dest_operand" "=w, w,r, m") > + (match_operand:DI 1 "move_double_src_operand" "c,Hi,m,cCm3"))] > "register_operand (operands[0], DImode) > - || register_operand (operands[1], DImode)" > + || register_operand (operands[1], DImode) > + || (satisfies_constraint_Cm3 (operands[1]) > + && memory_operand (operands[0], DImode))" > "* > { > switch (which_alternative) > @@ -1250,19 +1254,16 @@ archs4x, archs4xd, archs4xd_slow" > > case 2: > if (TARGET_LL64 > - && ((even_register_operand (operands[0], DImode) > - && memory_operand (operands[1], DImode)) > - || (memory_operand (operands[0], DImode) > - && even_register_operand (operands[1], DImode)))) > + && memory_operand (operands[1], DImode) > + && even_register_operand (operands[0], DImode)) > return \"ldd%U1%V1 %0,%1%&\"; > return \"#\"; > > case 3: > if (TARGET_LL64 > - && ((even_register_operand (operands[0], DImode) > - && memory_operand (operands[1], DImode)) > - || (memory_operand (operands[0], DImode) > - && even_register_operand (operands[1], DImode)))) > + && memory_operand (operands[0], DImode) > + && (even_register_operand (operands[1], DImode) > + || satisfies_constraint_Cm3 (operands[1]))) > return \"std%U0%V0 %1,%0\"; > return \"#\"; > } > diff --git a/gcc/testsuite/gcc.target/arc/add_n-combine.c b/gcc/testsuite/gcc.target/arc/add_n-combine.c > index db6454f..cd32ed3 100644 > --- a/gcc/testsuite/gcc.target/arc/add_n-combine.c > +++ b/gcc/testsuite/gcc.target/arc/add_n-combine.c > @@ -45,4 +45,4 @@ void f() { > a(at3.bn[bu]); > } > > -/* { dg-final { scan-rtl-dump-times "\\*add_n" 3 "combine" } } */ > +/* { dg-final { scan-rtl-dump-times "\\*add_n" 2 "combine" } } */ > diff --git a/gcc/testsuite/gcc.target/arc/store-merge-1.c b/gcc/testsuite/gcc.target/arc/store-merge-1.c > new file mode 100644 > index 0000000..4bb8dcb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arc/store-merge-1.c > @@ -0,0 +1,17 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O3" } */ > + > +/* This tests checks if we use st w6,[reg] format. */ > + > +typedef struct { > + unsigned long __val[2]; > +} sigset_t; > + > +int sigemptyset2 (sigset_t *set) > +{ > + set->__val[0] = 0; > + set->__val[1] = 0; > + return 0; > +} > + > +/* { dg-final { scan-assembler-times "st 0,\\\[r" 2 } } */ > -- > 1.9.1 >