[PATCH 1/4] [ARC] Add more additional register names

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* [PATCH 1/4] [ARC] Add more additional register names
@ 2018-07-16 12:29 Claudiu Zissulescu
  2018-07-16 12:29 ` [PATCH 4/4] [ARC] Update default optimizations for size Claudiu Zissulescu
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2018-07-16 12:29 UTC (permalink / raw)
  To: gcc-patches; +Cc: fbedard, andrew.burgess, claziss

From: claziss <claziss@synopsys.com>

gcc/
2017-06-14  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add additional
	register names.
---
 gcc/config/arc/arc.h | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 1780034aabe..3648314eaca 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -1215,7 +1215,15 @@ extern char rname56[], rname57[], rname58[], rname59[];
 {						\
   {"ilink",  29},				\
   {"r29",    29},				\
-  {"r30",    30}				\
+  {"r30",    30},				\
+  {"r40",    40},				\
+  {"r41",    41},				\
+  {"r42",    42},				\
+  {"r43",    43},				\
+  {"r56",    56},				\
+  {"r57",    57},				\
+  {"r58",    58},				\
+  {"r59",    59}				\
 }
 
 /* Entry to the insn conditionalizer.  */
-- 
2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 4/4] [ARC] Update default optimizations for size.
  2018-07-16 12:29 [PATCH 1/4] [ARC] Add more additional register names Claudiu Zissulescu
@ 2018-07-16 12:29 ` Claudiu Zissulescu
  2018-07-16 12:29 ` [PATCH 3/4] [ARC] Improve instruction selection for fp moves Claudiu Zissulescu
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2018-07-16 12:29 UTC (permalink / raw)
  To: gcc-patches; +Cc: fbedard, andrew.burgess

Update the list of default optimizations used for size compilations.

gcc/
2018-07-10  Claudiu Zissulescu  <claziss@synopsys.com>

	* common/config/arc/arc-common.c (arc_option_optimization_table):
	Update default optimizations for size.
---
 gcc/common/config/arc/arc-common.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/gcc/common/config/arc/arc-common.c b/gcc/common/config/arc/arc-common.c
index f866a0ad523..578431a279d 100644
--- a/gcc/common/config/arc/arc-common.c
+++ b/gcc/common/config/arc/arc-common.c
@@ -46,17 +46,22 @@ arc_option_init_struct (struct gcc_options *opts)
 #define OPT_LEVELS_3_PLUS_SPEED_ONLY OPT_LEVELS_3_PLUS
 static const struct default_options arc_option_optimization_table[] =
   {
-    { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_mRcq, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_mRcw, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_msize_level_, NULL, 1 },
-    { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
-    { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
-    { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_mearly_cbranchsi, NULL, 1 },
     { OPT_LEVELS_ALL, OPT_mbbit_peephole, NULL, 1 },
+    { OPT_LEVELS_SIZE, OPT_ftree_loop_optimize, NULL, 0},
+    { OPT_LEVELS_SIZE, OPT_fmove_loop_invariants, NULL, 0},
+    { OPT_LEVELS_SIZE, OPT_fbranch_count_reg, NULL, 0},
+    { OPT_LEVELS_SIZE, OPT_fdelayed_branch, NULL, 0 },
+    { OPT_LEVELS_SIZE, OPT_fsection_anchors, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_mq_class, NULL, 1 },
     { OPT_LEVELS_SIZE, OPT_mcase_vector_pcrel, NULL, 1 },
+    { OPT_LEVELS_SIZE, OPT_msize_level_, NULL, 3 },
+    { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
+    { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_msize_level_, NULL, 0 },
+    { OPT_LEVELS_3_PLUS_SPEED_ONLY, OPT_malign_call, NULL, 1 },
     { OPT_LEVELS_NONE, 0, NULL, 0 }
   };
 
-- 
2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 3/4] [ARC] Improve instruction selection for fp moves.
  2018-07-16 12:29 [PATCH 1/4] [ARC] Add more additional register names Claudiu Zissulescu
  2018-07-16 12:29 ` [PATCH 4/4] [ARC] Update default optimizations for size Claudiu Zissulescu
@ 2018-07-16 12:29 ` Claudiu Zissulescu
  2018-07-16 12:29 ` [PATCH 2/4] [ARX][FIX] Fix uncache attribute Claudiu Zissulescu
  2018-07-25 13:49 ` [PATCH 1/4] [ARC] Add more additional register names Andrew Burgess
  3 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2018-07-16 12:29 UTC (permalink / raw)
  To: gcc-patches; +Cc: fbedard, andrew.burgess

Improve selection of short instruction for fp-moves.

gcc/
2018-05-17  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.md (movsf_insn): Add short instruction selection.
	* config/arc/constraints.md (CfZ): New constraint.
	* config/arc/fpu.md (addssf3_fpu): Use CfZ constraint.
	(subsf3_fpu): Likewise.
	(cmpsf_fpu): Likewise.
	(cmpsf_fpu_uneq): Likewise.
---
 gcc/config/arc/arc.md         | 25 +++++++++------
 gcc/config/arc/constraints.md |  6 ++++
 gcc/config/arc/fpu.md         | 59 +++++++++++++++++------------------
 3 files changed, 50 insertions(+), 40 deletions(-)

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 26aa3b31649..8f27c0f2c05 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -1294,19 +1294,24 @@ archs4x, archs4xd, archs4xd_slow"
   "if (prepare_move_operands (operands, SFmode)) DONE;")
 
 (define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "move_dest_operand"    "=h,w,w,r,m")
-	(match_operand:SF 1 "move_src_operand"   "hCm1,c,E,m,c"))]
+  [(set (match_operand:SF 0 "move_dest_operand"   "=h,h,   r,r,  q,S,Usc,r,m")
+	(match_operand:SF 1 "move_src_operand"  "hCfZ,E,rCfZ,E,Uts,q,  E,m,r"))]
   "register_operand (operands[0], SFmode)
    || register_operand (operands[1], SFmode)"
   "@
-   mov%? %0,%1
-   mov%? %0,%1
-   mov%? %0,%1 ; %A1
-   ld%U1%V1 %0,%1
-   st%U0%V0 %1,%0"
-  [(set_attr "type" "move,move,move,load,store")
-   (set_attr "predicable" "no,yes,yes,no,no")
-   (set_attr "iscompact" "true,false,false,false,false")])
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1 ; %A1
+   mov%?\\t%0,%1
+   mov%?\\t%0,%1 ; %A1
+   ld%?%U1\\t%0,%1
+   st%?\\t%1,%0
+   st%U0%V0\\t%1,%0
+   ld%U1%V1\\t%0,%1
+   st%U0%V0\\t%1,%0"
+  [(set_attr "type" "move,move,move,move,load,store,store,load,store")
+   (set_attr "predicable" "no,no,yes,yes,no,no,no,no,no")
+   (set_attr "length" "*,*,4,*,*,*,*,*,*")
+   (set_attr "iscompact" "true,true_limm,false,false,true,true,false,false,false")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "move_dest_operand" "")
diff --git a/gcc/config/arc/constraints.md b/gcc/config/arc/constraints.md
index c304d535ad8..f9ef3f94dfe 100644
--- a/gcc/config/arc/constraints.md
+++ b/gcc/config/arc/constraints.md
@@ -314,6 +314,12 @@
   (and (match_code "const_double")
        (match_test "1")))
 
+(define_constraint "CfZ"
+  "@internal
+   Match a floating-point zero"
+  (and (match_code "const_double")
+       (match_test "op == CONST0_RTX (SFmode)")))
+
 ;; Memory constraints
 (define_memory_constraint "T"
   "@internal
diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md
index 9457922667e..6289e9c3f59 100644
--- a/gcc/config/arc/fpu.md
+++ b/gcc/config/arc/fpu.md
@@ -6,34 +6,34 @@
 
 ;; Addition
 (define_insn "*addsf3_fpu"
-  [(set (match_operand:SF 0 "register_operand"           "=r,r,r,r,r")
-	(plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,0,r,F")
-		 (match_operand:SF 2 "nonmemory_operand"  "r,r,F,F,r")))]
+  [(set (match_operand:SF 0 "register_operand"           "=r,r,  r,r,r,r")
+	(plus:SF (match_operand:SF 1 "nonmemory_operand" "%0,r,  r,0,r,F")
+		 (match_operand:SF 2 "nonmemory_operand"  "r,r,CfZ,F,F,r")))]
   "TARGET_FP_SP_BASE
    && (register_operand (operands[1], SFmode)
        || register_operand (operands[2], SFmode))"
-  "fsadd%? %0,%1,%2"
-  [(set_attr "length" "4,4,8,8,8")
+  "fsadd%?\\t%0,%1,%2"
+  [(set_attr "length" "4,4,4,8,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "fpu")
-   (set_attr "predicable" "yes,no,yes,no,no")
-   (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond")
+   (set_attr "predicable" "yes,no,no,yes,no,no")
+   (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond")
    ])
 
 ;; Subtraction
 (define_insn "*subsf3_fpu"
-  [(set (match_operand:SF 0 "register_operand"           "=r,r,r,r,r")
-	(minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r,0,r,F")
-		  (match_operand:SF 2 "nonmemory_operand" "r,r,F,F,r")))]
+  [(set (match_operand:SF 0 "register_operand"           "=r,r,  r,r,r,r")
+	(minus:SF (match_operand:SF 1 "nonmemory_operand" "0,r,  r,0,r,F")
+		  (match_operand:SF 2 "nonmemory_operand" "r,r,CfZ,F,F,r")))]
   "TARGET_FP_SP_BASE
    && (register_operand (operands[1], SFmode)
        || register_operand (operands[2], SFmode))"
-  "fssub%? %0,%1,%2"
-  [(set_attr "length" "4,4,8,8,8")
+  "fssub%?\\t%0,%1,%2"
+  [(set_attr "length" "4,4,4,8,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "fpu")
-   (set_attr "predicable" "yes,no,yes,no,no")
-   (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond")
+   (set_attr "predicable" "yes,no,no,yes,no,no")
+   (set_attr "cond" "canuse,nocond,nocond,canuse_limm,nocond,nocond")
    ])
 
 ;; Multiplication
@@ -44,7 +44,7 @@
   "TARGET_FP_SP_BASE
    && (register_operand (operands[1], SFmode)
        || register_operand (operands[2], SFmode))"
-  "fsmul%? %0,%1,%2"
+  "fsmul%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "fpu")
@@ -108,7 +108,7 @@
   "TARGET_FP_SP_FUSED
    && (register_operand (operands[1], SFmode)
        || register_operand (operands[2], SFmode))"
-  "fsmsub%? %0,%1,%2"
+  "fsmsub%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,8,8")
    (set_attr "predicable" "yes,no,yes,no,no")
    (set_attr "cond" "canuse,nocond,canuse_limm,nocond,nocond")
@@ -178,7 +178,7 @@
 		(match_operand:DF 2 "even_register_operand"  "r,r")
 		(reg:DF ARCV2_ACC)))]
   "TARGET_FP_DP_FUSED"
-  "fdmadd%? %0,%1,%2"
+  "fdmadd%?\\t%0,%1,%2"
   [(set_attr "length" "4,4")
    (set_attr "predicable" "yes,no")
    (set_attr "cond" "canuse,nocond")
@@ -191,7 +191,7 @@
 		(match_operand:DF 2 "even_register_operand"          "r,r")
 		(reg:DF ARCV2_ACC)))]
   "TARGET_FP_DP_FUSED"
-  "fdmsub%? %0,%1,%2"
+  "fdmsub%?\\t%0,%1,%2"
   [(set_attr "length" "4,4")
    (set_attr "predicable" "yes,no")
    (set_attr "cond" "canuse,nocond")
@@ -206,7 +206,7 @@
   "TARGET_FP_SP_SQRT
    && (register_operand (operands[1], SFmode)
        || register_operand (operands[2], SFmode))"
-  "fsdiv%? %0,%1,%2"
+  "fsdiv%?\\t%0,%1,%2"
   [(set_attr "length" "4,4,8,8,8")
    (set_attr "iscompact" "false")
    (set_attr "type" "fpu_sdiv")
@@ -225,31 +225,31 @@
   [(set (match_operand:SF 0 "register_operand"           "=r,r")
 	(sqrt:SF (match_operand:SF 1 "nonmemory_operand"  "r,F")))]
   "TARGET_FP_SP_SQRT"
-  "fssqrt %0,%1"
+  "fssqrt\\t%0,%1"
   [(set_attr "length" "4,8")
    (set_attr "type" "fpu_sdiv")])
 
 ;; Comparison
 (define_insn "*cmpsf_fpu"
   [(set (reg:CC_FPU CC_REG)
-	(compare:CC_FPU (match_operand:SF 0 "register_operand"  "r,r")
-			(match_operand:SF 1 "nonmemory_operand" "r,F")))]
+	(compare:CC_FPU (match_operand:SF 0 "register_operand"  "r,  r,r")
+			(match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))]
   "TARGET_FP_SP_BASE"
-  "fscmp%? %0, %1"
-  [(set_attr "length" "4,8")
+  "fscmp%?\\t%0,%1"
+  [(set_attr "length" "4,4,8")
    (set_attr "iscompact" "false")
    (set_attr "cond" "set")
    (set_attr "type" "fpu")
-   (set_attr "predicable" "yes,yes")])
+   (set_attr "predicable" "yes")])
 
 (define_insn "*cmpsf_fpu_uneq"
   [(set (reg:CC_FPU_UNEQ CC_REG)
 	(compare:CC_FPU_UNEQ
-	 (match_operand:SF 0 "register_operand"  "r,r")
-	 (match_operand:SF 1 "nonmemory_operand" "r,F")))]
+	 (match_operand:SF 0 "register_operand"  "r,  r,r")
+	 (match_operand:SF 1 "nonmemory_operand" "r,CfZ,F")))]
   "TARGET_FP_SP_BASE"
-  "fscmp %0, %1\\n\\tmov.v.f 0,0\\t;set Z flag"
-  [(set_attr "length" "8,12")
+  "fscmp\\t%0,%1\\n\\tmov.v.f\\t0,0\\t;set Z flag"
+  [(set_attr "length" "8,8,12")
    (set_attr "iscompact" "false")
    (set_attr "cond" "set")
    (set_attr "type" "fpu")])
@@ -274,7 +274,6 @@
    (set_attr "cond" "canuse,nocond")
    ])
 
-
 ;; Subtraction
 (define_insn "*subdf3_fpu"
   [(set (match_operand:DF 0 "even_register_operand"           "=r,r")
-- 
2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/4] [ARX][FIX] Fix uncache attribute.
  2018-07-16 12:29 [PATCH 1/4] [ARC] Add more additional register names Claudiu Zissulescu
  2018-07-16 12:29 ` [PATCH 4/4] [ARC] Update default optimizations for size Claudiu Zissulescu
  2018-07-16 12:29 ` [PATCH 3/4] [ARC] Improve instruction selection for fp moves Claudiu Zissulescu
@ 2018-07-16 12:29 ` Claudiu Zissulescu
  2018-07-25 13:49 ` [PATCH 1/4] [ARC] Add more additional register names Andrew Burgess
  3 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2018-07-16 12:29 UTC (permalink / raw)
  To: gcc-patches; +Cc: fbedard, andrew.burgess

gcc/
2018-05-09  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/arc.c (compact_memory_operand_p): Check for uncached
	accesses as well.
	(arc_is_uncached_mem_p): uncached applies to both the variable and
	the pointer.

testsuite/
2018-05-09  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/uncached-1.c: New test.
	* gcc.target/arc/uncached-2.c: Likewise.
---
 gcc/config/arc/arc.c                      | 40 +++++++++++++++--------
 gcc/testsuite/gcc.target/arc/uncached-1.c | 11 +++++++
 gcc/testsuite/gcc.target/arc/uncached-2.c |  9 +++++
 3 files changed, 46 insertions(+), 14 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/arc/uncached-1.c
 create mode 100644 gcc/testsuite/gcc.target/arc/uncached-2.c

diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index f36f88f920b..bf719eab115 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10450,6 +10450,10 @@ compact_memory_operand_p (rtx op, machine_mode mode,
   if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET)
     return false;
 
+  /* likewise for uncached types.  */
+  if (arc_is_uncached_mem_p (op))
+    return false;
+
   if (mode == VOIDmode)
     mode = GET_MODE (op);
 
@@ -10733,28 +10737,36 @@ arc_handle_uncached_attribute (tree *node,
 bool
 arc_is_uncached_mem_p (rtx pat)
 {
-  tree attrs;
-  tree ttype;
-  struct mem_attrs *refattrs;
+  tree attrs = NULL_TREE;
+  tree addr;
 
   if (!MEM_P (pat))
     return false;
 
   /* Get the memory attributes.  */
-  refattrs = MEM_ATTRS (pat);
-  if (!refattrs
-      || !refattrs->expr)
+  addr = MEM_EXPR (pat);
+  if (!addr)
     return false;
 
-  /* Get the type declaration.  */
-  ttype = TREE_TYPE (refattrs->expr);
-  if (!ttype)
-    return false;
+  /* Get the attributes.  */
+  if (TREE_CODE (addr) == MEM_REF)
+    {
+      attrs = TYPE_ATTRIBUTES (TREE_TYPE (addr));
+      if (lookup_attribute ("uncached", attrs))
+	return true;
 
-  /* Get the type attributes.  */
-  attrs = TYPE_ATTRIBUTES (ttype);
-  if (lookup_attribute ("uncached", attrs))
-    return true;
+      attrs = TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr, 0)));
+      if (lookup_attribute ("uncached", attrs))
+	return true;
+    }
+
+  /* For COMPONENT_REF, use the FIELD_DECL from tree operand 1.  */
+  if (TREE_CODE (addr) == COMPONENT_REF)
+    {
+      attrs = TYPE_ATTRIBUTES (TREE_TYPE (TREE_OPERAND (addr, 1)));
+      if (lookup_attribute ("uncached", attrs))
+	return true;
+    }
   return false;
 }
 
diff --git a/gcc/testsuite/gcc.target/arc/uncached-1.c b/gcc/testsuite/gcc.target/arc/uncached-1.c
new file mode 100644
index 00000000000..7a6bade81c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/uncached-1.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+
+volatile __attribute__((uncached))  int * status =
+  (volatile __attribute__((uncached)) int *) 0x04 ;
+
+int get_stat (void)
+{
+  return *status;
+}
+
+/* { dg-final { scan-assembler-times "ld\.di" 1 } } */
diff --git a/gcc/testsuite/gcc.target/arc/uncached-2.c b/gcc/testsuite/gcc.target/arc/uncached-2.c
new file mode 100644
index 00000000000..89eed326e01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arc/uncached-2.c
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+
+void clkgen_switch(unsigned int base, unsigned int offset, int val)
+{
+  volatile  unsigned int __attribute__ ((uncached)) *dest =
+    (volatile unsigned int __attribute__ ((uncached)) *) (base + offset);
+  *dest = val;
+}
+/* { dg-final { scan-assembler-times "st\.di" 1 } } */
-- 
2.17.1

^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/4] [ARC] Add more additional register names
  2018-07-16 12:29 [PATCH 1/4] [ARC] Add more additional register names Claudiu Zissulescu
                   ` (2 preceding siblings ...)
  2018-07-16 12:29 ` [PATCH 2/4] [ARX][FIX] Fix uncache attribute Claudiu Zissulescu
@ 2018-07-25 13:49 ` Andrew Burgess
  2018-07-25 15:10   ` Claudiu Zissulescu
  3 siblings, 1 reply; 6+ messages in thread
From: Andrew Burgess @ 2018-07-25 13:49 UTC (permalink / raw)
  To: Claudiu Zissulescu; +Cc: gcc-patches, fbedard, claziss

All the patches in this series look fine.

Thanks,
Andrew


* Claudiu Zissulescu <claziss@gmail.com> [2018-07-16 15:29:42 +0300]:

> From: claziss <claziss@synopsys.com>
> 
> gcc/
> 2017-06-14  Claudiu Zissulescu  <claziss@synopsys.com>
> 
> 	* config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add additional
> 	register names.
> ---
>  gcc/config/arc/arc.h | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index 1780034aabe..3648314eaca 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -1215,7 +1215,15 @@ extern char rname56[], rname57[], rname58[], rname59[];
>  {						\
>    {"ilink",  29},				\
>    {"r29",    29},				\
> -  {"r30",    30}				\
> +  {"r30",    30},				\
> +  {"r40",    40},				\
> +  {"r41",    41},				\
> +  {"r42",    42},				\
> +  {"r43",    43},				\
> +  {"r56",    56},				\
> +  {"r57",    57},				\
> +  {"r58",    58},				\
> +  {"r59",    59}				\
>  }
>  
>  /* Entry to the insn conditionalizer.  */
> -- 
> 2.17.1
> 

^ permalink raw reply	[flat|nested] 6+ messages in thread

* RE: [PATCH 1/4] [ARC] Add more additional register names
  2018-07-25 13:49 ` [PATCH 1/4] [ARC] Add more additional register names Andrew Burgess
@ 2018-07-25 15:10   ` Claudiu Zissulescu
  0 siblings, 0 replies; 6+ messages in thread
From: Claudiu Zissulescu @ 2018-07-25 15:10 UTC (permalink / raw)
  To: Andrew Burgess; +Cc: gcc-patches, Francois.Bedard

Pushed. Thank you for your review,
Claudiu
________________________________________
From: Andrew Burgess [andrew.burgess@embecosm.com]
Sent: Wednesday, July 25, 2018 3:49 PM
To: Claudiu Zissulescu
Cc: gcc-patches@gcc.gnu.org; Francois.Bedard@synopsys.com; claziss
Subject: Re: [PATCH 1/4] [ARC] Add more additional register names

All the patches in this series look fine.

Thanks,
Andrew


* Claudiu Zissulescu <claziss@gmail.com> [2018-07-16 15:29:42 +0300]:

> From: claziss <claziss@synopsys.com>
>
> gcc/
> 2017-06-14  Claudiu Zissulescu  <claziss@synopsys.com>
>
>       * config/arc/arc.h (ADDITIONAL_REGISTER_NAMES): Add additional
>       register names.
> ---
>  gcc/config/arc/arc.h | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index 1780034aabe..3648314eaca 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -1215,7 +1215,15 @@ extern char rname56[], rname57[], rname58[], rname59[];
>  {                                            \
>    {"ilink",  29},                            \
>    {"r29",    29},                            \
> -  {"r30",    30}                             \
> +  {"r30",    30},                            \
> +  {"r40",    40},                            \
> +  {"r41",    41},                            \
> +  {"r42",    42},                            \
> +  {"r43",    43},                            \
> +  {"r56",    56},                            \
> +  {"r57",    57},                            \
> +  {"r58",    58},                            \
> +  {"r59",    59}                             \
>  }
>
>  /* Entry to the insn conditionalizer.  */
> --
> 2.17.1
>

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2018-07-25 15:10 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-16 12:29 [PATCH 1/4] [ARC] Add more additional register names Claudiu Zissulescu
2018-07-16 12:29 ` [PATCH 4/4] [ARC] Update default optimizations for size Claudiu Zissulescu
2018-07-16 12:29 ` [PATCH 3/4] [ARC] Improve instruction selection for fp moves Claudiu Zissulescu
2018-07-16 12:29 ` [PATCH 2/4] [ARX][FIX] Fix uncache attribute Claudiu Zissulescu
2018-07-25 13:49 ` [PATCH 1/4] [ARC] Add more additional register names Andrew Burgess
2018-07-25 15:10   ` Claudiu Zissulescu

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