From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 130851 invoked by alias); 26 Jul 2018 09:14:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 130676 invoked by uid 89); 26 Jul 2018 09:14:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_HELO_PASS,SPF_PASS autolearn=ham version=3.3.2 spammy=Methods X-HELO: EUR03-DB5-obe.outbound.protection.outlook.com Received: from mail-eopbgr40046.outbound.protection.outlook.com (HELO EUR03-DB5-obe.outbound.protection.outlook.com) (40.107.4.46) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 26 Jul 2018 09:14:02 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector1-arm-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=mpCKpIl/jKV3zU8dQzrcYStwPucKDKX8Yv5y6mHDBsQ=; b=fJeWkEA2tFL1mygbtX19drC5ZlPeMh8Tf3Vvdwo2I3DD/xkFejSdzAMgvg5ICVqS7wyUhpv3rHccOqi9cxvkLP5HdeaU0kYShrlVu2mpHt+oDheUxz/M68g0IsfYoAAMSpXeWG/Rn62h/GNYAApMcNZXd308bMOHuAQ2OhpZs0E= Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; Received: from C02TF0U7HF1T.manchester.arm.com (217.140.106.32) by DB6PR0802MB2133.eurprd08.prod.outlook.com (2603:10a6:4:83::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.973.20; Thu, 26 Jul 2018 09:13:56 +0000 From: Alan Hayward To: gcc-patches@gcc.gnu.org Cc: nd@arm.com, Alan Hayward Subject: [PATCH v2 1/7] Add CLOBBER_HIGH expression Date: Thu, 26 Jul 2018 09:14:00 -0000 Message-Id: <20180726091329.26875-2-alan.hayward@arm.com> In-Reply-To: <20180726091329.26875-1-alan.hayward@arm.com> References: <20180726091329.26875-1-alan.hayward@arm.com> MIME-Version: 1.0 Content-Type: text/plain Return-Path: alan.hayward@arm.com Received-SPF: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-SW-Source: 2018-07/txt/msg01600.txt.bz2 Includes documentation. 2018-07-25 Alan Hayward * doc/rtl.texi (clobber_high): Add. (parallel): Add in clobber high * rtl.c (rtl_check_failed_code3): Add function. * rtl.def (CLOBBER_HIGH): Add expression. * rtl.h (RTL_CHECKC3): Add macro. (rtl_check_failed_code3): Add declaration. (XC3EXP): Add macro. --- gcc/doc/rtl.texi | 15 ++++++++++++++- gcc/rtl.c | 11 +++++++++++ gcc/rtl.def | 10 ++++++++++ gcc/rtl.h | 16 +++++++++++++++- 4 files changed, 50 insertions(+), 2 deletions(-) diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi index a37d9ac5389..20c57732679 100644 --- a/gcc/doc/rtl.texi +++ b/gcc/doc/rtl.texi @@ -3296,6 +3296,18 @@ There is one other known use for clobbering a pseudo register in a clobbered by the insn. In this case, using the same pseudo register in the clobber and elsewhere in the insn produces the expected results. +@findex clobber_high +@item (clobber_high @var{x}) +Represents the storing or possible storing of an unpredictable, +undescribed value into the upper parts of @var{x}. The mode of the expression +represents the lower parts of the register which will not be overwritten. +@code{reg} must be a reg expression. + +One place this is used is when calling into functions where the registers are +preserved, but only up to a given number of bits. For example when using +Aarch64 SVE, calling a TLS descriptor will cause only the lower 128 bits of +each of the vector registers to be preserved. + @findex use @item (use @var{x}) Represents the use of the value of @var{x}. It indicates that the @@ -3349,7 +3361,8 @@ Represents several side effects performed in parallel. The square brackets stand for a vector; the operand of @code{parallel} is a vector of expressions. @var{x0}, @var{x1} and so on are individual side effect expressions---expressions of code @code{set}, @code{call}, -@code{return}, @code{simple_return}, @code{clobber} or @code{use}. +@code{return}, @code{simple_return}, @code{clobber} @code{use} or +@code{clobber_high}. ``In parallel'' means that first all the values used in the individual side-effects are computed, and second all the actual side-effects are diff --git a/gcc/rtl.c b/gcc/rtl.c index 90bbc7c6861..985db1c14f0 100644 --- a/gcc/rtl.c +++ b/gcc/rtl.c @@ -856,6 +856,17 @@ rtl_check_failed_code2 (const_rtx r, enum rtx_code code1, enum rtx_code code2, func, trim_filename (file), line); } +void +rtl_check_failed_code3 (const_rtx r, enum rtx_code code1, enum rtx_code code2, + enum rtx_code code3, const char *file, int line, + const char *func) +{ + internal_error + ("RTL check: expected code '%s', '%s' or '%s', have '%s' in %s, at %s:%d", + GET_RTX_NAME (code1), GET_RTX_NAME (code2), GET_RTX_NAME (code3), + GET_RTX_NAME (GET_CODE (r)), func, trim_filename (file), line); +} + void rtl_check_failed_code_mode (const_rtx r, enum rtx_code code, machine_mode mode, bool not_mode, const char *file, int line, diff --git a/gcc/rtl.def b/gcc/rtl.def index 2578a0ccb9e..0ed27505545 100644 --- a/gcc/rtl.def +++ b/gcc/rtl.def @@ -312,6 +312,16 @@ DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) is considered undeletable before reload. */ DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) +/* Indicate that the upper parts of something are clobbered in a way that we + don't want to explain. The MODE references the lower bits that will be + preserved. Anything above that size will be clobbered. + + CLOBBER_HIGH only occurs as the operand of a PARALLEL rtx. It cannot appear + in other contexts, and unlike CLOBBER, it cannot appear on its own. + CLOBBER_HIGH can only be used with fixed register rtxes. */ + +DEF_RTL_EXPR(CLOBBER_HIGH, "clobber_high", "e", RTX_EXTRA) + /* Call a subroutine. Operand 1 is the address to call. Operand 2 is the number of arguments. */ diff --git a/gcc/rtl.h b/gcc/rtl.h index 565ce3abbe4..5e07e9bee80 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -1100,6 +1100,14 @@ is_a_helper ::test (rtx_insn *insn) __FUNCTION__); \ &_rtx->u.fld[_n]; })) +#define RTL_CHECKC3(RTX, N, C1, C2, C3) __extension__ \ +(*({ __typeof (RTX) const _rtx = (RTX); const int _n = (N); \ + const enum rtx_code _code = GET_CODE (_rtx); \ + if (_code != (C1) && _code != (C2) && _code != (C3)) \ + rtl_check_failed_code3 (_rtx, (C1), (C2), (C3), __FILE__, \ + __LINE__, __FUNCTION__); \ + &_rtx->u.fld[_n]; })) + #define RTVEC_ELT(RTVEC, I) __extension__ \ (*({ __typeof (RTVEC) const _rtvec = (RTVEC); const int _i = (I); \ if (_i < 0 || _i >= GET_NUM_ELEM (_rtvec)) \ @@ -1190,6 +1198,10 @@ extern void rtl_check_failed_code1 (const_rtx, enum rtx_code, const char *, extern void rtl_check_failed_code2 (const_rtx, enum rtx_code, enum rtx_code, const char *, int, const char *) ATTRIBUTE_NORETURN ATTRIBUTE_COLD; +extern void rtl_check_failed_code3 (const_rtx, enum rtx_code, enum rtx_code, + enum rtx_code, const char *, int, + const char *) + ATTRIBUTE_NORETURN ATTRIBUTE_COLD; extern void rtl_check_failed_code_mode (const_rtx, enum rtx_code, machine_mode, bool, const char *, int, const char *) ATTRIBUTE_NORETURN ATTRIBUTE_COLD; @@ -1208,6 +1220,7 @@ extern void rtvec_check_failed_bounds (const_rtvec, int, const char *, int, #define RTL_CHECK2(RTX, N, C1, C2) ((RTX)->u.fld[N]) #define RTL_CHECKC1(RTX, N, C) ((RTX)->u.fld[N]) #define RTL_CHECKC2(RTX, N, C1, C2) ((RTX)->u.fld[N]) +#define RTL_CHECKC3(RTX, N, C1, C2, C3) ((RTX)->u.fld[N]) #define RTVEC_ELT(RTVEC, I) ((RTVEC)->elem[I]) #define XWINT(RTX, N) ((RTX)->u.hwint[N]) #define CWI_ELT(RTX, I) ((RTX)->u.hwiv.elem[I]) @@ -1362,6 +1375,7 @@ extern void rtl_check_failed_flag (const char *, const_rtx, const char *, #define XCVECLEN(RTX, N, C) GET_NUM_ELEM (XCVEC (RTX, N, C)) #define XC2EXP(RTX, N, C1, C2) (RTL_CHECKC2 (RTX, N, C1, C2).rt_rtx) +#define XC3EXP(RTX, N, C1, C2, C3) (RTL_CHECKC3 (RTX, N, C1, C2, C3).rt_rtx) /* Methods of rtx_expr_list. */ @@ -2632,7 +2646,7 @@ do { \ /* For a SET rtx, SET_DEST is the place that is set and SET_SRC is the value it is set to. */ -#define SET_DEST(RTX) XC2EXP (RTX, 0, SET, CLOBBER) +#define SET_DEST(RTX) XC3EXP (RTX, 0, SET, CLOBBER, CLOBBER_HIGH) #define SET_SRC(RTX) XCEXP (RTX, 1, SET) #define SET_IS_RETURN_P(RTX) \ (RTL_FLAG_CHECK1 ("SET_IS_RETURN_P", (RTX), SET)->jump) -- 2.15.2 (Apple Git-101.1)