Re: [GCC][PATCH v2][Aarch64] Exploiting BFXIL when OR-ing two AND-operations with appropriate bitmasks

[James Greenhalgh <james.greenhalgh@arm.com>]

On Wed, Aug 01, 2018 at 10:07:23AM -0500, Sam Tebbs wrote:
> Hi all,
> 
> This patch adds an optimisation that exploits the AArch64 BFXIL
> instruction when or-ing the result of two bitwise and operations
> with non-overlapping bitmasks
> (e.g. (a & 0xFFFF0000) | (b & 0x0000FFFF)).
> 
> Example:
> 
> unsigned long long combine(unsigned long long a, unsigned long
> long b) {
>    return (a & 0xffffffff00000000ll) | (b & 0x00000000ffffffffll);
> }
> 
> void read(unsigned long long a, unsigned long long b, unsigned
> long long *c) {
>    *c = combine(a, b);
> }
> 
> When compiled with -O2, read would result in:
> 
> read:
>    and   x5, x1, #0xffffffff
>    and   x4, x0, #0xffffffff00000000
>    orr   x4, x4, x5
>    str   x4, [x2]
>    ret
> 
> But with this patch results in:
> 
> read:
>    mov    x4, x0
>    bfxil    x4, x1, 0, 32
>    str    x4, [x2]
>    ret
> 
> Bootstrapped and regtested on aarch64-none-linux-gnu and
> aarch64-none-elf with no regressions.
> 
> 
> gcc/
> 2018-08-01  Sam Tebbs<sam.tebbs@arm.com>
> 
>          PR target/85628
>          * config/aarch64/aarch64.md (*aarch64_bfxil):
>          Define.
>          * config/aarch64/constraints.md (Ulc): Define
>          * config/aarch64/aarch64-protos.h
>          (aarch64_is_left_consecutive): Define.

Hm, I'm not very sure about the naming here; "left consecutive" isn't a
common phrase to denote the mask you're looking for (exact_log2 (-i) != -1
if I'm reading right), and is misleading 0x0000ffff is 'left consecutive'
too, just with zeroes rather than ones.

>          * config/aarch64/aarch64.c (aarch64_is_left_consecutive):
>          New function.
> 
> gcc/testsuite
> 2018-08-01  Sam Tebbs<sam.tebbs@arm.com>
> 
>          PR target/85628
>          * gcc.target/aarch64/combine_bfxil.c: New file.
>          * gcc.target/aarch64/combine_bfxil_2.c: New file.
> 

> diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h
> index af5db9c595385f7586692258f750b6aceb3ed9c8..01d9e1bd634572fcfa60208ba4dc541805af5ccd 100644
> --- a/gcc/config/aarch64/aarch64-protos.h
> +++ b/gcc/config/aarch64/aarch64-protos.h
> @@ -574,4 +574,6 @@ rtl_opt_pass *make_pass_fma_steering (gcc::context *ctxt);
>  
>  poly_uint64 aarch64_regmode_natural_size (machine_mode);
>  
> +bool aarch64_is_left_consecutive (HOST_WIDE_INT);
> +
>  #endif /* GCC_AARCH64_PROTOS_H */
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index fa01475aa9ee579b6a3b2526295b622157120660..3cfa51b15af3e241672f1383cf881c12a44494a5 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -1454,6 +1454,14 @@ aarch64_hard_regno_caller_save_mode (unsigned regno, unsigned,
>      return SImode;
>  }
>  
> +/* Implement IS_LEFT_CONSECUTIVE.  Check if I's bits are consecutive

What is IS_LEFT_CONSECUTIVE - I don't see it elsewhere in the GCC code, so
what does the comment refer to implementing?

> +   ones from the MSB.  */
> +bool
> +aarch64_is_left_consecutive (HOST_WIDE_INT i)
> +{
> +  return (i | (i - 1)) == HOST_WIDE_INT_M1;

exact_log2(-i) != HOST_WIDE_INT_M1?

I don't have issues with the rest of the patch; but please try to find a more
descriptive name for this.

Thanks,
James