From: Richard Henderson <richard.henderson@linaro.org>
To: gcc-patches@gcc.gnu.org
Cc: ramana.radhakrishnan@arm.com, agraf@suse.de,
marcus.shawcroft@arm.com, james.greenhalgh@arm.com,
richard.earnshaw@arm.com
Subject: [PATCH, AArch64 v2 09/11] aarch64: Force TImode values into even registers
Date: Tue, 02 Oct 2018 16:19:00 -0000 [thread overview]
Message-ID: <20181002161915.18843-10-richard.henderson@linaro.org> (raw)
In-Reply-To: <20181002161915.18843-1-richard.henderson@linaro.org>
The LSE CASP instruction requires values to be placed in even
register pairs. A solution involving two additional register
classes was rejected in favor of the much simpler solution of
simply requiring all TImode values to be aligned.
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Force
16-byte modes held in GP registers to use an even regno.
---
gcc/config/aarch64/aarch64.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 49b47382b5d..ce4d7e51d00 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1451,10 +1451,14 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM)
return mode == Pmode;
- if (GP_REGNUM_P (regno) && known_le (GET_MODE_SIZE (mode), 16))
- return true;
-
- if (FP_REGNUM_P (regno))
+ if (GP_REGNUM_P (regno))
+ {
+ if (known_le (GET_MODE_SIZE (mode), 8))
+ return true;
+ else if (known_le (GET_MODE_SIZE (mode), 16))
+ return (regno & 1) == 0;
+ }
+ else if (FP_REGNUM_P (regno))
{
if (vec_flags & VEC_STRUCT)
return end_hard_regno (mode, regno) - 1 <= V31_REGNUM;
--
2.17.1
next prev parent reply other threads:[~2018-10-02 16:19 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-02 16:19 [PATCH, AArch64 v2 00/11] LSE atomics out-of-line Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 02/11] aarch64: Improve cas generation Richard Henderson
2018-10-30 20:37 ` James Greenhalgh
2018-10-02 16:19 ` [PATCH, AArch64 v2 07/11] aarch64: Add out-of-line functions for LSE atomics Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 11/11] Enable -matomic-ool by default Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 06/11] Add visibility to libfunc constructors Richard Henderson
2018-10-30 21:46 ` James Greenhalgh
2018-10-31 11:29 ` Richard Henderson
2018-10-31 17:46 ` Eric Botcazou
2018-10-31 19:04 ` Richard Henderson
2018-10-31 19:43 ` Eric Botcazou
2018-10-02 16:19 ` [PATCH, AArch64 v2 03/11] aarch64: Improve swp generation Richard Henderson
2018-10-30 20:50 ` James Greenhalgh
2018-10-02 16:19 ` [PATCH, AArch64 v2 08/11] aarch64: Implement -matomic-ool Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 01/11] aarch64: Simplify LSE cas generation Richard Henderson
2018-10-30 20:32 ` James Greenhalgh
2018-10-31 10:35 ` Richard Henderson
2018-10-02 16:19 ` [PATCH, AArch64 v2 04/11] aarch64: Improve atomic-op lse generation Richard Henderson
2018-10-30 21:40 ` James Greenhalgh
2018-10-02 16:19 ` Richard Henderson [this message]
2018-10-30 21:47 ` [PATCH, AArch64 v2 09/11] aarch64: Force TImode values into even registers James Greenhalgh
2018-10-02 16:36 ` [PATCH, AArch64 v2 10/11] aarch64: Implement TImode compare-and-swap Richard Henderson
2018-10-02 16:37 ` [PATCH, AArch64 v2 05/11] aarch64: Emit LSE st<op> instructions Richard Henderson
2018-10-30 21:42 ` James Greenhalgh
2018-10-31 11:13 ` Richard Henderson
2018-10-31 11:25 ` Richard Henderson
2018-10-31 15:49 ` Will Deacon
2018-10-31 17:35 ` Richard Henderson
2018-10-31 19:42 ` Will Deacon
2018-10-31 22:39 ` Richard Henderson
2018-10-11 17:44 ` [PATCH, AArch64 v2 00/11] LSE atomics out-of-line Richard Henderson
2018-10-22 14:01 ` Richard Henderson
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