* [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add
@ 2018-10-22 1:07 H.J. Lu
2018-10-22 1:08 ` [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot H.J. Lu
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: H.J. Lu @ 2018-10-22 1:07 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT add operations.
gcc/
PR target/72782
* config/i386/sse.md (avx512bcst): Updated for V4SI, V2DI, V8SI,
V4DI, V16SI and V8DI.
(*minus<mode>3<mask_name>_bcst): New.
(*plus<mode>3<mask_name>_bcst): Likewise.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-add-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-add-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-add-si-zmm-6.c: Likewise.
* gcc.target/i386/avx512f-sub-di-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-sub-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-add-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-add-si-ymm-1.c: Likewise.
* gcc.target/i386/avx512vl-sub-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-sub-si-ymm-1.c: Likewise.
---
gcc/config/i386/sse.md | 29 ++++++++++++++++++-
.../gcc.target/i386/avx512f-add-di-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-2.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-3.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-4.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-5.c | 12 ++++++++
.../gcc.target/i386/avx512f-add-si-zmm-6.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-di-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-2.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-3.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-4.c | 12 ++++++++
.../gcc.target/i386/avx512f-sub-si-zmm-5.c | 12 ++++++++
.../gcc.target/i386/avx512vl-add-si-xmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512vl-add-si-ymm-1.c | 12 ++++++++
.../gcc.target/i386/avx512vl-sub-si-xmm-1.c | 12 ++++++++
.../gcc.target/i386/avx512vl-sub-si-ymm-1.c | 12 ++++++++
18 files changed, 232 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 2c702ceed2d..2d4fac3f8f7 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -660,7 +660,10 @@
V16SF V8DF])
(define_mode_attr avx512bcst
- [(V4SF "%{1to4%}") (V2DF "%{1to2%}")
+ [(V4SI "%{1to4%}") (V2DI "%{1to2%}")
+ (V8SI "%{1to8%}") (V4DI "%{1to4%}")
+ (V16SI "%{1to16%}") (V8DI "%{1to8%}")
+ (V4SF "%{1to4%}") (V2DF "%{1to2%}")
(V8SF "%{1to8%}") (V4DF "%{1to4%}")
(V16SF "%{1to16%}") (V8DF "%{1to8%}")])
@@ -10408,6 +10411,30 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "<sseinsnmode>")])
+(define_insn "*sub<mode>3_bcst"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+ (minus:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 1 "register_operand" "v")
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+ "TARGET_AVX512F && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
+ "vpsub<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
+ [(set_attr "type" "sseiadd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
+(define_insn "*plus<mode>3_bcst"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+ (plus:VI48_AVX512VL
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
+ (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
+ "TARGET_AVX512F && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
+ "vpadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0|%0, %2, %1<avx512bcst>}"
+ [(set_attr "type" "sseiadd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "*<plusminus_insn><mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI48_AVX512VL
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
new file mode 100644
index 00000000000..eaf5093b9c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
new file mode 100644
index 00000000000..bdb5a1802cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
new file mode 100644
index 00000000000..de2148dbf53
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
new file mode 100644
index 00000000000..b581f8afefa
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpaddd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
new file mode 100644
index 00000000000..04f199fd1ab
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
new file mode 100644
index 00000000000..983d3906664
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
new file mode 100644
index 00000000000..54dba2b3f73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
new file mode 100644
index 00000000000..771f23df57a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
new file mode 100644
index 00000000000..3e4897c4a8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
new file mode 100644
index 00000000000..090f3ffbe62
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpsubd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
new file mode 100644
index 00000000000..1f75c88c3ec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpsubd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
new file mode 100644
index 00000000000..0617a7b151b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
new file mode 100644
index 00000000000..4e0c8451ac2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
new file mode 100644
index 00000000000..bf57563337e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128i
+#define vec
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
new file mode 100644
index 00000000000..54bdbebb20c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256i
+#define vec 256
+#define op add
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
new file mode 100644
index 00000000000..a29a2366a4f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128i
+#define vec
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
new file mode 100644
index 00000000000..3f248a3c08f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256i
+#define vec 256
+#define op sub
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
--
2.17.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot
2018-10-22 1:07 [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add H.J. Lu
@ 2018-10-22 1:08 ` H.J. Lu
2018-10-22 9:16 ` Uros Bizjak
2018-10-22 1:10 ` [PATCH 2/3] i386: Enable AVX512 memory broadcast for INT logic H.J. Lu
2018-10-22 8:40 ` [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add Uros Bizjak
2 siblings, 1 reply; 6+ messages in thread
From: H.J. Lu @ 2018-10-22 1:08 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT andnot operations.
gcc/
PR target/72782
* config/i386/sse.md (*andnot<mode>3_bst): New.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.
---
gcc/config/i386/sse.md | 13 +++++++++++++
.../gcc.target/i386/avx512f-andn-di-zmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-2.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-3.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-4.c | 12 ++++++++++++
.../gcc.target/i386/avx512f-andn-si-zmm-5.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-andn-si-xmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-andn-si-ymm-1.c | 12 ++++++++++++
9 files changed, 109 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 29f390ead1f..05bd5781804 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -12070,6 +12070,19 @@
]
(const_string "<sseinsnmode>")))])
+(define_insn "*andnot<mode>3_bst"
+ [(set (match_operand:VI 0 "register_operand" "=v")
+ (and:VI
+ (not:VI48_AVX512VL
+ (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
+ "TARGET_AVX512F"
+ "vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
+ [(set_attr "type" "sselog")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "*andnot<mode>3_mask"
[(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
(vec_merge:VI48_AVX512VL
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
new file mode 100644
index 00000000000..1450d3c1914
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
new file mode 100644
index 00000000000..c9d8a820295
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
new file mode 100644
index 00000000000..a9608ca095d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
new file mode 100644
index 00000000000..71751fc874c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
new file mode 100644
index 00000000000..d74c373d435
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
new file mode 100644
index 00000000000..8211815dbbb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op andnot
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
new file mode 100644
index 00000000000..0b084ae5f7b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m128i
+foo (__m128i x, int *f)
+{
+ return (__m128i) (~(__v4su) x & (__v4su) _mm_set1_epi32 (*f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
new file mode 100644
index 00000000000..cd27b40ba44
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m256i
+foo (__m256i x, int *f)
+{
+ return (__m256i) (~(__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
+}
--
2.17.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/3] i386: Enable AVX512 memory broadcast for INT logic
2018-10-22 1:07 [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add H.J. Lu
2018-10-22 1:08 ` [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot H.J. Lu
@ 2018-10-22 1:10 ` H.J. Lu
2018-10-22 9:02 ` Uros Bizjak
2018-10-22 8:40 ` [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add Uros Bizjak
2 siblings, 1 reply; 6+ messages in thread
From: H.J. Lu @ 2018-10-22 1:10 UTC (permalink / raw)
To: gcc-patches; +Cc: Uros Bizjak
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for INT logic operations.
gcc/
PR target/72782
* config/i386/sse.md (*<code><mode>3_bcst): New.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-and-di-zmm-1.c: New test.
* gcc.target/i386/avx512f-and-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-and-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-and-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-and-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-and-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-and-si-zmm-6.c: Likewise.
* gcc.target/i386/avx512f-or-di-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-or-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-or-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-or-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-or-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-or-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-or-si-zmm-6.c: Likewise.
* gcc.target/i386/avx512f-xor-di-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-xor-si-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-xor-si-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-xor-si-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-xor-si-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-xor-si-zmm-5.c: Likewise.
* gcc.target/i386/avx512f-xor-si-zmm-6.c: Likewise.
* gcc.target/i386/avx512vl-and-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-and-si-ymm-1.c: Likewise.
* gcc.target/i386/avx512vl-or-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-or-si-ymm-1.c: Likewise.
* gcc.target/i386/avx512vl-xor-si-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-xor-si-ymm-1.c: Likewise.
---
gcc/config/i386/sse.md | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-and-si-xmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-and-si-ymm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c | 12 ++++++++++++
gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-xor-si-xmm-1.c | 12 ++++++++++++
.../gcc.target/i386/avx512vl-xor-si-ymm-1.c | 12 ++++++++++++
28 files changed, 336 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 2d4fac3f8f7..29f390ead1f 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -12292,6 +12292,18 @@
]
(const_string "<sseinsnmode>")))])
+(define_insn "*<code><mode>3_bcst"
+ [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
+ (any_logic:VI48_AVX512VL
+ (vec_duplicate:VI48_AVX512VL
+ (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
+ (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
+ "TARGET_AVX512F && <mask_avx512vl_condition>"
+ "vp<logic><ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<avx512bcst>}"
+ [(set_attr "type" "sseiadd")
+ (set_attr "prefix" "evex")
+ (set_attr "mode" "<sseinsnmode>")])
+
(define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
[(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
(unspec:<avx512fmaskmode>
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c
new file mode 100644
index 00000000000..e919b26c70b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c
new file mode 100644
index 00000000000..0e7d8544477
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c
new file mode 100644
index 00000000000..19596f65f77
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c
new file mode 100644
index 00000000000..a3de58a23d6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c
new file mode 100644
index 00000000000..ce50edd375f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c
new file mode 100644
index 00000000000..d3fc8bac169
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c
new file mode 100644
index 00000000000..dfc3f91bf47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op and
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c
new file mode 100644
index 00000000000..7bbd971c0e8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vporq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c
new file mode 100644
index 00000000000..6e5583d0ae6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c
new file mode 100644
index 00000000000..c631b40f985
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c
new file mode 100644
index 00000000000..3d669e3c7c8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpord\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c
new file mode 100644
index 00000000000..78c11ae3a69
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c
new file mode 100644
index 00000000000..2002688e075
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c
new file mode 100644
index 00000000000..031e193eb9e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c
new file mode 100644
index 00000000000..6ea551fb603
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxorq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi64
+#define SCALAR long long
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c
new file mode 100644
index 00000000000..d0cb66c1179
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c
new file mode 100644
index 00000000000..5d241e43264
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-2.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c
new file mode 100644
index 00000000000..50289701bcc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpxord\[^\n\]*%zmm\[0-9\]+" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-3.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c
new file mode 100644
index 00000000000..55f0e1b7cfc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c
@@ -0,0 +1,12 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-4.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c
new file mode 100644
index 00000000000..efd62cbb8d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-5.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c
new file mode 100644
index 00000000000..cc7a44ba53d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512f -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
+
+#define type __m512i
+#define vec 512
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-6.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c
new file mode 100644
index 00000000000..da295152fa6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m128i
+foo (__m128i x, int *f)
+{
+ return (__m128i) ((__v4su) x & (__v4su) _mm_set1_epi32 (*f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c
new file mode 100644
index 00000000000..f2ba6c6eb86
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#include <immintrin.h>
+
+__m256i
+foo (__m256i x, int *f)
+{
+ return (__m256i) ((__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c
new file mode 100644
index 00000000000..66ab5504ce7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128i
+#define vec
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c
new file mode 100644
index 00000000000..3a87c34439f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256i
+#define vec 256
+#define op or
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c
new file mode 100644
index 00000000000..8197568ccf7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
+
+#define type __m128i
+#define vec
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c
new file mode 100644
index 00000000000..06933fe60c4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -O2" } */
+/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
+/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
+
+#define type __m256i
+#define vec 256
+#define op xor
+#define suffix epi32
+#define SCALAR int
+
+#include "avx512-binop-1.h"
--
2.17.2
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add
2018-10-22 1:07 [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add H.J. Lu
2018-10-22 1:08 ` [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot H.J. Lu
2018-10-22 1:10 ` [PATCH 2/3] i386: Enable AVX512 memory broadcast for INT logic H.J. Lu
@ 2018-10-22 8:40 ` Uros Bizjak
2 siblings, 0 replies; 6+ messages in thread
From: Uros Bizjak @ 2018-10-22 8:40 UTC (permalink / raw)
To: H. J. Lu; +Cc: gcc-patches
On Mon, Oct 22, 2018 at 12:59 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> Many AVX512 vector operations can broadcast from a scalar memory source.
> This patch enables memory broadcast for INT add operations.
>
> gcc/
>
> PR target/72782
> * config/i386/sse.md (avx512bcst): Updated for V4SI, V2DI, V8SI,
> V4DI, V16SI and V8DI.
> (*minus<mode>3<mask_name>_bcst): New.
> (*plus<mode>3<mask_name>_bcst): Likewise.
These patterns are named *add... and *sub.
> gcc/testsuite/
>
> PR target/72782
> * gcc.target/i386/avx512f-add-di-zmm-1.c: New test.
> * gcc.target/i386/avx512f-add-si-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-add-si-zmm-2.c: Likewise.
> * gcc.target/i386/avx512f-add-si-zmm-3.c: Likewise.
> * gcc.target/i386/avx512f-add-si-zmm-4.c: Likewise.
> * gcc.target/i386/avx512f-add-si-zmm-5.c: Likewise.
> * gcc.target/i386/avx512f-add-si-zmm-6.c: Likewise.
> * gcc.target/i386/avx512f-sub-di-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-sub-si-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-sub-si-zmm-2.c: Likewise.
> * gcc.target/i386/avx512f-sub-si-zmm-3.c: Likewise.
> * gcc.target/i386/avx512f-sub-si-zmm-4.c: Likewise.
> * gcc.target/i386/avx512f-sub-si-zmm-5.c: Likewise.
> * gcc.target/i386/avx512vl-add-si-xmm-1.c: Likewise.
> * gcc.target/i386/avx512vl-add-si-ymm-1.c: Likewise.
> * gcc.target/i386/avx512vl-sub-si-xmm-1.c: Likewise.
> * gcc.target/i386/avx512vl-sub-si-ymm-1.c: Likewise.
OK with an updated pattern name and ChangeLog.
Thanks,
Uros,
> ---
> gcc/config/i386/sse.md | 29 ++++++++++++++++++-
> .../gcc.target/i386/avx512f-add-di-zmm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512f-add-si-zmm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512f-add-si-zmm-2.c | 12 ++++++++
> .../gcc.target/i386/avx512f-add-si-zmm-3.c | 12 ++++++++
> .../gcc.target/i386/avx512f-add-si-zmm-4.c | 12 ++++++++
> .../gcc.target/i386/avx512f-add-si-zmm-5.c | 12 ++++++++
> .../gcc.target/i386/avx512f-add-si-zmm-6.c | 12 ++++++++
> .../gcc.target/i386/avx512f-sub-di-zmm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512f-sub-si-zmm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512f-sub-si-zmm-2.c | 12 ++++++++
> .../gcc.target/i386/avx512f-sub-si-zmm-3.c | 12 ++++++++
> .../gcc.target/i386/avx512f-sub-si-zmm-4.c | 12 ++++++++
> .../gcc.target/i386/avx512f-sub-si-zmm-5.c | 12 ++++++++
> .../gcc.target/i386/avx512vl-add-si-xmm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512vl-add-si-ymm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512vl-sub-si-xmm-1.c | 12 ++++++++
> .../gcc.target/i386/avx512vl-sub-si-ymm-1.c | 12 ++++++++
> 18 files changed, 232 insertions(+), 1 deletion(-)
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 2c702ceed2d..2d4fac3f8f7 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -660,7 +660,10 @@
> V16SF V8DF])
>
> (define_mode_attr avx512bcst
> - [(V4SF "%{1to4%}") (V2DF "%{1to2%}")
> + [(V4SI "%{1to4%}") (V2DI "%{1to2%}")
> + (V8SI "%{1to8%}") (V4DI "%{1to4%}")
> + (V16SI "%{1to16%}") (V8DI "%{1to8%}")
> + (V4SF "%{1to4%}") (V2DF "%{1to2%}")
> (V8SF "%{1to8%}") (V4DF "%{1to4%}")
> (V16SF "%{1to16%}") (V8DF "%{1to8%}")])
>
> @@ -10408,6 +10411,30 @@
> (set_attr "prefix" "orig,vex")
> (set_attr "mode" "<sseinsnmode>")])
>
> +(define_insn "*sub<mode>3_bcst"
> + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
> + (minus:VI48_AVX512VL
> + (match_operand:VI48_AVX512VL 1 "register_operand" "v")
> + (vec_duplicate:VI48_AVX512VL
> + (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
> + "TARGET_AVX512F && ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
> + "vpsub<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
> + [(set_attr "type" "sseiadd")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> +(define_insn "*plus<mode>3_bcst"
"*add<mode>3_bcst"
> + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
> + (plus:VI48_AVX512VL
> + (vec_duplicate:VI48_AVX512VL
> + (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
> + (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
> + "TARGET_AVX512F && ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
> + "vpadd<ssemodesuffix>\t{%1<avx512bcst>, %2, %0|%0, %2, %1<avx512bcst>}"
> + [(set_attr "type" "sseiadd")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> (define_insn "*<plusminus_insn><mode>3_mask"
> [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
> (vec_merge:VI48_AVX512VL
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
> new file mode 100644
> index 00000000000..eaf5093b9c4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-di-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi64
> +#define SCALAR long long
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
> new file mode 100644
> index 00000000000..bdb5a1802cc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
> new file mode 100644
> index 00000000000..de2148dbf53
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-2.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
> new file mode 100644
> index 00000000000..b581f8afefa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpaddd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-3.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
> new file mode 100644
> index 00000000000..04f199fd1ab
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-4.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-4.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
> new file mode 100644
> index 00000000000..983d3906664
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-5.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-5.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
> new file mode 100644
> index 00000000000..54dba2b3f73
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-add-si-zmm-6.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-6.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
> new file mode 100644
> index 00000000000..771f23df57a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-di-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpsubq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op sub
> +#define suffix epi64
> +#define SCALAR long long
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
> new file mode 100644
> index 00000000000..3e4897c4a8a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
> new file mode 100644
> index 00000000000..090f3ffbe62
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpsubd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-2.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
> new file mode 100644
> index 00000000000..1f75c88c3ec
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpsubd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-3.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
> new file mode 100644
> index 00000000000..0617a7b151b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-4.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-4.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
> new file mode 100644
> index 00000000000..4e0c8451ac2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-sub-si-zmm-5.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-5.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
> new file mode 100644
> index 00000000000..bf57563337e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-xmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
> +
> +#define type __m128i
> +#define vec
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
> new file mode 100644
> index 00000000000..54bdbebb20c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-add-si-ymm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpaddd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
> +
> +#define type __m256i
> +#define vec 256
> +#define op add
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
> new file mode 100644
> index 00000000000..a29a2366a4f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-xmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
> +
> +#define type __m128i
> +#define vec
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
> new file mode 100644
> index 00000000000..3f248a3c08f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-sub-si-ymm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpsubd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
> +
> +#define type __m256i
> +#define vec 256
> +#define op sub
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> --
> 2.17.2
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/3] i386: Enable AVX512 memory broadcast for INT logic
2018-10-22 1:10 ` [PATCH 2/3] i386: Enable AVX512 memory broadcast for INT logic H.J. Lu
@ 2018-10-22 9:02 ` Uros Bizjak
0 siblings, 0 replies; 6+ messages in thread
From: Uros Bizjak @ 2018-10-22 9:02 UTC (permalink / raw)
To: H. J. Lu; +Cc: gcc-patches
On Mon, Oct 22, 2018 at 12:59 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> Many AVX512 vector operations can broadcast from a scalar memory source.
> This patch enables memory broadcast for INT logic operations.
>
> gcc/
>
> PR target/72782
> * config/i386/sse.md (*<code><mode>3_bcst): New.
>
> gcc/testsuite/
>
> PR target/72782
> * gcc.target/i386/avx512f-and-di-zmm-1.c: New test.
> * gcc.target/i386/avx512f-and-si-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-and-si-zmm-2.c: Likewise.
> * gcc.target/i386/avx512f-and-si-zmm-3.c: Likewise.
> * gcc.target/i386/avx512f-and-si-zmm-4.c: Likewise.
> * gcc.target/i386/avx512f-and-si-zmm-5.c: Likewise.
> * gcc.target/i386/avx512f-and-si-zmm-6.c: Likewise.
> * gcc.target/i386/avx512f-or-di-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-or-si-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-or-si-zmm-2.c: Likewise.
> * gcc.target/i386/avx512f-or-si-zmm-3.c: Likewise.
> * gcc.target/i386/avx512f-or-si-zmm-4.c: Likewise.
> * gcc.target/i386/avx512f-or-si-zmm-5.c: Likewise.
> * gcc.target/i386/avx512f-or-si-zmm-6.c: Likewise.
> * gcc.target/i386/avx512f-xor-di-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-xor-si-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-xor-si-zmm-2.c: Likewise.
> * gcc.target/i386/avx512f-xor-si-zmm-3.c: Likewise.
> * gcc.target/i386/avx512f-xor-si-zmm-4.c: Likewise.
> * gcc.target/i386/avx512f-xor-si-zmm-5.c: Likewise.
> * gcc.target/i386/avx512f-xor-si-zmm-6.c: Likewise.
> * gcc.target/i386/avx512vl-and-si-xmm-1.c: Likewise.
> * gcc.target/i386/avx512vl-and-si-ymm-1.c: Likewise.
> * gcc.target/i386/avx512vl-or-si-xmm-1.c: Likewise.
> * gcc.target/i386/avx512vl-or-si-ymm-1.c: Likewise.
> * gcc.target/i386/avx512vl-xor-si-xmm-1.c: Likewise.
> * gcc.target/i386/avx512vl-xor-si-ymm-1.c: Likewise.
OK.
Thanks,
Uros.
> ---
> gcc/config/i386/sse.md | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c | 12 ++++++++++++
> .../gcc.target/i386/avx512vl-and-si-xmm-1.c | 12 ++++++++++++
> .../gcc.target/i386/avx512vl-and-si-ymm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c | 12 ++++++++++++
> gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c | 12 ++++++++++++
> .../gcc.target/i386/avx512vl-xor-si-xmm-1.c | 12 ++++++++++++
> .../gcc.target/i386/avx512vl-xor-si-ymm-1.c | 12 ++++++++++++
> 28 files changed, 336 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 2d4fac3f8f7..29f390ead1f 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -12292,6 +12292,18 @@
> ]
> (const_string "<sseinsnmode>")))])
>
> +(define_insn "*<code><mode>3_bcst"
> + [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
> + (any_logic:VI48_AVX512VL
> + (vec_duplicate:VI48_AVX512VL
> + (match_operand:<ssescalarmode> 1 "memory_operand" "m"))
> + (match_operand:VI48_AVX512VL 2 "register_operand" "v")))]
> + "TARGET_AVX512F && <mask_avx512vl_condition>"
> + "vp<logic><ssemodesuffix>\t{%1<avx512bcst>, %2, %0<mask_operand3>|%0<mask_operand3>, %2, %1<avx512bcst>}"
> + [(set_attr "type" "sseiadd")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> (define_insn "<avx512>_testm<mode>3<mask_scalar_merge_name>"
> [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=Yk")
> (unspec:<avx512fmaskmode>
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c
> new file mode 100644
> index 00000000000..e919b26c70b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-di-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi64
> +#define SCALAR long long
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c
> new file mode 100644
> index 00000000000..0e7d8544477
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c
> new file mode 100644
> index 00000000000..19596f65f77
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-2.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c
> new file mode 100644
> index 00000000000..a3de58a23d6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpandd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-3.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c
> new file mode 100644
> index 00000000000..ce50edd375f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-4.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-4.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c
> new file mode 100644
> index 00000000000..d3fc8bac169
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-5.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-5.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c
> new file mode 100644
> index 00000000000..dfc3f91bf47
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-and-si-zmm-6.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op and
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-6.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c
> new file mode 100644
> index 00000000000..7bbd971c0e8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-di-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vporq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi64
> +#define SCALAR long long
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c
> new file mode 100644
> index 00000000000..6e5583d0ae6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c
> new file mode 100644
> index 00000000000..c631b40f985
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-2.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c
> new file mode 100644
> index 00000000000..3d669e3c7c8
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpord\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-3.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c
> new file mode 100644
> index 00000000000..78c11ae3a69
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-4.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-4.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c
> new file mode 100644
> index 00000000000..2002688e075
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-5.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-5.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c
> new file mode 100644
> index 00000000000..031e193eb9e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-or-si-zmm-6.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-6.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c
> new file mode 100644
> index 00000000000..6ea551fb603
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-di-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpxorq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi64
> +#define SCALAR long long
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c
> new file mode 100644
> index 00000000000..d0cb66c1179
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c
> new file mode 100644
> index 00000000000..5d241e43264
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-2.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c
> new file mode 100644
> index 00000000000..50289701bcc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpxord\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-3.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c
> new file mode 100644
> index 00000000000..55f0e1b7cfc
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-4.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-4.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c
> new file mode 100644
> index 00000000000..efd62cbb8d2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-5.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-5.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c
> new file mode 100644
> index 00000000000..cc7a44ba53d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-xor-si-zmm-6.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-6.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c
> new file mode 100644
> index 00000000000..da295152fa6
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-xmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
> +
> +#include <immintrin.h>
> +
> +__m128i
> +foo (__m128i x, int *f)
> +{
> + return (__m128i) ((__v4su) x & (__v4su) _mm_set1_epi32 (*f));
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c
> new file mode 100644
> index 00000000000..f2ba6c6eb86
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-and-si-ymm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpandd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
> +
> +#include <immintrin.h>
> +
> +__m256i
> +foo (__m256i x, int *f)
> +{
> + return (__m256i) ((__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c
> new file mode 100644
> index 00000000000..66ab5504ce7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-xmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
> +
> +#define type __m128i
> +#define vec
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c
> new file mode 100644
> index 00000000000..3a87c34439f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-or-si-ymm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
> +
> +#define type __m256i
> +#define vec 256
> +#define op or
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c
> new file mode 100644
> index 00000000000..8197568ccf7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-xmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
> +
> +#define type __m128i
> +#define vec
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c
> new file mode 100644
> index 00000000000..06933fe60c4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-xor-si-ymm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpxord\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
> +
> +#define type __m256i
> +#define vec 256
> +#define op xor
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> --
> 2.17.2
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot
2018-10-22 1:08 ` [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot H.J. Lu
@ 2018-10-22 9:16 ` Uros Bizjak
0 siblings, 0 replies; 6+ messages in thread
From: Uros Bizjak @ 2018-10-22 9:16 UTC (permalink / raw)
To: H. J. Lu; +Cc: gcc-patches
On Mon, Oct 22, 2018 at 12:59 AM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> Many AVX512 vector operations can broadcast from a scalar memory source.
> This patch enables memory broadcast for INT andnot operations.
>
> gcc/
>
> PR target/72782
> * config/i386/sse.md (*andnot<mode>3_bst): New.
This pattern should be named ..._bcst, to be consistent with others.
> gcc/testsuite/
>
> PR target/72782
> * gcc.target/i386/avx512f-andn-di-zmm-1.c: New test.
> * gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise.
> * gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise.
> * gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise.
> * gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise.
> * gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise.
> * gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise.
> * gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise.
OK with updated pattern name and ChangeLog.
Thanks,
Uros.
> gcc/config/i386/sse.md | 13 +++++++++++++
> .../gcc.target/i386/avx512f-andn-di-zmm-1.c | 12 ++++++++++++
> .../gcc.target/i386/avx512f-andn-si-zmm-1.c | 12 ++++++++++++
> .../gcc.target/i386/avx512f-andn-si-zmm-2.c | 12 ++++++++++++
> .../gcc.target/i386/avx512f-andn-si-zmm-3.c | 12 ++++++++++++
> .../gcc.target/i386/avx512f-andn-si-zmm-4.c | 12 ++++++++++++
> .../gcc.target/i386/avx512f-andn-si-zmm-5.c | 12 ++++++++++++
> .../gcc.target/i386/avx512vl-andn-si-xmm-1.c | 12 ++++++++++++
> .../gcc.target/i386/avx512vl-andn-si-ymm-1.c | 12 ++++++++++++
> 9 files changed, 109 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
> create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index 29f390ead1f..05bd5781804 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -12070,6 +12070,19 @@
> ]
> (const_string "<sseinsnmode>")))])
>
> +(define_insn "*andnot<mode>3_bst"
*andnot<mode>3_bcst
> + [(set (match_operand:VI 0 "register_operand" "=v")
> + (and:VI
> + (not:VI48_AVX512VL
> + (match_operand:VI48_AVX512VL 1 "register_operand" "v"))
> + (vec_duplicate:VI48_AVX512VL
> + (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))]
> + "TARGET_AVX512F"
> + "vpandn<ssemodesuffix>\t{%2<avx512bcst>, %1, %0|%0, %1, %2<avx512bcst>}"
> + [(set_attr "type" "sselog")
> + (set_attr "prefix" "evex")
> + (set_attr "mode" "<sseinsnmode>")])
> +
> (define_insn "*andnot<mode>3_mask"
> [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v")
> (vec_merge:VI48_AVX512VL
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
> new file mode 100644
> index 00000000000..1450d3c1914
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op andnot
> +#define suffix epi64
> +#define SCALAR long long
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
> new file mode 100644
> index 00000000000..c9d8a820295
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op andnot
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-1.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
> new file mode 100644
> index 00000000000..a9608ca095d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op andnot
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-2.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
> new file mode 100644
> index 00000000000..71751fc874c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op andnot
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-3.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
> new file mode 100644
> index 00000000000..d74c373d435
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile { target { ! ia32 } } } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */
> +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op andnot
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-4.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
> new file mode 100644
> index 00000000000..8211815dbbb
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512f -O2" } */
> +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */
> +
> +#define type __m512i
> +#define vec 512
> +#define op andnot
> +#define suffix epi32
> +#define SCALAR int
> +
> +#include "avx512-binop-5.h"
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
> new file mode 100644
> index 00000000000..0b084ae5f7b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */
> +
> +#include <immintrin.h>
> +
> +__m128i
> +foo (__m128i x, int *f)
> +{
> + return (__m128i) (~(__v4su) x & (__v4su) _mm_set1_epi32 (*f));
> +}
> diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
> new file mode 100644
> index 00000000000..cd27b40ba44
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512vl -O2" } */
> +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */
> +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */
> +
> +#include <immintrin.h>
> +
> +__m256i
> +foo (__m256i x, int *f)
> +{
> + return (__m256i) (~(__v8su) x & (__v8su) _mm256_set1_epi32 (*f));
> +}
> --
> 2.17.2
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-10-22 6:14 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-10-22 1:07 [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add H.J. Lu
2018-10-22 1:08 ` [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot H.J. Lu
2018-10-22 9:16 ` Uros Bizjak
2018-10-22 1:10 ` [PATCH 2/3] i386: Enable AVX512 memory broadcast for INT logic H.J. Lu
2018-10-22 9:02 ` Uros Bizjak
2018-10-22 8:40 ` [PATCH 1/3] i386: Enable AVX512 memory broadcast for INT add Uros Bizjak
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