From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 33776 invoked by alias); 21 Oct 2018 22:59:17 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 33649 invoked by uid 89); 21 Oct 2018 22:59:16 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-ot1-f68.google.com Received: from mail-ot1-f68.google.com (HELO mail-ot1-f68.google.com) (209.85.210.68) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sun, 21 Oct 2018 22:59:14 +0000 Received: by mail-ot1-f68.google.com with SMTP id o14so38222563oth.4 for ; Sun, 21 Oct 2018 15:59:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=YUDanS1rMA9zOkez7ycBV8NdUbIJTnAjl468eLPkiPY=; b=Oqg8WVWSLn0leEA2YBAiYMk6Njy06ehzACryix+KXqFjYkFjAzTsORSJBy0ETP2p5Z NzmQVXGLfM/jqndv5axsMmAFafZRLkNWKou2pRrmQuu2LnBmyiJoYXeI2t6OrcLbyQ/h /WCgDSWs576mlDOFNKYbWUo5bRu2sk2Bmr3mTUv4G7mff73zeIpIaat8oF0G+LFfinPn UYVDRqkGi8k/I6EaJZ/Iq6Wwae/+jWAbr5FHSS4MpwkMa+wRFfOZyeN+AxW1r43XSv8V bERQ9AOm8+jhkkGVhhwXNa1/qOu8KE8rFgMJtXDM2rxGr4np/PqlE4C+P26yDbfFDqgQ PG7A== Return-Path: Received: from gnu-efi-2.localdomain ([2607:fb90:207:864d:1479:47a0:5a5f:6eb4]) by smtp.gmail.com with ESMTPSA id o64-v6sm9261588oig.6.2018.10.21.15.59.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Sun, 21 Oct 2018 15:59:12 -0700 (PDT) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 3/3] i386: Enable AVX512 memory broadcast for INT andnot Date: Mon, 22 Oct 2018 01:08:00 -0000 Message-Id: <20181021225843.28835-3-hjl.tools@gmail.com> In-Reply-To: <20181021225843.28835-1-hjl.tools@gmail.com> References: <20181021225843.28835-1-hjl.tools@gmail.com> X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg01286.txt.bz2 Many AVX512 vector operations can broadcast from a scalar memory source. This patch enables memory broadcast for INT andnot operations. gcc/ PR target/72782 * config/i386/sse.md (*andnot3_bst): New. gcc/testsuite/ PR target/72782 * gcc.target/i386/avx512f-andn-di-zmm-1.c: New test. * gcc.target/i386/avx512f-andn-si-zmm-1.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-2.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-3.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-4.c: Likewise. * gcc.target/i386/avx512f-andn-si-zmm-5.c: Likewise. * gcc.target/i386/avx512vl-andn-si-xmm-1.c: Likewise. * gcc.target/i386/avx512vl-andn-si-ymm-1.c: Likewise. --- gcc/config/i386/sse.md | 13 +++++++++++++ .../gcc.target/i386/avx512f-andn-di-zmm-1.c | 12 ++++++++++++ .../gcc.target/i386/avx512f-andn-si-zmm-1.c | 12 ++++++++++++ .../gcc.target/i386/avx512f-andn-si-zmm-2.c | 12 ++++++++++++ .../gcc.target/i386/avx512f-andn-si-zmm-3.c | 12 ++++++++++++ .../gcc.target/i386/avx512f-andn-si-zmm-4.c | 12 ++++++++++++ .../gcc.target/i386/avx512f-andn-si-zmm-5.c | 12 ++++++++++++ .../gcc.target/i386/avx512vl-andn-si-xmm-1.c | 12 ++++++++++++ .../gcc.target/i386/avx512vl-andn-si-ymm-1.c | 12 ++++++++++++ 9 files changed, 109 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 29f390ead1f..05bd5781804 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -12070,6 +12070,19 @@ ] (const_string "")))]) +(define_insn "*andnot3_bst" + [(set (match_operand:VI 0 "register_operand" "=v") + (and:VI + (not:VI48_AVX512VL + (match_operand:VI48_AVX512VL 1 "register_operand" "v")) + (vec_duplicate:VI48_AVX512VL + (match_operand: 2 "memory_operand" "m"))))] + "TARGET_AVX512F" + "vpandn\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sselog") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "*andnot3_mask" [(set (match_operand:VI48_AVX512VL 0 "register_operand" "=v") (vec_merge:VI48_AVX512VL diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c new file mode 100644 index 00000000000..1450d3c1914 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-di-zmm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpandnq\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vpbroadcastq\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512i +#define vec 512 +#define op andnot +#define suffix epi64 +#define SCALAR long long + +#include "avx512-binop-1.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c new file mode 100644 index 00000000000..c9d8a820295 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512i +#define vec 512 +#define op andnot +#define suffix epi32 +#define SCALAR int + +#include "avx512-binop-1.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c new file mode 100644 index 00000000000..a9608ca095d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */ + +#define type __m512i +#define vec 512 +#define op andnot +#define suffix epi32 +#define SCALAR int + +#include "avx512-binop-2.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c new file mode 100644 index 00000000000..71751fc874c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-3.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vpandnd\[^\n\]*%zmm\[0-9\]+" 1 } } */ + +#define type __m512i +#define vec 512 +#define op andnot +#define suffix epi32 +#define SCALAR int + +#include "avx512-binop-3.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c new file mode 100644 index 00000000000..d74c373d435 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-4.c @@ -0,0 +1,12 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" 1 } } */ +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+%zmm\[0-9\]+, %zmm\[0-9\]+, %zmm0" 1 } } */ + +#define type __m512i +#define vec 512 +#define op andnot +#define suffix epi32 +#define SCALAR int + +#include "avx512-binop-4.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c new file mode 100644 index 00000000000..8211815dbbb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512f-andn-si-zmm-5.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512f -O2" } */ +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\[^\n\]*\\\{1to\[1-8\]+\\\}, %zmm\[0-9\]+, %zmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%zmm\[0-9\]+" } } */ + +#define type __m512i +#define vec 512 +#define op andnot +#define suffix epi32 +#define SCALAR int + +#include "avx512-binop-5.h" diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c new file mode 100644 index 00000000000..0b084ae5f7b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-xmm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %xmm\[0-9\]+, %xmm0" 1 } } */ +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%xmm\[0-9\]+" } } */ + +#include + +__m128i +foo (__m128i x, int *f) +{ + return (__m128i) (~(__v4su) x & (__v4su) _mm_set1_epi32 (*f)); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c new file mode 100644 index 00000000000..cd27b40ba44 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-andn-si-ymm-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vpandnd\[ \\t\]+\\(%(?:eax|rdi|edi)\\)\\\{1to\[1-8\]+\\\}, %ymm\[0-9\]+, %ymm0" 1 } } */ +/* { dg-final { scan-assembler-not "vpbroadcastd\[^\n\]*%ymm\[0-9\]+" } } */ + +#include + +__m256i +foo (__m256i x, int *f) +{ + return (__m256i) (~(__v8su) x & (__v8su) _mm256_set1_epi32 (*f)); +} -- 2.17.2