From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20692 invoked by alias); 22 Oct 2018 21:06:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 20680 invoked by uid 89); 22 Oct 2018 21:06:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.1 required=5.0 tests=AWL,BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy=ing, quality X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 22 Oct 2018 21:06:18 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id w9ML6EQs029702; Mon, 22 Oct 2018 16:06:14 -0500 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id w9ML6Cf4029699; Mon, 22 Oct 2018 16:06:12 -0500 Date: Mon, 22 Oct 2018 22:46:00 -0000 From: Segher Boessenkool To: Jeff Law Cc: gcc-patches@gcc.gnu.org, bergner@linux.ibm.com, Alan Modra Subject: Re: [PATCH] combine: Do not combine moves from hard registers Message-ID: <20181022210611.GA5205@gate.crashing.org> References: <68abf72a5400b96b9a100966331d3ad2056648e7.1540237620.git.segher@kernel.crashing.org> <59f7ad07-5230-3b65-ed02-7f9e806c383e@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <59f7ad07-5230-3b65-ed02-7f9e806c383e@redhat.com> User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2018-10/txt/msg01366.txt.bz2 Hi Jeff, On Mon, Oct 22, 2018 at 02:52:12PM -0600, Jeff Law wrote: > I know we've gone back and forth on this stuff through the years, > particularly for targets with likely-to-spilled classes that are used > for register passing/return values. Right, there already was code to not copy to a pseudo for such registers, and this patch extends it to all hard (but not fixed) registers. That reduces code quality quite a bit though, because the move itself can often be combine. For that, this now adds an extra copy to a fresh pseudo, and that fixes this. (cc:ing Alan who did the previous attempt I remember). > I'm certainly willing to go with this as general guidance. I wouldn't > be surprised if we find that things like CSE, fwprop and other passes > need twiddling over time to mimick what you're doing in combine. Yes that could well be. I think fwprop is fine, but there could well be other passes. The asm problem in PR87600 no longer triggers, but it could be those passes stay away from asm, or something like that. Segher