From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 87280 invoked by alias); 13 Nov 2018 10:00:52 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 87247 invoked by uid 89); 13 Nov 2018 10:00:50 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.5 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy=claziss@gmail.com, clazissgmailcom, RAW, H*RU:sk:k73-v6s X-HELO: mail-wm1-f66.google.com Received: from mail-wm1-f66.google.com (HELO mail-wm1-f66.google.com) (209.85.128.66) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Nov 2018 10:00:48 +0000 Received: by mail-wm1-f66.google.com with SMTP id u13-v6so10793245wmc.4 for ; Tue, 13 Nov 2018 02:00:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=QSpPeIm1Tl6dyUs4UOsvkmJczESYsLp0NEvq1PcYyxw=; b=KfVcOyVdMB4KCSxIAEPbapkYI7RyQ9kQZV4D4qG7A3tZ1+zitG8wfP+4qoLrcn3JBT XCTsmkB1MfAE4t/tnD/Kh/Xyfgb6SIDe8g8CGP0xXIY+trfeY/w8TbG2FOR0EAiitm4U 06QVum3azd6xZOxDuCY3aT6n+lvDSkW8vxqu0DsKyjDynTZ3UxOHTSXut0Pe4/YVrK4U 8oHm1fan9SvcArGosb6GUWh8dklOKV7gPKX+qeWDKwqL2YchQrkampwjZGMj4cjhchX5 hVP6mO+/f45WwPbbH/Y17UCeVYDN+xRamChLRJeK4P0ceC5hjqJ+xugJu7i32OOpxKqp i/jg== Return-Path: Received: from localhost (host81-148-252-35.range81-148.btcentralplus.com. [81.148.252.35]) by smtp.gmail.com with ESMTPSA id k73-v6sm13193721wmd.33.2018.11.13.02.00.44 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 13 Nov 2018 02:00:44 -0800 (PST) Date: Tue, 13 Nov 2018 10:00:00 -0000 From: Andrew Burgess To: claziss@gmail.com Cc: Bernhard Reutner-Fischer , gcc-patches@gcc.gnu.org, fbedard@synopsys.com, claziss@synopsys.com Subject: Re: [PATCH 4/6] [ARC] Add peephole rules to combine store/loads into double store/loads Message-ID: <20181113100043.GE16539@embecosm.com> References: <20181010080016.12317-1-claziss@gmail.com> <20181010080016.12317-5-claziss@gmail.com> <20181022174935.GD2929@embecosm.com> <9DA56353-A551-4ADF-94F0-6BEF9BBB0658@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Fortune: Acting is an art which consists of keeping the audience from coughing. X-Editor: GNU Emacs [ http://www.gnu.org/software/emacs ] User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-11/txt/msg01061.txt.bz2 * claziss@gmail.com [2018-10-31 10:33:33 +0200]: > Thank you for your review. Please find attached a new respin patch with > your feedback in. > > Please let me know if it is ok, > Claudiu > From 4ff7d8419783eceeffbaf27df017d0a93c3af942 Mon Sep 17 00:00:00 2001 > From: Claudiu Zissulescu > Date: Thu, 9 Aug 2018 14:29:05 +0300 > Subject: [PATCH] [ARC] Add peephole rules to combine store/loads into double > store/loads > > Simple peephole rules which combines multiple ld/st instructions into > 64-bit load/store instructions. It only works for architectures which > are having double load/store option on. > > gcc/ > Claudiu Zissulescu > > * config/arc/arc-protos.h (gen_operands_ldd_std): Add. > * config/arc/arc.c (operands_ok_ldd_std): New function. > (mem_ok_for_ldd_std): Likewise. > (gen_operands_ldd_std): Likewise. > * config/arc/arc.md: Add peephole2 rules for std/ldd. Looks good. Thanks, Andrew > --- > gcc/config/arc/arc-protos.h | 1 + > gcc/config/arc/arc.c | 161 ++++++++++++++++++++++++++++++++++++ > gcc/config/arc/arc.md | 69 ++++++++++++++++ > 3 files changed, 231 insertions(+) > > diff --git a/gcc/config/arc/arc-protos.h b/gcc/config/arc/arc-protos.h > index 24bea6e1efb..55f8ed4c643 100644 > --- a/gcc/config/arc/arc-protos.h > +++ b/gcc/config/arc/arc-protos.h > @@ -46,6 +46,7 @@ extern int arc_return_address_register (unsigned int); > extern unsigned int arc_compute_function_type (struct function *); > extern bool arc_is_uncached_mem_p (rtx); > extern bool arc_lra_p (void); > +extern bool gen_operands_ldd_std (rtx *operands, bool load, bool commute); > #endif /* RTX_CODE */ > > extern unsigned int arc_compute_frame_size (int); > diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c > index 18dd0de6af7..daf785dbdb8 100644 > --- a/gcc/config/arc/arc.c > +++ b/gcc/config/arc/arc.c > @@ -10803,6 +10803,167 @@ arc_cannot_substitute_mem_equiv_p (rtx) > return true; > } > > +/* Checks whether the operands are valid for use in an LDD/STD > + instruction. Assumes that RT, and RT2 are REG. This is guaranteed > + by the patterns. Assumes that the address in the base register RN > + is word aligned. Pattern guarantees that both memory accesses use > + the same base register, the offsets are constants within the range, > + and the gap between the offsets is 4. If reload complete then > + check that registers are legal. */ > + > +static bool > +operands_ok_ldd_std (rtx rt, rtx rt2, HOST_WIDE_INT offset) > +{ > + unsigned int t, t2; > + > + if (!reload_completed) > + return true; > + > + if (!(SMALL_INT_RANGE (offset, (GET_MODE_SIZE (DImode) - 1) & (~0x03), > + (offset & (GET_MODE_SIZE (DImode) - 1) & 3 > + ? 0 : -(-GET_MODE_SIZE (DImode) | (~0x03)) >> 1)))) > + return false; > + > + t = REGNO (rt); > + t2 = REGNO (rt2); > + > + if ((t2 == PROGRAM_COUNTER_REGNO) > + || (t % 2 != 0) /* First destination register is not even. */ > + || (t2 != t + 1)) > + return false; > + > + return true; > +} > + > +/* Helper for gen_operands_ldd_std. Returns true iff the memory > + operand MEM's address contains an immediate offset from the base > + register and has no side effects, in which case it sets BASE and > + OFFSET accordingly. */ > + > +static bool > +mem_ok_for_ldd_std (rtx mem, rtx *base, rtx *offset) > +{ > + rtx addr; > + > + gcc_assert (base != NULL && offset != NULL); > + > + /* TODO: Handle more general memory operand patterns, such as > + PRE_DEC and PRE_INC. */ > + > + if (side_effects_p (mem)) > + return false; > + > + /* Can't deal with subregs. */ > + if (GET_CODE (mem) == SUBREG) > + return false; > + > + gcc_assert (MEM_P (mem)); > + > + *offset = const0_rtx; > + > + addr = XEXP (mem, 0); > + > + /* If addr isn't valid for DImode, then we can't handle it. */ > + if (!arc_legitimate_address_p (DImode, addr, > + reload_in_progress || reload_completed)) > + return false; > + > + if (REG_P (addr)) > + { > + *base = addr; > + return true; > + } > + else if (GET_CODE (addr) == PLUS || GET_CODE (addr) == MINUS) > + { > + *base = XEXP (addr, 0); > + *offset = XEXP (addr, 1); > + return (REG_P (*base) && CONST_INT_P (*offset)); > + } > + > + return false; > +} > + > +/* Called from peephole2 to replace two word-size accesses with a > + single LDD/STD instruction. Returns true iff we can generate a new > + instruction sequence. That is, both accesses use the same base > + register and the gap between constant offsets is 4. OPERANDS are > + the operands found by the peephole matcher; OPERANDS[0,1] are > + register operands, and OPERANDS[2,3] are the corresponding memory > + operands. LOAD indicates whether the access is load or store. */ > + > +bool > +gen_operands_ldd_std (rtx *operands, bool load, bool commute) > +{ > + int i, gap; > + HOST_WIDE_INT offsets[2], offset; > + int nops = 2; > + rtx cur_base, cur_offset, tmp; > + rtx base = NULL_RTX; > + > + /* Check that the memory references are immediate offsets from the > + same base register. Extract the base register, the destination > + registers, and the corresponding memory offsets. */ > + for (i = 0; i < nops; i++) > + { > + if (!mem_ok_for_ldd_std (operands[nops+i], &cur_base, &cur_offset)) > + return false; > + > + if (i == 0) > + base = cur_base; > + else if (REGNO (base) != REGNO (cur_base)) > + return false; > + > + offsets[i] = INTVAL (cur_offset); > + if (GET_CODE (operands[i]) == SUBREG) > + { > + tmp = SUBREG_REG (operands[i]); > + gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp)); > + operands[i] = tmp; > + } > + } > + > + /* Make sure there is no dependency between the individual loads. */ > + if (load && REGNO (operands[0]) == REGNO (base)) > + return false; /* RAW. */ > + > + if (load && REGNO (operands[0]) == REGNO (operands[1])) > + return false; /* WAW. */ > + > + /* Make sure the instructions are ordered with lower memory access first. */ > + if (offsets[0] > offsets[1]) > + { > + gap = offsets[0] - offsets[1]; > + offset = offsets[1]; > + > + /* Swap the instructions such that lower memory is accessed first. */ > + std::swap (operands[0], operands[1]); > + std::swap (operands[2], operands[3]); > + } > + else > + { > + gap = offsets[1] - offsets[0]; > + offset = offsets[0]; > + } > + > + /* Make sure accesses are to consecutive memory locations. */ > + if (gap != 4) > + return false; > + > + /* Make sure we generate legal instructions. */ > + if (operands_ok_ldd_std (operands[0], operands[1], offset)) > + return true; > + > + if (load && commute) > + { > + /* Try reordering registers. */ > + std::swap (operands[0], operands[1]); > + if (operands_ok_ldd_std (operands[0], operands[1], offset)) > + return true; > + } > + > + return false; > +} > + > #undef TARGET_USE_ANCHORS_FOR_SYMBOL_P > #define TARGET_USE_ANCHORS_FOR_SYMBOL_P arc_use_anchors_for_symbol_p > > diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md > index 1ed230fa5f0..526fd17a0cf 100644 > --- a/gcc/config/arc/arc.md > +++ b/gcc/config/arc/arc.md > @@ -6363,6 +6363,75 @@ archs4x, archs4xd, archs4xd_slow" > [(set (reg:CC CC_REG) (compare:CC (match_dup 3) > (ashift:SI (match_dup 1) (match_dup 2))))]) > > +(define_peephole2 ; std > + [(set (match_operand:SI 2 "memory_operand" "") > + (match_operand:SI 0 "register_operand" "")) > + (set (match_operand:SI 3 "memory_operand" "") > + (match_operand:SI 1 "register_operand" ""))] > + "TARGET_LL64" > + [(const_int 0)] > +{ > + if (!gen_operands_ldd_std (operands, false, false)) > + FAIL; > + operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); > + operands[2] = adjust_address (operands[2], DImode, 0); > + emit_insn (gen_rtx_SET (operands[2], operands[0])); > + DONE; > +}) > + > +(define_peephole2 ; ldd > + [(set (match_operand:SI 0 "register_operand" "") > + (match_operand:SI 2 "memory_operand" "")) > + (set (match_operand:SI 1 "register_operand" "") > + (match_operand:SI 3 "memory_operand" ""))] > + "TARGET_LL64" > + [(const_int 0)] > +{ > + if (!gen_operands_ldd_std (operands, true, false)) > + FAIL; > + operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); > + operands[2] = adjust_address (operands[2], DImode, 0); > + emit_insn (gen_rtx_SET (operands[0], operands[2])); > + DONE; > +}) > + > +;; We require consecutive registers for LDD instruction. Check if we > +;; can reorder them and use an LDD. > + > +(define_peephole2 ; swap the destination registers of two loads > + ; before a commutative operation. > + [(set (match_operand:SI 0 "register_operand" "") > + (match_operand:SI 2 "memory_operand" "")) > + (set (match_operand:SI 1 "register_operand" "") > + (match_operand:SI 3 "memory_operand" "")) > + (set (match_operand:SI 4 "register_operand" "") > + (match_operator:SI 5 "commutative_operator" > + [(match_operand 6 "register_operand" "") > + (match_operand 7 "register_operand" "") ]))] > + "TARGET_LL64 > + && (((rtx_equal_p (operands[0], operands[6])) > + && (rtx_equal_p (operands[1], operands[7]))) > + || ((rtx_equal_p (operands[0], operands[7])) > + && (rtx_equal_p (operands[1], operands[6])))) > + && (peep2_reg_dead_p (3, operands[0]) > + || rtx_equal_p (operands[0], operands[4])) > + && (peep2_reg_dead_p (3, operands[1]) > + || rtx_equal_p (operands[1], operands[4]))" > + [(set (match_dup 0) (match_dup 2)) > + (set (match_dup 4) (match_op_dup 5 [(match_dup 6) (match_dup 7)]))] > + { > + if (!gen_operands_ldd_std (operands, true, true)) > + { > + FAIL; > + } > + else > + { > + operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); > + operands[2] = adjust_address (operands[2], DImode, 0); > + } > + } > +) > + > ;; include the arc-FPX instructions > (include "fpx.md") > > -- > 2.17.1 >