* [RS6000] Ignore "c", "l" and "h" for register preference
@ 2018-11-13 3:05 Alan Modra
2018-11-13 11:37 ` Segher Boessenkool
0 siblings, 1 reply; 4+ messages in thread
From: Alan Modra @ 2018-11-13 3:05 UTC (permalink / raw)
To: gcc-patches; +Cc: Segher Boessenkool
This catches a few places where move insn patterns don't slightly
disparage CTR, LR and VRSAVE regs. Also fixes the doc for the rs6000
h constraint, and removes an r->cl alternative covered by r->h.
Segher okayed a patch adding "*" like this patch a long time ago.
Somehow I never committed it. This one does a few more things as
well, but I think it's sufficiently obvious to commit as such.
Bootstrapped etc. powerpc64le-linux and committed rev 266044.
* gcc/doc/md.texi (Machine Constraints): Correct rs6000 h constraint
description.
* config/rs6000/rs6000.md (movsi_internal1): Delete MT%0 case
covered by alternative.
(movcc_internal1): Ignore h for register preference.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat): Ignore c, l, h for register preference.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 16f37dafbb9..02e6e084785 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -6842,21 +6842,21 @@ (define_insn "movsi_low"
;; STW STFIWX STXSIWX LI LIS
;; # XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW
;; XXLXOR 0 XXLORC -1 P9 const MTVSRWZ MFVSRWZ
-;; MF%1 MT%0 MT%0 NOP
+;; MF%1 MT%0 NOP
(define_insn "*movsi_internal1"
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r, r, ?*wI, ?*wH,
m, ?Z, ?Z, r, r,
r, ?*wIwH, ?*wJwK, ?*wJwK, ?*wu,
?*wJwK, ?*wH, ?*wK, ?*wIwH, ?r,
- r, *c*l, *h, *h")
+ r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U, m, Z, Z,
r, wI, wH, I, L,
n, wIwH, O, wM, wB,
O, wM, wS, r, wIwH,
- *h, r, r, 0"))]
+ *h, r, 0"))]
"gpc_reg_operand (operands[0], SImode)
|| gpc_reg_operand (operands[1], SImode)"
@@ -6883,21 +6883,20 @@ (define_insn "*movsi_internal1"
mfvsrwz %0,%x1
mf%1 %0
mt%0 %1
- mt%0 %1
nop"
[(set_attr "type"
"*, *, load, fpload, fpload,
store, fpstore, fpstore, *, *,
*, veclogical, vecsimple, vecsimple, vecsimple,
veclogical, veclogical, vecsimple, mffgpr, mftgpr,
- *, *, *, *")
+ *, *, *")
(set_attr "length"
"4, 4, 4, 4, 4,
4, 4, 4, 4, 4,
8, 4, 4, 4, 4,
4, 4, 8, 4, 4,
- 4, 4, 4, 4")])
+ 4, 4, 4")])
;; Like movsi, but adjust a SF value to be used in a SI context, i.e.
;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0))
@@ -7175,9 +7174,9 @@ (define_expand "movcc"
(define_insn "*movcc_internal1"
[(set (match_operand:CC 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r,r,*c*l,r,m")
+ "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
(match_operand:CC 1 "general_operand"
- " y,r, r,O,x,y,r,I,h, r,m,r"))]
+ " y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], CCmode)
|| register_operand (operands[1], CCmode)"
"@
@@ -7329,11 +7328,11 @@ (define_insn "movsd_hardfloat"
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, cl, r, r, m, r,
+ "=r, *c*l, r, r, m, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
- "r, r, h, m, r, I,
+ "r, r, *h, m, r, I,
L, G, Fn, 0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
@@ -7600,7 +7599,7 @@ (define_insn "*mov<mode>_hardfloat64"
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, YZ, r, r, h,
+ r, YZ, r, r, *h,
0, wg, r, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
@@ -7641,11 +7640,11 @@ (define_insn "*mov<mode>_hardfloat64"
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=Y, r, r, cl, r, r,
+ "=Y, r, r, *c*l, r, r,
r, r, *h")
(match_operand:FMOVE64 1 "input_operand"
- "r, Y, r, r, h, G,
+ "r, Y, r, r, *h, G,
H, F, 0"))]
"TARGET_POWERPC64 && TARGET_SOFT_FLOAT
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index e5002e29d6f..1c37a053a94 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3273,7 +3273,7 @@ instructions.
Vector constant that can be loaded with XXSPLTIB & sign extension.
@item h
-@samp{MQ}, @samp{CTR}, or @samp{LINK} register
+@samp{VRSAVE}, @samp{CTR}, or @samp{LINK} register
@item c
@samp{CTR} register
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RS6000] Ignore "c", "l" and "h" for register preference
2018-11-13 3:05 [RS6000] Ignore "c", "l" and "h" for register preference Alan Modra
@ 2018-11-13 11:37 ` Segher Boessenkool
2018-11-19 6:36 ` Alan Modra
0 siblings, 1 reply; 4+ messages in thread
From: Segher Boessenkool @ 2018-11-13 11:37 UTC (permalink / raw)
To: Alan Modra; +Cc: gcc-patches
On Tue, Nov 13, 2018 at 01:35:42PM +1030, Alan Modra wrote:
> This catches a few places where move insn patterns don't slightly
> disparage CTR, LR and VRSAVE regs. Also fixes the doc for the rs6000
> h constraint, and removes an r->cl alternative covered by r->h.
>
> Segher okayed a patch adding "*" like this patch a long time ago.
> Somehow I never committed it. This one does a few more things as
> well, but I think it's sufficiently obvious to commit as such.
> Bootstrapped etc. powerpc64le-linux and committed rev 266044.
Thanks.
I'd like to move to "cl" instead of "h" though :-)
vrsave is not an allocatable register (it's a fixed register). We do
not have to handle it in the general mov patterns at all, just needs a
separate pattern just for this.
> (define_insn "*movcc_internal1"
> [(set (match_operand:CC 0 "nonimmediate_operand"
> - "=y,x,?y,y,r,r,r,r,r,*c*l,r,m")
> + "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
> (match_operand:CC 1 "general_operand"
> - " y,r, r,O,x,y,r,I,h, r,m,r"))]
> + " y,r, r,O,x,y,r,I,*h, r,m,r"))]
Here you see that vrsave as dest already is not supported (and doesn't
have to be, it is never generated).
Ideally "h" does not exist anymore, and "c" and "l" are mentioned nowhere
in the normal mov patterns.
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RS6000] Ignore "c", "l" and "h" for register preference
2018-11-13 11:37 ` Segher Boessenkool
@ 2018-11-19 6:36 ` Alan Modra
2018-11-19 7:20 ` Segher Boessenkool
0 siblings, 1 reply; 4+ messages in thread
From: Alan Modra @ 2018-11-19 6:36 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: gcc-patches
On Tue, Nov 13, 2018 at 05:37:07AM -0600, Segher Boessenkool wrote:
> On Tue, Nov 13, 2018 at 01:35:42PM +1030, Alan Modra wrote:
> > This catches a few places where move insn patterns don't slightly
> > disparage CTR, LR and VRSAVE regs. Also fixes the doc for the rs6000
> > h constraint, and removes an r->cl alternative covered by r->h.
> >
> > Segher okayed a patch adding "*" like this patch a long time ago.
> > Somehow I never committed it. This one does a few more things as
> > well, but I think it's sufficiently obvious to commit as such.
> > Bootstrapped etc. powerpc64le-linux and committed rev 266044.
>
> Thanks.
>
> I'd like to move to "cl" instead of "h" though :-)
>
> vrsave is not an allocatable register (it's a fixed register). We do
> not have to handle it in the general mov patterns at all, just needs a
> separate pattern just for this.
Yes, I had the same thought, but then it wouldn't have been quite such
an obvious patch, and I figure that getting there from where we are
now is not worse than before the patch I committed.
I'll write you a patch to get rid of "h" if it's less work for you to
review my patch than it is to write it yourself. What would you like?
--
Alan Modra
Australia Development Lab, IBM
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [RS6000] Ignore "c", "l" and "h" for register preference
2018-11-19 6:36 ` Alan Modra
@ 2018-11-19 7:20 ` Segher Boessenkool
0 siblings, 0 replies; 4+ messages in thread
From: Segher Boessenkool @ 2018-11-19 7:20 UTC (permalink / raw)
To: Alan Modra; +Cc: gcc-patches
Morning!
On Mon, Nov 19, 2018 at 05:06:07PM +1030, Alan Modra wrote:
> On Tue, Nov 13, 2018 at 05:37:07AM -0600, Segher Boessenkool wrote:
> > On Tue, Nov 13, 2018 at 01:35:42PM +1030, Alan Modra wrote:
> > > This catches a few places where move insn patterns don't slightly
> > > disparage CTR, LR and VRSAVE regs. Also fixes the doc for the rs6000
> > > h constraint, and removes an r->cl alternative covered by r->h.
> > >
> > > Segher okayed a patch adding "*" like this patch a long time ago.
> > > Somehow I never committed it. This one does a few more things as
> > > well, but I think it's sufficiently obvious to commit as such.
> > > Bootstrapped etc. powerpc64le-linux and committed rev 266044.
> >
> > Thanks.
> >
> > I'd like to move to "cl" instead of "h" though :-)
> >
> > vrsave is not an allocatable register (it's a fixed register). We do
> > not have to handle it in the general mov patterns at all, just needs a
> > separate pattern just for this.
>
> Yes, I had the same thought, but then it wouldn't have been quite such
> an obvious patch, and I figure that getting there from where we are
> now is not worse than before the patch I committed.
>
> I'll write you a patch to get rid of "h" if it's less work for you to
> review my patch than it is to write it yourself. What would you like?
Oh, this patch is approved, sorry I didn't yet say that. Thanks!
I'd like to remove "h", or at least our use of it; I'm afraid there may
still be users of it though, in asm. Let's do it at the start of the
GCC 10 cycle?
Segher
^ permalink raw reply [flat|nested] 4+ messages in thread
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2018-11-13 3:05 [RS6000] Ignore "c", "l" and "h" for register preference Alan Modra
2018-11-13 11:37 ` Segher Boessenkool
2018-11-19 6:36 ` Alan Modra
2018-11-19 7:20 ` Segher Boessenkool
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