From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 106649 invoked by alias); 29 Nov 2018 21:41:01 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 106637 invoked by uid 89); 29 Nov 2018 21:41:00 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00,GIT_PATCH_2,GIT_PATCH_3,SPF_HELO_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mx1.redhat.com Received: from mx1.redhat.com (HELO mx1.redhat.com) (209.132.183.28) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Nov 2018 21:40:58 +0000 Received: from smtp.corp.redhat.com (int-mx05.intmail.prod.int.phx2.redhat.com [10.5.11.15]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 279D13082190; Thu, 29 Nov 2018 21:40:57 +0000 (UTC) Received: from tucnak.zalov.cz (ovpn-117-214.ams2.redhat.com [10.36.117.214]) by smtp.corp.redhat.com (Postfix) with ESMTPS id 9B78A5EDE4; Thu, 29 Nov 2018 21:40:56 +0000 (UTC) Received: from tucnak.zalov.cz (localhost [127.0.0.1]) by tucnak.zalov.cz (8.15.2/8.15.2) with ESMTP id wATLeskS023952; Thu, 29 Nov 2018 22:40:54 +0100 Received: (from jakub@localhost) by tucnak.zalov.cz (8.15.2/8.15.2/Submit) id wATLeqNg023951; Thu, 29 Nov 2018 22:40:52 +0100 Date: Thu, 29 Nov 2018 21:41:00 -0000 From: Jakub Jelinek To: Uros Bizjak Cc: "gcc-patches@gcc.gnu.org" Subject: Re: [PATCH] Optimize integral lt + blend into just blend (PR target/54700) Message-ID: <20181129214052.GS12380@tucnak> Reply-To: Jakub Jelinek References: <20181129075956.GE12380@tucnak> <20181129162829.GP12380@tucnak> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.2 (2017-12-15) X-IsSubscribed: yes X-SW-Source: 2018-11/txt/msg02502.txt.bz2 On Thu, Nov 29, 2018 at 05:41:59PM +0100, Uros Bizjak wrote: > On Thu, Nov 29, 2018 at 5:28 PM Jakub Jelinek wrote: > > > > On Thu, Nov 29, 2018 at 05:21:53PM +0100, Uros Bizjak wrote: > > > > > * g++.target/i386/avx2-check.h: New file. > > > > > * g++.target/i386/m128-check.h: New file. > > > > > * g++.target/i386/m256-check.h: New file. > > > > > * g++.target/i386/avx-os-support.h: New file. > > > > > > > > OK. > > > > > > On a second thought, should we rather use (pre-reload?) > > > define_insn_and_split to split the combination to the blend insn? > > > > I've already committed it. But can work on a patch that does that tomorrow. > > Thanks. You will probably need to split it after reload, since a > change from intvec->FPvec is needed. Like this? Bootstrapped/regtested on x86_64-linux and i686-linux. 2018-11-29 Jakub Jelinek PR target/54700 * config/i386/sse.md (*_blendv_lt, *_blendv_ltint, *_pblendvb_lt): Change define_insn into define_insn_and_split. --- gcc/config/i386/sse.md.jj 2018-11-29 15:32:27.597301378 +0100 +++ gcc/config/i386/sse.md 2018-11-29 18:52:42.747904630 +0100 @@ -15682,7 +15682,7 @@ (define_insn "sse4_1_blendv")))]) -(define_insn "*_blendv_lt" +(define_insn_and_split "*_blendv_lt" [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x") (unspec:VF_128_256 [(match_operand:VF_128_256 1 "register_operand" "0,0,x") @@ -15693,10 +15693,12 @@ (define_insn "*_blendv 4 "const0_operand" "C,C,C")) 0)] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "@ - blendv\t{%3, %2, %0|%0, %2, %3} - blendv\t{%3, %2, %0|%0, %2, %3} - vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "#" + "&& reload_completed" + [(set (match_dup 0) + (unspec:VF_128_256 + [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))] + "operands[3] = gen_lowpart (mode, operands[3]);" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "length_immediate" "1") @@ -15712,7 +15714,7 @@ (define_mode_attr ssefltmodesuffix (define_mode_attr ssefltvecmode [(V2DI "V2DF") (V4DI "V4DF") (V4SI "V4SF") (V8SI "V8SF")]) -(define_insn "*_blendv_ltint" +(define_insn_and_split "*_blendv_ltint" [(set (match_operand: 0 "register_operand" "=Yr,*x,x") (unspec: [(match_operand: 1 "register_operand" "0,0,x") @@ -15723,10 +15725,17 @@ (define_insn "*_blendv\t{%3, %2, %0|%0, %2, %3} - blendv\t{%3, %2, %0|%0, %2, %3} - vblendv\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "#" + "&& reload_completed" + [(set (match_dup 0) + (unspec: + [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))] +{ + operands[0] = gen_lowpart (mode, operands[0]); + operands[1] = gen_lowpart (mode, operands[1]); + operands[2] = gen_lowpart (mode, operands[2]); + operands[3] = gen_lowpart (mode, operands[3]); +} [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "length_immediate" "1") @@ -15834,7 +15843,7 @@ (define_insn "_pblendvb" (set_attr "btver2_decode" "vector,vector,vector") (set_attr "mode" "")]) -(define_insn "*_pblendvb_lt" +(define_insn_and_split "*_pblendvb_lt" [(set (match_operand:VI1_AVX2 0 "register_operand" "=Yr,*x,x") (unspec:VI1_AVX2 [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x") @@ -15843,10 +15852,12 @@ (define_insn "*_pblendvb_lt (match_operand:VI1_AVX2 4 "const0_operand" "C,C,C"))] UNSPEC_BLENDV))] "TARGET_SSE4_1" - "@ - pblendvb\t{%3, %2, %0|%0, %2, %3} - pblendvb\t{%3, %2, %0|%0, %2, %3} - vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}" + "#" + "" + [(set (match_dup 0) + (unspec:VI1_AVX2 + [(match_dup 1) (match_dup 2) (match_dup 3)] UNSPEC_BLENDV))] + "" [(set_attr "isa" "noavx,noavx,avx") (set_attr "type" "ssemov") (set_attr "prefix_extra" "1") Jakub