From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 19915 invoked by alias); 4 Dec 2018 20:16:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 19480 invoked by uid 89); 4 Dec 2018 20:16:13 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy= X-HELO: gate.crashing.org Received: from gate.crashing.org (HELO gate.crashing.org) (63.228.1.57) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 04 Dec 2018 20:16:11 +0000 Received: from gate.crashing.org (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id wB4KG6hp010818; Tue, 4 Dec 2018 14:16:07 -0600 Received: (from segher@localhost) by gate.crashing.org (8.14.1/8.14.1/Submit) id wB4KG47O010817; Tue, 4 Dec 2018 14:16:04 -0600 Date: Tue, 04 Dec 2018 20:16:00 -0000 From: Segher Boessenkool To: Paul Clarke Cc: gcc-patches@gcc.gnu.org Subject: Re: [PATCH 1/3][rs6000] x86-compat vector intrinsics fixes for BE, 32bit Message-ID: <20181204201603.GI3803@gate.crashing.org> References: Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.4.2.3i X-IsSubscribed: yes X-SW-Source: 2018-12/txt/msg00229.txt.bz2 Hi! On Tue, Dec 04, 2018 at 08:59:03AM -0600, Paul Clarke wrote: > Fix general endian and 32-bit mode issues found in the > compatibility implementations of the x86 vector intrinsics when running the > associated test suite tests. (The tests had been inadvertently made to PASS > without actually running the test code. A later patch fixes this issue.) > > In a few cases, the opportunity was taken to update the vector API used in > the implementations to the preferred functions from the > OpenPOWER 64-Bit ELF V2 ABI Specification. > > [gcc] > > 2018-12-03 Paul A. Clarke > > PR target/88316 > * config/rs6000/mmintrin.h (_mm_unpackhi_pi8): Fix for big-endian. > (_mm_unpacklo_pi8): Likewise. > (_mm_mulhi_pi16): Likewise. > (_mm_packs_pi16): Fix for big-endian. Use preferred API. > (_mm_packs_pi32): Likewise. > (_mm_packs_pu16): Likewise. > * config/rs6000/xmmintrin.h (_mm_cvtss_si32): Fix for big-endian. > (_mm_cvtss_si64): Likewise. > (_mm_cvtpi32x2_ps): Likewise. > (_mm_shuffle_ps): Likewise. > (_mm_movemask_pi8): Likewise. > (_mm_mulhi_pu16): Likewise. > (_mm_sad_pu8): Likewise. > (_mm_sad_pu8): Likewise. > (_mm_cvtpu16_ps): Fix for big-endian. Use preferred API. > (_mm_cvtpu8_ps): Likewise. > * config/rs6000/emmintrin.h (_mm_movemask_pd): Fix for big-endian. > (_mm_mul_epu32): Likewise. > (_mm_bsrli_si128): Likewise. > (_mm_movemask_epi8): Likewise. > (_mm_shufflehi_epi16): Likewise. > (_mm_shufflelo_epi16): Likewise. > (_mm_shuffle_epi32): Likewise. > * config/rs6000/pmmintrin.h (_mm_hadd_ps): Fix for big-endian. > (_mm_sub_ps): Likewise. > * config/rs6000/mmintrin.h (_mm_cmpeq_pi8): Fix for 32-bit mode. > @@ -1612,7 +1608,8 @@ _mm_bsrli_si128 (__m128i __A, const int __N) > const __v16qu zeros = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; > > if (__N < 16) > - if (__builtin_constant_p(__N)) > + if (__builtin_constant_p(__N) && > + __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__) Please just use __LITTLE_ENDIAN__, as the rest of these files already does. (More times in this patch; also BIG). Okay for trunk with that fixed. Thanks! Do you have new testcases, too? Or is all this caught by existing testcases? Segher