From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 90843 invoked by alias); 9 Feb 2019 13:24:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 90029 invoked by uid 89); 9 Feb 2019 13:24:04 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=Hx-languages-length:1862, HContent-Transfer-Encoding:8bit X-HELO: mga01.intel.com Received: from mga01.intel.com (HELO mga01.intel.com) (192.55.52.88) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 09 Feb 2019 13:24:01 +0000 Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 09 Feb 2019 05:23:53 -0800 Received: from gnu-cfl-1.sc.intel.com ([172.25.70.237]) by fmsmga004.fm.intel.com with ESMTP; 09 Feb 2019 05:23:53 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 17/43] i386: Emulate MMX mmx_pinsrw with SSE Date: Sat, 09 Feb 2019 13:24:00 -0000 Message-Id: <20190209132352.1828-18-hjl.tools@gmail.com> In-Reply-To: <20190209132352.1828-1-hjl.tools@gmail.com> References: <20190209132352.1828-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg00518.txt.bz2 Emulate MMX mmx_pinsrw with SSE. Only SSE register source operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 27 +++++++++++++++++++-------- 1 file changed, 19 insertions(+), 8 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index fced8fd4a10..ad33e587352 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1328,25 +1328,36 @@ }) (define_insn "*mmx_pinsrw" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,Yx,Yy") (vec_merge:V4HI (vec_duplicate:V4HI - (match_operand:HI 2 "nonimmediate_operand" "rm")) - (match_operand:V4HI 1 "register_operand" "0") + (match_operand:HI 2 "nonimmediate_operand" "rm,rm,rm")) + (match_operand:V4HI 1 "register_operand" "0,0,Yy") (match_operand:SI 3 "const_int_operand")))] "(TARGET_SSE || TARGET_3DNOW_A) && ((unsigned) exact_log2 (INTVAL (operands[3])) < GET_MODE_NUNITS (V4HImode))" { operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); - if (MEM_P (operands[2])) - return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; + if (TARGET_MMX_WITH_SSE && TARGET_AVX) + { + if (MEM_P (operands[2])) + return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}"; + else + return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}"; + } else - return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; + { + if (MEM_P (operands[2])) + return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; + else + return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; + } } - [(set_attr "type" "mmxcvt") + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_pextrw" [(set (match_operand:SI 0 "register_operand" "=r,r") -- 2.20.1