From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Uros Bizjak <ubizjak@gmail.com>
Subject: [PATCH 41/43] i386: Implement V2SF add/sub/mul with SEE
Date: Sat, 09 Feb 2019 13:25:00 -0000 [thread overview]
Message-ID: <20190209132352.1828-42-hjl.tools@gmail.com> (raw)
In-Reply-To: <20190209132352.1828-1-hjl.tools@gmail.com>
In 64-bit mode, implement V2SF add/sub/mul with SEE. Only SSE register
source operand is allowed.
gcc/
PR target/89028
* config/i386/i386.md (comm): Handle mult.
* config/i386/mmx.md (plusminusmult): New.
(plusminusmult_insn): Likewse.
(plusminusmult_mnemonic): Likewse.
(plusminusmult_type): Likewse.
(mmx_addv2sf3): Add "&& !TARGET_MMX_WITH_SSE".
(*mmx_addv2sf3): Likewise.
(mmx_subv2sf3): Likewise.
(mmx_subrv2sf3): Likewise.
(*mmx_subv2sf3): Likewise.
(mmx_mulv2sf3): Likewise.
(*mmx_mulv2sf3): Likewise.
(<plusminusmult_insn>v2sf3): New.
(*sse_<plusminusmult_insn>v2sf3): Likewise.
gcc/testsuite/
PR target/89028
* gcc.target/i386/pr89028-2.c: New test.
* gcc.target/i386/pr89028-3.c: Likewise.
* gcc.target/i386/pr89028-4.c: Likewise.
* gcc.target/i386/pr89028-5.c: Likewise.
* gcc.target/i386/pr89028-6.c: Likewise.
* gcc.target/i386/pr89028-7.c: Likewise.
---
gcc/config/i386/i386.md | 3 +-
gcc/config/i386/mmx.md | 56 ++++++++++++++++++++---
gcc/testsuite/gcc.target/i386/pr89028-2.c | 11 +++++
gcc/testsuite/gcc.target/i386/pr89028-3.c | 14 ++++++
gcc/testsuite/gcc.target/i386/pr89028-4.c | 14 ++++++
gcc/testsuite/gcc.target/i386/pr89028-5.c | 11 +++++
gcc/testsuite/gcc.target/i386/pr89028-6.c | 14 ++++++
gcc/testsuite/gcc.target/i386/pr89028-7.c | 14 ++++++
8 files changed, 129 insertions(+), 8 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/pr89028-2.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr89028-3.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr89028-4.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr89028-5.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr89028-6.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr89028-7.c
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 72685107fc0..cda973c0fbf 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -873,7 +873,8 @@
;; Mark commutative operators as such in constraints.
(define_code_attr comm [(plus "%") (ss_plus "%") (us_plus "%")
- (minus "") (ss_minus "") (us_minus "")])
+ (minus "") (ss_minus "") (us_minus "")
+ (mult "%")])
;; Mapping of max and min
(define_code_iterator maxmin [smax smin umax umin])
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 31db0e8b0c7..b2af9ace2c3 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -63,6 +63,20 @@
;; Instruction suffix for truncations with saturation.
(define_code_attr s_trunsuffix [(ss_truncate "s") (us_truncate "u")])
+(define_code_iterator plusminusmult [plus minus mult])
+
+;; Base name for define_insn
+(define_code_attr plusminusmult_insn
+ [(plus "add") (minus "sub") (mult "mul")])
+
+;; Base name for insn mnemonic.
+(define_code_attr plusminusmult_mnemonic
+ [(plus "add") (minus "sub") (mult "mul")])
+
+;; Insn type name for insn mnemonic.
+(define_code_attr plusminusmult_type
+ [(plus "add") (minus "add") (mult "mul")])
+
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Move patterns
@@ -277,14 +291,16 @@
(plus:V2SF
(match_operand:V2SF 1 "nonimmediate_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
- "TARGET_3DNOW"
+ "TARGET_3DNOW && !TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (PLUS, V2SFmode, operands);")
(define_insn "*mmx_addv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(plus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
+ "TARGET_3DNOW
+ && !TARGET_MMX_WITH_SSE
+ && ix86_binary_operator_ok (PLUS, V2SFmode, operands)"
"pfadd\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxadd")
(set_attr "prefix_extra" "1")
@@ -294,19 +310,21 @@
[(set (match_operand:V2SF 0 "register_operand")
(minus:V2SF (match_operand:V2SF 1 "register_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
- "TARGET_3DNOW")
+ "TARGET_3DNOW && !TARGET_MMX_WITH_SSE")
(define_expand "mmx_subrv2sf3"
[(set (match_operand:V2SF 0 "register_operand")
(minus:V2SF (match_operand:V2SF 2 "register_operand")
(match_operand:V2SF 1 "nonimmediate_operand")))]
- "TARGET_3DNOW")
+ "TARGET_3DNOW && !TARGET_MMX_WITH_SSE")
(define_insn "*mmx_subv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y,y")
(minus:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "0,ym")
(match_operand:V2SF 2 "nonimmediate_operand" "ym,0")))]
- "TARGET_3DNOW && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
+ "TARGET_3DNOW
+ && !TARGET_MMX_WITH_SSE
+ && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
pfsub\t{%2, %0|%0, %2}
pfsubr\t{%1, %0|%0, %1}"
@@ -318,19 +336,43 @@
[(set (match_operand:V2SF 0 "register_operand")
(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand")
(match_operand:V2SF 2 "nonimmediate_operand")))]
- "TARGET_3DNOW"
+ "TARGET_3DNOW && !TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (MULT, V2SFmode, operands);")
(define_insn "*mmx_mulv2sf3"
[(set (match_operand:V2SF 0 "register_operand" "=y")
(mult:V2SF (match_operand:V2SF 1 "nonimmediate_operand" "%0")
(match_operand:V2SF 2 "nonimmediate_operand" "ym")))]
- "TARGET_3DNOW && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
+ "TARGET_3DNOW
+ && !TARGET_MMX_WITH_SSE
+ && ix86_binary_operator_ok (MULT, V2SFmode, operands)"
"pfmul\t{%2, %0|%0, %2}"
[(set_attr "type" "mmxmul")
(set_attr "prefix_extra" "1")
(set_attr "mode" "V2SF")])
+(define_expand "<plusminusmult_insn>v2sf3"
+ [(set (match_operand:V2SF 0 "register_operand")
+ (plusminusmult:V2SF
+ (match_operand:V2SF 1 "nonimmediate_operand")
+ (match_operand:V2SF 2 "nonimmediate_operand")))]
+ "TARGET_MMX_WITH_SSE"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, V2SFmode, operands);")
+
+(define_insn "*sse_<plusminusmult_insn>v2sf3"
+ [(set (match_operand:V2SF 0 "register_operand" "=Yx,Yy")
+ (plusminusmult:V2SF
+ (match_operand:V2SF 1 "nonimmediate_operand" "<comm>0,Yy")
+ (match_operand:V2SF 2 "nonimmediate_operand" "Yx,Yy")))]
+ "TARGET_MMX_WITH_SSE
+ && ix86_binary_operator_ok (<CODE>, V4SFmode, operands)"
+ "@
+ <plusminusmult_mnemonic>ps\t{%2, %0|%0, %2}
+ v<plusminusmult_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "isa" "noavx,avx")
+ (set_attr "type" "sse<plusminusmult_type>")
+ (set_attr "mode" "V4SF")])
+
(define_expand "mmx_<code>v2sf3"
[(set (match_operand:V2SF 0 "register_operand")
(smaxmin:V2SF
diff --git a/gcc/testsuite/gcc.target/i386/pr89028-2.c b/gcc/testsuite/gcc.target/i386/pr89028-2.c
new file mode 100644
index 00000000000..d096b0b6863
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89028-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-mmx" } */
+/* { dg-final { scan-assembler-times "addps" 1 } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+__v2sf
+foo1 (__v2sf x, __v2sf y)
+{
+ return x + y;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89028-3.c b/gcc/testsuite/gcc.target/i386/pr89028-3.c
new file mode 100644
index 00000000000..0fa187aaf72
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89028-3.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-mmx" } */
+/* { dg-final { scan-assembler-times "movlps" 2 } } */
+/* { dg-final { scan-assembler-times "addps" 1 } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+extern __v2sf x, y, z;
+
+__v2sf
+foo2 (void)
+{
+ return x + y;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89028-4.c b/gcc/testsuite/gcc.target/i386/pr89028-4.c
new file mode 100644
index 00000000000..b25f67632cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89028-4.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-mmx" } */
+/* { dg-final { scan-assembler-times "movlps" 1 } } */
+/* { dg-final { scan-assembler-times "addps" 1 } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+extern __v2sf x, y, z;
+
+void
+foo3 (__v2sf x, __v2sf y)
+{
+ z = x + y;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89028-5.c b/gcc/testsuite/gcc.target/i386/pr89028-5.c
new file mode 100644
index 00000000000..4ead7187605
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89028-5.c
@@ -0,0 +1,11 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-mmx" } */
+/* { dg-final { scan-assembler-times "mulps" 1 } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+__v2sf
+foo1 (__v2sf x, __v2sf y)
+{
+ return x * y;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89028-6.c b/gcc/testsuite/gcc.target/i386/pr89028-6.c
new file mode 100644
index 00000000000..9277c848c6c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89028-6.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-mmx" } */
+/* { dg-final { scan-assembler-times "movlps" 2 } } */
+/* { dg-final { scan-assembler-times "mulps" 1 } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+extern __v2sf x, y, z;
+
+__v2sf
+foo2 (void)
+{
+ return x * y;
+}
diff --git a/gcc/testsuite/gcc.target/i386/pr89028-7.c b/gcc/testsuite/gcc.target/i386/pr89028-7.c
new file mode 100644
index 00000000000..c8af7b2a4e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr89028-7.c
@@ -0,0 +1,14 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2 -msse2 -mno-mmx" } */
+/* { dg-final { scan-assembler-times "movlps" 1 } } */
+/* { dg-final { scan-assembler-times "mulps" 1 } } */
+
+typedef float __v2sf __attribute__ ((__vector_size__ (8)));
+
+extern __v2sf x, y, z;
+
+void
+foo3 (__v2sf x, __v2sf y)
+{
+ z = x * y;
+}
--
2.20.1
next prev parent reply other threads:[~2019-02-09 13:25 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-09 13:24 [PATCH 00/43] V2: Emulate MMX intrinsics with SSE H.J. Lu
2019-02-09 13:23 ` [PATCH 08/43] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 " H.J. Lu
2019-02-09 13:24 ` [PATCH 17/43] i386: Emulate MMX mmx_pinsrw " H.J. Lu
2019-02-09 13:24 ` [PATCH 07/43] i386: Emulate MMX mmx_pmaddwd " H.J. Lu
2019-02-09 13:24 ` [PATCH 03/43] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-09 13:24 ` [PATCH 04/43] i386: Emulate MMX plusminus/sat_plusminus with SSE H.J. Lu
2019-02-09 14:19 ` Uros Bizjak
2019-02-09 13:24 ` [PATCH 02/43] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-09 13:24 ` [PATCH 15/43] i386: Emulate MMX sse_cvtpi2ps with SSE H.J. Lu
2019-02-09 13:24 ` [PATCH 09/43] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-10 10:27 ` Uros Bizjak
2019-02-09 13:24 ` [PATCH 11/43] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 " H.J. Lu
2019-02-09 13:24 ` [PATCH 06/43] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-09 13:24 ` [PATCH 14/43] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi " H.J. Lu
2019-02-09 14:28 ` Uros Bizjak
2019-02-09 13:24 ` [PATCH 12/43] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-09 13:25 ` [PATCH 29/43] i386: Emulate MMX ssse3_pmaddubsw " H.J. Lu
2019-02-09 13:25 ` [PATCH 24/43] i386: Emulate MMX mmx_psadbw " H.J. Lu
2019-02-09 13:25 ` [PATCH 40/43] i386: Enable 8-byte vectorizer for TARGET_MMX_WITH_SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 34/43] i386: Emulate MMX abs<mode>2 with SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 23/43] i386: Emulate MMX mmx_uavgv4hi3 " H.J. Lu
2019-02-09 13:25 ` [PATCH 43/43] i386: Implement V2SF comparisons " H.J. Lu
2019-02-09 13:25 ` [PATCH 25/43] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-09 13:25 ` [PATCH 30/43] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 05/43] i386: Emulate MMX mulv4hi3 " H.J. Lu
2019-02-10 10:17 ` Uros Bizjak
2019-02-09 13:25 ` [PATCH 27/43] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 " H.J. Lu
2019-02-09 13:25 ` [PATCH 20/43] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-09 13:25 ` [PATCH 33/43] i386: Emulate MMX ssse3_palignrdi " H.J. Lu
2019-02-09 13:25 ` [PATCH 38/43] i386: Add tests for MMX intrinsic emulations " H.J. Lu
2019-02-09 13:25 ` [PATCH 32/43] i386: Emulate MMX ssse3_psign<mode>3 " H.J. Lu
2019-02-09 13:25 ` [PATCH 16/43] i386: Emulate MMX mmx_pextrw " H.J. Lu
2019-02-09 13:25 ` [PATCH 26/43] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-09 13:25 ` [PATCH 13/43] i386: Emulate MMX pshufw with SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 22/43] i386: Emulate MMX mmx_uavgv8qi3 " H.J. Lu
2019-02-09 13:25 ` [PATCH 36/43] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 01/43] i386: Allow 64-bit vector modes in SSE registers H.J. Lu
2019-02-09 14:09 ` Uros Bizjak
2019-02-09 14:32 ` H.J. Lu
2019-02-09 15:03 ` Uros Bizjak
2019-02-09 15:08 ` H.J. Lu
2019-02-09 18:27 ` Uros Bizjak
2019-02-09 18:32 ` H.J. Lu
2019-02-09 18:42 ` Uros Bizjak
2019-02-09 18:53 ` H.J. Lu
2019-02-09 13:25 ` [PATCH 31/43] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-09 13:25 ` [PATCH 28/43] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 35/43] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 18/43] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE H.J. Lu
2019-02-09 13:25 ` [PATCH 19/43] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-09 13:25 ` [PATCH 37/43] i386: Allow MMX intrinsic emulation " H.J. Lu
2019-02-09 14:43 ` Uros Bizjak
2019-02-09 13:25 ` H.J. Lu [this message]
2019-02-09 13:25 ` [PATCH 10/43] i386: Emulate MMX mmx_andnot<mode>3 " H.J. Lu
2019-02-10 10:28 ` Uros Bizjak
2019-02-09 13:25 ` [PATCH 39/43] i386: Also enable SSSE3 __m64 tests in 64-bit mode H.J. Lu
2019-02-09 13:25 ` [PATCH 42/43] i386: Implement V2SF <-> V2SI conversions with SEE H.J. Lu
2019-02-09 13:25 ` [PATCH 21/43] i386: Emulate MMX maskmovq with SSE2 maskmovdqu H.J. Lu
2019-02-09 13:53 ` [PATCH 00/43] V2: Emulate MMX intrinsics with SSE Uros Bizjak
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