From: Jakub Jelinek <jakub@redhat.com>
To: Uros Bizjak <ubizjak@gmail.com>
Cc: "H.J. Lu" <hjl.tools@gmail.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] i386: Use EXT_REX_SSE_REG_P in *movoi_internal_avx/movti_internal
Date: Mon, 11 Feb 2019 16:24:00 -0000 [thread overview]
Message-ID: <20190211162424.GG2135@tucnak> (raw)
In-Reply-To: <CAFULd4Ydin5mS3Ovmw5gJHfrWFm=Qxfw4aadCSwTqvMTfjyGLA@mail.gmail.com>
On Mon, Feb 11, 2019 at 04:56:45PM +0100, Uros Bizjak wrote:
> > Let's first define what MODE_XI means in standard_sse_constant_opcode
> > as well as in all these mov patterns for with and without AVX512VL. Without
> > a clear definition, we can't get out of this mess.
>
> INT_MODE (OI, 32);
> INT_MODE (XI, 64);
>
> So, XI_MODE represents 64 INTEGER bytes = 64 * 8 = 512 bit operation,
> in case of const_1, all 512 bits set.
>
> We can load zeros with narrower instruction, (e.g. 256 bit by inherent
> zeroing of highpart in case of 128 bit xor), so TImode in this case.
>
> Some targets prefer V4SF mode, so they will emit float xorps for zeroing
>
> Then the introduction of AVX512F fubared everything by overloading the
> meaning of insn mode.
I don't see much changes in AVX512F here, most of the behavior has been
there already in AVX.
Most of the SSE/AVX/AVX512 instructions affect the whole register,
usually there is DEST[MAX_VL-1:VL] <- 0 at the end of each instruction.
But, using the MAX_VL to determine get_attr_mode doesn't seem really useful,
because that changes dynamically at runtime based on the actual hw, not on
what we've been compiled for.
So, I believe we want to use that VL value to determine the bitsize of the
mode corresponding to get_attr_mode. And in that case, for
*movoi_internal_avx and *movti_internal, I believe the right mode is MODE_OI
resp. MODE_TI for AVX512VL, because e.g.
vmovdqa32 %ymm12, %ymm23
is a VL = 256 instruction, not VL = 512. Similarly, if we want to set
%ymm25 to all ones, i.e. movoi_internal_avx, we use
vpternlogd $0xFF, %ymm25, %ymm25, %ymm25
which is again VL = 256 instruction, so should use MODE_OI.
We'd need to use
vmovdqa32 %zmm12, %zmm23
or
vpternlogd $0xFF, %zmm25, %zmm25, %zmm25
instructions for AVX512F without AVX512VL, but as has been discussed, this
won't really happen, because hard_regno_mode_ok refuses to allocate 256-bit
or 128-bit modes in ext sse registers.
Jakub
next prev parent reply other threads:[~2019-02-11 16:24 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-07 21:11 [PATCH] i386: Use OI/TImode in *mov[ot]i_internal_avx with AVX512VL H.J. Lu
2019-02-08 9:51 ` Uros Bizjak
2019-02-08 11:29 ` H.J. Lu
2019-02-09 0:31 ` [PATCH] i386: Use EXT_REX_SSE_REG_P in *movoi_internal_avx/movti_internal H.J. Lu
2019-02-09 9:50 ` Uros Bizjak
2019-02-09 9:56 ` Jakub Jelinek
2019-02-09 10:40 ` Jakub Jelinek
2019-02-09 10:51 ` Jakub Jelinek
2019-02-09 12:12 ` H.J. Lu
2019-02-09 12:22 ` Jakub Jelinek
2019-02-09 13:39 ` Jakub Jelinek
2019-02-11 13:11 ` H.J. Lu
2019-02-11 13:15 ` Uros Bizjak
2019-02-11 13:29 ` H.J. Lu
2019-02-11 13:51 ` Uros Bizjak
2019-02-11 14:32 ` H.J. Lu
2019-02-11 15:57 ` Uros Bizjak
2019-02-11 16:03 ` H.J. Lu
2019-02-11 16:24 ` Jakub Jelinek [this message]
2019-02-14 2:34 ` [PATCH] i386: Properly encode xmm16-xmm31/ymm16-ymm31 for vector move H.J. Lu
2019-02-11 13:47 ` [PATCH] i386: Use EXT_REX_SSE_REG_P in *movoi_internal_avx/movti_internal Jakub Jelinek
2019-02-12 18:03 ` [PATCH] i386: Use OI/TImode in *mov[ot]i_internal_avx with AVX512VL Uros Bizjak
2019-02-12 19:01 ` H.J. Lu
2019-02-11 2:35 ` Alan Modra
2019-02-11 7:23 ` Uros Bizjak
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