From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 97591 invoked by alias); 11 Feb 2019 22:55:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 97582 invoked by uid 89); 11 Feb 2019 22:55:57 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=HContent-Transfer-Encoding:8bit X-HELO: mga17.intel.com Received: from mga17.intel.com (HELO mga17.intel.com) (192.55.52.151) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 11 Feb 2019 22:55:56 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 11 Feb 2019 14:55:54 -0800 Received: from gnu-cfl-1.sc.intel.com ([172.25.70.237]) by fmsmga002.fm.intel.com with ESMTP; 11 Feb 2019 14:55:54 -0800 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 01/40] i386: Allow MMX register modes in SSE registers Date: Mon, 11 Feb 2019 22:55:00 -0000 Message-Id: <20190211225553.32050-2-hjl.tools@gmail.com> In-Reply-To: <20190211225553.32050-1-hjl.tools@gmail.com> References: <20190211225553.32050-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg00810.txt.bz2 In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386.c (ix86_set_reg_reg_cost): Also support VALID_MMX_WITH_SSE_REG_MODE. (ix86_vector_mode_supported_p): Likewise. * config/i386/i386.h (TARGET_MMX_WITH_SSE): New. (TARGET_MMX_WITH_SSE_P): Likewise. --- gcc/config/i386/i386.c | 5 +++-- gcc/config/i386/i386.h | 5 +++++ 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 12bc7926f86..61e602bdb38 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -40235,7 +40235,8 @@ ix86_set_reg_reg_cost (machine_mode mode) || (TARGET_AVX && VALID_AVX256_REG_MODE (mode)) || (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode)) || (TARGET_SSE && VALID_SSE_REG_MODE (mode)) - || (TARGET_MMX && VALID_MMX_REG_MODE (mode))) + || ((TARGET_MMX || TARGET_MMX_WITH_SSE) + && VALID_MMX_REG_MODE (mode))) units = GET_MODE_SIZE (mode); } @@ -44061,7 +44062,7 @@ ix86_vector_mode_supported_p (machine_mode mode) return true; if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode)) return true; - if (TARGET_MMX && VALID_MMX_REG_MODE (mode)) + if ((TARGET_MMX ||TARGET_MMX_WITH_SSE) && VALID_MMX_REG_MODE (mode)) return true; if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode)) return true; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 83b025e0cf5..db814d9ed17 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -201,6 +201,11 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_16BIT TARGET_CODE16 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) +#define TARGET_MMX_WITH_SSE \ + (TARGET_64BIT && TARGET_SSE2) +#define TARGET_MMX_WITH_SSE_P(x) \ + (TARGET_64BIT_P (x) && TARGET_SSE2_P (x)) + #include "config/vxworks-dummy.h" #include "config/i386/i386-opts.h" -- 2.20.1