From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Uros Bizjak <ubizjak@gmail.com>
Subject: [PATCH 27/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE
Date: Thu, 14 Feb 2019 12:33:00 -0000 [thread overview]
Message-ID: <20190214123031.13301-28-hjl.tools@gmail.com> (raw)
In-Reply-To: <20190214123031.13301-1-hjl.tools@gmail.com>
Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE by moving bits
64:95 to bits 32:63 in SSE register. Only SSE register source operand
is allowed.
PR target/89021
* config/i386/sse.md (ssse3_ph<plusminus_mnemonic>wv4hi3):
Changed to define_insn_and_split to support SSE emulation.
---
gcc/config/i386/sse.md | 34 ++++++++++++++++++++++++++--------
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index b1bab15af41..97cbd250dd4 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -15257,13 +15257,13 @@
(set_attr "prefix" "orig,vex")
(set_attr "mode" "TI")])
-(define_insn "ssse3_ph<plusminus_mnemonic>wv4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
+(define_insn_and_split "ssse3_ph<plusminus_mnemonic>wv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
(vec_concat:V4HI
(vec_concat:V2HI
(ssse3_plusminus:HI
(vec_select:HI
- (match_operand:V4HI 1 "register_operand" "0")
+ (match_operand:V4HI 1 "register_operand" "0,0,Yv")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
(ssse3_plusminus:HI
@@ -15272,19 +15272,37 @@
(vec_concat:V2HI
(ssse3_plusminus:HI
(vec_select:HI
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")
+ (match_operand:V4HI 2 "nonimmediate_operand" "ym,x,Yv")
(parallel [(const_int 0)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
(ssse3_plusminus:HI
(vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
(vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
- "TARGET_SSSE3"
- "ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}"
- [(set_attr "type" "sseiadd")
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
+ "@
+ ph<plusminus_mnemonic>w\t{%2, %0|%0, %2}
+ #
+ #"
+ "TARGET_MMX_WITH_SSE && reload_completed"
+ [(const_int 0)]
+{
+ /* Generate SSE version of the operation. */
+ rtx op0 = lowpart_subreg (V8HImode, operands[0],
+ GET_MODE (operands[0]));
+ rtx op1 = lowpart_subreg (V8HImode, operands[1],
+ GET_MODE (operands[1]));
+ rtx op2 = lowpart_subreg (V8HImode, operands[2],
+ GET_MODE (operands[2]));
+ emit_insn (gen_ssse3_ph<plusminus_mnemonic>wv8hi3 (op0, op1, op2));
+ ix86_move_vector_high_sse_to_mmx (op0);
+ DONE;
+}
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "sseiadd")
(set_attr "atom_unit" "complex")
(set_attr "prefix_extra" "1")
(set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
- (set_attr "mode" "DI")])
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "avx2_ph<plusminus_mnemonic>dv8si3"
[(set (match_operand:V8SI 0 "register_operand" "=x")
--
2.20.1
next prev parent reply other threads:[~2019-02-14 12:33 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-14 12:31 [PATCH 00/40] V5: Emulate MMX intrinsics " H.J. Lu
2019-02-14 12:31 ` [PATCH 06/40] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-14 12:31 ` [PATCH 12/40] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-14 12:31 ` [PATCH 08/40] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 " H.J. Lu
2019-02-14 14:04 ` Uros Bizjak
2019-02-14 12:31 ` [PATCH 20/40] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-14 12:31 ` [PATCH 05/40] i386: Emulate MMX mulv4hi3 " H.J. Lu
2019-02-14 12:31 ` [PATCH 07/40] i386: Emulate MMX mmx_pmaddwd " H.J. Lu
2019-02-14 12:31 ` [PATCH 17/40] i386: Emulate MMX mmx_pinsrw " H.J. Lu
2019-02-14 12:31 ` [PATCH 40/40] i386: Also enable SSSE3 __m64 tests in 64-bit mode H.J. Lu
2019-02-14 20:21 ` Uros Bizjak
2019-02-14 20:43 ` Uros Bizjak
2019-02-14 20:56 ` H.J. Lu
2019-02-14 21:57 ` [PATCH, testsuite]: Re-enable 64-bit form in gcc.target/i386/ssse3-*.c on AVX targets Uros Bizjak
2019-02-14 12:31 ` [PATCH 02/40] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-14 12:31 ` [PATCH 31/40] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-14 14:21 ` Uros Bizjak
2019-02-14 12:31 ` [PATCH 16/40] i386: Emulate MMX mmx_pextrw with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 10/40] i386: Emulate MMX mmx_andnot<mode>3 " H.J. Lu
2019-02-14 12:31 ` [PATCH 35/40] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 13/40] i386: Emulate MMX pshufw with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 23/40] i386: Emulate MMX mmx_uavgv4hi3 " H.J. Lu
2019-02-14 12:31 ` [PATCH 03/40] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-14 12:31 ` [PATCH 14/40] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE H.J. Lu
2019-02-14 12:31 ` [PATCH 04/40] i386: Emulate MMX plusminus/sat_plusminus " H.J. Lu
2019-02-14 12:33 ` [PATCH 33/40] i386: Emulate MMX ssse3_palignrdi " H.J. Lu
2019-02-14 12:33 ` [PATCH 26/40] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-14 12:33 ` H.J. Lu [this message]
2019-02-14 12:33 ` [PATCH 22/40] i386: Emulate MMX mmx_uavgv8qi3 with SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 38/40] i386: Enable TM MMX intrinsics with SSE2 H.J. Lu
2019-02-14 12:33 ` [PATCH 15/40] i386: Emulate MMX sse_cvtpi2ps with SSE H.J. Lu
2019-02-14 14:14 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 37/40] i386: Allow MMX intrinsic emulation " H.J. Lu
2019-02-14 20:07 ` Uros Bizjak
2019-02-14 20:50 ` H.J. Lu
2019-02-14 20:54 ` Uros Bizjak
2019-02-14 21:02 ` H.J. Lu
2019-02-14 22:57 ` Uros Bizjak
2019-02-14 23:13 ` H.J. Lu
2019-02-14 23:14 ` H.J. Lu
2019-02-14 23:21 ` Uros Bizjak
2019-02-14 23:24 ` H.J. Lu
2019-02-15 12:04 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 34/40] i386: Emulate MMX abs<mode>2 " H.J. Lu
2019-02-14 12:33 ` [PATCH 25/40] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-14 14:17 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 36/40] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 18/40] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 19/40] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-14 12:33 ` [PATCH 39/40] i386: Add tests for MMX intrinsic emulations " H.J. Lu
2019-02-15 12:21 ` Uros Bizjak
2019-02-14 12:33 ` [PATCH 11/40] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 09/40] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 30/40] i386: Emulate MMX ssse3_pmulhrswv4hi3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 32/40] i386: Emulate MMX ssse3_psign<mode>3 " H.J. Lu
2019-02-14 12:33 ` [PATCH 01/40] i386: Allow MMX register modes in SSE registers H.J. Lu
2019-02-14 12:33 ` [PATCH 21/40] i386: Emulate MMX maskmovq with SSE2 maskmovdqu H.J. Lu
2019-02-14 12:33 ` [PATCH 28/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 with SSE H.J. Lu
2019-02-14 12:33 ` [PATCH 29/40] i386: Emulate MMX ssse3_pmaddubsw " H.J. Lu
2019-02-14 12:33 ` [PATCH 24/40] i386: Emulate MMX mmx_psadbw " H.J. Lu
2019-02-14 18:18 ` [PATCH 41/40] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE Uros Bizjak
-- strict thread matches above, loose matches on Subject: below --
2019-02-11 22:56 [PATCH 00/40] V4: Emulate MMX intrinsics with SSE H.J. Lu
2019-02-11 22:56 ` [PATCH 27/40] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 " H.J. Lu
2019-02-12 11:22 ` Uros Bizjak
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