From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 98813 invoked by alias); 16 Feb 2019 00:34:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 98800 invoked by uid 89); 16 Feb 2019 00:34:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pf1-f195.google.com Received: from mail-pf1-f195.google.com (HELO mail-pf1-f195.google.com) (209.85.210.195) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 16 Feb 2019 00:34:12 +0000 Received: by mail-pf1-f195.google.com with SMTP id c123so5633600pfb.0 for ; Fri, 15 Feb 2019 16:34:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a/ysuuvdoUwnkVvVfVz2t+479KOe5Z680aKMx7v/ZBs=; b=i+yrfg9qSWKZqcHWaUzg9oZyEfqwkAeM4FV1QUHk2YR4pjBs/K4FLUQkQ8HhP7rE5w rd4yicyJ/WkymvStdDGZsoy8yLUZHr2Hcov+JDTNibpJz53vRY82vb96ru5hhqyqyp5b foFzgI9MABFkVk6jDveeuaXsJnRv5csKFXAM1bStkUtNSmY/bgdNgGQX8H4hwhX3YMNf 6u9RLMJlBRoJYsf558eFroF6YA6H6Rbr0iohEun7hnH1aa5hpLRKm8WfKVRFnW++W/Ps 983zndYlUeowMld/RGeVhO6VRDOx7KJR/qBgcr908hccXUxGLZUt48xkuuQH9gPYlL4J c5mA== Return-Path: Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id t6sm7178499pgu.46.2019.02.15.16.34.09 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 15 Feb 2019 16:34:09 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 78554C02CA; Fri, 15 Feb 2019 16:34:08 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 01/42] i386: Allow MMX register modes in SSE registers Date: Sat, 16 Feb 2019 00:34:00 -0000 Message-Id: <20190216003408.23761-2-hjl.tools@gmail.com> In-Reply-To: <20190216003408.23761-1-hjl.tools@gmail.com> References: <20190216003408.23761-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg01255.txt.bz2 In 64-bit mode, SSE2 can be used to emulate MMX instructions without 3DNOW. We can use SSE2 to support MMX register modes. PR target/89021 * config/i386/i386-c.c (ix86_target_macros_internal): Define __MMX_WITH_SSE__ for TARGET_MMX_WITH_SSE. * config/i386/i386.c (ix86_set_reg_reg_cost): Add support for TARGET_MMX_WITH_SSE with VALID_MMX_REG_MODE. (ix86_vector_mode_supported_p): Likewise. * config/i386/i386.h (TARGET_MMX_WITH_SSE): New. --- gcc/config/i386/i386-c.c | 2 ++ gcc/config/i386/i386.c | 5 +++-- gcc/config/i386/i386.h | 2 ++ 3 files changed, 7 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/i386-c.c b/gcc/config/i386/i386-c.c index 5e7e46fcebe..213e1b56c6b 100644 --- a/gcc/config/i386/i386-c.c +++ b/gcc/config/i386/i386-c.c @@ -548,6 +548,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__CLDEMOTE__"); if (isa_flag2 & OPTION_MASK_ISA_PTWRITE) def_or_undef (parse_in, "__PTWRITE__"); + if (TARGET_MMX_WITH_SSE) + def_or_undef (parse_in, "__MMX_WITH_SSE__"); if (TARGET_IAMCU) { def_or_undef (parse_in, "__iamcu"); diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 3e5f52175d2..7d7dd80930e 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -40490,7 +40490,8 @@ ix86_set_reg_reg_cost (machine_mode mode) || (TARGET_AVX && VALID_AVX256_REG_MODE (mode)) || (TARGET_SSE2 && VALID_SSE2_REG_MODE (mode)) || (TARGET_SSE && VALID_SSE_REG_MODE (mode)) - || (TARGET_MMX && VALID_MMX_REG_MODE (mode))) + || ((TARGET_MMX || TARGET_MMX_WITH_SSE) + && VALID_MMX_REG_MODE (mode))) units = GET_MODE_SIZE (mode); } @@ -44316,7 +44317,7 @@ ix86_vector_mode_supported_p (machine_mode mode) return true; if (TARGET_AVX512F && VALID_AVX512F_REG_MODE (mode)) return true; - if (TARGET_MMX && VALID_MMX_REG_MODE (mode)) + if ((TARGET_MMX ||TARGET_MMX_WITH_SSE) && VALID_MMX_REG_MODE (mode)) return true; if (TARGET_3DNOW && VALID_MMX_REG_MODE_3DNOW (mode)) return true; diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 4fd8bc40a34..91b233022c2 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -201,6 +201,8 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see #define TARGET_16BIT TARGET_CODE16 #define TARGET_16BIT_P(x) TARGET_CODE16_P(x) +#define TARGET_MMX_WITH_SSE (TARGET_64BIT && TARGET_SSE2) + #include "config/vxworks-dummy.h" #include "config/i386/i386-opts.h" -- 2.20.1