From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Uros Bizjak <ubizjak@gmail.com>
Subject: [PATCH 21/42] i386: Emulate MMX maskmovq with SSE2 maskmovdqu
Date: Sat, 16 Feb 2019 00:43:00 -0000 [thread overview]
Message-ID: <20190216003408.23761-22-hjl.tools@gmail.com> (raw)
In-Reply-To: <20190216003408.23761-1-hjl.tools@gmail.com>
Emulate MMX maskmovq with SSE2 maskmovdqu for TARGET_MMX_WITH_SSE by
zero-extending source and mask operands to 128 bits. Handle unmapped
bits 64:127 at memory address by adjusting source and mask operands
together with memory address.
PR target/89021
* config/i386/xmmintrin.h: Emulate MMX maskmovq with SSE2
maskmovdqu for __MMX_WITH_SSE__.
---
gcc/config/i386/xmmintrin.h | 61 +++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/gcc/config/i386/xmmintrin.h b/gcc/config/i386/xmmintrin.h
index 58284378514..a915f6c87d7 100644
--- a/gcc/config/i386/xmmintrin.h
+++ b/gcc/config/i386/xmmintrin.h
@@ -1165,7 +1165,68 @@ _m_pshufw (__m64 __A, int const __N)
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
_mm_maskmove_si64 (__m64 __A, __m64 __N, char *__P)
{
+#ifdef __MMX_WITH_SSE__
+ /* Emulate MMX maskmovq with SSE2 maskmovdqu and handle unmapped bits
+ 64:127 at address __P. */
+ typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+ typedef char __v16qi __attribute__ ((__vector_size__ (16)));
+ /* Zero-extend __A and __N to 128 bits. */
+ __v2di __A128 = __extension__ (__v2di) { ((__v1di) __A)[0], 0 };
+ __v2di __N128 = __extension__ (__v2di) { ((__v1di) __N)[0], 0 };
+
+ /* Check the alignment of __P. */
+ __SIZE_TYPE__ offset = ((__SIZE_TYPE__) __P) & 0xf;
+ if (offset)
+ {
+ /* If the misalignment of __P > 8, subtract __P by 8 bytes.
+ Otherwise, subtract __P by the misalignment. */
+ if (offset > 8)
+ offset = 8;
+ __P = (char *) (((__SIZE_TYPE__) __P) - offset);
+
+ /* Shift __A128 and __N128 to the left by the adjustment. */
+ switch (offset)
+ {
+ case 1:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 8);
+ break;
+ case 2:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 2 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 2 * 8);
+ break;
+ case 3:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 3 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 3 * 8);
+ break;
+ case 4:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 4 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 4 * 8);
+ break;
+ case 5:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 5 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 5 * 8);
+ break;
+ case 6:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 6 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 6 * 8);
+ break;
+ case 7:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 7 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 7 * 8);
+ break;
+ case 8:
+ __A128 = __builtin_ia32_pslldqi128 (__A128, 8 * 8);
+ __N128 = __builtin_ia32_pslldqi128 (__N128, 8 * 8);
+ break;
+ default:
+ break;
+ }
+ }
+ __builtin_ia32_maskmovdqu ((__v16qi)__A128, (__v16qi)__N128, __P);
+#else
__builtin_ia32_maskmovq ((__v8qi)__A, (__v8qi)__N, __P);
+#endif
}
extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__))
--
2.20.1
next prev parent reply other threads:[~2019-02-16 0:43 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-16 0:34 [PATCH 00/42] V7: Emulate MMX intrinsics with SSE H.J. Lu
2019-02-16 0:34 ` [PATCH 04/42] i386: Emulate MMX plusminus/sat_plusminus " H.J. Lu
2019-02-16 0:34 ` [PATCH 09/42] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-16 0:34 ` [PATCH 17/42] i386: Emulate MMX mmx_pinsrw " H.J. Lu
2019-02-16 9:08 ` Uros Bizjak
2019-02-16 14:57 ` H.J. Lu
2019-02-16 0:34 ` [PATCH 29/42] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 " H.J. Lu
2019-02-16 0:34 ` [PATCH 15/42] i386: Emulate MMX sse_cvtpi2ps " H.J. Lu
2019-02-16 0:34 ` [PATCH 06/42] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-16 0:34 ` [PATCH 36/42] i386: Correct <ssse3_avx2>_pmulhrsw<mode>3[_mask] H.J. Lu
2019-02-16 9:28 ` Uros Bizjak
2019-02-16 0:34 ` [PATCH 13/42] i386: Emulate MMX pshufw with SSE H.J. Lu
2019-02-16 0:34 ` [PATCH 08/42] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 " H.J. Lu
2019-02-16 0:34 ` [PATCH 23/42] i386: Emulate MMX mmx_uavgv4hi3 " H.J. Lu
2019-02-16 0:34 ` [PATCH 10/42] i386: Emulate MMX mmx_andnot<mode>3 " H.J. Lu
2019-02-16 0:34 ` [PATCH 02/42] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-16 0:34 ` [PATCH 33/42] i386: Emulate MMX ssse3_psign<mode>3 with SSE H.J. Lu
2019-02-16 0:34 ` [PATCH 01/42] i386: Allow MMX register modes in SSE registers H.J. Lu
2019-02-16 0:34 ` [PATCH 14/42] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE H.J. Lu
2019-02-16 0:34 ` [PATCH 11/42] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 " H.J. Lu
2019-02-16 0:34 ` [PATCH 34/42] i386: Emulate MMX ssse3_palignrdi " H.J. Lu
2019-02-16 0:34 ` [PATCH 16/42] i386: Emulate MMX mmx_pextrw " H.J. Lu
2019-02-16 0:34 ` [PATCH 18/42] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin " H.J. Lu
2019-02-16 0:34 ` [PATCH 20/42] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-16 0:34 ` [PATCH 03/42] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-16 0:35 ` [PATCH 05/42] i386: Emulate MMX mulv4hi3 with SSE H.J. Lu
2019-02-16 0:35 ` [PATCH 19/42] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-16 0:35 ` [PATCH 30/42] i386: Emulate MMX ssse3_pmaddubsw " H.J. Lu
2019-02-16 0:35 ` [PATCH 07/42] i386: Emulate MMX mmx_pmaddwd " H.J. Lu
2019-02-16 0:35 ` [PATCH 42/42] i386: Add tests for MMX intrinsic emulations " H.J. Lu
2019-02-16 0:43 ` [PATCH 22/42] i386: Emulate MMX mmx_uavgv8qi3 " H.J. Lu
2019-02-16 0:43 ` [PATCH 25/42] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-16 0:43 ` [PATCH 24/42] i386: Emulate MMX mmx_psadbw with SSE H.J. Lu
2019-02-16 0:43 ` [PATCH 27/42] i386: Make _mm_empty () as NOP when MMX is disabled H.J. Lu
2019-02-16 8:58 ` Uros Bizjak
2019-02-16 14:56 ` H.J. Lu
2019-02-16 19:02 ` Uros Bizjak
2019-02-16 0:43 ` [PATCH 32/42] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-16 0:43 ` [PATCH 38/42] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-16 0:43 ` [PATCH 37/42] Prevent allocation of MMX registers " H.J. Lu
2019-02-16 0:43 ` [PATCH 31/42] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE H.J. Lu
2019-02-16 0:43 ` [PATCH 26/42] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-16 0:43 ` [PATCH 40/42] i386: Allow MMX intrinsic emulation with SSE H.J. Lu
2019-02-16 0:43 ` [PATCH 28/42] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 " H.J. Lu
2019-02-16 0:43 ` [PATCH 12/42] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-16 0:43 ` [PATCH 41/42] i386: Enable TM MMX intrinsics with SSE2 H.J. Lu
2019-02-16 0:43 ` H.J. Lu [this message]
2019-02-16 0:43 ` [PATCH 39/42] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-16 9:50 ` Uros Bizjak
2019-02-16 0:43 ` [PATCH 35/42] i386: Emulate MMX abs<mode>2 with SSE H.J. Lu
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