From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Uros Bizjak <ubizjak@gmail.com>
Subject: [PATCH 18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE
Date: Sat, 16 Feb 2019 22:47:00 -0000 [thread overview]
Message-ID: <20190216224032.4889-19-hjl.tools@gmail.com> (raw)
In-Reply-To: <20190216224032.4889-1-hjl.tools@gmail.com>
Emulate MMX V4HI smaxmin/V8QI umaxmin with SSE. Only SSE register source
operand is allowed.
PR target/89021
* config/i386/mmx.md (mmx_<code>v4hi3): Also check TARGET_MMX
and TARGET_MMX_WITH_SSE.
(mmx_<code>v8qi3): Likewise.
(smaxmin:<code>v4hi3): New.
(umaxmin:<code>v8qi3): Likewise.
(smaxmin:*mmx_<code>v4hi3): Add SSE emulation.
(umaxmin:*mmx_<code>v8qi3): Likewise.
---
gcc/config/i386/mmx.md | 68 +++++++++++++++++++++++++++++-------------
1 file changed, 48 insertions(+), 20 deletions(-)
diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index dea2be1d8e2..edfb8623701 100644
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -923,40 +923,68 @@
(define_expand "mmx_<code>v4hi3"
[(set (match_operand:V4HI 0 "register_operand")
(smaxmin:V4HI
- (match_operand:V4HI 1 "nonimmediate_operand")
- (match_operand:V4HI 2 "nonimmediate_operand")))]
- "TARGET_SSE || TARGET_3DNOW_A"
+ (match_operand:V4HI 1 "register_mmxmem_operand")
+ (match_operand:V4HI 2 "register_mmxmem_operand")))]
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && (TARGET_SSE || TARGET_3DNOW_A)"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
+
+(define_expand "<code>v4hi3"
+ [(set (match_operand:V4HI 0 "register_operand")
+ (smaxmin:V4HI
+ (match_operand:V4HI 1 "register_operand")
+ (match_operand:V4HI 2 "register_operand")))]
+ "TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, V4HImode, operands);")
(define_insn "*mmx_<code>v4hi3"
- [(set (match_operand:V4HI 0 "register_operand" "=y")
+ [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv")
(smaxmin:V4HI
- (match_operand:V4HI 1 "nonimmediate_operand" "%0")
- (match_operand:V4HI 2 "nonimmediate_operand" "ym")))]
- "(TARGET_SSE || TARGET_3DNOW_A)
+ (match_operand:V4HI 1 "register_mmxmem_operand" "%0,0,Yv")
+ (match_operand:V4HI 2 "register_mmxmem_operand" "ym,x,Yv")))]
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && (TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (<CODE>, V4HImode, operands)"
- "p<maxmin_int>w\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
+ "@
+ p<maxmin_int>w\t{%2, %0|%0, %2}
+ p<maxmin_int>w\t{%2, %0|%0, %2}
+ vp<maxmin_int>w\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "mmxadd,sseiadd,sseiadd")
+ (set_attr "mode" "DI,TI,TI")])
(define_expand "mmx_<code>v8qi3"
[(set (match_operand:V8QI 0 "register_operand")
(umaxmin:V8QI
- (match_operand:V8QI 1 "nonimmediate_operand")
- (match_operand:V8QI 2 "nonimmediate_operand")))]
- "TARGET_SSE || TARGET_3DNOW_A"
+ (match_operand:V8QI 1 "register_mmxmem_operand")
+ (match_operand:V8QI 2 "register_mmxmem_operand")))]
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && (TARGET_SSE || TARGET_3DNOW_A)"
+ "ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
+
+(define_expand "<code>v8qi3"
+ [(set (match_operand:V8QI 0 "register_operand")
+ (umaxmin:V8QI
+ (match_operand:V8QI 1 "register_operand")
+ (match_operand:V8QI 2 "register_operand")))]
+ "TARGET_MMX_WITH_SSE"
"ix86_fixup_binary_operands_no_copy (<CODE>, V8QImode, operands);")
(define_insn "*mmx_<code>v8qi3"
- [(set (match_operand:V8QI 0 "register_operand" "=y")
+ [(set (match_operand:V8QI 0 "register_operand" "=y,x,Yv")
(umaxmin:V8QI
- (match_operand:V8QI 1 "nonimmediate_operand" "%0")
- (match_operand:V8QI 2 "nonimmediate_operand" "ym")))]
- "(TARGET_SSE || TARGET_3DNOW_A)
+ (match_operand:V8QI 1 "register_mmxmem_operand" "%0,0,Yv")
+ (match_operand:V8QI 2 "register_mmxmem_operand" "ym,x,Yv")))]
+ "(TARGET_MMX || TARGET_MMX_WITH_SSE)
+ && (TARGET_SSE || TARGET_3DNOW_A)
&& ix86_binary_operator_ok (<CODE>, V8QImode, operands)"
- "p<maxmin_int>b\t{%2, %0|%0, %2}"
- [(set_attr "type" "mmxadd")
- (set_attr "mode" "DI")])
+ "@
+ p<maxmin_int>b\t{%2, %0|%0, %2}
+ p<maxmin_int>b\t{%2, %0|%0, %2}
+ vp<maxmin_int>b\t{%2, %1, %0|%0, %1, %2}"
+ [(set_attr "mmx_isa" "native,x64_noavx,x64_avx")
+ (set_attr "type" "mmxadd,sseiadd,sseiadd")
+ (set_attr "mode" "DI,TI,TI")])
(define_insn "mmx_ashr<mode>3"
[(set (match_operand:MMXMODE24 0 "register_operand" "=y,x,Yv")
--
2.20.1
next prev parent reply other threads:[~2019-02-16 22:47 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-16 22:41 [PATCH 00/41] V8: Emulate MMX intrinsics " H.J. Lu
2019-02-16 22:40 ` [PATCH 03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-16 22:40 ` [PATCH 08/41] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 01/41] i386: Allow MMX register modes in SSE registers H.J. Lu
2019-02-16 22:40 ` [PATCH 11/41] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 12/41] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-16 22:40 ` [PATCH 06/41] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-16 22:40 ` [PATCH 04/41] i386: Emulate MMX plusminus/sat_plusminus " H.J. Lu
2019-02-16 22:40 ` [PATCH 15/41] i386: Emulate MMX sse_cvtpi2ps " H.J. Lu
2019-02-16 22:40 ` [PATCH 09/41] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 16/41] i386: Emulate MMX mmx_pextrw " H.J. Lu
2019-02-16 22:41 ` [PATCH 14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi " H.J. Lu
2019-02-16 22:41 ` [PATCH 31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-16 22:41 ` [PATCH 17/41] i386: Emulate MMX mmx_pinsrw with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 05/41] i386: Emulate MMX mulv4hi3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 25/41] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-16 22:41 ` [PATCH 10/41] i386: Emulate MMX mmx_andnot<mode>3 with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 13/41] i386: Emulate MMX pshufw " H.J. Lu
2019-02-16 22:41 ` [PATCH 33/41] i386: Emulate MMX ssse3_psign<mode>3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 27/41] i386: Make _mm_empty () as NOP for TARGET_MMX_WITH_SSE H.J. Lu
2019-02-17 9:45 ` Uros Bizjak
2019-02-17 13:38 ` H.J. Lu
2019-02-16 22:41 ` [PATCH 28/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 07/41] i386: Emulate MMX mmx_pmaddwd " H.J. Lu
2019-02-16 22:41 ` [PATCH 40/41] i386: Enable TM MMX intrinsics with SSE2 H.J. Lu
2019-02-16 22:42 ` [PATCH 41/41] i386: Add tests for MMX intrinsic emulations with SSE H.J. Lu
2019-02-16 22:46 ` [PATCH 20/41] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-16 22:46 ` [PATCH 19/41] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-16 22:47 ` [PATCH 38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-17 16:25 ` Uros Bizjak
2019-02-17 17:03 ` H.J. Lu
2019-02-17 17:09 ` Uros Bizjak
2019-02-17 17:15 ` H.J. Lu
2019-02-17 17:22 ` Uros Bizjak
2019-02-17 17:28 ` H.J. Lu
2019-02-17 18:50 ` Uros Bizjak
2019-02-17 20:49 ` H.J. Lu
2019-02-16 22:47 ` [PATCH 36/41] Prevent allocation of MMX registers " H.J. Lu
2019-02-18 12:56 ` Uros Bizjak
2019-02-16 22:47 ` [PATCH 23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE H.J. Lu
2019-02-16 22:47 ` H.J. Lu [this message]
2019-02-16 22:47 ` [PATCH 30/41] i386: Emulate MMX ssse3_pmaddubsw " H.J. Lu
2019-02-16 22:47 ` [PATCH 37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 39/41] i386: Allow MMX intrinsic emulation with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 24/41] i386: Emulate MMX mmx_psadbw " H.J. Lu
2019-02-16 22:47 ` [PATCH 22/41] i386: Emulate MMX mmx_uavgv8qi3 " H.J. Lu
2019-02-16 22:47 ` [PATCH 35/41] i386: Emulate MMX abs<mode>2 " H.J. Lu
2019-02-16 22:47 ` [PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-16 22:47 ` [PATCH 32/41] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-16 22:47 ` [PATCH 21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu H.J. Lu
2019-02-16 22:47 ` [PATCH 34/41] i386: Emulate MMX ssse3_palignrdi with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 29/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 " H.J. Lu
2019-02-17 10:33 ` [PATCH 00/41] V8: Emulate MMX intrinsics " Uros Bizjak
2019-02-17 13:42 ` H.J. Lu
2019-02-17 15:54 ` Uros Bizjak
2019-02-17 15:57 ` Uros Bizjak
2019-02-17 17:10 ` H.J. Lu
2019-02-17 17:27 ` Uros Bizjak
2019-02-17 17:37 ` H.J. Lu
2019-02-17 18:49 ` Uros Bizjak
2019-02-17 20:47 ` H.J. Lu
2019-02-18 14:22 ` H.J. Lu
2019-02-18 14:37 ` Uros Bizjak
2019-02-18 14:48 ` H.J. Lu
2019-02-18 18:39 [PATCH 00/41] V9: " H.J. Lu
2019-02-18 18:44 ` [PATCH 18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin " H.J. Lu
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