From: "H.J. Lu" <hjl.tools@gmail.com>
To: gcc-patches@gcc.gnu.org
Cc: Uros Bizjak <ubizjak@gmail.com>
Subject: [PATCH 40/41] i386: Enable TM MMX intrinsics with SSE2
Date: Sat, 16 Feb 2019 22:41:00 -0000 [thread overview]
Message-ID: <20190216224032.4889-41-hjl.tools@gmail.com> (raw)
In-Reply-To: <20190216224032.4889-1-hjl.tools@gmail.com>
This pach enables TM MMX intrinsics with SSE2 when MMX is disabled.
PR target/89021
* config/i386/i386.c (bdesc_tm): Enable MMX intrinsics with
SSE2.
---
gcc/config/i386/i386.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 073a2534d1f..319a98f824a 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31065,13 +31065,13 @@ static const struct builtin_description bdesc_##kind[] = \
we're lazy. Add casts to make them fit. */
static const struct builtin_description bdesc_tm[] =
{
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_WM64", (enum ix86_builtins) BUILT_IN_TM_STORE_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_WaWM64", (enum ix86_builtins) BUILT_IN_TM_STORE_WAW_M64, UNKNOWN, VOID_FTYPE_PV2SI_V2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RaRM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAR_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM64", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M64, UNKNOWN, V2SI_FTYPE_PCV2SI },
{ OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WM128", (enum ix86_builtins) BUILT_IN_TM_STORE_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
{ OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_WaRM128", (enum ix86_builtins) BUILT_IN_TM_STORE_WAR_M128, UNKNOWN, VOID_FTYPE_PV4SF_V4SF },
@@ -31089,7 +31089,7 @@ static const struct builtin_description bdesc_tm[] =
{ OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RaWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RAW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
{ OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_RfWM256", (enum ix86_builtins) BUILT_IN_TM_LOAD_RFW_M256, UNKNOWN, V8SF_FTYPE_PCV8SF },
- { OPTION_MASK_ISA_MMX, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
+ { OPTION_MASK_ISA_MMX | OPTION_MASK_ISA_SSE2, 0, CODE_FOR_nothing, "__builtin__ITM_LM64", (enum ix86_builtins) BUILT_IN_TM_LOG_M64, UNKNOWN, VOID_FTYPE_PCVOID },
{ OPTION_MASK_ISA_SSE, 0, CODE_FOR_nothing, "__builtin__ITM_LM128", (enum ix86_builtins) BUILT_IN_TM_LOG_M128, UNKNOWN, VOID_FTYPE_PCVOID },
{ OPTION_MASK_ISA_AVX, 0, CODE_FOR_nothing, "__builtin__ITM_LM256", (enum ix86_builtins) BUILT_IN_TM_LOG_M256, UNKNOWN, VOID_FTYPE_PCVOID },
};
--
2.20.1
next prev parent reply other threads:[~2019-02-16 22:41 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-16 22:41 [PATCH 00/41] V8: Emulate MMX intrinsics with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 11/41] i386: Emulate MMX mmx_eq/mmx_gt<mode>3 " H.J. Lu
2019-02-16 22:40 ` [PATCH 09/41] i386: Emulate MMX <any_logic><mode>3 " H.J. Lu
2019-02-16 22:40 ` [PATCH 12/41] i386: Emulate MMX vec_dupv2si " H.J. Lu
2019-02-16 22:40 ` [PATCH 06/41] i386: Emulate MMX smulv4hi3_highpart " H.J. Lu
2019-02-16 22:40 ` [PATCH 01/41] i386: Allow MMX register modes in SSE registers H.J. Lu
2019-02-16 22:40 ` [PATCH 04/41] i386: Emulate MMX plusminus/sat_plusminus with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 03/41] i386: Emulate MMX punpcklXX/punpckhXX with SSE punpcklXX H.J. Lu
2019-02-16 22:40 ` [PATCH 08/41] i386: Emulate MMX ashr<mode>3/<shift_insn><mode>3 with SSE H.J. Lu
2019-02-16 22:40 ` [PATCH 15/41] i386: Emulate MMX sse_cvtpi2ps " H.J. Lu
2019-02-16 22:41 ` [PATCH 16/41] i386: Emulate MMX mmx_pextrw " H.J. Lu
2019-02-16 22:41 ` [PATCH 25/41] i386: Emulate MMX movntq with SSE2 movntidi H.J. Lu
2019-02-16 22:41 ` [PATCH 31/41] i386: Emulate MMX ssse3_pmulhrswv4hi3 with SSE H.J. Lu
2019-02-16 22:41 ` H.J. Lu [this message]
2019-02-16 22:41 ` [PATCH 07/41] i386: Emulate MMX mmx_pmaddwd " H.J. Lu
2019-02-16 22:41 ` [PATCH 05/41] i386: Emulate MMX mulv4hi3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 28/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>wv4hi3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 10/41] i386: Emulate MMX mmx_andnot<mode>3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 33/41] i386: Emulate MMX ssse3_psign<mode>3 " H.J. Lu
2019-02-16 22:41 ` [PATCH 02/41] i386: Emulate MMX packsswb/packssdw/packuswb with SSE2 H.J. Lu
2019-02-16 22:41 ` [PATCH 13/41] i386: Emulate MMX pshufw with SSE H.J. Lu
2019-02-16 22:41 ` [PATCH 17/41] i386: Emulate MMX mmx_pinsrw " H.J. Lu
2019-02-16 22:41 ` [PATCH 27/41] i386: Make _mm_empty () as NOP for TARGET_MMX_WITH_SSE H.J. Lu
2019-02-17 9:45 ` Uros Bizjak
2019-02-17 13:38 ` H.J. Lu
2019-02-16 22:41 ` [PATCH 14/41] i386: Emulate MMX sse_cvtps2pi/sse_cvttps2pi with SSE H.J. Lu
2019-02-16 22:42 ` [PATCH 41/41] i386: Add tests for MMX intrinsic emulations " H.J. Lu
2019-02-16 22:46 ` [PATCH 19/41] i386: Emulate MMX mmx_pmovmskb " H.J. Lu
2019-02-16 22:46 ` [PATCH 20/41] i386: Emulate MMX mmx_umulv4hi3_highpart " H.J. Lu
2019-02-16 22:47 ` [PATCH 36/41] Prevent allocation of MMX registers with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-18 12:56 ` Uros Bizjak
2019-02-16 22:47 ` [PATCH 30/41] i386: Emulate MMX ssse3_pmaddubsw with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 29/41] i386: Emulate MMX ssse3_ph<plusminus_mnemonic>dv2si3 " H.J. Lu
2019-02-16 22:47 ` [PATCH 38/41] i386: Allow MMX vector expanders with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-17 16:25 ` Uros Bizjak
2019-02-17 17:03 ` H.J. Lu
2019-02-17 17:09 ` Uros Bizjak
2019-02-17 17:15 ` H.J. Lu
2019-02-17 17:22 ` Uros Bizjak
2019-02-17 17:28 ` H.J. Lu
2019-02-17 18:50 ` Uros Bizjak
2019-02-17 20:49 ` H.J. Lu
2019-02-16 22:47 ` [PATCH 26/41] i386: Emulate MMX umulv1siv1di3 with SSE2 H.J. Lu
2019-02-16 22:47 ` [PATCH 23/41] i386: Emulate MMX mmx_uavgv4hi3 with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 22/41] i386: Emulate MMX mmx_uavgv8qi3 " H.J. Lu
2019-02-16 22:47 ` [PATCH 18/41] i386: Emulate MMX V4HI smaxmin/V8QI umaxmin " H.J. Lu
2019-02-16 22:47 ` [PATCH 37/41] i386: Allow MMXMODE moves with TARGET_MMX_WITH_SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 32/41] i386: Emulate MMX pshufb with SSE version H.J. Lu
2019-02-16 22:47 ` [PATCH 39/41] i386: Allow MMX intrinsic emulation with SSE H.J. Lu
2019-02-16 22:47 ` [PATCH 35/41] i386: Emulate MMX abs<mode>2 " H.J. Lu
2019-02-16 22:47 ` [PATCH 24/41] i386: Emulate MMX mmx_psadbw " H.J. Lu
2019-02-16 22:47 ` [PATCH 21/41] i386: Emulate MMX maskmovq with SSE2 maskmovdqu H.J. Lu
2019-02-16 22:47 ` [PATCH 34/41] i386: Emulate MMX ssse3_palignrdi with SSE H.J. Lu
2019-02-17 10:33 ` [PATCH 00/41] V8: Emulate MMX intrinsics " Uros Bizjak
2019-02-17 13:42 ` H.J. Lu
2019-02-17 15:54 ` Uros Bizjak
2019-02-17 15:57 ` Uros Bizjak
2019-02-17 17:10 ` H.J. Lu
2019-02-17 17:27 ` Uros Bizjak
2019-02-17 17:37 ` H.J. Lu
2019-02-17 18:49 ` Uros Bizjak
2019-02-17 20:47 ` H.J. Lu
2019-02-18 14:22 ` H.J. Lu
2019-02-18 14:37 ` Uros Bizjak
2019-02-18 14:48 ` H.J. Lu
2019-02-18 18:39 [PATCH 00/41] V9: " H.J. Lu
2019-02-18 18:44 ` [PATCH 40/41] i386: Enable TM MMX intrinsics with SSE2 H.J. Lu
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