From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 91344 invoked by alias); 18 Feb 2019 18:44:21 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 91199 invoked by uid 89); 18 Feb 2019 18:44:20 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-pg1-f177.google.com Received: from mail-pg1-f177.google.com (HELO mail-pg1-f177.google.com) (209.85.215.177) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 18 Feb 2019 18:44:18 +0000 Received: by mail-pg1-f177.google.com with SMTP id u9so5355829pgo.7 for ; Mon, 18 Feb 2019 10:44:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jvCSJ9tUgswwad2fnfV0YdoNB/2R7Kxm20CwT9zhQf8=; b=OFUzETYk54Mkf5daBoo5hzANI4NDLZxjuACH9sHl0qtVGjAhSfdFplbxxRea+gsfWH 4u7MZwoZMF5kZXPA+ud2ggSLTNrvZzyPs0kX6zc9BXjTefIogHj93jsN3ifvryiG0OYh Eg62SBOEa/QVIA++xA6UuROUCchLhROpjdqTTicyygAr756kTEugzHs1rXfeRsJnCqGX XCHe6zgsz+ure6/sW0jRwR5iOwenyoEcIlLslmUk8ZkoFsb5KqZZQSd3YLEF/63OWu2N GGMQUHC5Ytdjckufl5ciL3CtEswNfIaIehr6Zefg1XZF3aSOlQc++Pfk+8gfoI8BDjnz S8+w== Return-Path: Received: from gnu-cfl-2.localdomain (c-73-93-86-59.hsd1.ca.comcast.net. [73.93.86.59]) by smtp.gmail.com with ESMTPSA id z15sm6178220pgc.25.2019.02.18.10.44.12 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 18 Feb 2019 10:44:13 -0800 (PST) Received: from gnu-cfl-2.hsd1.ca.comcast.net (localhost [IPv6:::1]) by gnu-cfl-2.localdomain (Postfix) with ESMTP id 3D103C0350; Mon, 18 Feb 2019 10:36:58 -0800 (PST) From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: [PATCH 17/41] i386: Emulate MMX mmx_pinsrw with SSE Date: Mon, 18 Feb 2019 18:44:00 -0000 Message-Id: <20190218183657.16296-18-hjl.tools@gmail.com> In-Reply-To: <20190218183657.16296-1-hjl.tools@gmail.com> References: <20190218183657.16296-1-hjl.tools@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2019-02/txt/msg01501.txt.bz2 Emulate MMX mmx_pinsrw with SSE. Only SSE register destination operand is allowed. PR target/89021 * config/i386/mmx.md (mmx_pinsrw): Also check TARGET_MMX and TARGET_MMX_WITH_SSE. (*mmx_pinsrw): Add SSE emulation. --- gcc/config/i386/mmx.md | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 28725f48282..dea2be1d8e2 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1282,32 +1282,45 @@ (match_operand:SI 2 "nonimmediate_operand")) (match_operand:V4HI 1 "register_operand") (match_operand:SI 3 "const_0_to_3_operand")))] - "TARGET_SSE || TARGET_3DNOW_A" + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" { operands[2] = gen_lowpart (HImode, operands[2]); operands[3] = GEN_INT (1 << INTVAL (operands[3])); }) (define_insn "*mmx_pinsrw" - [(set (match_operand:V4HI 0 "register_operand" "=y") + [(set (match_operand:V4HI 0 "register_operand" "=y,x,Yv") (vec_merge:V4HI (vec_duplicate:V4HI - (match_operand:HI 2 "nonimmediate_operand" "rm")) - (match_operand:V4HI 1 "register_operand" "0") + (match_operand:HI 2 "nonimmediate_operand" "rm,rm,rm")) + (match_operand:V4HI 1 "register_operand" "0,0,Yv") (match_operand:SI 3 "const_int_operand")))] - "(TARGET_SSE || TARGET_3DNOW_A) + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A) && ((unsigned) exact_log2 (INTVAL (operands[3])) < GET_MODE_NUNITS (V4HImode))" { operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3]))); - if (MEM_P (operands[2])) - return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; + if (TARGET_MMX_WITH_SSE && TARGET_AVX) + { + if (MEM_P (operands[2])) + return "vpinsrw\t{%3, %2, %1, %0|%0, %1, %2, %3}"; + else + return "vpinsrw\t{%3, %k2, %1, %0|%0, %1, %k2, %3}"; + } else - return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; + { + if (MEM_P (operands[2])) + return "pinsrw\t{%3, %2, %0|%0, %2, %3}"; + else + return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}"; + } } - [(set_attr "type" "mmxcvt") + [(set_attr "mmx_isa" "native,x64_noavx,x64_avx") + (set_attr "type" "mmxcvt,sselog,sselog") (set_attr "length_immediate" "1") - (set_attr "mode" "DI")]) + (set_attr "mode" "DI,TI,TI")]) (define_insn "mmx_pextrw" [(set (match_operand:SI 0 "register_operand" "=r,r") -- 2.20.1