* [PATCH] x86: (Reapply) Move AESNI generation to Skylake and Goldmont
@ 2019-02-21 23:34 Thiago Macieira
2019-02-21 23:35 ` H.J. Lu
0 siblings, 1 reply; 3+ messages in thread
From: Thiago Macieira @ 2019-02-21 23:34 UTC (permalink / raw)
To: gcc-patches; +Cc: hjl.tools, Martin Liška, Uros Bizjak
This is a repeat of commit r263989, which commit r264052 accidentally
reverted.
Original commit message:
The instruction set first appeared with Westmere, but not all processors
in that and the next few generations have the instructions. According to
Wikipedia[1], the first generation in which all SKUs have AES
instructions are Skylake and Goldmont. I can't find any Skylake,
Kabylake, Kabylake-R or Cannon Lake currently listed at
https://ark.intel.com that says "Intel® AES New Instructions" "No".
[1] https://en.wikipedia.org/wiki/AES_instruction_set
2018-08-30 Thiago Macieira <thiago.macieira@intel.com>
* config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
(PTA_SKYLAKE): Add PTA_AES.
(PTA_GOLDMONT): Likewise.
---
gcc/config/i386/i386.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 4fd8bc40a34..2cb16d9fbf6 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2360,7 +2360,7 @@ const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
| PTA_POPCNT;
-const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
| PTA_XSAVEOPT;
const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
@@ -2369,7 +2369,7 @@ const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
| PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
| PTA_RDSEED;
-const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
@@ -2387,7 +2387,7 @@ const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
| PTA_AVX512F | PTA_AVX512CD;
const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE
| PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
| PTA_FSGSBASE;
const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
--
2.20.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: (Reapply) Move AESNI generation to Skylake and Goldmont
2019-02-21 23:34 [PATCH] x86: (Reapply) Move AESNI generation to Skylake and Goldmont Thiago Macieira
@ 2019-02-21 23:35 ` H.J. Lu
2019-02-22 18:47 ` H.J. Lu
0 siblings, 1 reply; 3+ messages in thread
From: H.J. Lu @ 2019-02-21 23:35 UTC (permalink / raw)
To: Thiago Macieira; +Cc: GCC Patches, Martin Liška, Uros Bizjak
[-- Attachment #1: Type: text/plain, Size: 1017 bytes --]
On Thu, Feb 21, 2019 at 3:10 PM Thiago Macieira
<thiago.macieira@intel.com> wrote:
>
> This is a repeat of commit r263989, which commit r264052 accidentally
> reverted.
>
> Original commit message:
>
> The instruction set first appeared with Westmere, but not all processors
> in that and the next few generations have the instructions. According to
> Wikipedia[1], the first generation in which all SKUs have AES
> instructions are Skylake and Goldmont. I can't find any Skylake,
> Kabylake, Kabylake-R or Cannon Lake currently listed at
> https://ark.intel.com that says "Intel® AES New Instructions" "No".
>
> [1] https://en.wikipedia.org/wiki/AES_instruction_set
>
> 2018-08-30 Thiago Macieira <thiago.macieira@intel.com>
>
> * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
> (PTA_SKYLAKE): Add PTA_AES.
> (PTA_GOLDMONT): Likewise.
I opened:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89444
and I will check it in for Thiago tomorrow.
--
H.J.
[-- Attachment #2: 0001-x86-Reapply-Move-AESNI-generation-to-Skylake-and-Gol.patch --]
[-- Type: text/x-patch, Size: 2480 bytes --]
From afd1b863fcc0d29c5ce6fa68db7680286f63e6b2 Mon Sep 17 00:00:00 2001
From: Thiago Macieira <thiago.macieira@intel.com>
Date: Thu, 21 Feb 2019 15:10:18 -0800
Subject: [PATCH] x86: (Reapply) Move AESNI generation to Skylake and Goldmont
This is a repeat of commit r263989, which commit r264052 accidentally
reverted.
2019-02-21 Thiago Macieira <thiago.macieira@intel.com>
PR target/89444
* config/i386/i386.h (PTA_WESTMERE): Remove PTA_AES.
(PTA_SKYLAKE): Add PTA_AES.
(PTA_GOLDMONT): Likewise.
---
gcc/config/i386/i386.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 4fd8bc40a34..2cb16d9fbf6 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -2360,7 +2360,7 @@ const wide_int_bitmask PTA_CORE2 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
| PTA_SSE3 | PTA_SSSE3 | PTA_CX16 | PTA_FXSR;
const wide_int_bitmask PTA_NEHALEM = PTA_CORE2 | PTA_SSE4_1 | PTA_SSE4_2
| PTA_POPCNT;
-const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_AES | PTA_PCLMUL;
+const wide_int_bitmask PTA_WESTMERE = PTA_NEHALEM | PTA_PCLMUL;
const wide_int_bitmask PTA_SANDYBRIDGE = PTA_WESTMERE | PTA_AVX | PTA_XSAVE
| PTA_XSAVEOPT;
const wide_int_bitmask PTA_IVYBRIDGE = PTA_SANDYBRIDGE | PTA_FSGSBASE
@@ -2369,7 +2369,7 @@ const wide_int_bitmask PTA_HASWELL = PTA_IVYBRIDGE | PTA_AVX2 | PTA_BMI
| PTA_BMI2 | PTA_LZCNT | PTA_FMA | PTA_MOVBE | PTA_HLE;
const wide_int_bitmask PTA_BROADWELL = PTA_HASWELL | PTA_ADX | PTA_PRFCHW
| PTA_RDSEED;
-const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_CLFLUSHOPT
+const wide_int_bitmask PTA_SKYLAKE = PTA_BROADWELL | PTA_AES | PTA_CLFLUSHOPT
| PTA_XSAVEC | PTA_XSAVES | PTA_SGX;
const wide_int_bitmask PTA_SKYLAKE_AVX512 = PTA_SKYLAKE | PTA_AVX512F
| PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU
@@ -2387,7 +2387,7 @@ const wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF | PTA_AVX512ER
| PTA_AVX512F | PTA_AVX512CD;
const wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
const wide_int_bitmask PTA_SILVERMONT = PTA_WESTMERE | PTA_MOVBE | PTA_RDRND;
-const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_SHA | PTA_XSAVE
+const wide_int_bitmask PTA_GOLDMONT = PTA_SILVERMONT | PTA_AES | PTA_SHA | PTA_XSAVE
| PTA_RDSEED | PTA_XSAVEC | PTA_XSAVES | PTA_CLFLUSHOPT | PTA_XSAVEOPT
| PTA_FSGSBASE;
const wide_int_bitmask PTA_GOLDMONT_PLUS = PTA_GOLDMONT | PTA_RDPID
--
2.20.1
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] x86: (Reapply) Move AESNI generation to Skylake and Goldmont
2019-02-21 23:35 ` H.J. Lu
@ 2019-02-22 18:47 ` H.J. Lu
0 siblings, 0 replies; 3+ messages in thread
From: H.J. Lu @ 2019-02-22 18:47 UTC (permalink / raw)
To: Thiago Macieira; +Cc: GCC Patches, Martin Liška, Uros Bizjak
On Thu, Feb 21, 2019 at 3:25 PM H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Feb 21, 2019 at 3:10 PM Thiago Macieira
> <thiago.macieira@intel.com> wrote:
> >
> > This is a repeat of commit r263989, which commit r264052 accidentally
> > reverted.
> >
> > Original commit message:
> >
> > The instruction set first appeared with Westmere, but not all processors
> > in that and the next few generations have the instructions. According to
> > Wikipedia[1], the first generation in which all SKUs have AES
> > instructions are Skylake and Goldmont. I can't find any Skylake,
> > Kabylake, Kabylake-R or Cannon Lake currently listed at
> > https://ark.intel.com that says "Intel® AES New Instructions" "No".
> >
> > [1] https://en.wikipedia.org/wiki/AES_instruction_set
> >
> > 2018-08-30 Thiago Macieira <thiago.macieira@intel.com>
> >
> > * config/i386/i386.c (PTA_WESTMERE): Remove PTA_AES.
> > (PTA_SKYLAKE): Add PTA_AES.
> > (PTA_GOLDMONT): Likewise.
>
> I opened:
>
> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=89444
>
> and I will check it in for Thiago tomorrow.
>
Now, r263989 has been re-applied. I got
FAIL: g++.target/i386/mv16.C -std=gnu++14 execution test
FAIL: g++.target/i386/mv16.C -std=gnu++17 execution test
FAIL: g++.target/i386/mv16.C -std=gnu++98 execution test
On Westmere. Shouldn't this
case PROCESSOR_NEHALEM:
if (new_target->x_ix86_isa_flags & OPTION_MASK_ISA_AES)
{
arg_str = "westmere";
priority = P_AES;
}
else
be removed?
--
H.J.
^ permalink raw reply [flat|nested] 3+ messages in thread
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2019-02-21 23:35 ` H.J. Lu
2019-02-22 18:47 ` H.J. Lu
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