* Use predicates for RTL objects
@ 2019-08-02 17:38 Arvind Sankar
2019-08-02 17:50 ` Segher Boessenkool
0 siblings, 1 reply; 33+ messages in thread
From: Arvind Sankar @ 2019-08-02 17:38 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 3995 bytes --]
Hi, I have taken a crack at the beginner GCC project mentioned at
https://gcc.gnu.org/projects/beginner.html to replace uses of GET_CODE
to check rtx_code with the appropriate predicate macros.
Would someone be able to review/actually apply the changes if they look
acceptable?
Most of the change is auto-generated using the enclosed script [1]. In
addition I have added 3 new predicates to rtl.h: CONST_VECTOR_P,
CONST_STRING_P and CONST_P. After the autogenned patch there is a small
cleanup for a couple instances where the existing comparison is split
across source lines and wasn't picked up by the script.
I have tested by building stage1 and comparing the object files vs
trunk. The only changes are in constant strings in build/genpreds.o and
build/genattrtab.o. The configuration was
configure --enable-checking=none --disable-bootstrap
RTL checking had to be disabled as otherwise there are some line-number
differences in code in rtl.h.
I have left out the architecture-specific files in common/config and
config for now. If the approach looks reasonable I can go through arch
by arch and test by building cross-compilers?
[1] Script used to edit files (run in gcc subdir):
#! /bin/sh
codes="CONST_INT|CONST_WIDE_INT|CONST_FIXED|CONST_DOUBLE|CONST_VECTOR|CONST_STRING|CONST|REG|SUBREG|MEM|LABEL_REF|SYMBOL_REF|DEBUG_INSN"
find . -path ./config -prune -o -path ./common/config -prune -o -path ./testsuite -prune -o -type f -regex '.*\.\(c\|cc\|h\)' \! -path ./rtl.h -print | xargs \
perl -pi -e 's/\bGET_CODE[ ]?(\((?:(?>[^()]+)|(?1))*\)) (?|(!)=|==) ('$codes')\b/$2$3_P $1/g'
Remaining instances of GET_CODE usage with counts (in the generic code):
224 SET
207 PLUS
194 PARALLEL
135 CLOBBER
86 USE
66 ZERO_EXTRACT
62 AND
60 STRICT_LOW_PART
59 VALUE
54 CLOBBER_HIGH
48 SEQUENCE
43 CONCAT
41 NOT
41 ASM_OPERANDS
40 ZERO_EXTEND
40 IOR
39 MULT
39 LSHIFTRT
37 ASHIFT
33 NEG
31 code
28 ASM_INPUT
28 ASHIFTRT
27 SCRATCH
27 MINUS
26 COMPARE
25 SIGN_EXTEND
25 EQ_ATTR
24 PC
24 EXPR_LIST
23 COND_EXEC
22 IF_THEN_ELSE
21 XOR
20 UNSPEC
19 CALL
16 GET_CODE
15 INSN_LIST
14 NE
12 LO_SUM
12 CC0
11 TRUNCATE
11 TRAP_IF
11 PRE_MODIFY
11 PRE_DEC
11 MATCH_OPERAND
11 HIGH
11 EQ_ATTR_ALT
10 VEC_CONCAT
10 PRE_INC
10 MATCH_SCRATCH
10 EQ
8 VAR_LOCATION
8 POST_DEC
8 MATCH_DUP
8 FLOAT_EXTEND
8 ABS
7 VEC_DUPLICATE
7 UNSPEC_VOLATILE
7 POST_MODIFY
7 GT
7 ENTRY_VALUE
7 DEBUG_IMPLICIT_PTR
7 COND
7 BSWAP
6 VEC_SELECT
6 ROTATE
6 DEFINE_INSN_AND_REWRITE
6 ATTR
6 ADDR_DIFF_VEC
5 VEC_MERGE
5 POST_INC
5 INT_LIST
5 FLOAT
5 CONCATN
4 LT
4 GE
4 DEFINE_PEEPHOLE2
4 DEFINE_INSN
4 DEFINE_EXPAND
4 DEBUG_EXPR
4 CLZ
3 UNSIGNED_FLOAT
3 MATCH_OPERATOR
3 MATCH_OP_DUP
3 GTU
3 FFS
3 DEFINE_INSN_AND_SPLIT
3 ADDR_VEC
2 SMIN
2 SIGN_EXTRACT
2 ROTATERT
2 reversed_comparison_code
2 RETURN
2 NOTE
2 MATCH_PAR_DUP
2 MATCH_PARALLEL
2 MATCH_CODE
2 LTU
2 GEU
2 FLOAT_TRUNCATE
2 DEFINE_SPLIT
2 DEFINE_ENUM_ATTR
2 DEBUG_PARAMETER_REF
2 ADDRESS
1 UNSIGNED_FIX
1 UMIN
1 UDIV
1 STACK_PUSH_CODE
1 STACK_POP_CODE
1 SIMPLE_RETURN
1 SET_ATTR
1 POPCOUNT
1 outer_code
1 ncode
1 loc_code
1 LABEL
1 invcode
1 FIX
1 EH_RETURN
1 DIV
1 DEFINE_SPECIAL_PREDICATE
1 DEFINE_SPECIAL_MEMORY_CONSTRAINT
1 DEFINE_PEEPHOLE
1 DEFINE_MEMORY_CONSTRAINT
1 DEFINE_ATTR
1 DEFINE_ASM_ATTRIBUTES
1 DEFINE_ADDRESS_CONSTRAINT
1 comp
1 cand
[-- Attachment #2: rtl.h --]
[-- Type: text/x-patch, Size: 1297 bytes --]
From d0c0f39c90f384aba3d21780ef4751033429cb75 Mon Sep 17 00:00:00 2001
From: Arvind Sankar <nivedita@alum.mit.edu>
Date: Thu, 1 Aug 2019 13:31:49 -0400
Subject: [PATCH 1/3] Define rtx_code predicates for CONST_VECTOR, CONST_STRING
and CONST
---
gcc/rtl.h | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 039ab05f951..731a1477b0b 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -823,10 +823,19 @@ struct GTY(()) rtvec_def {
(CONST_INT_P (X) || CONST_DOUBLE_AS_INT_P (X))
#endif
-/* Predicate yielding true iff X is an rtx for a double-int. */
+/* Predicate yielding true iff X is an rtx for a floating point constant. */
#define CONST_DOUBLE_AS_FLOAT_P(X) \
(GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
+/* Predicate yielding nonzero iff X is an rtx for a constant vector. */
+#define CONST_VECTOR_P(X) (GET_CODE (X) == CONST_VECTOR)
+
+/* Predicate yielding nonzero iff X is an rtx for a constant string */
+#define CONST_STRING_P(X) (GET_CODE (X) == CONST_STRING)
+
+/* Predicate yielding nonzero iff X is an rtx for a constant expression. */
+#define CONST_P(X) (GET_CODE (X) == CONST)
+
/* Predicate yielding nonzero iff X is a label insn. */
#define LABEL_P(X) (GET_CODE (X) == CODE_LABEL)
--
2.21.0
[-- Attachment #3: Auto-generated patch --]
[-- Type: text/x-patch, Size: 246531 bytes --]
From 349e79c84ed6fff52744128abe9a278758a26146 Mon Sep 17 00:00:00 2001
From: Arvind Sankar <nivedita@alum.mit.edu>
Date: Thu, 1 Aug 2019 13:32:53 -0400
Subject: [PATCH 2/3] Use rtx_code predicates instead of GET_CODE
---
gcc/alias.c | 18 ++---
gcc/asan.c | 2 +-
gcc/bb-reorder.c | 2 +-
gcc/bt-load.c | 2 +-
gcc/builtins.c | 2 +-
gcc/caller-save.c | 4 +-
gcc/calls.c | 10 +--
gcc/cfgbuild.c | 4 +-
gcc/cfgcleanup.c | 2 +-
gcc/cfgexpand.c | 8 +-
gcc/cfgrtl.c | 4 +-
gcc/combine.c | 166 ++++++++++++++++++++--------------------
gcc/cprop.c | 6 +-
gcc/cse.c | 94 +++++++++++------------
gcc/cselib.c | 8 +-
gcc/dbxout.c | 24 +++---
gcc/defaults.h | 2 +-
gcc/df-core.c | 4 +-
gcc/df-problems.c | 6 +-
gcc/df-scan.c | 18 ++---
gcc/df.h | 4 +-
gcc/dojump.c | 2 +-
gcc/dse.c | 8 +-
gcc/dwarf2asm.c | 6 +-
gcc/dwarf2out.c | 62 +++++++--------
gcc/emit-rtl.c | 16 ++--
gcc/explow.c | 20 ++---
gcc/expmed.c | 24 +++---
gcc/expr.c | 48 ++++++------
gcc/final.c | 22 +++---
gcc/function.c | 2 +-
gcc/fwprop.c | 18 ++---
gcc/gcse-common.c | 2 +-
gcc/gcse.c | 8 +-
gcc/genattr.c | 2 +-
gcc/genattrtab.c | 18 ++---
gcc/genpreds.c | 10 +--
gcc/genrecog.c | 2 +-
gcc/gensupport.c | 8 +-
gcc/ifcvt.c | 20 ++---
gcc/internal-fn.c | 6 +-
gcc/ira-build.c | 2 +-
gcc/ira-conflicts.c | 4 +-
gcc/ira-costs.c | 10 +--
gcc/ira-emit.c | 2 +-
gcc/ira-lives.c | 18 ++---
gcc/ira.c | 12 +--
gcc/jump.c | 36 ++++-----
gcc/loop-doloop.c | 2 +-
gcc/loop-invariant.c | 6 +-
gcc/loop-iv.c | 20 ++---
gcc/loop-unroll.c | 2 +-
gcc/lower-subreg.c | 18 ++---
gcc/lra-constraints.c | 56 +++++++-------
gcc/lra-eliminations.c | 12 +--
gcc/lra.c | 6 +-
gcc/mode-switching.c | 14 ++--
gcc/modulo-sched.c | 2 +-
gcc/optabs.c | 6 +-
gcc/postreload-gcse.c | 4 +-
gcc/postreload.c | 20 ++---
gcc/print-rtl.c | 4 +-
gcc/read-rtl-function.c | 6 +-
gcc/read-rtl.c | 2 +-
gcc/recog.c | 12 +--
gcc/ree.c | 12 +--
gcc/reg-stack.c | 14 ++--
gcc/regcprop.c | 6 +-
gcc/reginfo.c | 26 +++----
gcc/regrename.c | 10 +--
gcc/reload.c | 76 +++++++++---------
gcc/reload1.c | 66 ++++++++--------
gcc/reorg.c | 16 ++--
gcc/resource.c | 6 +-
gcc/rtl.c | 6 +-
gcc/rtlanal.c | 56 +++++++-------
gcc/rtlhooks.c | 2 +-
gcc/sched-deps.c | 12 +--
gcc/sched-rgn.c | 4 +-
gcc/sel-sched.c | 2 +-
gcc/simplify-rtx.c | 104 ++++++++++++-------------
gcc/symtab.c | 4 +-
gcc/tree-ssa-address.c | 10 +--
gcc/valtrack.c | 6 +-
gcc/var-tracking.c | 68 ++++++++--------
gcc/varasm.c | 26 +++----
gcc/xcoffout.h | 2 +-
87 files changed, 752 insertions(+), 752 deletions(-)
diff --git a/gcc/alias.c b/gcc/alias.c
index 2755df72907..e41bc133746 100644
--- a/gcc/alias.c
+++ b/gcc/alias.c
@@ -2222,7 +2222,7 @@ base_alias_check (rtx x, rtx x_base, rtx y, rtx y_base,
return 1;
/* Differing symbols not accessed via AND never alias. */
- if (GET_CODE (x_base) == SYMBOL_REF && GET_CODE (y_base) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x_base) && SYMBOL_REF_P (y_base))
return compare_base_symbol_refs (x_base, y_base) != 0;
if (GET_CODE (x_base) != ADDRESS && GET_CODE (y_base) != ADDRESS)
@@ -2444,7 +2444,7 @@ memrefs_conflict_p (poly_int64 xsize, rtx x, poly_int64 ysize, rtx y,
else
y = addr_side_effect_eval (y, maybe_lt (ysize, 0) ? -ysize : ysize, 0);
- if (GET_CODE (x) == SYMBOL_REF && GET_CODE (y) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_P (y))
{
int cmp = compare_base_symbol_refs (x,y);
@@ -2617,16 +2617,16 @@ memrefs_conflict_p (poly_int64 xsize, rtx x, poly_int64 ysize, rtx y,
return offset_overlap_p (c, xsize, ysize);
}
- if (GET_CODE (x) == CONST)
+ if (CONST_P (x))
{
- if (GET_CODE (y) == CONST)
+ if (CONST_P (y))
return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
ysize, canon_rtx (XEXP (y, 0)), c);
else
return memrefs_conflict_p (xsize, canon_rtx (XEXP (x, 0)),
ysize, y, c);
}
- if (GET_CODE (y) == CONST)
+ if (CONST_P (y))
return memrefs_conflict_p (xsize, x, ysize,
canon_rtx (XEXP (y, 0)), c);
@@ -2954,8 +2954,8 @@ true_dependence_1 (const_rtx mem, machine_mode mem_mode, rtx mem_addr,
return 1;
base = find_base_term (x_addr);
- if (base && (GET_CODE (base) == LABEL_REF
- || (GET_CODE (base) == SYMBOL_REF
+ if (base && (LABEL_REF_P (base)
+ || (SYMBOL_REF_P (base)
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
@@ -3063,8 +3063,8 @@ write_dependence_p (const_rtx mem,
base = find_base_term (true_mem_addr);
if (! writep
&& base
- && (GET_CODE (base) == LABEL_REF
- || (GET_CODE (base) == SYMBOL_REF
+ && (LABEL_REF_P (base)
+ || (SYMBOL_REF_P (base)
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
diff --git a/gcc/asan.c b/gcc/asan.c
index a731bd490b4..9976f709a88 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1805,7 +1805,7 @@ asan_protect_global (tree decl, bool ignore_decl_rtl_set_p)
{
rtl = DECL_RTL (decl);
- if (!MEM_P (rtl) || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF)
+ if (!MEM_P (rtl) || !SYMBOL_REF_P (XEXP (rtl, 0)))
return false;
symbol = XEXP (rtl, 0);
diff --git a/gcc/bb-reorder.c b/gcc/bb-reorder.c
index 0ac39140c6c..43623e00d76 100644
--- a/gcc/bb-reorder.c
+++ b/gcc/bb-reorder.c
@@ -2167,7 +2167,7 @@ fix_crossing_conditional_branches (void)
new_label = gen_label_rtx ();
emit_label (new_label);
- gcc_assert (GET_CODE (old_label) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (old_label));
old_jump_target = old_jump_insn->jump_target ();
new_jump = as_a <rtx_jump_insn *>
(emit_jump_insn (targetm.gen_jump (old_jump_target)));
diff --git a/gcc/bt-load.c b/gcc/bt-load.c
index f68879ca49a..11eee41e9d5 100644
--- a/gcc/bt-load.c
+++ b/gcc/bt-load.c
@@ -226,7 +226,7 @@ insn_sets_btr_p (const rtx_insn *insn, int check_const, int *regno)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = XEXP (dest, 0);
if (REG_P (dest)
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 695a9d191af..c01c9d4c789 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -1796,7 +1796,7 @@ expand_builtin_apply (rtx function, rtx arguments, rtx argsize)
/* Ensure address is valid. SYMBOL_REF is already valid, so no need,
and we don't want to load it into a register as an optimization,
because prepare_call_address already did it if it should be done. */
- if (GET_CODE (function) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (function))
function = memory_address (FUNCTION_MODE, function);
/* Generate the actual call instruction and save the return value. */
diff --git a/gcc/caller-save.c b/gcc/caller-save.c
index 7c1de894976..e816d080b82 100644
--- a/gcc/caller-save.c
+++ b/gcc/caller-save.c
@@ -955,7 +955,7 @@ mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data)
int regno, endregno, i;
HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
rtx inner = SUBREG_REG (reg);
if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
@@ -990,7 +990,7 @@ add_stored_regs (rtx reg, const_rtx setter, void *data)
if (GET_CODE (setter) == CLOBBER)
return;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& REG_P (SUBREG_REG (reg))
&& REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/calls.c b/gcc/calls.c
index 7507b698e27..7be7d3b7211 100644
--- a/gcc/calls.c
+++ b/gcc/calls.c
@@ -217,7 +217,7 @@ prepare_call_address (tree fndecl_or_type, rtx funexp, rtx static_chain_value,
{
/* Make a valid memory address and copy constants through pseudo-regs,
but not for a constant address if -fno-function-cse. */
- if (GET_CODE (funexp) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (funexp))
{
/* If it's an indirect call by descriptor, generate code to perform
runtime identification of the pointer and load the descriptor. */
@@ -393,7 +393,7 @@ emit_call_1 (rtx funexp, tree fntree ATTRIBUTE_UNUSED, tree fndecl ATTRIBUTE_UNU
/* Ensure address is valid. SYMBOL_REF is already valid, so no need,
and we don't want to load it into a register as an optimization,
because prepare_call_address already did it if it should be done. */
- if (GET_CODE (funexp) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (funexp))
funexp = memory_address (FUNCTION_MODE, funexp);
funmem = gen_rtx_MEM (FUNCTION_MODE, funexp);
@@ -1004,7 +1004,7 @@ precompute_register_parameters (int num_actuals, struct arg_data *args,
loading the parameters registers. */
else if ((! (REG_P (args[i].value)
- || (GET_CODE (args[i].value) == SUBREG
+ || (SUBREG_P (args[i].value)
&& REG_P (SUBREG_REG (args[i].value)))))
&& args[i].mode != BLKmode
&& (set_src_cost (args[i].value, args[i].mode,
@@ -4286,7 +4286,7 @@ expand_call (tree exp, rtx target, int ignore)
{
datum = XEXP (DECL_RTL (fndecl), 0);
gcc_assert (datum != NULL_RTX
- && GET_CODE (datum) == SYMBOL_REF);
+ && SYMBOL_REF_P (datum));
}
last = last_call_insn ();
add_reg_note (last, REG_CALL_DECL, datum);
@@ -5333,7 +5333,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value,
if (flag_ipa_ra)
{
rtx datum = orgfun;
- gcc_assert (GET_CODE (datum) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (datum));
rtx_call_insn *last = last_call_insn ();
add_reg_note (last, REG_CALL_DECL, datum);
}
diff --git a/gcc/cfgbuild.c b/gcc/cfgbuild.c
index 934325c6538..8ac13b753dd 100644
--- a/gcc/cfgbuild.c
+++ b/gcc/cfgbuild.c
@@ -273,7 +273,7 @@ make_edges (basic_block min, basic_block max, int update_p)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2)))
make_label_edge (edge_cache, bb,
label_ref_label (XEXP (SET_SRC (tmp), 2)), 0);
}
@@ -414,7 +414,7 @@ purge_dead_tablejump_edges (basic_block bb, rtx_jump_table_data *table)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2)))
mark_tablejump_edge (label_ref_label (XEXP (SET_SRC (tmp), 2)));
for (ei = ei_start (bb->succs); (e = ei_safe_edge (ei)); )
diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c
index b9307631e1c..e6d3b00364f 100644
--- a/gcc/cfgcleanup.c
+++ b/gcc/cfgcleanup.c
@@ -1209,7 +1209,7 @@ old_insns_match_p (int mode ATTRIBUTE_UNUSED, rtx_insn *i1, rtx_insn *i2)
if (flag_sanitize & SANITIZE_ADDRESS)
{
rtx call = get_call_rtx_from (i1);
- if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (call && SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol)
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 33af991573f..8f573140d62 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -3786,7 +3786,7 @@ expand_gimple_stmt_1 (gimple *stmt)
bool promoted = false;
target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
promoted = true;
ops.code = gimple_assign_rhs_code (assign_stmt);
@@ -4411,7 +4411,7 @@ expand_debug_expr (tree exp)
op0 = make_decl_rtl_for_debug (exp);
if (!MEM_P (op0)
- || GET_CODE (XEXP (op0, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op0, 0))
|| SYMBOL_REF_DECL (XEXP (op0, 0)) != exp)
return NULL;
}
@@ -5481,8 +5481,8 @@ expand_debug_locations (void)
gcc_assert (mode == GET_MODE (val)
|| (GET_MODE (val) == VOIDmode
&& (CONST_SCALAR_INT_P (val)
- || GET_CODE (val) == CONST_FIXED
- || GET_CODE (val) == LABEL_REF)));
+ || CONST_FIXED_P (val)
+ || LABEL_REF_P (val))));
}
INSN_VAR_LOCATION_LOC (insn) = val;
diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c
index bdef400537d..41c7eb8d217 100644
--- a/gcc/cfgrtl.c
+++ b/gcc/cfgrtl.c
@@ -1217,7 +1217,7 @@ patch_jump_insn (rtx_insn *insn, rtx_insn *old_label, basic_block new_bb)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2))
&& label_ref_label (XEXP (SET_SRC (tmp), 2)) == old_label)
{
XEXP (SET_SRC (tmp), 2) = gen_rtx_LABEL_REF (Pmode,
@@ -1238,7 +1238,7 @@ patch_jump_insn (rtx_insn *insn, rtx_insn *old_label, basic_block new_bb)
for (i = 0; i < n; ++i)
{
rtx old_ref = ASM_OPERANDS_LABEL (tmp, i);
- gcc_assert (GET_CODE (old_ref) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (old_ref));
if (XEXP (old_ref, 0) == old_label)
{
ASM_OPERANDS_LABEL (tmp, i)
diff --git a/gcc/combine.c b/gcc/combine.c
index f7b1ebc8cc0..38bcf60c62d 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -582,7 +582,7 @@ find_single_use_1 (rtx dest, rtx *loc)
if (GET_CODE (SET_DEST (x)) != CC0
&& GET_CODE (SET_DEST (x)) != PC
&& !REG_P (SET_DEST (x))
- && ! (GET_CODE (SET_DEST (x)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& !read_modify_subreg_p (SET_DEST (x))))
break;
@@ -738,7 +738,7 @@ do_SUBST (rtx *into, rtx newval)
when do_SUBST is called to replace the operand thereof, so we
perform this test on oldval instead, checking whether an
invalid replacement took place before we got here. */
- gcc_assert (!(GET_CODE (oldval) == SUBREG
+ gcc_assert (!(SUBREG_P (oldval)
&& CONST_INT_P (SUBREG_REG (oldval))));
gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
&& CONST_INT_P (XEXP (oldval, 0))));
@@ -2222,7 +2222,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
rtx subdest;
while (GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT)
inner_dest = XEXP (inner_dest, 0);
@@ -2265,7 +2265,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
STACK_POINTER_REGNUM, since these are always considered to be
live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
subdest = dest;
- if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
+ if (SUBREG_P (subdest) && !partial_subreg_p (subdest))
subdest = SUBREG_REG (subdest);
if (pi3dest_killed
&& REG_P (subdest)
@@ -2352,9 +2352,9 @@ cant_combine_insn_p (rtx_insn *insn)
return 0;
src = SET_SRC (set);
dest = SET_DEST (set);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
src = SUBREG_REG (src);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (src) && REG_P (dest)
&& ((HARD_REGISTER_P (src)
@@ -2476,7 +2476,7 @@ adjust_for_new_dest (rtx_insn *insn)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
gcc_assert (REG_P (reg));
@@ -2530,7 +2530,7 @@ reg_subword_p (rtx x, rtx reg)
|| GET_CODE (x) == ZERO_EXTRACT)
x = XEXP (x, 0);
- return GET_CODE (x) == SUBREG
+ return SUBREG_P (x)
&& SUBREG_REG (x) == reg
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
}
@@ -2779,13 +2779,13 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if ((set0 = single_set (i0))
/* Ensure the source of SET0 is a MEM, possibly buried inside
an extension. */
- && (GET_CODE (SET_SRC (set0)) == MEM
+ && (MEM_P (SET_SRC (set0))
|| ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
|| GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
- && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
+ && MEM_P (XEXP (SET_SRC (set0), 0))))
&& (set3 = single_set (i3))
/* Ensure the destination of SET3 is a MEM. */
- && GET_CODE (SET_DEST (set3)) == MEM
+ && MEM_P (SET_DEST (set3))
/* Would it be better to extract the base address for the MEM
in SET3 and look for that? I don't have cases where it matters
but I could envision such cases. */
@@ -3625,7 +3625,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (((REG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
- || (GET_CODE (SET_DEST (set1)) == SUBREG
+ || (SUBREG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set1)))
@@ -3636,14 +3636,14 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (((REG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
- || (GET_CODE (SET_DEST (set0)) == SUBREG
+ || (SUBREG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED,
SUBREG_REG (SET_DEST (set0)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set0)))
{
rtx dest = SET_DEST (set1);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!reg_used_between_p (dest, i2, i3))
{
@@ -3800,12 +3800,12 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
|| GET_CODE (new_i3_dest) == STRICT_LOW_PART
- || GET_CODE (new_i3_dest) == SUBREG)
+ || SUBREG_P (new_i3_dest))
new_i3_dest = XEXP (new_i3_dest, 0);
while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
|| GET_CODE (new_i2_dest) == STRICT_LOW_PART
- || GET_CODE (new_i2_dest) == SUBREG)
+ || SUBREG_P (new_i2_dest))
new_i2_dest = XEXP (new_i2_dest, 0);
if (REG_P (new_i3_dest)
@@ -4037,7 +4037,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
HOST_BITS_PER_INT)
&& (reg_stat[REGNO (temp_expr)].nonzero_bits
!= GET_MODE_MASK (word_mode))))
- && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
+ && ! (SUBREG_P (SET_DEST (XVECEXP (newpat, 0, 1)))
&& (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
(REG_P (temp_expr)
&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
@@ -4112,7 +4112,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (!modified_between_p (SET_SRC (set1), i2, i3)
&& !(REG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
- && !(GET_CODE (SET_DEST (set1)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set1))))
&& !modified_between_p (SET_DEST (set1), i2, i3)
@@ -4128,7 +4128,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (!modified_between_p (SET_SRC (set0), i2, i3)
&& !(REG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
- && !(GET_CODE (SET_DEST (set0)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set0))))
&& !modified_between_p (SET_DEST (set0), i2, i3)
@@ -4970,8 +4970,8 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
case MEM:
/* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
using LO_SUM and HIGH. */
- if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
- || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
+ if (HAVE_lo_sum && (CONST_P (XEXP (x, 0))
+ || SYMBOL_REF_P (XEXP (x, 0))))
{
machine_mode address_mode = get_address_mode (x);
@@ -5045,7 +5045,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 0)))))
{
@@ -5062,7 +5062,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 1)))))
{
@@ -5082,7 +5082,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
This will occur on machines that just support REG + CONST
and have a constant moved through some previous computation. */
if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
}
@@ -5093,7 +5093,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
MEM_ADDR_SPACE (x))
&& ! OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
break;
@@ -5108,7 +5108,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& GET_CODE (SET_SRC (x)) != COMPARE
&& GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
&& !OBJECT_P (SET_SRC (x))
- && ! (GET_CODE (SET_SRC (x)) == SUBREG
+ && ! (SUBREG_P (SET_SRC (x))
&& OBJECT_P (SUBREG_REG (SET_SRC (x)))))
return &SET_SRC (x);
@@ -5313,7 +5313,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (BINARY_P (SET_SRC (x))
&& CONSTANT_P (XEXP (SET_SRC (x), 1))
&& (OBJECT_P (XEXP (SET_SRC (x), 0))
- || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
+ || (SUBREG_P (XEXP (SET_SRC (x), 0))
&& OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
return &XEXP (SET_SRC (x), 1);
@@ -5361,7 +5361,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
constant. It may be better to try splitting (plus (mult B -C) A)
instead if this isn't a multiply by a power of two. */
if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
- && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 1), 1))
&& !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
{
machine_mode mode = GET_MODE (x);
@@ -5382,7 +5382,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (!set_src
&& (GET_CODE (XEXP (x, 0)) == MULT
|| (GET_CODE (XEXP (x, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return loc;
default:
@@ -5626,7 +5626,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
tieable and it is valid if X is a SET that copies
FROM to CC0. */
- if (GET_CODE (to) == SUBREG
+ if (SUBREG_P (to)
&& !targetm.modes_tieable_p (GET_MODE (to),
GET_MODE (SUBREG_REG (to)))
&& ! (code == SUBREG
@@ -5676,7 +5676,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
return new_rtx;
- if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
+ if (SUBREG_P (x) && CONST_SCALAR_INT_P (new_rtx))
{
machine_mode mode = GET_MODE (x);
@@ -5830,14 +5830,14 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
if ((BINARY_P (x)
&& ((!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
|| (!OBJECT_P (XEXP (x, 1))
- && ! (GET_CODE (XEXP (x, 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 1))
&& OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
|| (UNARY_P (x)
&& (!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
{
rtx cond, true_rtx, false_rtx;
@@ -6049,7 +6049,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
complex if it was just a register. */
if (!REG_P (temp)
- && ! (GET_CODE (temp) == SUBREG
+ && ! (SUBREG_P (temp)
&& REG_P (SUBREG_REG (temp)))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
@@ -6103,7 +6103,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
/* (const (const X)) can become (const X). Do it this way rather than
returning the inner CONST since CONST can be shared with a
REG_EQUAL note. */
- if (GET_CODE (XEXP (x, 0)) == CONST)
+ if (CONST_P (XEXP (x, 0)))
SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
break;
@@ -6151,7 +6151,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
"a = (b & 8) == 0;" */
if (XEXP (x, 1) == constm1_rtx
&& !REG_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& REG_P (SUBREG_REG (XEXP (x, 0))))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& nonzero_bits (XEXP (x, 0), int_mode) == 1)
@@ -6587,7 +6587,7 @@ simplify_if_then_else (rtx x)
&& !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
|| true_rtx == const0_rtx
|| (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
- || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
+ || (SUBREG_P (true_rtx) && OBJECT_P (SUBREG_REG (true_rtx))
&& !OBJECT_P (false_rtx))
|| reg_mentioned_p (true_rtx, false_rtx)
|| rtx_equal_p (false_rtx, XEXP (cond, 0))))
@@ -6712,7 +6712,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6729,7 +6729,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6750,7 +6750,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
@@ -6767,7 +6767,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
@@ -7051,7 +7051,7 @@ simplify_set (rtx x)
be undefined. On machine where it is defined, this transformation is safe
as long as M1 and M2 have the same number of words. */
- if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
+ if (SUBREG_P (src) && subreg_lowpart_p (src)
&& !OBJECT_P (SUBREG_REG (src))
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (src)),
@@ -7063,7 +7063,7 @@ simplify_set (rtx x)
GET_MODE (SUBREG_REG (src)),
GET_MODE (src)))
&& (REG_P (dest)
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest)))))
{
SUBST (SET_DEST (x),
@@ -7387,7 +7387,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& HWI_COMPUTABLE_MODE_P (mode)
@@ -7407,7 +7407,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
@@ -7482,7 +7482,7 @@ expand_field_assignment (const_rtx x)
while (1)
{
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
- && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
+ && SUBREG_P (XEXP (SET_DEST (x), 0)))
{
rtx x0 = XEXP (SET_DEST (x), 0);
if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
@@ -7524,7 +7524,7 @@ expand_field_assignment (const_rtx x)
/* If the destination is a subreg that overwrites the whole of the inner
register, we can move the subreg to the source. */
- else if (GET_CODE (SET_DEST (x)) == SUBREG
+ else if (SUBREG_P (SET_DEST (x))
/* We need SUBREGs to compute nonzero_bits properly. */
&& nonzero_sign_valid
&& !read_modify_subreg_p (SET_DEST (x)))
@@ -7538,7 +7538,7 @@ expand_field_assignment (const_rtx x)
else
break;
- while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
+ while (SUBREG_P (inner) && subreg_lowpart_p (inner))
inner = SUBREG_REG (inner);
/* Don't attempt bitwise arithmetic on non scalar integer modes. */
@@ -7631,7 +7631,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (pos_rtx && CONST_INT_P (pos_rtx))
pos = INTVAL (pos_rtx), pos_rtx = 0;
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& subreg_lowpart_p (inner)
&& (paradoxical_subreg_p (inner)
/* If trying or potentionally trying to extract
@@ -7764,7 +7764,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (in_dest)
return (MEM_P (new_rtx) ? new_rtx
- : (GET_CODE (new_rtx) != SUBREG
+ : (!SUBREG_P (new_rtx)
? gen_rtx_CLOBBER (tmode, const0_rtx)
: gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
@@ -8189,7 +8189,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
}
/* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG
+ else if (SUBREG_P (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0))
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
&inner_mode)
@@ -8294,7 +8294,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
the constant (limited to the smaller mode) has only zero bits where
the sub expression has known zero bits, this can be expressed as
a zero_extend. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG)
+ else if (SUBREG_P (XEXP (x, 0)))
{
rtx sub;
@@ -8365,7 +8365,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
seem worth the effort; the case checked for occurs on Alpha. */
if (!OBJECT_P (lhs)
- && ! (GET_CODE (lhs) == SUBREG
+ && ! (SUBREG_P (lhs)
&& (OBJECT_P (SUBREG_REG (lhs))))
&& CONST_INT_P (rhs)
&& INTVAL (rhs) >= 0
@@ -8410,7 +8410,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
to the recursive make_compound_operation call. */
if (subreg_code == COMPARE
&& (!subreg_lowpart_p (x)
- || GET_CODE (inner) == SUBREG
+ || SUBREG_P (inner)
/* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
is (const_int 0), rather than
(subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
@@ -8440,7 +8440,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* If we have something other than a SUBREG, we might have
done an expansion, so rerun ourselves. */
- if (GET_CODE (newer) != SUBREG)
+ if (!SUBREG_P (newer))
newer = make_compound_operation (newer, in_code);
/* force_to_mode can expand compounds. If it just re-expanded
@@ -8450,7 +8450,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* Likewise if it re-expanded the compound only partially.
This happens for SUBREG of ZERO_EXTRACT if they extract
the same number of bits. */
- || (GET_CODE (newer) == SUBREG
+ || (SUBREG_P (newer)
&& (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
|| GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
&& GET_CODE (inner) == AND
@@ -8777,7 +8777,7 @@ force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
/* We can ignore the effect of a SUBREG if it narrows the mode or
if the constant masks to zero all the bits the mode doesn't have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& (partial_subreg_p (x)
|| (mask
@@ -9711,13 +9711,13 @@ rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
/* Check for a paradoxical SUBREG of a MEM compared with the MEM.
Note that all SUBREGs of MEM are paradoxical; otherwise they
would have been rewritten. */
- if (MEM_P (x) && GET_CODE (y) == SUBREG
+ if (MEM_P (x) && SUBREG_P (y)
&& MEM_P (SUBREG_REG (y))
&& rtx_equal_p (SUBREG_REG (y),
gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
return 1;
- if (MEM_P (y) && GET_CODE (x) == SUBREG
+ if (MEM_P (y) && SUBREG_P (x)
&& MEM_P (SUBREG_REG (x))
&& rtx_equal_p (SUBREG_REG (x),
gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
@@ -9770,7 +9770,7 @@ make_field_assignment (rtx x)
return x;
}
- if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
+ if (GET_CODE (src) == AND && SUBREG_P (XEXP (src, 0))
&& subreg_lowpart_p (XEXP (src, 0))
&& partial_subreg_p (XEXP (src, 0))
&& GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
@@ -9842,7 +9842,7 @@ make_field_assignment (rtx x)
narrowing SUBREG, which we can just strip for the purposes of
identifying the constant-field assignment. */
scalar_int_mode src_mode = mode;
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& subreg_lowpart_p (src)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
src = SUBREG_REG (src);
@@ -11622,7 +11622,7 @@ change_zero_ext (rtx pat)
}
}
else if (GET_CODE (x) == ZERO_EXTEND
- && GET_CODE (XEXP (x, 0)) == SUBREG
+ && SUBREG_P (XEXP (x, 0))
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
&& !paradoxical_subreg_p (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0)))
@@ -11781,7 +11781,7 @@ gen_lowpart_for_combine (machine_mode omode, rtx x)
/* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
won't know what to do. So we will strip off the SUBREG here and
process normally. */
- if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
{
x = SUBREG_REG (x);
@@ -12076,8 +12076,8 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
&& GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
&& GET_CODE (XEXP (op0, 0)) == ASHIFT
&& GET_CODE (XEXP (op1, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
- && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (op0, 0), 0))
+ && SUBREG_P (XEXP (XEXP (op1, 0), 0))
&& is_a <scalar_int_mode> (GET_MODE (op0), &mode)
&& (is_a <scalar_int_mode>
(GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
@@ -12151,7 +12151,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
int changed = 0;
if (paradoxical_subreg_p (inner_op0)
- && GET_CODE (inner_op1) == SUBREG
+ && SUBREG_P (inner_op1)
&& HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
&& (GET_MODE (SUBREG_REG (inner_op0))
== GET_MODE (SUBREG_REG (inner_op1)))
@@ -12729,7 +12729,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
fits in both M1 and M2 and the SUBREG is either paradoxical
or represents the low part, permute the SUBREG and the AND
and try again. */
- if (GET_CODE (XEXP (op0, 0)) == SUBREG
+ if (SUBREG_P (XEXP (op0, 0))
&& CONST_INT_P (XEXP (op0, 1)))
{
unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
@@ -13008,7 +13008,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
op0 = make_compound_operation (op0, op0_mco_code);
op1 = make_compound_operation (op1, SET);
- if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
+ if (SUBREG_P (op0) && subreg_lowpart_p (op0)
&& is_int_mode (GET_MODE (op0), &mode)
&& is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
&& (code == NE || code == EQ))
@@ -13376,7 +13376,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
{
rtx_insn *record_dead_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!record_dead_insn)
@@ -13397,7 +13397,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
else if (GET_CODE (setter) == SET
- && GET_CODE (SET_DEST (setter)) == SUBREG
+ && SUBREG_P (SET_DEST (setter))
&& SUBREG_REG (SET_DEST (setter)) == dest
&& known_le (GET_MODE_PRECISION (GET_MODE (dest)),
BITS_PER_WORD)
@@ -13577,7 +13577,7 @@ record_truncated_value (rtx x)
machine_mode truncated_mode;
reg_stat_type *rsp;
- if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && REG_P (SUBREG_REG (x)))
{
machine_mode original_mode = GET_MODE (SUBREG_REG (x));
truncated_mode = GET_MODE (x);
@@ -13629,7 +13629,7 @@ record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
static void
check_promoted_subreg (rtx_insn *insn, rtx x)
{
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& REG_P (SUBREG_REG (x)))
record_promoted_value (insn, x);
@@ -13775,7 +13775,7 @@ get_last_value (const_rtx x)
/* If this is a non-paradoxical SUBREG, get the value of its operand and
then convert it to the desired mode. If this is a paradoxical SUBREG,
we cannot predict what values the "extra" bits might have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& !paradoxical_subreg_p (x)
&& (value = get_last_value (SUBREG_REG (x))) != 0)
@@ -13982,7 +13982,7 @@ mark_used_regs_combine (rtx x)
the address. */
rtx testreg = SET_DEST (x);
- while (GET_CODE (testreg) == SUBREG
+ while (SUBREG_P (testreg)
|| GET_CODE (testreg) == ZERO_EXTRACT
|| GET_CODE (testreg) == STRICT_LOW_PART)
testreg = XEXP (testreg, 0);
@@ -14162,7 +14162,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
if (GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& !read_modify_subreg_p (dest)))
{
move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
@@ -14171,7 +14171,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
/* If this is some other SUBREG, we know it replaces the entire
value, so use that as the destination. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
/* If this is a MEM, adjust deaths of anything used in the address.
@@ -14225,7 +14225,7 @@ reg_bitfield_target_p (rtx x, rtx body)
else
return 0;
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
target = SUBREG_REG (target);
if (!REG_P (target))
@@ -14483,14 +14483,14 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
/* ??? Ignore the without-reg_equal-note problem for now. */
if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
|| ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
- && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (tem_note, 0))
&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
place = i3;
if (i2
&& (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
|| ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
- && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (tem_note, 0))
&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
{
if (place)
@@ -14624,7 +14624,7 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
if (set != 0)
for (inner_dest = SET_DEST (set);
(GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT);
inner_dest = XEXP (inner_dest, 0))
;
@@ -14892,7 +14892,7 @@ distribute_links (struct insn_link *links)
reg = SET_DEST (set);
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (!REG_P (reg))
@@ -14911,7 +14911,7 @@ distribute_links (struct insn_link *links)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (reg == pc_rtx)
diff --git a/gcc/cprop.c b/gcc/cprop.c
index 65c0130cc07..eeb5b161882 100644
--- a/gcc/cprop.c
+++ b/gcc/cprop.c
@@ -250,7 +250,7 @@ insert_set_in_table (rtx dest, rtx src, rtx_insn *insn,
static bool
cprop_constant_p (const_rtx x)
{
- return CONSTANT_P (x) && (GET_CODE (x) != CONST || shared_const_p (x));
+ return CONSTANT_P (x) && (!CONST_P (x) || shared_const_p (x));
}
/* Determine whether the rtx X should be treated as a register that can
@@ -741,7 +741,7 @@ try_replace_reg (rtx from, rtx to, rtx_insn *insn)
|| CONSTANT_P (SET_SRC (set))
|| (note != 0
&& REG_NOTE_KIND (note) == REG_EQUAL
- && (GET_CODE (XEXP (note, 0)) == CONST
+ && (CONST_P (XEXP (note, 0))
|| CONSTANT_P (XEXP (note, 0)))))
check_rtx_costs = false;
@@ -1621,7 +1621,7 @@ bypass_block (basic_block bb, rtx_insn *setcc, rtx_insn *jump)
edest = FALLTHRU_EDGE (bb);
dest = edest->insns.r ? NULL : edest->dest;
}
- else if (GET_CODE (new_rtx) == LABEL_REF)
+ else if (LABEL_REF_P (new_rtx))
{
dest = BLOCK_FOR_INSN (XEXP (new_rtx, 0));
/* Don't bypass edges containing instructions. */
diff --git a/gcc/cse.c b/gcc/cse.c
index 35840a6d5ca..f5da30df68e 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -722,7 +722,7 @@ static int
notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno)
{
scalar_int_mode int_mode, inner_mode;
- return ((GET_CODE (x) == SUBREG
+ return ((SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& is_int_mode (mode, &int_mode)
&& is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode)
@@ -1171,7 +1171,7 @@ insert_regs (rtx x, struct table_elt *classp, int modified)
not be accessible because its hash code will have changed. So assign
a quantity number now. */
- else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))
+ else if (SUBREG_P (x) && REG_P (SUBREG_REG (x))
&& ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x))))
{
insert_regs (SUBREG_REG (x), NULL, 0);
@@ -1289,7 +1289,7 @@ find_reg_offset_for_const (struct table_elt *anchor_elt, HOST_WIDE_INT offs,
if (REG_P (elt->exp)
|| (GET_CODE (elt->exp) == PLUS
&& REG_P (XEXP (elt->exp, 0))
- && GET_CODE (XEXP (elt->exp, 1)) == CONST_INT))
+ && CONST_INT_P (XEXP (elt->exp, 1))))
{
rtx x;
@@ -1679,7 +1679,7 @@ insert_with_costs (rtx x, struct table_elt *classp, unsigned int hash,
/* If this is a constant with symbolic value,
and it has a term with an explicit integer value,
link it up with related expressions. */
- if (GET_CODE (x) == CONST)
+ if (CONST_P (x))
{
rtx subexp = get_related_value (x);
unsigned subhash;
@@ -1828,7 +1828,7 @@ check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr)
static void
invalidate_reg (rtx x, bool clobber_high)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
/* If X is a register, dependencies on its contents are recorded
through the qty number mechanism. Just change the qty number of
@@ -1984,7 +1984,7 @@ static void
invalidate_dest (rtx dest)
{
if (REG_P (dest)
- || GET_CODE (dest) == SUBREG
+ || SUBREG_P (dest)
|| MEM_P (dest))
invalidate (dest, VOIDmode);
else if (GET_CODE (dest) == STRICT_LOW_PART
@@ -2028,7 +2028,7 @@ remove_invalid_subreg_refs (unsigned int regno, poly_uint64 offset,
next = p->next_same_hash;
if (!REG_P (exp)
- && (GET_CODE (exp) != SUBREG
+ && (!SUBREG_P (exp)
|| !REG_P (SUBREG_REG (exp))
|| REGNO (SUBREG_REG (exp)) != regno
|| ranges_maybe_overlap_p (SUBREG_BYTE (exp),
@@ -2051,7 +2051,7 @@ rehash_using_reg (rtx x)
struct table_elt *p, *next;
unsigned hash;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
/* If X is not a register or if the register is known not to be in any
@@ -2163,7 +2163,7 @@ use_related_value (rtx x, struct table_elt *elt)
if (elt != 0 && elt->related_value != 0)
relt = elt;
- else if (elt == 0 && GET_CODE (x) == CONST)
+ else if (elt == 0 && CONST_P (x))
{
rtx subexp = get_related_value (x);
if (subexp != 0)
@@ -3537,41 +3537,41 @@ fold_rtx (rtx x, rtx_insn *insn)
with that LABEL_REF as its second operand. If so, the result is
the first operand of that MINUS. This handles switches with an
ADDR_DIFF_VEC table. */
- if (const_arg1 && GET_CODE (const_arg1) == LABEL_REF)
+ if (const_arg1 && LABEL_REF_P (const_arg1))
{
rtx y
= GET_CODE (folded_arg0) == MINUS ? folded_arg0
: lookup_as_function (folded_arg0, MINUS);
- if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF
+ if (y != 0 && LABEL_REF_P (XEXP (y, 1))
&& label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg1))
return XEXP (y, 0);
/* Now try for a CONST of a MINUS like the above. */
- if ((y = (GET_CODE (folded_arg0) == CONST ? folded_arg0
+ if ((y = (CONST_P (folded_arg0) ? folded_arg0
: lookup_as_function (folded_arg0, CONST))) != 0
&& GET_CODE (XEXP (y, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (y, 0), 1))
&& label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg1))
return XEXP (XEXP (y, 0), 0);
}
/* Likewise if the operands are in the other order. */
- if (const_arg0 && GET_CODE (const_arg0) == LABEL_REF)
+ if (const_arg0 && LABEL_REF_P (const_arg0))
{
rtx y
= GET_CODE (folded_arg1) == MINUS ? folded_arg1
: lookup_as_function (folded_arg1, MINUS);
- if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF
+ if (y != 0 && LABEL_REF_P (XEXP (y, 1))
&& label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg0))
return XEXP (y, 0);
/* Now try for a CONST of a MINUS like the above. */
- if ((y = (GET_CODE (folded_arg1) == CONST ? folded_arg1
+ if ((y = (CONST_P (folded_arg1) ? folded_arg1
: lookup_as_function (folded_arg1, CONST))) != 0
&& GET_CODE (XEXP (y, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (y, 0), 1))
&& label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg0))
return XEXP (XEXP (y, 0), 0);
}
@@ -3811,7 +3811,7 @@ equiv_constant (rtx x)
if (x == 0 || CONSTANT_P (x))
return x;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
machine_mode mode = GET_MODE (x);
machine_mode imode = GET_MODE (SUBREG_REG (x));
@@ -4310,7 +4310,7 @@ find_sets_in_insn (rtx_insn *insn, struct set **psets)
and not be misled by unchanged instructions
that were unconditional jumps to begin with. */
if (SET_DEST (x) == pc_rtx
- && GET_CODE (SET_SRC (x)) == LABEL_REF)
+ && LABEL_REF_P (SET_SRC (x)))
;
/* Don't count call-insns, (set (reg 0) (call ...)), as a set.
The hard function value register is used only once, to copy to
@@ -4334,7 +4334,7 @@ find_sets_in_insn (rtx_insn *insn, struct set **psets)
/* As above, we ignore unconditional jumps and call-insns and
ignore the result of apply_change_group. */
if (SET_DEST (y) == pc_rtx
- && GET_CODE (SET_SRC (y)) == LABEL_REF)
+ && LABEL_REF_P (SET_SRC (y)))
;
else if (GET_CODE (SET_SRC (y)) == CALL)
;
@@ -4517,7 +4517,7 @@ canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets)
canon_reg (XEXP (dest, 2), insn), 1);
}
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -4842,8 +4842,8 @@ cse_insn (rtx_insn *insn)
"constant" here so we will record it. This allows us
to fold switch statements when an ADDR_DIFF_VEC is used. */
|| (GET_CODE (src_folded) == MINUS
- && GET_CODE (XEXP (src_folded, 0)) == LABEL_REF
- && GET_CODE (XEXP (src_folded, 1)) == LABEL_REF)))
+ && LABEL_REF_P (XEXP (src_folded, 0))
+ && LABEL_REF_P (XEXP (src_folded, 1)))))
src_const = src_folded, src_const_elt = elt;
else if (src_const == 0 && src_eqv_here && CONSTANT_P (src_eqv_here))
src_const = src_eqv_here, src_const_elt = src_eqv_elt;
@@ -4871,7 +4871,7 @@ cse_insn (rtx_insn *insn)
/* See if there is a register linearly related to a constant
equivalent of SRC. */
if (src_const
- && (GET_CODE (src_const) == CONST
+ && (CONST_P (src_const)
|| (src_const_elt && src_const_elt->related_value != 0)))
{
src_related = use_related_value (src_const, src_const_elt);
@@ -5029,7 +5029,7 @@ cse_insn (rtx_insn *insn)
if (targetm.const_anchor
&& !src_related
&& src_const
- && GET_CODE (src_const) == CONST_INT)
+ && CONST_INT_P (src_const))
{
src_related = try_const_anchors (src_const, mode);
src_related_is_const_anchor = src_related != NULL_RTX;
@@ -5066,7 +5066,7 @@ cse_insn (rtx_insn *insn)
looking for. */
if (paradoxical_subreg_p (p->exp)
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (p->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (p->exp)))))
@@ -5155,7 +5155,7 @@ cse_insn (rtx_insn *insn)
/* If this was an indirect jump insn, a known label will really be
cheaper even though it looks more expensive. */
- if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF)
+ if (dest == pc_rtx && src_const && LABEL_REF_P (src_const))
src_folded = src_const, src_folded_cost = src_folded_regcost = -1;
/* Terminate loop when replacement made. This must terminate since
@@ -5177,7 +5177,7 @@ cse_insn (rtx_insn *insn)
/* It is okay, though, if the rtx we're trying to match
will ignore any of the bits we can't predict. */
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (elt->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (elt->exp)))))
@@ -5341,11 +5341,11 @@ cse_insn (rtx_insn *insn)
barriers). */
if (n_sets == 1 && dest == pc_rtx
&& (trial == pc_rtx
- || (GET_CODE (trial) == LABEL_REF
+ || (LABEL_REF_P (trial)
&& ! condjump_p (insn))))
{
/* Don't substitute non-local labels, this confuses CFG. */
- if (GET_CODE (trial) == LABEL_REF
+ if (LABEL_REF_P (trial)
&& LABEL_REF_NONLOCAL_P (trial))
continue;
@@ -5371,7 +5371,7 @@ cse_insn (rtx_insn *insn)
/* Reject certain invalid forms of CONST that we create. */
else if (CONSTANT_P (trial)
- && GET_CODE (trial) == CONST
+ && CONST_P (trial)
/* Reject cases that will cause decode_rtx_const to
die. On the alpha when simplifying a switch, we
get (const (truncate (minus (label_ref)
@@ -5380,8 +5380,8 @@ cse_insn (rtx_insn *insn)
/* Likewise on IA-64, except without the
truncate. */
|| (GET_CODE (XEXP (trial, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (trial, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (trial, 0), 1)) == LABEL_REF)))
+ && LABEL_REF_P (XEXP (XEXP (trial, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (trial, 0), 1)))))
/* Do nothing for this case. */
;
@@ -5501,12 +5501,12 @@ cse_insn (rtx_insn *insn)
&& REG_P (dest)
&& src_const
&& !REG_P (src_const)
- && !(GET_CODE (src_const) == SUBREG
+ && !(SUBREG_P (src_const)
&& REG_P (SUBREG_REG (src_const)))
- && !(GET_CODE (src_const) == CONST
+ && !(CONST_P (src_const)
&& GET_CODE (XEXP (src_const, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (src_const, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (src_const, 0), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (XEXP (src_const, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (src_const, 0), 1)))
&& !rtx_equal_p (src, src_const))
{
/* Make sure that the rtx is not shared. */
@@ -5522,7 +5522,7 @@ cse_insn (rtx_insn *insn)
do_not_record = 0;
/* Look within any ZERO_EXTRACT to the MEM or REG within it. */
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -5599,7 +5599,7 @@ cse_insn (rtx_insn *insn)
/* If this SET is now setting PC to a label, we know it used to
be a conditional or computed branch. */
- else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF
+ else if (dest == pc_rtx && LABEL_REF_P (src)
&& !LABEL_REF_NONLOCAL_P (src))
{
/* We reemit the jump in as many cases as possible just in
@@ -5853,7 +5853,7 @@ cse_insn (rtx_insn *insn)
previous quantity's chain.
Needed for memory if this is a nonvarying address, unless
we have just done an invalidate_memory that covers even those. */
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
invalidate (dest, VOIDmode);
else if (MEM_P (dest))
invalidate (dest, VOIDmode);
@@ -5975,7 +5975,7 @@ cse_insn (rtx_insn *insn)
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = SUBREG_REG (XEXP (dest, 0));
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
/* Registers must also be inserted into chains for quantities. */
if (insert_regs (dest, sets[i].src_elt, 1))
{
@@ -5998,7 +5998,7 @@ cse_insn (rtx_insn *insn)
if (targetm.const_anchor
&& REG_P (dest)
&& SCALAR_INT_MODE_P (GET_MODE (dest))
- && GET_CODE (sets[i].src_elt->exp) == CONST_INT)
+ && CONST_INT_P (sets[i].src_elt->exp))
insert_const_anchors (dest, sets[i].src_elt->exp, GET_MODE (dest));
elt->in_memory = (MEM_P (sets[i].inner_dest)
@@ -6019,7 +6019,7 @@ cse_insn (rtx_insn *insn)
Note the loop below will find SUBREG_REG (DEST) since we have
already entered SRC and DEST of the SET in the table. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& (known_equal_after_align_down
(GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) - 1,
GET_MODE_SIZE (GET_MODE (dest)) - 1,
@@ -6147,7 +6147,7 @@ invalidate_from_clobbers (rtx_insn *insn)
rtx ref = XEXP (x, 0);
if (ref)
{
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6170,7 +6170,7 @@ invalidate_from_clobbers (rtx_insn *insn)
if (GET_CODE (y) == CLOBBER)
{
rtx ref = XEXP (y, 0);
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6231,7 +6231,7 @@ invalidate_from_sets_and_clobbers (rtx_insn *insn)
rtx clobbered = XEXP (y, 0);
if (REG_P (clobbered)
- || GET_CODE (clobbered) == SUBREG)
+ || SUBREG_P (clobbered))
invalidate (clobbered, VOIDmode);
else if (GET_CODE (clobbered) == STRICT_LOW_PART
|| GET_CODE (clobbered) == ZERO_EXTRACT)
@@ -6582,7 +6582,7 @@ check_for_label_ref (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == LABEL_REF
+ if (LABEL_REF_P (x)
&& !LABEL_REF_NONLOCAL_P (x)
&& (!JUMP_P (insn)
|| !label_is_jump_target_p (label_ref_label (x), insn))
diff --git a/gcc/cselib.c b/gcc/cselib.c
index 7b0545e779c..a1f1120eebd 100644
--- a/gcc/cselib.c
+++ b/gcc/cselib.c
@@ -457,7 +457,7 @@ invariant_or_equiv_p (cselib_val *v)
&& v->locs->next == NULL)
{
if (CONSTANT_P (v->locs->loc)
- && (GET_CODE (v->locs->loc) != CONST
+ && (!CONST_P (v->locs->loc)
|| !references_value_p (v->locs->loc, 0)))
return true;
/* Although a debug expr may be bound to different expressions,
@@ -1474,7 +1474,7 @@ expand_loc (struct elt_loc_list *p, struct expand_value_data *evd,
fprintf (dump_file, "\n");
}
if (GET_CODE (p->loc) == LO_SUM
- && GET_CODE (XEXP (p->loc, 1)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (p->loc, 1))
&& p->setting_insn
&& (note = find_reg_note (p->setting_insn, REG_EQUAL, NULL_RTX))
&& XEXP (note, 0) == XEXP (p->loc, 1))
@@ -1692,7 +1692,7 @@ cselib_expand_value_rtx_1 (rtx orig, struct expand_value_data *evd,
GET_MODE (SUBREG_REG (orig)),
SUBREG_BYTE (orig));
if (scopy == NULL
- || (GET_CODE (scopy) == SUBREG
+ || (SUBREG_P (scopy)
&& !REG_P (SUBREG_REG (scopy))
&& !MEM_P (SUBREG_REG (scopy))))
return NULL;
@@ -2376,7 +2376,7 @@ cselib_invalidate_mem (rtx mem_rtx)
void
cselib_invalidate_rtx (rtx dest, const_rtx setter)
{
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 81577dfe5cd..330504ef5b4 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -2740,7 +2740,7 @@ dbxout_symbol (tree decl, int local ATTRIBUTE_UNUSED)
if (context && DECL_FROM_INLINE (decl))
break;
if (!MEM_P (decl_rtl)
- || GET_CODE (XEXP (decl_rtl, 0)) != SYMBOL_REF)
+ || !SYMBOL_REF_P (XEXP (decl_rtl, 0)))
break;
if (flag_debug_only_used_symbols)
@@ -3000,11 +3000,11 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
If the decl was from an inline function, then its rtl
is not identically the rtl that was used in this
particular compilation. */
- if (GET_CODE (home) == SUBREG)
+ if (SUBREG_P (home))
{
rtx value = home;
- while (GET_CODE (value) == SUBREG)
+ while (SUBREG_P (value))
value = SUBREG_REG (value);
if (REG_P (value))
{
@@ -3033,7 +3033,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
no letter at all, and N_LSYM, for auto variable,
r and N_RSYM for register variable. */
- if (MEM_P (home) && GET_CODE (XEXP (home, 0)) == SYMBOL_REF)
+ if (MEM_P (home) && SYMBOL_REF_P (XEXP (home, 0)))
{
if (TREE_PUBLIC (decl))
{
@@ -3058,13 +3058,13 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
dumped into a constant pool. Alternatively, the symbol
in the constant pool might be referenced by a different
symbol. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& CONSTANT_POOL_ADDRESS_P (addr))
{
bool marked;
rtx tmp = get_pool_constant_mark (addr, &marked);
- if (GET_CODE (tmp) == SYMBOL_REF)
+ if (SYMBOL_REF_P (tmp))
{
addr = tmp;
if (CONSTANT_POOL_ADDRESS_P (addr))
@@ -3072,7 +3072,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
else
marked = true;
}
- else if (GET_CODE (tmp) == LABEL_REF)
+ else if (LABEL_REF_P (tmp))
{
addr = tmp;
marked = true;
@@ -3177,7 +3177,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
number = DEBUGGER_AUTO_OFFSET (XEXP (home, 0));
}
else if (MEM_P (home)
- && GET_CODE (XEXP (home, 0)) == CONST)
+ && CONST_P (XEXP (home, 0)))
{
/* Handle an obscure case which can arise when optimizing and
when there are few available registers. (This is *always*
@@ -3329,17 +3329,17 @@ dbxout_common_check (tree decl, int *value)
return NULL;
home = DECL_RTL (decl);
- if (home == NULL_RTX || GET_CODE (home) != MEM)
+ if (home == NULL_RTX || !MEM_P (home))
return NULL;
sym_addr = dbxout_expand_expr (DECL_VALUE_EXPR (decl));
- if (sym_addr == NULL_RTX || GET_CODE (sym_addr) != MEM)
+ if (sym_addr == NULL_RTX || !MEM_P (sym_addr))
return NULL;
sym_addr = XEXP (sym_addr, 0);
- if (GET_CODE (sym_addr) == CONST)
+ if (CONST_P (sym_addr))
sym_addr = XEXP (sym_addr, 0);
- if ((GET_CODE (sym_addr) == SYMBOL_REF || GET_CODE (sym_addr) == PLUS)
+ if ((SYMBOL_REF_P (sym_addr) || GET_CODE (sym_addr) == PLUS)
&& DECL_INITIAL (decl) == 0)
{
diff --git a/gcc/defaults.h b/gcc/defaults.h
index af7ea185f1e..f4bdc7b0247 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1170,7 +1170,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
/* For most ports anything that evaluates to a constant symbolic
or integer value is acceptable as a constant address. */
#ifndef CONSTANT_ADDRESS_P
-#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && GET_CODE (X) != CONST_DOUBLE)
+#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && !CONST_DOUBLE_P (X))
#endif
#ifndef MAX_FIXED_MODE_SIZE
diff --git a/gcc/df-core.c b/gcc/df-core.c
index be19aba0f1e..1eae8dba891 100644
--- a/gcc/df-core.c
+++ b/gcc/df-core.c
@@ -1955,7 +1955,7 @@ df_find_def (rtx_insn *insn, rtx reg)
{
df_ref def;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -1984,7 +1984,7 @@ df_find_use (rtx_insn *insn, rtx reg)
{
df_ref use;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
diff --git a/gcc/df-problems.c b/gcc/df-problems.c
index d32c688510c..bc3f38a94bd 100644
--- a/gcc/df-problems.c
+++ b/gcc/df-problems.c
@@ -2811,7 +2811,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
int which_subword = -1;
bool changed = false;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (orig_reg);
regno = REGNO (reg);
reg_mode = GET_MODE (reg);
@@ -2819,7 +2819,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
|| maybe_ne (GET_MODE_SIZE (reg_mode), 2 * UNITS_PER_WORD))
return true;
- if (GET_CODE (orig_reg) == SUBREG
+ if (SUBREG_P (orig_reg)
&& read_modify_subreg_p (orig_reg))
{
gcc_assert (DF_REF_FLAGS_IS_SET (ref, DF_REF_PARTIAL));
@@ -4002,7 +4002,7 @@ find_memory_stores (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
int *pflags = (int *)data;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = XEXP (x, 0);
/* Treat stores to SP as stores to memory, this will prevent problems
when there are references to the stack frame. */
diff --git a/gcc/df-scan.c b/gcc/df-scan.c
index 03294a8a2c3..c3d52be4e49 100644
--- a/gcc/df-scan.c
+++ b/gcc/df-scan.c
@@ -2474,7 +2474,7 @@ df_ref_create_structure (enum df_ref_class cl,
int ref_flags)
{
df_ref this_ref = NULL;
- unsigned int regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ unsigned int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
struct df_scan_problem_data *problem_data
= (struct df_scan_problem_data *) df_scan->problem_data;
@@ -2561,9 +2561,9 @@ df_ref_record (enum df_ref_class cl,
{
unsigned int regno;
- gcc_checking_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
+ gcc_checking_assert (REG_P (reg) || SUBREG_P (reg));
- regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
if (regno < FIRST_PSEUDO_REGISTER)
{
struct df_mw_hardreg *hardreg = NULL;
@@ -2573,7 +2573,7 @@ df_ref_record (enum df_ref_class cl,
unsigned int endregno;
df_ref ref;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno += subreg_regno_offset (regno, GET_MODE (SUBREG_REG (reg)),
SUBREG_BYTE (reg), GET_MODE (reg));
@@ -2590,7 +2590,7 @@ df_ref_record (enum df_ref_class cl,
{
/* Sets to a subreg of a multiword register are partial.
Sets to a non-subreg of a multiword register are not. */
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
ref_flags |= DF_REF_PARTIAL;
ref_flags |= DF_REF_MW_HARDREG;
@@ -2673,7 +2673,7 @@ df_def_record_1 (class df_collection_rec *collection_rec,
df_ref_record (DF_REF_BASE, collection_rec,
dst, NULL, bb, insn_info, DF_REF_REG_USE, flags);
}
- else if (GET_CODE (dst) == SUBREG && REG_P (SUBREG_REG (dst)))
+ else if (SUBREG_P (dst) && REG_P (SUBREG_REG (dst)))
{
if (read_modify_subreg_p (dst))
flags |= DF_REF_READ_WRITE | DF_REF_PARTIAL;
@@ -2753,7 +2753,7 @@ df_find_hard_reg_defs_1 (rtx dst, HARD_REG_SET *defs)
/* At this point if we do not have a reg or a subreg, just return. */
if (REG_P (dst) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (dst));
- else if (GET_CODE (dst) == SUBREG
+ else if (SUBREG_P (dst)
&& REG_P (SUBREG_REG (dst)) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (SUBREG_REG (dst)));
}
@@ -2919,7 +2919,7 @@ df_uses_record (class df_collection_rec *collection_rec,
SUBREG. */
dst = XEXP (dst, 0);
df_uses_record (collection_rec,
- (GET_CODE (dst) == SUBREG) ? &SUBREG_REG (dst) : temp,
+ (SUBREG_P (dst)) ? &SUBREG_REG (dst) : temp,
DF_REF_REG_USE, bb, insn_info,
DF_REF_READ_WRITE | DF_REF_STRICT_LOW_PART);
}
@@ -2930,7 +2930,7 @@ df_uses_record (class df_collection_rec *collection_rec,
DF_REF_REG_USE, bb, insn_info, flags);
df_uses_record (collection_rec, &XEXP (dst, 2),
DF_REF_REG_USE, bb, insn_info, flags);
- if (GET_CODE (XEXP (dst,0)) == MEM)
+ if (MEM_P (XEXP (dst,0)))
df_uses_record (collection_rec, &XEXP (dst, 0),
DF_REF_REG_USE, bb, insn_info,
flags);
diff --git a/gcc/df.h b/gcc/df.h
index 2e3b825065e..039fe9e9b22 100644
--- a/gcc/df.h
+++ b/gcc/df.h
@@ -647,10 +647,10 @@ public:
/* Macros to access the elements within the ref structure. */
-#define DF_REF_REAL_REG(REF) (GET_CODE ((REF)->base.reg) == SUBREG \
+#define DF_REF_REAL_REG(REF) (SUBREG_P ((REF)->base.reg) \
? SUBREG_REG ((REF)->base.reg) : ((REF)->base.reg))
#define DF_REF_REGNO(REF) ((REF)->base.regno)
-#define DF_REF_REAL_LOC(REF) (GET_CODE (*((REF)->regular_ref.loc)) == SUBREG \
+#define DF_REF_REAL_LOC(REF) (SUBREG_P (*((REF)->regular_ref.loc)) \
? &SUBREG_REG (*((REF)->regular_ref.loc)) : ((REF)->regular_ref.loc))
#define DF_REF_REG(REF) ((REF)->base.reg)
#define DF_REF_LOC(REF) (DF_REF_CLASS (REF) == DF_REF_REGULAR ? \
diff --git a/gcc/dojump.c b/gcc/dojump.c
index bac37a357a9..040d2c260fb 100644
--- a/gcc/dojump.c
+++ b/gcc/dojump.c
@@ -610,7 +610,7 @@ do_jump (tree exp, rtx_code_label *if_false_label,
temp = expand_normal (exp);
do_pending_stack_adjust ();
/* The RTL optimizers prefer comparisons against pseudos. */
- if (GET_CODE (temp) == SUBREG)
+ if (SUBREG_P (temp))
{
/* Compare promoted variables in their promoted mode. */
if (SUBREG_PROMOTED_VAR_P (temp)
diff --git a/gcc/dse.c b/gcc/dse.c
index 8d7358d02b4..4ddf0277b64 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1056,7 +1056,7 @@ const_or_frame_p (rtx x)
if (CONSTANT_P (x))
return true;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* Note that we have to test for the actual rtx used for the frame
and arg pointers and not just the register number in case we have
@@ -1158,7 +1158,7 @@ canon_address (rtx mem,
fprintf (dump_file, "\n");
}
- if (GET_CODE (address) == CONST)
+ if (CONST_P (address))
address = XEXP (address, 0);
address = strip_offset_and_add (address, offset);
@@ -1464,7 +1464,7 @@ record_store (rtx body, bb_info_t bb_info)
/* No place to keep the value after ra. */
&& !reload_completed
&& (REG_P (SET_SRC (body))
- || GET_CODE (SET_SRC (body)) == SUBREG
+ || SUBREG_P (SET_SRC (body))
|| CONSTANT_P (SET_SRC (body)))
&& !MEM_VOLATILE_P (mem)
/* Sometimes the store and reload is used for truncation and
@@ -2439,7 +2439,7 @@ scan_insn (bb_info_t bb_info, rtx_insn *insn)
if (!const_call
&& (call = get_call_rtx_from (insn))
&& (sym = XEXP (XEXP (call, 0), 0))
- && GET_CODE (sym) == SYMBOL_REF
+ && SYMBOL_REF_P (sym)
&& SYMBOL_REF_DECL (sym)
&& TREE_CODE (SYMBOL_REF_DECL (sym)) == FUNCTION_DECL
&& fndecl_built_in_p (SYMBOL_REF_DECL (sym), BUILT_IN_MEMSET))
diff --git a/gcc/dwarf2asm.c b/gcc/dwarf2asm.c
index 488e54b72ec..fc655272ed8 100644
--- a/gcc/dwarf2asm.c
+++ b/gcc/dwarf2asm.c
@@ -912,7 +912,7 @@ dw2_force_const_mem (rtx x, bool is_public)
if (! indirect_pool)
indirect_pool = hash_map<const char *, tree>::create_ggc (64);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
key = XSTR (x, 0);
tree *slot = indirect_pool->get (key);
@@ -1078,13 +1078,13 @@ dw2_asm_output_encoded_addr_rtx (int encoding, rtx addr, bool is_public,
#ifdef ASM_OUTPUT_DWARF_DATAREL
case DW_EH_PE_datarel:
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
ASM_OUTPUT_DWARF_DATAREL (asm_out_file, size, XSTR (addr, 0));
break;
#endif
case DW_EH_PE_pcrel:
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
#ifdef ASM_OUTPUT_DWARF_PCREL
ASM_OUTPUT_DWARF_PCREL (asm_out_file, size, XSTR (addr, 0));
#else
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index aa7fd7eb465..b81e3ab88b5 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -4222,7 +4222,7 @@ static inline int
is_pseudo_reg (const_rtx rtl)
{
return ((REG_P (rtl) && REGNO (rtl) >= FIRST_PSEUDO_REGISTER)
- || (GET_CODE (rtl) == SUBREG
+ || (SUBREG_P (rtl)
&& REGNO (SUBREG_REG (rtl)) >= FIRST_PSEUDO_REGISTER));
}
@@ -6925,7 +6925,7 @@ attr_checksum (dw_attr_node *at, struct md5_ctx *ctx, int *mark)
case dw_val_class_addr:
r = AT_addr (at);
- gcc_assert (GET_CODE (r) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (r));
CHECKSUM_STRING (XSTR (r, 0));
break;
@@ -7225,7 +7225,7 @@ attr_checksum_ordered (enum dwarf_tag tag, dw_attr_node *at,
case dw_val_class_addr:
r = AT_addr (at);
- gcc_assert (GET_CODE (r) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (r));
CHECKSUM_ULEB128 (DW_FORM_string);
CHECKSUM_STRING (XSTR (r, 0));
break;
@@ -14503,7 +14503,7 @@ const_ok_for_output_1 (rtx rtl)
rather than DECL_THREAD_LOCAL_P is not just an optimization. */
if (flag_checking
&& (XVECLEN (rtl, 0) == 0
- || GET_CODE (XVECEXP (rtl, 0, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XVECEXP (rtl, 0, 0))
|| SYMBOL_REF_TLS_MODEL (XVECEXP (rtl, 0, 0)) == TLS_MODEL_NONE))
inform (current_function_decl
? DECL_SOURCE_LOCATION (current_function_decl)
@@ -14619,10 +14619,10 @@ const_ok_for_output_1 (rtx rtl)
static bool
const_ok_for_output (rtx rtl)
{
- if (GET_CODE (rtl) == SYMBOL_REF)
+ if (SYMBOL_REF_P (rtl))
return const_ok_for_output_1 (rtl);
- if (GET_CODE (rtl) == CONST)
+ if (CONST_P (rtl))
{
subrtx_var_iterator::array_type array;
FOR_EACH_SUBRTX_VAR (iter, array, XEXP (rtl, 0), ALL)
@@ -15129,7 +15129,7 @@ clz_loc_descriptor (rtx rtl, scalar_int_mode mode,
msb = immed_wide_int_const
(wi::set_bit_in_zero (GET_MODE_PRECISION (mode) - 1,
GET_MODE_PRECISION (mode)), mode);
- if (GET_CODE (msb) == CONST_INT && INTVAL (msb) < 0)
+ if (CONST_INT_P (msb) && INTVAL (msb) < 0)
tmp = new_loc_descr (HOST_BITS_PER_WIDE_INT == 32
? DW_OP_const4u : HOST_BITS_PER_WIDE_INT == 64
? DW_OP_const8u : DW_OP_constu, INTVAL (msb), 0);
@@ -15755,7 +15755,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode,
goto symref;
}
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_TLS_MODEL (rtl) != TLS_MODEL_NONE)
{
dw_loc_descr_ref temp;
@@ -15779,7 +15779,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode,
if (!const_ok_for_output (rtl))
{
- if (GET_CODE (rtl) == CONST)
+ if (CONST_P (rtl))
switch (GET_CODE (XEXP (rtl, 0)))
{
case NOT:
@@ -16813,7 +16813,7 @@ loc_descriptor (rtx rtl, machine_mode mode,
if (mode == VOIDmode
|| CONST_SCALAR_INT_P (XEXP (rtl, 0))
|| CONST_DOUBLE_AS_FLOAT_P (XEXP (rtl, 0))
- || GET_CODE (XEXP (rtl, 0)) == CONST_VECTOR)
+ || CONST_VECTOR_P (XEXP (rtl, 0)))
{
loc_result = loc_descriptor (XEXP (rtl, 0), mode, initialized);
break;
@@ -17129,11 +17129,11 @@ dw_sra_loc_expr (tree decl, rtx loc)
}
do
{
- if (GET_CODE (varloc) == CONST
+ if (CONST_P (varloc)
|| GET_CODE (varloc) == SIGN_EXTEND
|| GET_CODE (varloc) == ZERO_EXTEND)
varloc = XEXP (varloc, 0);
- else if (GET_CODE (varloc) == SUBREG)
+ else if (SUBREG_P (varloc))
varloc = SUBREG_REG (varloc);
else
break;
@@ -17453,7 +17453,7 @@ cst_pool_loc_descr (tree loc)
gcc_assert (!rtl);
return 0;
}
- gcc_assert (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (rtl, 0)));
/* TODO: We might get more coverage if we was actually delaying expansion
of all expressions till end of compilation when constant pools are fully
@@ -18421,7 +18421,7 @@ loc_list_from_tree_1 (tree loc, int want_address,
val &= GET_MODE_MASK (DECL_MODE (loc));
ret = int_loc_descriptor (val);
}
- else if (GET_CODE (rtl) == CONST_STRING)
+ else if (CONST_STRING_P (rtl))
{
expansion_failed (loc, NULL_RTX, "CONST_STRING");
return 0;
@@ -19687,7 +19687,7 @@ add_const_value_attribute (dw_die_ref die, rtx rtl)
return false;
case MEM:
- if (GET_CODE (XEXP (rtl, 0)) == CONST_STRING
+ if (CONST_STRING_P (XEXP (rtl, 0))
&& MEM_READONLY_P (rtl)
&& GET_MODE (rtl) == BLKmode)
{
@@ -20063,7 +20063,7 @@ rtl_for_decl_location (tree decl)
{
rtl = make_decl_rtl_for_debug (decl);
if (!MEM_P (rtl)
- || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (rtl, 0))
|| SYMBOL_REF_DECL (XEXP (rtl, 0)) != decl)
rtl = NULL_RTX;
}
@@ -20165,7 +20165,7 @@ add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p)
the location. */
rtl = rtl_for_decl_location (decl);
- if (rtl && (CONSTANT_P (rtl) || GET_CODE (rtl) == CONST_STRING)
+ if (rtl && (CONSTANT_P (rtl) || CONST_STRING_P (rtl))
&& add_const_value_attribute (die, rtl))
return true;
@@ -20186,7 +20186,7 @@ add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p)
rtl = NOTE_VAR_LOCATION_LOC (node->loc);
if (GET_CODE (rtl) == EXPR_LIST)
rtl = XEXP (rtl, 0);
- if ((CONSTANT_P (rtl) || GET_CODE (rtl) == CONST_STRING)
+ if ((CONSTANT_P (rtl) || CONST_STRING_P (rtl))
&& add_const_value_attribute (die, rtl))
return true;
}
@@ -21798,7 +21798,7 @@ decl_start_label (tree decl)
gcc_assert (MEM_P (x));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
fnname = XSTR (x, 0);
return fnname;
@@ -23816,7 +23816,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die)
if (single_element_loc_list_p (loc)
&& loc->expr->dw_loc_opc == DW_OP_addr
&& loc->expr->dw_loc_next == NULL
- && GET_CODE (loc->expr->dw_loc_oprnd1.v.val_addr) == SYMBOL_REF)
+ && SYMBOL_REF_P (loc->expr->dw_loc_oprnd1.v.val_addr))
{
rtx x = loc->expr->dw_loc_oprnd1.v.val_addr;
loc->expr->dw_loc_oprnd1.v.val_addr
@@ -27334,7 +27334,7 @@ dwarf2out_var_location (rtx_insn *loc_note)
if (GET_CODE (x) == CALL)
x = XEXP (x, 0);
if (!MEM_P (x)
- || GET_CODE (XEXP (x, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (x, 0))
|| !SYMBOL_REF_DECL (XEXP (x, 0))
|| (TREE_CODE (SYMBOL_REF_DECL (XEXP (x, 0)))
!= FUNCTION_DECL))
@@ -27512,7 +27512,7 @@ create_label:
if (MEM_P (XEXP (x, 0)))
x = XEXP (x, 0);
/* First, look for a memory access to a symbol_ref. */
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& SYMBOL_REF_DECL (XEXP (x, 0))
&& TREE_CODE (SYMBOL_REF_DECL (XEXP (x, 0))) == FUNCTION_DECL)
ca_loc->symbol_ref = XEXP (x, 0);
@@ -29855,7 +29855,7 @@ resolve_one_addr (rtx *addr)
{
rtx rtl = *addr;
- if (GET_CODE (rtl) == CONST_STRING)
+ if (CONST_STRING_P (rtl))
{
size_t len = strlen (XSTR (rtl, 0)) + 1;
tree t = build_string (len, XSTR (rtl, 0));
@@ -29866,7 +29866,7 @@ resolve_one_addr (rtx *addr)
if (!rtl || !MEM_P (rtl))
return false;
rtl = XEXP (rtl, 0);
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_DECL (rtl)
&& !TREE_ASM_WRITTEN (SYMBOL_REF_DECL (rtl)))
return false;
@@ -29875,7 +29875,7 @@ resolve_one_addr (rtx *addr)
return true;
}
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_DECL (rtl))
{
if (TREE_CONSTANT_POOL_ADDRESS_P (rtl))
@@ -29887,7 +29887,7 @@ resolve_one_addr (rtx *addr)
return false;
}
- if (GET_CODE (rtl) == CONST)
+ if (CONST_P (rtl))
{
subrtx_ptr_iterator::array_type array;
FOR_EACH_SUBRTX_PTR (iter, array, &XEXP (rtl, 0), ALL)
@@ -29915,7 +29915,7 @@ string_cst_pool_decl (tree t)
if (!rtl || !MEM_P (rtl))
return NULL_RTX;
rtl = XEXP (rtl, 0);
- if (GET_CODE (rtl) != SYMBOL_REF
+ if (!SYMBOL_REF_P (rtl)
|| SYMBOL_REF_DECL (rtl) == NULL_TREE)
return NULL_RTX;
@@ -29953,14 +29953,14 @@ optimize_one_addr_into_implicit_ptr (dw_loc_descr_ref loc)
dw_die_ref ref = NULL;
tree decl;
- if (GET_CODE (rtl) == CONST
+ if (CONST_P (rtl)
&& GET_CODE (XEXP (rtl, 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (rtl, 0), 1)))
{
offset = INTVAL (XEXP (XEXP (rtl, 0), 1));
rtl = XEXP (XEXP (rtl, 0), 0);
}
- if (GET_CODE (rtl) == CONST_STRING)
+ if (CONST_STRING_P (rtl))
{
size_t len = strlen (XSTR (rtl, 0)) + 1;
tree t = build_string (len, XSTR (rtl, 0));
@@ -29972,7 +29972,7 @@ optimize_one_addr_into_implicit_ptr (dw_loc_descr_ref loc)
if (!rtl)
return false;
}
- if (GET_CODE (rtl) == SYMBOL_REF && SYMBOL_REF_DECL (rtl))
+ if (SYMBOL_REF_P (rtl) && SYMBOL_REF_DECL (rtl))
{
decl = SYMBOL_REF_DECL (rtl);
if (VAR_P (decl) && !DECL_EXTERNAL (decl))
@@ -30596,7 +30596,7 @@ resolve_addr (dw_die_ref die)
if (l != NULL
&& l->dw_loc_next == NULL
&& l->dw_loc_opc == DW_OP_addr
- && GET_CODE (l->dw_loc_oprnd1.v.val_addr) == SYMBOL_REF
+ && SYMBOL_REF_P (l->dw_loc_oprnd1.v.val_addr)
&& SYMBOL_REF_DECL (l->dw_loc_oprnd1.v.val_addr)
&& a->dw_attr == DW_AT_location)
{
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index a667cdab94e..13cfd0b00ea 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -1294,7 +1294,7 @@ set_reg_attrs_from_value (rtx reg, rtx x)
while (GET_CODE (x) == SIGN_EXTEND
|| GET_CODE (x) == ZERO_EXTEND
|| GET_CODE (x) == TRUNCATE
- || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x)))
+ || (SUBREG_P (x) && subreg_lowpart_p (x)))
{
#if defined(POINTERS_EXTEND_UNSIGNED)
if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED)
@@ -1377,7 +1377,7 @@ set_reg_attrs_for_decl_rtl (tree t, rtx x)
if (!t)
return;
tree tdecl = t;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
gcc_assert (subreg_lowpart_p (x));
x = SUBREG_REG (x);
@@ -1595,8 +1595,8 @@ gen_lowpart_common (machine_mode mode, rtx x)
else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode))
return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
}
- else if (GET_CODE (x) == SUBREG || REG_P (x)
- || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
+ else if (SUBREG_P (x) || REG_P (x)
+ || GET_CODE (x) == CONCAT || CONST_VECTOR_P (x)
|| CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
|| CONST_POLY_INT_P (x))
return lowpart_subreg (mode, x, innermode);
@@ -1690,7 +1690,7 @@ subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes)
int
subreg_lowpart_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return 1;
else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
return 0;
@@ -3348,7 +3348,7 @@ make_safe_from (rtx x, rtx other)
if ((MEM_P (other)
&& ! CONSTANT_P (x)
&& !REG_P (x)
- && GET_CODE (x) != SUBREG)
+ && !SUBREG_P (x))
|| (REG_P (other)
&& (REGNO (other) < FIRST_PSEUDO_REGISTER
|| reg_mentioned_p (other, x))))
@@ -5416,7 +5416,7 @@ set_for_reg_notes (rtx insn)
reg = XEXP (reg, 0);
/* Check that we have a register. */
- if (!(REG_P (reg) || GET_CODE (reg) == SUBREG))
+ if (!(REG_P (reg) || SUBREG_P (reg)))
return NULL_RTX;
return pat;
@@ -6004,7 +6004,7 @@ gen_vec_duplicate (machine_mode mode, rtx x)
/* A subroutine of const_vec_series_p that handles the case in which:
- (GET_CODE (X) == CONST_VECTOR
+ (CONST_VECTOR_P (X)
&& CONST_VECTOR_NPATTERNS (X) == 1
&& !CONST_VECTOR_DUPLICATE_P (X))
diff --git a/gcc/explow.c b/gcc/explow.c
index 7eb854bca4a..a742030451f 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -117,12 +117,12 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
/* If this is a reference to the constant pool, try replacing it with
a reference to a new constant. If the resulting address isn't
valid, don't return it because we have no way to validize it. */
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
{
rtx cst = get_pool_constant (XEXP (x, 0));
- if (GET_CODE (cst) == CONST_VECTOR
+ if (CONST_VECTOR_P (cst)
&& GET_MODE_INNER (GET_MODE (cst)) == mode)
{
cst = gen_lowpart (mode, cst);
@@ -197,7 +197,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
if (maybe_ne (c, 0))
x = gen_rtx_PLUS (mode, x, gen_int_mode (c, mode));
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
return x;
else if (all_constant)
return gen_rtx_CONST (mode, x);
@@ -549,7 +549,7 @@ use_anchored_address (rtx x)
/* Split the address into a base and offset. */
base = XEXP (x, 0);
offset = 0;
- if (GET_CODE (base) == CONST
+ if (CONST_P (base)
&& GET_CODE (XEXP (base, 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (base, 0), 1)))
{
@@ -558,7 +558,7 @@ use_anchored_address (rtx x)
}
/* Check whether BASE is suitable for anchors. */
- if (GET_CODE (base) != SYMBOL_REF
+ if (!SYMBOL_REF_P (base)
|| !SYMBOL_REF_HAS_BLOCK_INFO_P (base)
|| SYMBOL_REF_ANCHOR_P (base)
|| SYMBOL_REF_BLOCK (base) == NULL
@@ -680,17 +680,17 @@ force_reg (machine_mode mode, rtx x)
known alignment of that pointer. */
{
unsigned align = 0;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
align = BITS_PER_UNIT;
if (SYMBOL_REF_DECL (x) && DECL_P (SYMBOL_REF_DECL (x)))
align = DECL_ALIGN (SYMBOL_REF_DECL (x));
}
- else if (GET_CODE (x) == LABEL_REF)
+ else if (LABEL_REF_P (x))
align = BITS_PER_UNIT;
- else if (GET_CODE (x) == CONST
+ else if (CONST_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))
{
rtx s = XEXP (XEXP (x, 0), 0);
@@ -2178,7 +2178,7 @@ anti_adjust_stack_and_probe (rtx size, bool adjust_back)
if (temp != const0_rtx)
{
/* Manual CSE if the difference is not known at compile-time. */
- if (GET_CODE (temp) != CONST_INT)
+ if (!CONST_INT_P (temp))
temp = gen_rtx_MINUS (Pmode, size, rounded_size_op);
anti_adjust_stack (temp);
emit_stack_probe (stack_pointer_rtx);
diff --git a/gcc/expmed.c b/gcc/expmed.c
index c582f3a1e62..25d19a05794 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -622,7 +622,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
/* If xop0 is a register, we need it in OP_MODE
to make it acceptable to the format of insv. */
- if (GET_CODE (xop0) == SUBREG)
+ if (SUBREG_P (xop0))
/* We can't just change the mode, because this might clobber op0,
and we will need the original value of op0 if insv fails. */
xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
@@ -635,7 +635,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
truncate the result to the original destination. Note that we can't
just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
X) 0)) is (reg:N X). */
- if (GET_CODE (xop0) == SUBREG
+ if (SUBREG_P (xop0)
&& REG_P (SUBREG_REG (xop0))
&& !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
op_mode))
@@ -735,7 +735,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
{
rtx op0 = str_rtx;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += subreg_memory_offset (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -875,7 +875,7 @@ store_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
rtx arg0 = op0;
unsigned HOST_WIDE_INT subreg_off;
- if (GET_CODE (arg0) == SUBREG)
+ if (SUBREG_P (arg0))
{
/* Else we've got some float mode source being extracted into
a different float mode destination -- this combination of
@@ -1330,7 +1330,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -1375,7 +1375,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
&& unit > BITS_PER_UNIT
&& maybe_gt (bitpos + bitsdone - thispos + unit, bitregion_end + 1)
&& !REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
{
unit = unit / 2;
continue;
@@ -1520,7 +1520,7 @@ extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
/* If op0 is a register, we need it in EXT_MODE to make it
acceptable to the format of ext(z)v. */
- if (GET_CODE (op0) == SUBREG && op0_mode.require () != ext_mode)
+ if (SUBREG_P (op0) && op0_mode.require () != ext_mode)
return NULL_RTX;
if (REG_P (op0) && op0_mode.require () != ext_mode)
op0 = gen_lowpart_SUBREG (ext_mode, op0);
@@ -1604,7 +1604,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
if (tmode == VOIDmode)
tmode = mode;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -1764,7 +1764,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
/* If we got a SUBREG, force it into a register since we
aren't going to be able to do another SUBREG on it. */
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (imode, op0);
}
else
@@ -2250,7 +2250,7 @@ extract_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -2477,7 +2477,7 @@ expand_shift_1 (enum tree_code code, machine_mode mode, rtx shifted,
op1 = gen_int_shift_amount (mode,
(unsigned HOST_WIDE_INT) INTVAL (op1)
% GET_MODE_BITSIZE (scalar_mode));
- else if (GET_CODE (op1) == SUBREG
+ else if (SUBREG_P (op1)
&& subreg_lowpart_p (op1)
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1)))
&& SCALAR_INT_MODE_P (GET_MODE (op1)))
@@ -3349,7 +3349,7 @@ expand_mult_const (machine_mode mode, rtx op0, HOST_WIDE_INT val,
we've set the inner register and must properly indicate that. */
tem = op0, nmode = mode;
accum_inner = accum;
- if (GET_CODE (accum) == SUBREG)
+ if (SUBREG_P (accum))
{
accum_inner = SUBREG_REG (accum);
nmode = GET_MODE (accum_inner);
diff --git a/gcc/expr.c b/gcc/expr.c
index 20e3f9ce337..7dd41e85656 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -227,7 +227,7 @@ convert_move (rtx to, rtx from, int unsignedp)
TO here. */
scalar_int_mode to_int_mode;
- if (GET_CODE (from) == SUBREG
+ if (SUBREG_P (from)
&& SUBREG_PROMOTED_VAR_P (from)
&& is_a <scalar_int_mode> (to_mode, &to_int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (from))
@@ -238,7 +238,7 @@ convert_move (rtx to, rtx from, int unsignedp)
from_mode = to_int_mode;
}
- gcc_assert (GET_CODE (to) != SUBREG || !SUBREG_PROMOTED_VAR_P (to));
+ gcc_assert (!SUBREG_P (to) || !SUBREG_PROMOTED_VAR_P (to));
if (to_mode == from_mode
|| (from_mode == VOIDmode && CONSTANT_P (from)))
@@ -437,7 +437,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
so that we always generate the same set of insns for
better cse'ing; if an intermediate assignment occurred,
we won't be doing the operation directly on the SUBREG. */
- if (optimize > 0 && GET_CODE (from) == SUBREG)
+ if (optimize > 0 && SUBREG_P (from))
from = force_reg (from_mode, from);
emit_unop_insn (code, to, from, equiv_code);
return;
@@ -519,7 +519,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
convert_move (to, gen_lowpart (word_mode, from), 0);
return;
@@ -538,7 +538,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
&& !targetm.hard_regno_mode_ok (REGNO (from), to_mode))
@@ -656,7 +656,7 @@ convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp)
/* If FROM is a SUBREG that indicates that we have already done at least
the required extension, strip it. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (x))
@@ -1659,7 +1659,7 @@ rtx
emit_block_move (rtx x, rtx y, rtx size, enum block_op_methods method)
{
unsigned HOST_WIDE_INT max, min = 0;
- if (GET_CODE (size) == CONST_INT)
+ if (CONST_INT_P (size))
min = max = UINTVAL (size);
else
max = GET_MODE_MASK (GET_MODE (size));
@@ -3052,7 +3052,7 @@ rtx
clear_storage (rtx object, rtx size, enum block_op_methods method)
{
unsigned HOST_WIDE_INT max, min = 0;
- if (GET_CODE (size) == CONST_INT)
+ if (CONST_INT_P (size))
min = max = UINTVAL (size);
else
max = GET_MODE_MASK (GET_MODE (size));
@@ -3255,7 +3255,7 @@ read_complex_part (rtx cplx, bool imag_p)
ibitsize = GET_MODE_BITSIZE (imode);
/* Special case reads from complex constants that got spilled to memory. */
- if (MEM_P (cplx) && GET_CODE (XEXP (cplx, 0)) == SYMBOL_REF)
+ if (MEM_P (cplx) && SYMBOL_REF_P (XEXP (cplx, 0)))
{
tree decl = SYMBOL_REF_DECL (XEXP (cplx, 0));
if (decl && TREE_CODE (decl) == COMPLEX_CST)
@@ -3587,7 +3587,7 @@ emit_move_ccmode (machine_mode mode, rtx x, rtx y)
static bool
undefined_operand_subword_p (const_rtx op, int i)
{
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
return false;
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_int64 offset = i * UNITS_PER_WORD + subreg_memory_offset (op);
@@ -3656,7 +3656,7 @@ emit_move_multi_word (machine_mode mode, rtx x, rtx y)
gcc_assert (xpart && ypart);
- need_clobber |= (GET_CODE (xpart) == SUBREG);
+ need_clobber |= (SUBREG_P (xpart));
last_insn = emit_move_insn (xpart, ypart);
}
@@ -4759,7 +4759,7 @@ optimize_bitfield_assignment_op (poly_uint64 pbitsize,
offset1 = (offset1 - bitpos) / BITS_PER_UNIT;
str_rtx = adjust_address (str_rtx, str_mode, offset1);
}
- else if (!REG_P (str_rtx) && GET_CODE (str_rtx) != SUBREG)
+ else if (!REG_P (str_rtx) && !SUBREG_P (str_rtx))
return false;
/* If the bit field covers the whole REG/MEM, store_field
@@ -5554,7 +5554,7 @@ store_expr (tree exp, rtx target, int call_param_p,
return NULL_RTX;
}
- else if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ else if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -6953,7 +6953,7 @@ store_field (rtx target, poly_int64 bitsize, poly_int64 bitpos,
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
|| REG_P (target)
- || GET_CODE (target) == SUBREG
+ || SUBREG_P (target)
/* If the field isn't aligned enough to store as an ordinary memref,
store it as a bit field. */
|| (mode != BLKmode
@@ -7448,9 +7448,9 @@ force_operand (rtx value, rtx target)
/* Check for a PIC address load. */
if ((code == PLUS || code == MINUS)
&& XEXP (value, 0) == pic_offset_table_rtx
- && (GET_CODE (XEXP (value, 1)) == SYMBOL_REF
- || GET_CODE (XEXP (value, 1)) == LABEL_REF
- || GET_CODE (XEXP (value, 1)) == CONST))
+ && (SYMBOL_REF_P (XEXP (value, 1))
+ || LABEL_REF_P (XEXP (value, 1))
+ || CONST_P (XEXP (value, 1))))
{
if (!subtarget)
subtarget = gen_reg_rtx (GET_MODE (value));
@@ -7605,7 +7605,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
/* If this is a subreg of a hard register, declare it unsafe, otherwise,
find the underlying pseudo. */
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
x = SUBREG_REG (x);
if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
@@ -7749,7 +7749,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
with it. */
if (exp_rtl)
{
- if (GET_CODE (exp_rtl) == SUBREG)
+ if (SUBREG_P (exp_rtl))
{
exp_rtl = SUBREG_REG (exp_rtl);
if (REG_P (exp_rtl)
@@ -8518,7 +8518,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
a promoted SUBREG, clear that indication since we now
have to do the proper extension. */
if (TYPE_UNSIGNED (TREE_TYPE (treeop0)) != unsignedp
- && GET_CODE (op0) == SUBREG)
+ && SUBREG_P (op0))
SUBREG_PROMOTED_VAR_P (op0) = 0;
return REDUCE_BIT_FIELD (op0);
@@ -10678,7 +10678,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
for (int i = 0; i < 2; i++)
{
rtx op = read_complex_part (op0, i != 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = force_reg (GET_MODE (op), op);
rtx temp = gen_lowpart_common (GET_MODE_INNER (mode1),
op);
@@ -10803,7 +10803,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
(which we know to be the width of a basic mode), then
storing into memory, and changing the mode to BLKmode. */
if (mode1 == VOIDmode
- || REG_P (op0) || GET_CODE (op0) == SUBREG
+ || REG_P (op0) || SUBREG_P (op0)
|| (mode1 != BLKmode && ! direct_load[(int) mode1]
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
@@ -11114,7 +11114,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
GET_MODE_PRECISION (GET_MODE (op0)))
&& !COMPLEX_MODE_P (GET_MODE (op0)))
{
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (GET_MODE (op0), op0);
temp = gen_lowpart_common (mode, op0);
if (temp)
@@ -12271,7 +12271,7 @@ do_tablejump (rtx index, machine_mode mode, rtx range, rtx table_label,
sign-extended subreg, and RANGE does not have the sign bit set, then
we have a value that is valid for both sign and zero extension. In
this case, we get better code if we sign extend. */
- if (GET_CODE (index) == SUBREG
+ if (SUBREG_P (index)
&& SUBREG_PROMOTED_VAR_P (index)
&& SUBREG_PROMOTED_SIGNED_P (index)
&& ((width = GET_MODE_PRECISION (as_a <scalar_int_mode> (mode)))
diff --git a/gcc/final.c b/gcc/final.c
index fefc4874b24..ec396230a3a 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -1611,7 +1611,7 @@ get_some_local_dynamic_name ()
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
return some_local_dynamic_name = XSTR (x, 0);
@@ -2798,17 +2798,17 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
&& insn != last_ignored_compare)
{
rtx src1, src2;
- if (GET_CODE (SET_SRC (set)) == SUBREG)
+ if (SUBREG_P (SET_SRC (set)))
SET_SRC (set) = alter_subreg (&SET_SRC (set), true);
src1 = SET_SRC (set);
src2 = NULL_RTX;
if (GET_CODE (SET_SRC (set)) == COMPARE)
{
- if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 0)))
XEXP (SET_SRC (set), 0)
= alter_subreg (&XEXP (SET_SRC (set), 0), true);
- if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 1)))
XEXP (SET_SRC (set), 1)
= alter_subreg (&XEXP (SET_SRC (set), 1), true);
if (XEXP (SET_SRC (set), 1)
@@ -3093,7 +3093,7 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
{
rtx x = call_from_call_insn (call_insn);
x = XEXP (x, 0);
- if (x && MEM_P (x) && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
+ if (x && MEM_P (x) && SYMBOL_REF_P (XEXP (x, 0)))
{
tree t;
x = XEXP (x, 0);
@@ -3318,7 +3318,7 @@ cleanup_subreg_operands (rtx_insn *insn)
already if we are inside a match_operator expression that
matches the else clause. Instead we test the underlying
expression directly. */
- if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.operand_loc[i]))
{
recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i], true);
changed = true;
@@ -3331,7 +3331,7 @@ cleanup_subreg_operands (rtx_insn *insn)
for (i = 0; i < recog_data.n_dups; i++)
{
- if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.dup_loc[i]))
{
*recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i], true);
changed = true;
@@ -4003,7 +4003,7 @@ output_asm_label (rtx x)
{
char buf[256];
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
x = label_ref_label (x);
if (LABEL_P (x)
|| (NOTE_P (x)
@@ -4024,7 +4024,7 @@ mark_symbol_refs_as_used (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
if (tree t = SYMBOL_REF_DECL (x))
assemble_external (t);
}
@@ -4042,7 +4042,7 @@ mark_symbol_refs_as_used (rtx x)
void
output_operand (rtx x, int code ATTRIBUTE_UNUSED)
{
- if (x && GET_CODE (x) == SUBREG)
+ if (x && SUBREG_P (x))
x = alter_subreg (&x, true);
/* X must not be a pseudo reg. */
@@ -4183,7 +4183,7 @@ output_addr_const (FILE *file, rtx x)
fprintf (file, "-");
if ((CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0)
|| GET_CODE (XEXP (x, 1)) == PC
- || GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ || SYMBOL_REF_P (XEXP (x, 1)))
output_addr_const (file, XEXP (x, 1));
else
{
diff --git a/gcc/function.c b/gcc/function.c
index 2a0061cad35..bd9672e3e44 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -3210,7 +3210,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
/* If op1 is a hard register that is likely spilled, first
force it into a pseudo, otherwise combiner might extend
its lifetime too much. */
- if (GET_CODE (t) == SUBREG)
+ if (SUBREG_P (t))
t = SUBREG_REG (t);
if (REG_P (t)
&& HARD_REGISTER_P (t)
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 137864cb61b..c38963bf9ce 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -372,7 +372,7 @@ canonicalize_address (rtx x)
case PLUS:
if (GET_CODE (XEXP (x, 0)) == PLUS
|| GET_CODE (XEXP (x, 0)) == ASHIFT
- || GET_CODE (XEXP (x, 0)) == CONST)
+ || CONST_P (XEXP (x, 0)))
canonicalize_address (XEXP (x, 0));
x = XEXP (x, 1);
@@ -738,7 +738,7 @@ propagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx,
flags = 0;
if (REG_P (new_rtx)
|| CONSTANT_P (new_rtx)
- || (GET_CODE (new_rtx) == SUBREG
+ || (SUBREG_P (new_rtx)
&& REG_P (SUBREG_REG (new_rtx))
&& !paradoxical_subreg_p (new_rtx)))
flags |= PR_CAN_APPEAR;
@@ -1146,7 +1146,7 @@ free_load_extend (rtx src, rtx_insn *insn)
rtx patt = PATTERN (DF_REF_INSN (def));
if (GET_CODE (patt) == SET
- && GET_CODE (SET_SRC (patt)) == MEM
+ && MEM_P (SET_SRC (patt))
&& rtx_equal_p (SET_DEST (patt), reg))
return true;
}
@@ -1165,7 +1165,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
/* Only consider subregs... */
machine_mode use_mode = GET_MODE (use_reg);
- if (GET_CODE (use_reg) != SUBREG
+ if (!SUBREG_P (use_reg)
|| !REG_P (SET_DEST (def_set)))
return false;
@@ -1178,7 +1178,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
these SUBREGs just say how to treat the register. */
use_insn = DF_REF_INSN (use);
src = SET_SRC (def_set);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& REG_P (SUBREG_REG (src))
&& REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER
&& GET_MODE (SUBREG_REG (src)) == use_mode
@@ -1327,17 +1327,17 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
/* If def and use are subreg, check if they match. */
reg = DF_REF_REG (use);
- if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ if (SUBREG_P (reg) && SUBREG_P (SET_DEST (def_set)))
{
if (maybe_ne (SUBREG_BYTE (SET_DEST (def_set)), SUBREG_BYTE (reg)))
return false;
}
/* Check if the def had a subreg, but the use has the whole reg. */
- else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ else if (REG_P (reg) && SUBREG_P (SET_DEST (def_set)))
return false;
/* Check if the use has a subreg, but the def had the whole reg. Unlike the
previous case, the optimization is possible and often useful indeed. */
- else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set)))
+ else if (SUBREG_P (reg) && REG_P (SET_DEST (def_set)))
reg = SUBREG_REG (reg);
/* Make sure that we can treat REG as having the same mode as the
@@ -1406,7 +1406,7 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
set_reg_equal = (note == NULL_RTX
&& REG_P (SET_DEST (use_set))
&& !REG_P (src)
- && !(GET_CODE (src) == SUBREG
+ && !(SUBREG_P (src)
&& REG_P (SUBREG_REG (src)))
&& !reg_mentioned_p (SET_DEST (use_set),
SET_SRC (use_set))
diff --git a/gcc/gcse-common.c b/gcc/gcse-common.c
index e6e4b642b58..0e40adb44af 100644
--- a/gcc/gcse-common.c
+++ b/gcc/gcse-common.c
@@ -40,7 +40,7 @@ canon_list_insert (rtx dest, const_rtx x ATTRIBUTE_UNUSED, void *data)
int bb;
modify_pair pair;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/gcse.c b/gcc/gcse.c
index ff2771bdc04..357f8a2ddb2 100644
--- a/gcc/gcse.c
+++ b/gcc/gcse.c
@@ -984,7 +984,7 @@ mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
struct mem_conflict_info *mci = (struct mem_conflict_info *) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -1478,7 +1478,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
@@ -1735,7 +1735,7 @@ prune_expressions (bool pre_p)
of the tables. */
if (MEM_P (x))
{
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
continue;
@@ -3381,7 +3381,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
const_rtx set = single_set_gcse (insn);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
diff --git a/gcc/genattr.c b/gcc/genattr.c
index 352303dd9da..14e98d7926b 100644
--- a/gcc/genattr.c
+++ b/gcc/genattr.c
@@ -37,7 +37,7 @@ gen_attr (md_rtx_info *info)
{
const char *p;
rtx attr = info->def;
- int is_const = GET_CODE (XEXP (attr, 2)) == CONST;
+ int is_const = CONST_P (XEXP (attr, 2));
if (is_const)
const_attrs.safe_push (attr);
diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c
index cdf0b5c12dc..28940497aa1 100644
--- a/gcc/genattrtab.c
+++ b/gcc/genattrtab.c
@@ -739,7 +739,7 @@ check_attr_test (file_location loc, rtx exp, attr_desc *attr)
else
{
for (av = attr2->first_value; av; av = av->next)
- if (GET_CODE (av->value) == CONST_STRING
+ if (CONST_STRING_P (av->value)
&& ! strcmp (XSTR (exp, 1), XSTR (av->value, 0)))
break;
@@ -813,8 +813,8 @@ check_attr_test (file_location loc, rtx exp, attr_desc *attr)
case LE: case LT: case GT: case GE:
case LEU: case LTU: case GTU: case GEU:
case NE: case EQ:
- if (GET_CODE (XEXP (exp, 0)) == SYMBOL_REF
- && GET_CODE (XEXP (exp, 1)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (exp, 0))
+ && SYMBOL_REF_P (XEXP (exp, 1)))
exp = attr_rtx (GET_CODE (exp),
attr_rtx (SYMBOL_REF, XSTR (XEXP (exp, 0), 0)),
attr_rtx (SYMBOL_REF, XSTR (XEXP (exp, 1), 0)));
@@ -892,7 +892,7 @@ check_attr_value (file_location loc, rtx exp, class attr_desc *attr)
}
for (av = attr->first_value; av; av = av->next)
- if (GET_CODE (av->value) == CONST_STRING
+ if (CONST_STRING_P (av->value)
&& ! strcmp (XSTR (av->value, 0), XSTR (exp, 0)))
break;
@@ -3101,7 +3101,7 @@ gen_attr (md_rtx_info *info)
add_attr_value (attr, p);
}
- if (GET_CODE (XEXP (def, 2)) == CONST)
+ if (CONST_P (XEXP (def, 2)))
{
attr->is_const = 1;
if (attr->is_numeric)
@@ -3715,7 +3715,7 @@ write_test_expr (FILE *outf, rtx exp, unsigned int attrs_cached, int flags,
/* The address of the branch target. */
case MATCH_DUP:
fprintf (outf,
- "INSN_ADDRESSES_SET_P () ? INSN_ADDRESSES (INSN_UID (GET_CODE (operands[%d]) == LABEL_REF ? XEXP (operands[%d], 0) : operands[%d])) : 0",
+ "INSN_ADDRESSES_SET_P () ? INSN_ADDRESSES (INSN_UID (LABEL_REF_P (operands[%d]) ? XEXP (operands[%d], 0) : operands[%d])) : 0",
XINT (exp, 0), XINT (exp, 0), XINT (exp, 0));
break;
@@ -5000,7 +5000,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (dfa_file,
"extern int internal_dfa_insn_code_%s (rtx_insn *);\n",
XSTR (val->value, 0));
@@ -5012,7 +5012,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (latency_file,
"extern int insn_default_latency_%s (rtx_insn *);\n",
XSTR (val->value, 0));
@@ -5024,7 +5024,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (attr_file,
"extern int internal_dfa_insn_code_%s (rtx_insn *);\n"
"extern int insn_default_latency_%s (rtx_insn *);\n",
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 556c4bdd869..1d9baea9f44 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -103,7 +103,7 @@ process_define_predicate (md_rtx_info *info)
(define_predicate "basereg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
})
@@ -112,7 +112,7 @@ process_define_predicate (md_rtx_info *info)
static inline int basereg_operand_1(rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
}
@@ -1247,14 +1247,14 @@ write_tm_constrs_h (void)
error ("you can't use lval or hval");
#else
if (needs_hval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode == VOIDmode)"
" hval = CONST_DOUBLE_HIGH (op);");
if (needs_lval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode == VOIDmode)"
" lval = CONST_DOUBLE_LOW (op);");
#endif
if (needs_rval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode != VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode != VOIDmode)"
" rval = CONST_DOUBLE_REAL_VALUE (op);");
write_predicate_stmts (c->exp);
diff --git a/gcc/genrecog.c b/gcc/genrecog.c
index f20089eeee8..82b00fde9ed 100644
--- a/gcc/genrecog.c
+++ b/gcc/genrecog.c
@@ -1687,7 +1687,7 @@ simplify_tests (state *s)
for (decision *d = s->first; d; d = d->next)
{
uint64_t label;
- /* Convert checks for GET_CODE (x) == CONST_INT and XWINT (x, 0) == N
+ /* Convert checks for CONST_INT_P (x) and XWINT (x, 0) == N
into checks for const_int_rtx[N'], if N is suitably small. */
if (d->test.kind == rtx_test::CODE
&& d->if_statement_p (&label)
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index 1aab7119901..8bdd0ae7502 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -683,7 +683,7 @@ is_predicable (class queue_elem *elem)
|| strcmp (XSTR (SET_DEST (sub), 0), "predicable") != 0)
break;
sub = SET_SRC (sub);
- if (GET_CODE (sub) == CONST_STRING)
+ if (CONST_STRING_P (sub))
{
value = XSTR (sub, 0);
goto found;
@@ -775,7 +775,7 @@ has_subst_attribute (class queue_elem *elem, class queue_elem *subst_elem)
|| strcmp (XSTR (SET_DEST (cur_attr), 0), subst_name) != 0)
break;
cur_attr = SET_SRC (cur_attr);
- if (GET_CODE (cur_attr) == CONST_STRING)
+ if (CONST_STRING_P (cur_attr))
{
value = XSTR (cur_attr, 0);
goto found;
@@ -1415,7 +1415,7 @@ alter_attrs_for_insn (rtx insn)
if (strcmp (XSTR (SET_DEST (sub), 0), "predicable") == 0)
{
sub = SET_SRC (sub);
- if (GET_CODE (sub) == CONST_STRING)
+ if (CONST_STRING_P (sub))
{
predicable_idx = i;
XSTR (sub, 0) = "ce_enabled";
@@ -3156,7 +3156,7 @@ needs_barrier_p (rtx x)
{
return (GET_CODE (x) == SET
&& GET_CODE (SET_DEST (x)) == PC
- && GET_CODE (SET_SRC (x)) == LABEL_REF);
+ && LABEL_REF_P (SET_SRC (x)));
}
#define NS "NULL"
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index e0c9522057a..a62b1265599 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -310,7 +310,7 @@ rtx_interchangeable_p (const_rtx a, const_rtx b)
if (!rtx_equal_p (a, b))
return false;
- if (GET_CODE (a) != MEM)
+ if (!MEM_P (a))
return true;
/* A dead type-unsafe memory reference is legal, but a live type-unsafe memory
@@ -438,7 +438,7 @@ cond_exec_get_condition (rtx_insn *jump)
/* If this branches to JUMP_LABEL when the condition is false,
reverse the condition. */
- if (GET_CODE (XEXP (test_if, 2)) == LABEL_REF
+ if (LABEL_REF_P (XEXP (test_if, 2))
&& label_ref_label (XEXP (test_if, 2)) == JUMP_LABEL (jump))
{
enum rtx_code rev = reversed_comparison_code (cond, jump);
@@ -832,7 +832,7 @@ noce_emit_store_flag (struct noce_if_info *if_info, rtx x, int reversep,
{
rtx set = pc_set (if_info->jump);
cond = XEXP (SET_SRC (set), 0);
- if (GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ if (LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (if_info->jump))
reversep = !reversep;
if (if_info->then_else_reversed)
@@ -905,7 +905,7 @@ noce_emit_move_insn (rtx x, rtx y)
start_sequence ();
/* Check that the SET_SRC is reasonable before calling emit_move_insn,
otherwise construct a suitable SET pattern ourselves. */
- insn = (OBJECT_P (y) || CONSTANT_P (y) || GET_CODE (y) == SUBREG)
+ insn = (OBJECT_P (y) || CONSTANT_P (y) || SUBREG_P (y))
? emit_move_insn (x, y)
: emit_insn (gen_rtx_SET (x, y));
seq = get_insns ();
@@ -1720,7 +1720,7 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code,
if (reload_completed)
return NULL_RTX;
- if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG)
+ if (SUBREG_P (vtrue) && SUBREG_P (vfalse))
{
rtx reg_vtrue = SUBREG_REG (vtrue);
rtx reg_vfalse = SUBREG_REG (vfalse);
@@ -2316,7 +2316,7 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
set = pc_set (if_info->jump);
cond = XEXP (SET_SRC (set), 0);
reverse
- = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ = LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (if_info->jump);
if (if_info->then_else_reversed)
reverse = !reverse;
@@ -2630,7 +2630,7 @@ noce_try_abs (struct noce_if_info *if_info)
return FALSE;
}
if (MEM_P (c)
- && GET_CODE (XEXP (c, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (c, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (c, 0)))
c = get_pool_constant (XEXP (c, 0));
@@ -2928,7 +2928,7 @@ noce_get_condition (rtx_insn *jump, rtx_insn **earliest, bool then_else_reversed
/* If this branches to JUMP_LABEL when the condition is false,
reverse the condition. */
- reverse = (GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ reverse = (LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump));
/* We may have to reverse because the caller's if block is not canonical,
@@ -3335,7 +3335,7 @@ bb_ok_for_noce_convert_multiple_sets (basic_block test_bb)
return false;
if (!(REG_P (src)
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& subreg_lowpart_p (src))))
return false;
@@ -3710,7 +3710,7 @@ check_cond_move_block (basic_block bb,
modified earlier in the block. */
if ((REG_P (src)
&& vals->get (src))
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& vals->get (SUBREG_REG (src))))
return FALSE;
diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
index 10673769958..58fcc5de017 100644
--- a/gcc/internal-fn.c
+++ b/gcc/internal-fn.c
@@ -658,7 +658,7 @@ expand_arith_overflow_result_store (tree lhs, rtx target,
static void
expand_ubsan_result_store (rtx target, rtx res)
{
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -2898,7 +2898,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
guarantee that the instruction will leave the upper bits of the
register in the state required by SUBREG_PROMOTED_SIGN. */
rtx dest = lhs_rtx;
- if (dest && GET_CODE (dest) == SUBREG && SUBREG_PROMOTED_VAR_P (dest))
+ if (dest && SUBREG_P (dest) && SUBREG_PROMOTED_VAR_P (dest))
dest = NULL_RTX;
create_output_operand (&ops[0], dest, insn_data[icode].operand[0].mode);
@@ -2926,7 +2926,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
If the return value has a nonintegral type, its mode must match
the instruction result. */
- if (GET_CODE (lhs_rtx) == SUBREG && SUBREG_PROMOTED_VAR_P (lhs_rtx))
+ if (SUBREG_P (lhs_rtx) && SUBREG_PROMOTED_VAR_P (lhs_rtx))
{
/* If this is a scalar in a register that is stored in a wider
mode than the declared mode, compute the result into its
diff --git a/gcc/ira-build.c b/gcc/ira-build.c
index c7457fa4431..200ed52ad55 100644
--- a/gcc/ira-build.c
+++ b/gcc/ira-build.c
@@ -1850,7 +1850,7 @@ create_insn_allocnos (rtx x, rtx outer, bool output_p)
if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
{
a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
- if (outer != NULL && GET_CODE (outer) == SUBREG)
+ if (outer != NULL && SUBREG_P (outer))
{
machine_mode wmode = GET_MODE (outer);
if (partial_subreg_p (ALLOCNO_WMODE (a), wmode))
diff --git a/gcc/ira-conflicts.c b/gcc/ira-conflicts.c
index 813a6d4103c..fc471bb8770 100644
--- a/gcc/ira-conflicts.c
+++ b/gcc/ira-conflicts.c
@@ -207,7 +207,7 @@ allocnos_conflict_for_copy_p (ira_allocno_t a1, ira_allocno_t a2)
/* Check that X is REG or SUBREG of REG. */
#define REG_SUBREG_P(x) \
- (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))))
+ (REG_P (x) || (SUBREG_P (x) && REG_P (SUBREG_REG (x))))
/* Return X if X is a REG, otherwise it should be SUBREG of REG and
the function returns the reg in this case. *OFFSET will be set to
@@ -220,7 +220,7 @@ go_through_subreg (rtx x, int *offset)
*offset = 0;
if (REG_P (x))
return x;
- ira_assert (GET_CODE (x) == SUBREG);
+ ira_assert (SUBREG_P (x));
reg = SUBREG_REG (x);
ira_assert (REG_P (reg));
if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index c7feaba3718..1838a0ea538 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1297,11 +1297,11 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& known_eq (GET_MODE_SIZE (GET_MODE (dest)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
dest = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& known_eq (GET_MODE_SIZE (GET_MODE (src)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
src = SUBREG_REG (src);
@@ -1404,7 +1404,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
{
memcpy (op_costs[i], init_cost, struct_costs_size);
- if (GET_CODE (recog_data.operand[i]) == SUBREG)
+ if (SUBREG_P (recog_data.operand[i]))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
if (MEM_P (recog_data.operand[i]))
@@ -1475,7 +1475,7 @@ scan_one_insn (rtx_insn *insn)
if (pat_code == USE || pat_code == CLOBBER)
{
rtx x = XEXP (PATTERN (insn), 0);
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
&& have_regs_of_mode[GET_MODE (x)])
ira_init_register_move_cost_if_necessary (GET_MODE (x));
@@ -1542,7 +1542,7 @@ scan_one_insn (rtx_insn *insn)
{
rtx op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/ira-emit.c b/gcc/ira-emit.c
index 255af307b3c..846dd5d501b 100644
--- a/gcc/ira-emit.c
+++ b/gcc/ira-emit.c
@@ -941,7 +941,7 @@ emit_move_list (move_t list, int freq)
if ((set = single_set (insn)) != NULL_RTX)
{
dest = SET_DEST (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
ira_assert (REG_P (dest));
regno = REGNO (dest);
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index 2029027125a..f1fae3c1ec7 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -416,7 +416,7 @@ mark_ref_live (df_ref ref)
rtx reg = DF_REF_REG (ref);
rtx orig_reg = reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -545,11 +545,11 @@ mark_ref_dead (df_ref def)
if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
- && (GET_CODE (orig_reg) != SUBREG
+ && (!SUBREG_P (orig_reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER
|| !read_modify_subreg_p (orig_reg)))
return;
@@ -573,7 +573,7 @@ make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
rtx orig_reg = reg;
ira_allocno_t a;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
@@ -646,7 +646,7 @@ check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
if (def_cl == NO_REGS)
return;
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
@@ -766,7 +766,7 @@ mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
{
rtx dreg = DF_REF_REG (def);
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
continue;
@@ -875,7 +875,7 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
{
op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == SCRATCH
@@ -934,7 +934,7 @@ process_single_reg_class_operands (bool in_p, int freq)
operand_a = NULL;
- if (GET_CODE (operand) == SUBREG)
+ if (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand)
@@ -1337,7 +1337,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
{
rtx ureg = DF_REF_REG (use);
- if (GET_CODE (ureg) == SUBREG)
+ if (SUBREG_P (ureg))
ureg = SUBREG_REG (ureg);
if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
continue;
diff --git a/gcc/ira.c b/gcc/ira.c
index c58daba6e79..9f7a72e3fe5 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -2206,7 +2206,7 @@ ira_bad_reload_regno_1 (int regno, rtx x)
enum reg_class pref;
/* We only deal with pseudo regs. */
- if (! x || GET_CODE (x) != REG)
+ if (! x || !REG_P (x))
return false;
x_regno = REGNO (x);
@@ -3323,7 +3323,7 @@ set_paradoxical_subreg (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
{
const_rtx subreg = *iter;
- if (GET_CODE (subreg) == SUBREG)
+ if (SUBREG_P (subreg))
{
const_rtx reg = SUBREG_REG (subreg);
if (REG_P (reg) && paradoxical_subreg_p (subreg))
@@ -3933,12 +3933,12 @@ indirect_jump_optimize (void)
rtx_insn *def_insn = DF_REF_INSN (def);
rtx lab = NULL_RTX;
rtx set = single_set (def_insn);
- if (set && GET_CODE (SET_SRC (set)) == LABEL_REF)
+ if (set && LABEL_REF_P (SET_SRC (set)))
lab = SET_SRC (set);
else
{
rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX);
- if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF)
+ if (eqnote && LABEL_REF_P (XEXP (eqnote, 0)))
lab = XEXP (eqnote, 0);
}
if (lab && validate_replace_rtx (SET_SRC (x), lab, insn))
@@ -4225,7 +4225,7 @@ build_insn_chain (void)
conservative and treat the definition as a partial
definition of the full register rather than a full
definition of a specific part of the register. */
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)
&& get_subreg_tracking_sizes (reg, &outer_size,
&inner_size, &start))
@@ -4321,7 +4321,7 @@ build_insn_chain (void)
|| pseudo_for_reload_consideration_p (regno))
{
HOST_WIDE_INT outer_size, inner_size, start;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (use,
DF_REF_SIGN_EXTRACT
| DF_REF_ZERO_EXTRACT)
diff --git a/gcc/jump.c b/gcc/jump.c
index ce5cee523c3..2ec071a6235 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -263,7 +263,7 @@ maybe_propagate_label_ref (rtx_insn *jump_insn, rtx_insn *prev_nonjump_insn)
if (label_set != NULL
/* The source must be the direct LABEL_REF, not a
PLUS, UNSPEC, IF_THEN_ELSE etc. */
- && GET_CODE (SET_SRC (label_set)) == LABEL_REF
+ && LABEL_REF_P (SET_SRC (label_set))
&& (rtx_equal_p (label_dest, pc_src)
|| (GET_CODE (pc_src) == IF_THEN_ELSE
&& (rtx_equal_p (label_dest, XEXP (pc_src, 1))
@@ -773,7 +773,7 @@ simplejump_p (const rtx_insn *insn)
return (JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (SET_DEST (PATTERN (insn))) == PC
- && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF);
+ && LABEL_REF_P (SET_SRC (PATTERN (insn))));
}
/* Return nonzero if INSN is a (possibly) conditional jump
@@ -792,15 +792,15 @@ condjump_p (const rtx_insn *insn)
return 0;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return 1;
else
return (GET_CODE (x) == IF_THEN_ELSE
&& ((GET_CODE (XEXP (x, 2)) == PC
- && (GET_CODE (XEXP (x, 1)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (x, 1))
|| ANY_RETURN_P (XEXP (x, 1))))
|| (GET_CODE (XEXP (x, 1)) == PC
- && (GET_CODE (XEXP (x, 2)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (x, 2))
|| ANY_RETURN_P (XEXP (x, 2))))));
}
@@ -824,16 +824,16 @@ condjump_in_parallel_p (const rtx_insn *insn)
return 0;
if (GET_CODE (SET_DEST (x)) != PC)
return 0;
- if (GET_CODE (SET_SRC (x)) == LABEL_REF)
+ if (LABEL_REF_P (SET_SRC (x)))
return 1;
if (GET_CODE (SET_SRC (x)) != IF_THEN_ELSE)
return 0;
if (XEXP (SET_SRC (x), 2) == pc_rtx
- && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (SET_SRC (x), 1))
|| ANY_RETURN_P (XEXP (SET_SRC (x), 1))))
return 1;
if (XEXP (SET_SRC (x), 1) == pc_rtx
- && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (SET_SRC (x), 2))
|| ANY_RETURN_P (XEXP (SET_SRC (x), 2))))
return 1;
return 0;
@@ -868,7 +868,7 @@ any_uncondjump_p (const rtx_insn *insn)
const_rtx x = pc_set (insn);
if (!x)
return 0;
- if (GET_CODE (SET_SRC (x)) != LABEL_REF)
+ if (!LABEL_REF_P (SET_SRC (x)))
return 0;
if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
return 0;
@@ -911,13 +911,13 @@ condjump_label (const rtx_insn *insn)
if (!x)
return NULL_RTX;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return x;
if (GET_CODE (x) != IF_THEN_ELSE)
return NULL_RTX;
- if (XEXP (x, 2) == pc_rtx && GET_CODE (XEXP (x, 1)) == LABEL_REF)
+ if (XEXP (x, 2) == pc_rtx && LABEL_REF_P (XEXP (x, 1)))
return XEXP (x, 1);
- if (XEXP (x, 1) == pc_rtx && GET_CODE (XEXP (x, 2)) == LABEL_REF)
+ if (XEXP (x, 1) == pc_rtx && LABEL_REF_P (XEXP (x, 2)))
return XEXP (x, 2);
return NULL_RTX;
}
@@ -1438,7 +1438,7 @@ redirect_exp_1 (rtx *loc, rtx olabel, rtx nlabel, rtx_insn *insn)
|| x == olabel)
{
x = redirect_target (nlabel);
- if (GET_CODE (x) == LABEL_REF && loc == &PATTERN (insn))
+ if (LABEL_REF_P (x) && loc == &PATTERN (insn))
x = gen_rtx_SET (pc_rtx, x);
validate_change (insn, loc, x, 1);
return;
@@ -1446,7 +1446,7 @@ redirect_exp_1 (rtx *loc, rtx olabel, rtx nlabel, rtx_insn *insn)
if (code == SET && SET_DEST (x) == pc_rtx
&& ANY_RETURN_P (nlabel)
- && GET_CODE (SET_SRC (x)) == LABEL_REF
+ && LABEL_REF_P (SET_SRC (x))
&& label_ref_label (SET_SRC (x)) == olabel)
{
validate_change (insn, loc, nlabel, 1);
@@ -1690,7 +1690,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int reg_x = -1, reg_y = -1;
@@ -1728,7 +1728,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
reg_x = reg_renumber[reg_x];
}
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
reg_y = REGNO (SUBREG_REG (y));
byte_y = SUBREG_BYTE (y);
@@ -1900,7 +1900,7 @@ true_regnum (const_rtx x)
return reg_renumber[REGNO (x)];
return REGNO (x);
}
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
int base = true_regnum (SUBREG_REG (x));
if (base >= 0
@@ -1924,7 +1924,7 @@ true_regnum (const_rtx x)
unsigned int
reg_or_subregno (const_rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
return REGNO (reg);
diff --git a/gcc/loop-doloop.c b/gcc/loop-doloop.c
index 0efe7b449ff..e30d17be3ef 100644
--- a/gcc/loop-doloop.c
+++ b/gcc/loop-doloop.c
@@ -190,7 +190,7 @@ doloop_condition_get (rtx_insn *doloop_pat)
if (GET_CODE (cmp) != SET
|| SET_DEST (cmp) != pc_rtx
|| GET_CODE (SET_SRC (cmp)) != IF_THEN_ELSE
- || GET_CODE (XEXP (SET_SRC (cmp), 1)) != LABEL_REF
+ || !LABEL_REF_P (XEXP (SET_SRC (cmp), 1))
|| XEXP (SET_SRC (cmp), 2) != pc_rtx)
return 0;
diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
index 644ecfc6fbb..a69eec6cda5 100644
--- a/gcc/loop-invariant.c
+++ b/gcc/loop-invariant.c
@@ -1269,7 +1269,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
/* Considered invariant insns have only one set. */
gcc_assert (set != NULL_RTX);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
@@ -1793,7 +1793,7 @@ move_invariant_reg (class loop *loop, unsigned invno)
need to create a temporary register. */
set = single_set (inv->insn);
reg = dest = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
regno = REGNO (reg);
@@ -2060,7 +2060,7 @@ static void
mark_reg_store (rtx reg, const_rtx setter ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c
index 2274cc3075b..5c39106170b 100644
--- a/gcc/loop-iv.c
+++ b/gcc/loop-iv.c
@@ -219,7 +219,7 @@ simple_reg_p (rtx reg)
{
unsigned r;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
if (!subreg_lowpart_p (reg))
return false;
@@ -338,7 +338,7 @@ iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def)
*def = NULL;
if (!simple_reg_p (reg))
return GRD_INVALID;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -680,7 +680,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
(set x':DI (plus:DI y:DI 1))
(set x:SI (subreg:SI (x':DI)). */
- if (GET_CODE (op0) != SUBREG)
+ if (!SUBREG_P (op0))
return false;
if (GET_MODE (SUBREG_REG (op0)) != outer_mode)
return false;
@@ -705,7 +705,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
return false;
}
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
if (!subreg_lowpart_p (next))
return false;
@@ -737,7 +737,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
outer_step))
return false;
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
scalar_int_mode amode;
if (!is_a <scalar_int_mode> (GET_MODE (next), &amode)
@@ -1119,7 +1119,7 @@ iv_analyze_op (rtx_insn *insn, scalar_int_mode mode, rtx op, class rtx_iv *iv)
if (function_invariant_p (op))
res = GRD_INVARIANT;
- else if (GET_CODE (op) == SUBREG)
+ else if (SUBREG_P (op))
{
scalar_int_mode inner_mode;
if (!subreg_lowpart_p (op)
@@ -1175,7 +1175,7 @@ iv_analyze (rtx_insn *insn, scalar_int_mode mode, rtx val, class rtx_iv *iv)
following insns. */
if (simple_reg_p (val))
{
- if (GET_CODE (val) == SUBREG)
+ if (SUBREG_P (val))
reg = SUBREG_REG (val);
else
reg = val;
@@ -1321,7 +1321,7 @@ altered_reg_used (const_rtx x, bitmap alt)
static void
mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt)
{
- if (GET_CODE (expr) == SUBREG)
+ if (SUBREG_P (expr))
expr = SUBREG_REG (expr);
if (!REG_P (expr))
return;
@@ -1502,7 +1502,7 @@ implies_p (rtx a, rtx b)
op1 = XEXP (a, 1);
if (REG_P (op0)
- || (GET_CODE (op0) == SUBREG
+ || (SUBREG_P (op0)
&& REG_P (SUBREG_REG (op0))))
{
rtx r = simplify_replace_rtx (b, op0, op1);
@@ -1511,7 +1511,7 @@ implies_p (rtx a, rtx b)
}
if (REG_P (op1)
- || (GET_CODE (op1) == SUBREG
+ || (SUBREG_P (op1)
&& REG_P (SUBREG_REG (op1))))
{
rtx r = simplify_replace_rtx (b, op1, op0);
diff --git a/gcc/loop-unroll.c b/gcc/loop-unroll.c
index 63fccd23fae..b75d13492c5 100644
--- a/gcc/loop-unroll.c
+++ b/gcc/loop-unroll.c
@@ -1419,7 +1419,7 @@ analyze_insn_to_expand_var (class loop *loop, rtx_insn *insn)
return NULL;
if (!REG_P (dest)
- && !(GET_CODE (dest) == SUBREG
+ && !(SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest))))
return NULL;
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index e1418e5ec51..9f8e194b403 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -300,16 +300,16 @@ init_lower_subreg (void)
static bool
simple_move_operand (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!OBJECT_P (x))
return false;
- if (GET_CODE (x) == LABEL_REF
- || GET_CODE (x) == SYMBOL_REF
+ if (LABEL_REF_P (x)
+ || SYMBOL_REF_P (x)
|| GET_CODE (x) == HIGH
- || GET_CODE (x) == CONST)
+ || CONST_P (x))
return false;
if (MEM_P (x)
@@ -492,7 +492,7 @@ find_decomposable_subregs (rtx *loc, enum classify_move_insn *pcmi)
FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
{
rtx x = *iter;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx inner = SUBREG_REG (x);
unsigned int regno, outer_size, inner_size, outer_words, inner_words;
@@ -698,7 +698,7 @@ simplify_gen_subreg_concatn (machine_mode outermode, rtx op,
If OP is a SUBREG of a CONCATN, then it must be a simple mode
change with the same size and offset 0, or it must extract a
part. We shouldn't see anything else here. */
- if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN)
+ if (SUBREG_P (op) && GET_CODE (SUBREG_REG (op)) == CONCATN)
{
rtx op2;
@@ -757,7 +757,7 @@ resolve_reg_p (rtx x)
static bool
resolve_subreg_p (rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
return resolve_reg_p (SUBREG_REG (x));
}
@@ -933,7 +933,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
}
}
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& resolve_reg_p (SUBREG_REG (src))
&& (maybe_ne (SUBREG_BYTE (src), 0)
|| maybe_ne (orig_size, GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))))
@@ -947,7 +947,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
/* Similarly if we are copying to a SUBREG of a decomposed reg where
the SUBREG is larger than word size. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& resolve_reg_p (SUBREG_REG (dest))
&& (maybe_ne (SUBREG_BYTE (dest), 0)
|| maybe_ne (orig_size,
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index f2584075937..65ccbf3798f 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -162,7 +162,7 @@ static int new_insn_uid_start;
static inline rtx *
strip_subreg (rtx *loc)
{
- return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
+ return loc && SUBREG_P (*loc) ? &SUBREG_REG (*loc) : loc;
}
/* Return hard regno of REGNO or if it is was not assigned to a hard
@@ -269,7 +269,7 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
&& curr_insn_set != NULL
&& ((OBJECT_P (SET_SRC (curr_insn_set))
&& ! CONSTANT_P (SET_SRC (curr_insn_set)))
- || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ || (SUBREG_P (SET_SRC (curr_insn_set))
&& OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
&& ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
/* When we don't know what class will be used finally for reload
@@ -601,7 +601,7 @@ get_reload_reg (enum op_type type, machine_mode mode, rtx original,
GET_MODE_SIZE (mode)))
continue;
reg = lowpart_subreg (mode, reg, GET_MODE (reg));
- if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
+ if (reg == NULL_RTX || !SUBREG_P (reg))
continue;
}
*result_reg = reg;
@@ -680,7 +680,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (x == y)
return true;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
+ && (REG_P (y) || (SUBREG_P (y) && REG_P (SUBREG_REG (y)))))
{
int j;
@@ -717,10 +717,10 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (code == REG && REG_P (y))
return REGNO (x) == REGNO (y);
- if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
+ if (code == REG && SUBREG_P (y) && REG_P (SUBREG_REG (y))
&& x == SUBREG_REG (y))
return true;
- if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
+ if (REG_P (y) && code == SUBREG && REG_P (SUBREG_REG (x))
&& SUBREG_REG (x) == y)
return true;
@@ -829,7 +829,7 @@ narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
registers for several reloads of one insn. */
if (INSN_UID (curr_insn) >= new_insn_uid_start)
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
return;
@@ -946,7 +946,7 @@ match_reload (signed char out, signed char *ins, signed char *outs,
rtx_insn *clobber = emit_clobber (new_out_reg);
LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
LRA_SUBREG_P (new_in_reg) = 1;
- if (GET_CODE (in_rtx) == SUBREG)
+ if (SUBREG_P (in_rtx))
{
rtx subreg_reg = SUBREG_REG (in_rtx);
@@ -1125,7 +1125,7 @@ emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
if (! MEM_P (val))
{
val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
- GET_CODE (val) == SUBREG
+ SUBREG_P (val)
? SUBREG_REG (val) : val);
LRA_SUBREG_P (val) = 1;
}
@@ -1156,9 +1156,9 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
lra_assert (curr_insn_set != NULL_RTX);
dreg = dest = SET_DEST (curr_insn_set);
sreg = src = SET_SRC (curr_insn_set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dreg = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
sreg = SUBREG_REG (src);
if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
return false;
@@ -1355,7 +1355,7 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
machine_mode mode;
bool subreg_p, before_p = false;
- subreg_p = GET_CODE (*loc) == SUBREG;
+ subreg_p = SUBREG_P (*loc);
if (subreg_p)
{
reg = SUBREG_REG (*loc);
@@ -1483,7 +1483,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode)
before = after = NULL;
- if (GET_CODE (operand) != SUBREG)
+ if (!SUBREG_P (operand))
return false;
mode = GET_MODE (operand);
@@ -1961,7 +1961,7 @@ process_alt_operands (int only_alternative)
operand_reg[nop] = reg = op;
biggest_mode[nop] = GET_MODE (op);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
biggest_mode[nop] = wider_subreg_mode (op);
operand_reg[nop] = reg = SUBREG_REG (op);
@@ -2600,7 +2600,7 @@ process_alt_operands (int only_alternative)
if (curr_static_id->operand[nop].strict_low
&& REG_P (op)
&& hard_regno[nop] < 0
- && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
+ && SUBREG_P (*curr_id->operand_loc[nop])
&& ira_class_hard_regs_num[this_alternative] > 0
&& (!targetm.hard_regno_mode_ok
(ira_class_hard_regs[this_alternative][0],
@@ -2904,7 +2904,7 @@ process_alt_operands (int only_alternative)
if (curr_insn_set != NULL_RTX && n_operands == 2
/* Prevent processing non-move insns. */
- && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ && (SUBREG_P (SET_SRC (curr_insn_set))
|| SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
&& ((! curr_alt_win[0] && ! curr_alt_win[1]
&& REG_P (no_subreg_reg_operand[0])
@@ -3338,7 +3338,7 @@ process_address_1 (int nop, bool check_only_p,
&& get_constraint_type (cn) == CT_FIXED_FORM
&& constraint_satisfied_p (op, cn)))
decompose_mem_address (&ad, op);
- else if (GET_CODE (op) == SUBREG
+ else if (SUBREG_P (op)
&& MEM_P (SUBREG_REG (op)))
decompose_mem_address (&ad, SUBREG_REG (op));
else
@@ -3886,7 +3886,7 @@ curr_insn_transform (bool check_only_p)
continue;
old = op = *curr_id->operand_loc[i];
- if (GET_CODE (old) == SUBREG)
+ if (SUBREG_P (old))
old = SUBREG_REG (old);
subst = get_equiv_with_elimination (old, curr_insn);
original_subreg_reg_mode[i] = VOIDmode;
@@ -3896,7 +3896,7 @@ curr_insn_transform (bool check_only_p)
equiv_substition_p[i] = true;
subst = copy_rtx (subst);
lra_assert (REG_P (old));
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
*curr_id->operand_loc[i] = subst;
else
{
@@ -4154,7 +4154,7 @@ curr_insn_transform (bool check_only_p)
enum reg_class new_class;
rtx reg = *curr_id->operand_loc[i];
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
@@ -4176,7 +4176,7 @@ curr_insn_transform (bool check_only_p)
rtx subreg = NULL_RTX;
machine_mode mode = curr_operand_mode[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4272,10 +4272,10 @@ curr_insn_transform (bool check_only_p)
&& (curr_insn_set == NULL_RTX
|| !((REG_P (SET_SRC (curr_insn_set))
|| MEM_P (SET_SRC (curr_insn_set))
- || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
+ || SUBREG_P (SET_SRC (curr_insn_set)))
&& (REG_P (SET_DEST (curr_insn_set))
|| MEM_P (SET_DEST (curr_insn_set))
- || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
+ || SUBREG_P (SET_DEST (curr_insn_set))))))
optional_p = true;
else if (goal_alt_matched[i][0] != -1
&& curr_static_id->operand[i].type == OP_OUT
@@ -4355,7 +4355,7 @@ curr_insn_transform (bool check_only_p)
loc = curr_id->operand_loc[i];
mode = curr_operand_mode[i];
- if (GET_CODE (*loc) == SUBREG)
+ if (SUBREG_P (*loc))
{
reg = SUBREG_REG (*loc);
poly_int64 byte = SUBREG_BYTE (*loc);
@@ -4485,7 +4485,7 @@ curr_insn_transform (bool check_only_p)
lra_assert (REG_P (reg));
regno = REGNO (reg);
op = *curr_id->operand_loc[i]; /* Substitution. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
@@ -4948,7 +4948,7 @@ lra_constraints (bool first_p)
/* The equivalence pseudo could be set up as SUBREG in a
case when it is a call restore insn in a mode
different from the pseudo mode. */
- if (GET_CODE (dest_reg) == SUBREG)
+ if (SUBREG_P (dest_reg))
dest_reg = SUBREG_REG (dest_reg);
if ((REG_P (dest_reg)
&& (x = get_equiv (dest_reg)) != dest_reg
@@ -6765,7 +6765,7 @@ fix_bb_live_info (bitmap live, bitmap removed_pseudos)
static int
get_regno (rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
return REGNO (reg);
@@ -6950,7 +6950,7 @@ remove_inheritance_pseudos (bitmap remove_pseudos)
&& (restore_rtx
= lra_reg_info[dregno].restore_rtx) != NULL_RTX)
{
- if (GET_CODE (SET_DEST (set)) == SUBREG)
+ if (SUBREG_P (SET_DEST (set)))
SUBREG_REG (SET_DEST (set)) = restore_rtx;
else
SET_DEST (set) = restore_rtx;
diff --git a/gcc/lra-eliminations.c b/gcc/lra-eliminations.c
index 943da888848..a4b21c79e5e 100644
--- a/gcc/lra-eliminations.c
+++ b/gcc/lra-eliminations.c
@@ -226,9 +226,9 @@ form_sum (rtx x, rtx y)
constant will have been placed second. */
if (CONSTANT_P (x) && CONSTANT_P (y))
{
- if (GET_CODE (x) == CONST)
+ if (CONST_P (x))
x = XEXP (x, 0);
- if (GET_CODE (y) == CONST)
+ if (CONST_P (y))
y = XEXP (y, 0);
return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));
@@ -287,7 +287,7 @@ move_plus_up (rtx x)
rtx subreg_reg;
machine_mode x_mode, subreg_reg_mode;
- if (GET_CODE (x) != SUBREG || !subreg_lowpart_p (x))
+ if (!SUBREG_P (x) || !subreg_lowpart_p (x))
return x;
subreg_reg = SUBREG_REG (x);
x_mode = GET_MODE (x);
@@ -932,7 +932,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -943,7 +943,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (ep = get_elimination (reg)) != NULL)
@@ -964,7 +964,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
}
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx);
/* If we have a nonzero offset, and the source is already a
simple REG, the following transformation would increase
diff --git a/gcc/lra.c b/gcc/lra.c
index d7593998f97..f7790f2e154 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -384,9 +384,9 @@ lra_emit_add (rtx x, rtx y, rtx z)
base = a1;
index = a2;
}
- if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
+ if ((base != NULL_RTX && ! (REG_P (base) || SUBREG_P (base)))
|| (index != NULL_RTX
- && ! (REG_P (index) || GET_CODE (index) == SUBREG))
+ && ! (REG_P (index) || SUBREG_P (index)))
|| (disp != NULL_RTX && ! CONSTANT_P (disp))
|| (scale != NULL_RTX && ! CONSTANT_P (scale)))
{
@@ -1459,7 +1459,7 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
code = GET_CODE (x);
mode = GET_MODE (x);
subreg_p = false;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
mode = wider_subreg_mode (x);
if (read_modify_subreg_p (x))
diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index 2ff21a40081..5e3bacb1e18 100644
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -212,7 +212,7 @@ reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -266,7 +266,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
&& EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
&& NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
&& GET_CODE (PATTERN (last_insn)) == USE
- && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
+ && REG_P ((ret_reg = XEXP (PATTERN (last_insn), 0))))
{
int ret_start = REGNO (ret_reg);
int nregs = REG_NREGS (ret_reg);
@@ -302,7 +302,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
case USE:
/* Skip USEs of multiple return registers.
__builtin_apply pattern is also handled here. */
- if (GET_CODE (XEXP (return_copy_pat, 0)) == REG
+ if (REG_P (XEXP (return_copy_pat, 0))
&& (targetm.calls.function_value_regno_p
(REGNO (XEXP (return_copy_pat, 0)))))
{
@@ -344,7 +344,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
the previous insn is the clobber for
the return register. */
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG
+ if (REG_P (copy_reg)
&& !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
{
if (INSN_P (PREV_INSN (return_copy)))
@@ -358,10 +358,10 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
}
}
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG)
+ if (REG_P (copy_reg))
copy_start = REGNO (copy_reg);
- else if (GET_CODE (copy_reg) == SUBREG
- && GET_CODE (SUBREG_REG (copy_reg)) == REG)
+ else if (SUBREG_P (copy_reg)
+ && REG_P (SUBREG_REG (copy_reg)))
copy_start = REGNO (SUBREG_REG (copy_reg));
else
{
diff --git a/gcc/modulo-sched.c b/gcc/modulo-sched.c
index c355594bb6b..4ebd514daed 100644
--- a/gcc/modulo-sched.c
+++ b/gcc/modulo-sched.c
@@ -1477,7 +1477,7 @@ sms_schedule (void)
&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
&& !reg_mentioned_p (count_reg, insn))
|| (INSN_P (insn) && (set = single_set (insn))
- && GET_CODE (SET_DEST (set)) == SUBREG))
+ && SUBREG_P (SET_DEST (set))))
break;
}
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 06bcaab1f55..77a58bdde2c 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -208,7 +208,7 @@ widen_operand (rtx op, machine_mode mode, machine_mode oldmode,
a promoted object differs from our extension. */
if (! no_extend
|| !is_a <scalar_int_mode> (mode, &int_mode)
- || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)
+ || (SUBREG_P (op) && SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_CHECK_PROMOTED_SIGN (op, unsignedp)))
return convert_modes (mode, oldmode, op, unsignedp);
@@ -5276,7 +5276,7 @@ debug_optab_libfuncs (void)
rtx l = optab_libfunc ((optab) i, (machine_mode) j);
if (l)
{
- gcc_assert (GET_CODE (l) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (l));
fprintf (stderr, "%s\t%s:\t%s\n",
GET_RTX_NAME (optab_to_code ((optab) i)),
GET_MODE_NAME (j),
@@ -5293,7 +5293,7 @@ debug_optab_libfuncs (void)
(machine_mode) k);
if (l)
{
- gcc_assert (GET_CODE (l) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (l));
fprintf (stderr, "%s\t%s\t%s:\t%s\n",
GET_RTX_NAME (optab_to_code ((optab) i)),
GET_MODE_NAME (j),
diff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c
index e4737670883..429a44a4762 100644
--- a/gcc/postreload-gcse.c
+++ b/gcc/postreload-gcse.c
@@ -618,7 +618,7 @@ find_mem_conflicts (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
rtx mem_op = (rtx) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -733,7 +733,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 728aa9b0ed5..7bdf04a5a56 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -1418,7 +1418,7 @@ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
int i;
machine_mode mode = GET_MODE (dst);
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
{
regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
GET_MODE (SUBREG_REG (dst)),
@@ -1670,7 +1670,7 @@ move2add_record_mode (rtx reg)
int regno, nregs;
machine_mode mode = GET_MODE (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno = subreg_regno (reg);
nregs = subreg_nregs (reg);
@@ -2053,16 +2053,16 @@ reload_cse_move2add (rtx_insn *first)
(set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
...
(set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
- if ((GET_CODE (src) == SYMBOL_REF
- || (GET_CODE (src) == CONST
+ if ((SYMBOL_REF_P (src)
+ || (CONST_P (src)
&& GET_CODE (XEXP (src, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (src, 0), 0))
&& CONST_INT_P (XEXP (XEXP (src, 0), 1))))
&& dbg_cnt (cse2_move2add))
{
rtx sym, off;
- if (GET_CODE (src) == SYMBOL_REF)
+ if (SYMBOL_REF_P (src))
{
sym = src;
off = const0_rtx;
@@ -2188,7 +2188,7 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
return;
}
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
regno = subreg_regno (dst);
else if (REG_P (dst))
regno = REGNO (dst);
@@ -2204,14 +2204,14 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
rtx off;
note = find_reg_equal_equiv_note (insn);
- if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
+ if (note && SYMBOL_REF_P (XEXP (note, 0)))
{
sym = XEXP (note, 0);
off = const0_rtx;
}
- else if (note && GET_CODE (XEXP (note, 0)) == CONST
+ else if (note && CONST_P (XEXP (note, 0))
&& GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (XEXP (note, 0), 0), 0))
&& CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
{
sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index 10948efddd9..53212ce878f 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -215,7 +215,7 @@ rtx_writer::print_rtx_operand_code_0 (const_rtx in_rtx ATTRIBUTE_UNUSED,
int idx ATTRIBUTE_UNUSED)
{
#ifndef GENERATOR_FILE
- if (idx == 1 && GET_CODE (in_rtx) == SYMBOL_REF)
+ if (idx == 1 && SYMBOL_REF_P (in_rtx))
{
int flags = SYMBOL_REF_FLAGS (in_rtx);
if (flags)
@@ -573,7 +573,7 @@ rtx_writer::print_rtx_operand_code_u (const_rtx in_rtx, int idx)
rtx sub = XEXP (in_rtx, idx);
enum rtx_code subc = GET_CODE (sub);
- if (GET_CODE (in_rtx) == LABEL_REF)
+ if (LABEL_REF_P (in_rtx))
{
if (subc == NOTE
&& NOTE_KIND (sub) == NOTE_INSN_DELETED_LABEL)
diff --git a/gcc/read-rtl-function.c b/gcc/read-rtl-function.c
index f41f54a0d4a..0a3f79c8c36 100644
--- a/gcc/read-rtl-function.c
+++ b/gcc/read-rtl-function.c
@@ -955,7 +955,7 @@ function_reader::read_rtx_operand_u (rtx x, int idx)
{
/* In compact mode, the PREV/NEXT insn uids are not dumped, so skip
the "uu" when reading. */
- if (is_compact () && GET_CODE (x) != LABEL_REF)
+ if (is_compact () && !LABEL_REF_P (x))
return;
struct md_name name;
@@ -1446,7 +1446,7 @@ ensure_regno (int regno)
static rtx
consolidate_reg (rtx x)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
unsigned int regno = REGNO (x);
@@ -1463,7 +1463,7 @@ consolidate_reg (rtx x)
if (regno_reg_rtx[regno] == NULL)
regno_reg_rtx[regno] = x;
/* Use it. */
- gcc_assert (GET_CODE (regno_reg_rtx[regno]) == REG);
+ gcc_assert (REG_P (regno_reg_rtx[regno]));
gcc_assert (REGNO (regno_reg_rtx[regno]) == regno);
if (GET_MODE (x) == GET_MODE (regno_reg_rtx[regno]))
return regno_reg_rtx[regno];
diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c
index 3b5d9997603..3dcf35b8f17 100644
--- a/gcc/read-rtl.c
+++ b/gcc/read-rtl.c
@@ -255,7 +255,7 @@ find_int (const char *name)
static void
apply_int_iterator (rtx x, unsigned int index, int value)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
SUBREG_BYTE (x) = value;
else
XINT (x, index) = value;
diff --git a/gcc/recog.c b/gcc/recog.c
index a9f584bc0dc..5b6e957b2b4 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -123,7 +123,7 @@ asm_labels_ok (rtx body)
return true;
for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
- if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
+ if (!LABEL_REF_P (ASM_OPERANDS_LABEL (asmop, i)))
return false;
return true;
@@ -1087,7 +1087,7 @@ address_operand (rtx op, machine_mode mode)
int
register_operand (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
rtx sub = SUBREG_REG (op);
@@ -1213,7 +1213,7 @@ const_scalar_int_operand (rtx op, machine_mode mode)
int
const_double_operand (rtx op, machine_mode mode)
{
- return (GET_CODE (op) == CONST_DOUBLE)
+ return (CONST_DOUBLE_P (op))
&& (GET_MODE (op) == mode || mode == VOIDmode);
}
#else
@@ -1360,7 +1360,7 @@ memory_operand (rtx op, machine_mode mode)
return 0;
inner = op;
- if (GET_CODE (inner) == SUBREG)
+ if (SUBREG_P (inner))
inner = SUBREG_REG (inner);
return (MEM_P (inner) && general_operand (op, mode));
@@ -1374,7 +1374,7 @@ indirect_operand (rtx op, machine_mode mode)
{
/* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
if (! reload_completed
- && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
+ && SUBREG_P (op) && MEM_P (SUBREG_REG (op)))
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
@@ -2603,7 +2603,7 @@ constrain_operands (int strict, alternative_mask alternatives)
if (UNARY_P (op))
op = XEXP (op, 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (REG_P (SUBREG_REG (op))
&& REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ree.c b/gcc/ree.c
index c63e1591ae3..ddd31ab6c06 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -268,7 +268,7 @@ update_reg_equal_equiv_notes (rtx_insn *insn, machine_mode new_mode,
rtx orig_src = XEXP (*loc, 0);
/* Update equivalency constants. Recall that RTL constants are
sign-extended. */
- if (GET_CODE (orig_src) == CONST_INT
+ if (CONST_INT_P (orig_src)
&& HWI_COMPUTABLE_MODE_P (new_mode))
{
if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
@@ -336,7 +336,7 @@ combine_set_extension (ext_cand *cand, rtx_insn *curr_insn, rtx *orig_set)
/* Merge constants by directly moving the constant into the register under
some conditions. Recall that RTL constants are sign-extended. */
- if (GET_CODE (orig_src) == CONST_INT
+ if (CONST_INT_P (orig_src)
&& HWI_COMPUTABLE_MODE_P (cand->mode))
{
if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
@@ -467,7 +467,7 @@ get_defs (rtx_insn *insn, rtx reg, vec<rtx_insn *> *dest)
FOR_EACH_INSN_USE (use, insn)
{
- if (GET_CODE (DF_REF_REG (use)) == SUBREG)
+ if (SUBREG_P (DF_REF_REG (use)))
return NULL;
if (REGNO (DF_REF_REG (use)) == REGNO (reg))
break;
@@ -541,10 +541,10 @@ is_cond_copy_insn (rtx_insn *insn, rtx *reg1, rtx *reg2)
if (expr != NULL_RTX
&& GET_CODE (expr) == SET
- && GET_CODE (SET_DEST (expr)) == REG
+ && REG_P (SET_DEST (expr))
&& GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG
- && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG)
+ && REG_P (XEXP (SET_SRC (expr), 1))
+ && REG_P (XEXP (SET_SRC (expr), 2)))
{
*reg1 = XEXP (SET_SRC (expr), 1);
*reg2 = XEXP (SET_SRC (expr), 2);
diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index 710f14a9544..45b0b35160a 100644
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -492,7 +492,7 @@ check_asm_stack_operands (rtx_insn *insn)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
@@ -510,7 +510,7 @@ check_asm_stack_operands (rtx_insn *insn)
rtx clobber = XVECEXP (body, 0, i);
rtx reg = XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
reg = SUBREG_REG (reg);
if (STACK_REG_P (reg))
@@ -908,7 +908,7 @@ emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg)
i1src = XEXP (i1src, 0);
if (REG_P (i1dest)
&& REGNO (i1dest) == FIRST_STACK_REG
- && (MEM_P (i1src) || GET_CODE (i1src) == CONST_DOUBLE)
+ && (MEM_P (i1src) || CONST_DOUBLE_P (i1src))
&& !side_effects_p (i1src)
&& hard_regno == FIRST_STACK_REG + 1
&& i1 != BB_HEAD (current_block))
@@ -949,7 +949,7 @@ emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg)
%st to %st(1), consider swapping them. */
if (REG_P (i2dest)
&& REGNO (i2dest) == FIRST_STACK_REG
- && (MEM_P (i2src) || GET_CODE (i2src) == CONST_DOUBLE)
+ && (MEM_P (i2src) || CONST_DOUBLE_P (i2src))
/* Ensure i2 doesn't have other side-effects. */
&& !side_effects_p (i2src)
/* And that the two instructions can actually be
@@ -2139,7 +2139,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
{
recog_data.operand_loc[i] = & SUBREG_REG (recog_data.operand[i]);
@@ -2163,7 +2163,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (note, 0);
rtx *loc = & XEXP (note, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
@@ -2196,7 +2196,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (clobber, 0);
rtx *loc = & XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
diff --git a/gcc/regcprop.c b/gcc/regcprop.c
index a18c24f4797..680cf15e719 100644
--- a/gcc/regcprop.c
+++ b/gcc/regcprop.c
@@ -189,7 +189,7 @@ kill_value_regno (unsigned int regno, unsigned int nregs,
static void
kill_value (const_rtx x, struct value_data *vd)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx tmp = simplify_subreg (GET_MODE (x), SUBREG_REG (x),
GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
@@ -541,13 +541,13 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reginfo.c b/gcc/reginfo.c
index 4832affd436..ebbdae1fb54 100644
--- a/gcc/reginfo.c
+++ b/gcc/reginfo.c
@@ -1109,7 +1109,7 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
case SET:
/* Count a set of the destination if it is a register. */
for (dest = SET_DEST (x);
- GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
+ SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART
|| GET_CODE (dest) == ZERO_EXTRACT;
dest = XEXP (dest, 0))
;
@@ -1143,22 +1143,22 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
&& CONST_INT_P (XEXP (SET_SRC (x), 1))
&& REG_P (XEXP (SET_SRC (x), 0))
&& REG_POINTER (XEXP (SET_SRC (x), 0)))
- || GET_CODE (SET_SRC (x)) == CONST
- || GET_CODE (SET_SRC (x)) == SYMBOL_REF
- || GET_CODE (SET_SRC (x)) == LABEL_REF
+ || CONST_P (SET_SRC (x))
+ || SYMBOL_REF_P (SET_SRC (x))
+ || LABEL_REF_P (SET_SRC (x))
|| (GET_CODE (SET_SRC (x)) == HIGH
- && (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
- || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
+ && (CONST_P (XEXP (SET_SRC (x), 0))
+ || SYMBOL_REF_P (XEXP (SET_SRC (x), 0))
+ || LABEL_REF_P (XEXP (SET_SRC (x), 0))))
|| ((GET_CODE (SET_SRC (x)) == PLUS
|| GET_CODE (SET_SRC (x)) == LO_SUM)
- && (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
- || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
- || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
+ && (CONST_P (XEXP (SET_SRC (x), 1))
+ || SYMBOL_REF_P (XEXP (SET_SRC (x), 1))
+ || LABEL_REF_P (XEXP (SET_SRC (x), 1))))
|| ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
- && (GET_CODE (XEXP (note, 0)) == CONST
- || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
+ && (CONST_P (XEXP (note, 0))
+ || SYMBOL_REF_P (XEXP (note, 0))
+ || LABEL_REF_P (XEXP (note, 0))))))
REG_POINTER (SET_DEST (x)) = 1;
/* If this is setting a register from a register or from a simple
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 73c0ceda341..0ce4d180880 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1055,7 +1055,7 @@ note_sets_clobbers (rtx x, const_rtx set, void *data)
enum rtx_code code = *(enum rtx_code *)data;
class du_head *chain;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!REG_P (x) || GET_CODE (set) != code)
return;
@@ -1088,8 +1088,8 @@ scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions act
a single output. */
if (recog_data.n_operands == 2
&& GET_CODE (pat) == SET
- && GET_CODE (SET_DEST (pat)) == REG
- && GET_CODE (SET_SRC (pat)) == REG
+ && REG_P (SET_DEST (pat))
+ && REG_P (SET_SRC (pat))
&& terminated_this_insn
&& terminated_this_insn->nregs
== REG_NREGS (recog_data.operand[1]))
@@ -1291,13 +1291,13 @@ scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reload.c b/gcc/reload.c
index 72cc38a0e09..fa26e017766 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -840,7 +840,7 @@ reload_inner_reg_of_subreg (rtx x, machine_mode mode, bool output)
rtx inner;
/* Only SUBREGs are problematical. */
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
inner = SUBREG_REG (x);
@@ -1051,7 +1051,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
no choice, so we hope we do get the right register class there. */
scalar_int_mode inner_mode;
- if (in != 0 && GET_CODE (in) == SUBREG
+ if (in != 0 && SUBREG_P (in)
&& (subreg_lowpart_p (in) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (in)),
inmode, rclass)
@@ -1149,7 +1149,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
entitled to clobber it all (except in the case of a word mode subreg
or of a STRICT_LOW_PART, in that latter case the constraint should
label it input-output.) */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& (subreg_lowpart_p (out) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (out)),
outmode, rclass)
@@ -1232,13 +1232,13 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
/* If IN is a SUBREG of a hard register, make a new REG. This
simplifies some of the cases below. */
- if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
+ if (in != 0 && SUBREG_P (in) && REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
/* Similarly for OUT. */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
@@ -1270,12 +1270,12 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
#ifdef LIMIT_RELOAD_CLASS
if (in_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (inmode, rclass);
- else if (in != 0 && GET_CODE (in) == SUBREG)
+ else if (in != 0 && SUBREG_P (in))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass);
if (out_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (outmode, rclass);
- if (out != 0 && GET_CODE (out) == SUBREG)
+ if (out != 0 && SUBREG_P (out))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass);
#endif
@@ -1351,7 +1351,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (subreg_in_class == NO_REGS
&& in != 0
&& (REG_P (in)
- || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
+ || (SUBREG_P (in) && REG_P (SUBREG_REG (in))))
&& reg_or_subregno (in) < FIRST_PSEUDO_REGISTER)
subreg_in_class = REGNO_REG_CLASS (reg_or_subregno (in));
/* If a memory location is needed for the copy, make one. */
@@ -1383,7 +1383,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (out != 0
&& (REG_P (out)
- || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
+ || (SUBREG_P (out) && REG_P (SUBREG_REG (out))))
&& reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
&& (targetm.secondary_memory_needed
(outmode, rclass, REGNO_REG_CLASS (reg_or_subregno (out)))))
@@ -1597,7 +1597,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
Is there any simple coherent way to describe the two together?
What's going on here. */
&& (in != out
- || (GET_CODE (in) == SUBREG
+ || (SUBREG_P (in)
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (in)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))),
@@ -1951,7 +1951,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
respectively refers to a hard register. */
/* Find the inside of any subregs. */
- while (GET_CODE (out) == SUBREG)
+ while (SUBREG_P (out))
{
if (REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
@@ -1961,7 +1961,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
GET_MODE (out));
out = SUBREG_REG (out);
}
- while (GET_CODE (in) == SUBREG)
+ while (SUBREG_P (in))
{
if (REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
@@ -2134,7 +2134,7 @@ hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
{
rtx op0 = SET_DEST (x);
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
op0 = SUBREG_REG (op0);
if (REG_P (op0))
{
@@ -2204,7 +2204,7 @@ operands_match_p (rtx x, rtx y)
if (x == y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int j;
@@ -2222,7 +2222,7 @@ operands_match_p (rtx x, rtx y)
else
i = REGNO (x);
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
j = REGNO (SUBREG_REG (y));
if (j >= FIRST_PSEUDO_REGISTER)
@@ -2408,7 +2408,7 @@ decompose (rtx x)
}
}
- if (GET_CODE (addr) == CONST)
+ if (CONST_P (addr))
{
addr = XEXP (addr, 0);
all_const = 1;
@@ -2432,7 +2432,7 @@ decompose (rtx x)
base = addr;
offset = const0_rtx;
}
- if (GET_CODE (offset) == CONST)
+ if (CONST_P (offset))
offset = XEXP (offset, 0);
if (GET_CODE (offset) == PLUS)
{
@@ -2836,7 +2836,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we now have a simple operand where we used to have a
PLUS or MULT, re-recognize and try again. */
if ((OBJECT_P (*recog_data.operand_loc[i])
- || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ || SUBREG_P (*recog_data.operand_loc[i]))
&& (GET_CODE (recog_data.operand[i]) == MULT
|| GET_CODE (recog_data.operand[i]) == PLUS))
{
@@ -3073,7 +3073,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
the REG or MEM (or maybe even a constant) within.
(Constants can occur as a result of reg_equiv_constant.) */
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
{
/* Offset only matters when operand is a REG and
it is a hard reg. This is because it is passed
@@ -3692,7 +3692,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
it's costly to reload it, so reload the input instead. */
if (small_register_class_p (this_alternative[i])
&& (REG_P (recog_data.operand[j])
- || GET_CODE (recog_data.operand[j]) == SUBREG))
+ || SUBREG_P (recog_data.operand[j])))
{
losers++;
this_alternative_win[j] = 0;
@@ -3907,7 +3907,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* Reloads of SUBREGs of CONSTANT RTXs are handled later in
push_reload so we have to let them pass here. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4086,7 +4086,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -4136,7 +4136,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
{
operand = *recog_data.operand_loc[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand))
{
@@ -4163,7 +4163,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -4200,7 +4200,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we're replacing an operand with a LABEL_REF, we need to
make sure that there's a REG_LABEL_OPERAND note attached to
this instruction. */
- if (GET_CODE (substitution) == LABEL_REF
+ if (LABEL_REF_P (substitution)
&& !find_reg_note (insn, REG_LABEL_OPERAND,
label_ref_label (substitution))
/* For a JUMP_P, if it was a branch target it must have
@@ -5035,7 +5035,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
taken care of above. */
if (ind_levels == 0
- || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
+ || (SYMBOL_REF_P (XEXP (tem, 0)) && ! indirect_symref_ok)
|| MEM_P (XEXP (tem, 0))
|| ! (REG_P (XEXP (tem, 0))
|| (GET_CODE (XEXP (tem, 0)) == PLUS
@@ -5229,7 +5229,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
/* If AD is an address in the constant pool, the MEM rtx may be shared.
Unshare it so we can safely alter it. */
- if (memrefloc && GET_CODE (ad) == SYMBOL_REF
+ if (memrefloc && SYMBOL_REF_P (ad)
&& CONSTANT_POOL_ADDRESS_P (ad))
{
*memrefloc = copy_rtx (*memrefloc);
@@ -5350,9 +5350,9 @@ form_sum (machine_mode mode, rtx x, rtx y)
constant will have been placed second. */
if (CONSTANT_P (x) && CONSTANT_P (y))
{
- if (GET_CODE (x) == CONST)
+ if (CONST_P (x))
x = XEXP (x, 0);
- if (GET_CODE (y) == CONST)
+ if (CONST_P (y))
y = XEXP (y, 0);
return gen_rtx_CONST (VOIDmode, gen_rtx_PLUS (mode, x, y));
@@ -5505,7 +5505,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
rtx op0 = orig_op0;
rtx op1 = orig_op1;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
@@ -5518,7 +5518,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
GET_MODE (orig_op0))));
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
@@ -6266,7 +6266,7 @@ subst_reloads (rtx_insn *insn)
/* If we're replacing a LABEL_REF with a register, there must
already be an indication (to e.g. flow) which label this
register refers to. */
- gcc_assert (GET_CODE (*r->where) != LABEL_REF
+ gcc_assert (!LABEL_REF_P (*r->where)
|| !JUMP_P (insn)
|| find_reg_note (insn,
REG_LABEL_OPERAND,
@@ -6362,7 +6362,7 @@ find_replacement (rtx *loc)
return reloadreg;
}
- else if (reloadreg && GET_CODE (*loc) == SUBREG
+ else if (reloadreg && SUBREG_P (*loc)
&& r->where == &SUBREG_REG (*loc))
{
if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
@@ -6455,7 +6455,7 @@ refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -6531,9 +6531,9 @@ reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
/* If either argument is a constant, then modifying X cannot affect IN. */
if (CONSTANT_P (x) || CONSTANT_P (in))
return 0;
- else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ else if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
return refers_to_mem_for_reload_p (in);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
regno = REGNO (SUBREG_REG (x));
if (regno < FIRST_PSEUDO_REGISTER)
@@ -6942,7 +6942,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
{
rtx dest = SET_DEST (pat);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -6981,7 +6981,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
{
rtx dest = SET_DEST (v1);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 38ee356a791..d30badc0c4f 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2436,13 +2436,13 @@ set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
case IF_THEN_ELSE:
tem = XEXP (SET_SRC (x), 1);
- if (GET_CODE (tem) == LABEL_REF)
+ if (LABEL_REF_P (tem))
set_label_offsets (label_ref_label (tem), insn, initial_p);
else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
break;
tem = XEXP (SET_SRC (x), 2);
- if (GET_CODE (tem) == LABEL_REF)
+ if (LABEL_REF_P (tem))
set_label_offsets (label_ref_label (tem), insn, initial_p);
else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
break;
@@ -2850,7 +2850,7 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
|| known_eq (x_size, new_size))
)
return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
- else if (insn && GET_CODE (insn) == DEBUG_INSN)
+ else if (insn && DEBUG_INSN_P (insn))
return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
else
return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
@@ -3270,7 +3270,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
if (plus_cst_src)
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -3282,7 +3282,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
rtx reg = XEXP (plus_cst_src, 0);
poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
@@ -3292,7 +3292,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
offset += ep->offset;
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
to_rtx);
/* If we have a nonzero offset, and the source is already
@@ -3721,7 +3721,7 @@ mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
/* A SUBREG of a hard register here is just changing its mode. We should
not see a SUBREG of an eliminable hard register, but check just in
case. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (dest == hard_frame_pointer_rtx)
@@ -4422,7 +4422,7 @@ strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
rather than simplifying it to another hard register, then the
mode change cannot be properly represented. For example, OTHER
might be valid in its current mode, but not in the new one. */
- if (GET_CODE (tem) == SUBREG
+ if (SUBREG_P (tem)
&& REG_P (other)
&& HARD_REGISTER_P (other))
return false;
@@ -4829,7 +4829,7 @@ forget_old_reloads_1 (rtx x, const_rtx setter,
/* note_stores does give us subregs of hard regs,
subreg_regno_offset requires a hard reg. */
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
{
/* We ignore the subreg offset when calculating the regno,
because we are using the entire underlying hard register
@@ -5589,10 +5589,10 @@ gen_reload_chain_without_interm_reg_p (int r1, int r2)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -5994,7 +5994,7 @@ function_invariant_p (const_rtx x)
return 1;
if (GET_CODE (x) == PLUS
&& (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 1)))
return 1;
return 0;
}
@@ -6281,7 +6281,7 @@ choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
static rtx
replaced_subreg (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
return find_replacement (&SUBREG_REG (x));
return x;
}
@@ -6467,7 +6467,7 @@ choose_reload_regs (class insn_chain *chain)
regno = REGNO (rld[r].in_reg);
mode = GET_MODE (rld[r].in_reg);
}
- else if (GET_CODE (rld[r].in_reg) == SUBREG
+ else if (SUBREG_P (rld[r].in_reg)
&& REG_P (SUBREG_REG (rld[r].in_reg)))
{
regno = REGNO (SUBREG_REG (rld[r].in_reg));
@@ -6493,7 +6493,7 @@ choose_reload_regs (class insn_chain *chain)
/* This won't work, since REGNO can be a pseudo reg number.
Also, it takes much more hair to keep track of all the things
that can invalidate an inherited reload of part of a pseudoreg. */
- else if (GET_CODE (rld[r].in) == SUBREG
+ else if (SUBREG_P (rld[r].in)
&& REG_P (SUBREG_REG (rld[r].in)))
regno = subreg_regno (rld[r].in);
#endif
@@ -6663,7 +6663,7 @@ choose_reload_regs (class insn_chain *chain)
Make a new REG since this might be used in an
address and not all machines support SUBREGs
there. */
- gcc_assert (GET_CODE (equiv) == SUBREG);
+ gcc_assert (SUBREG_P (equiv));
regno = subreg_regno (equiv);
equiv = gen_rtx_REG (rld[r].mode, regno);
/* If we choose EQUIV as the reload register, but the
@@ -6914,7 +6914,7 @@ choose_reload_regs (class insn_chain *chain)
check_reg = rld[r].reg_rtx;
else if (reload_override_in[r]
&& (REG_P (reload_override_in[r])
- || GET_CODE (reload_override_in[r]) == SUBREG))
+ || SUBREG_P (reload_override_in[r])))
check_reg = reload_override_in[r];
else
continue;
@@ -7131,7 +7131,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
determine whether a secondary reload is needed. */
if (reload_override_in[j]
&& (REG_P (rl->in_reg)
- || (GET_CODE (rl->in_reg) == SUBREG
+ || (SUBREG_P (rl->in_reg)
&& REG_P (SUBREG_REG (rl->in_reg)))))
{
oldequiv = old;
@@ -7141,7 +7141,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
oldequiv = old;
else if (REG_P (oldequiv))
oldequiv_reg = oldequiv;
- else if (GET_CODE (oldequiv) == SUBREG)
+ else if (SUBREG_P (oldequiv))
oldequiv_reg = SUBREG_REG (oldequiv);
reloadreg = reload_reg_rtx_for_input[j];
@@ -7163,7 +7163,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
/* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
OLDEQUIV. */
- while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
+ while (SUBREG_P (oldequiv) && GET_MODE (oldequiv) != mode)
oldequiv = SUBREG_REG (oldequiv);
if (GET_MODE (oldequiv) != VOIDmode
&& mode != GET_MODE (oldequiv))
@@ -7342,7 +7342,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
not in the right mode. */
tmp = oldequiv;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7351,14 +7351,14 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (oldequiv) == SUBREG)
+ || SUBREG_P (oldequiv))
real_oldequiv = rl->in;
else
real_oldequiv = reg_equiv_mem (REGNO (tmp));
}
tmp = old;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7367,7 +7367,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (old) == SUBREG)
+ || SUBREG_P (old))
real_old = rl->in;
else
real_old = reg_equiv_mem (REGNO (tmp));
@@ -7542,7 +7542,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
&& REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
&& (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
|| reg_equiv_constant (REGNO (oldequiv)) != 0))
- || (GET_CODE (oldequiv) == SUBREG
+ || (SUBREG_P (oldequiv)
&& REG_P (SUBREG_REG (oldequiv))
&& (REGNO (SUBREG_REG (oldequiv))
>= FIRST_PSEUDO_REGISTER)
@@ -7949,7 +7949,7 @@ do_output_reload (class insn_chain *chain, struct reload *rl, int j)
return;
}
/* Likewise for a SUBREG of an operand that dies. */
- else if (GET_CODE (old) == SUBREG
+ else if (SUBREG_P (old)
&& REG_P (SUBREG_REG (old))
&& (note = find_reg_note (insn, REG_UNUSED,
SUBREG_REG (old))) != 0)
@@ -8098,7 +8098,7 @@ emit_reload_insns (class insn_chain *chain)
{
rtx reg = rld[r].in_reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg)
@@ -8507,10 +8507,10 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -8569,7 +8569,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
code = optab_handler (add_optab, GET_MODE (out));
- if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
+ if (CONSTANT_P (op1) || MEM_P (op1) || SUBREG_P (op1)
|| (REG_P (op1)
&& REGNO (op1) >= FIRST_PSEUDO_REGISTER)
|| (code != CODE_FOR_nothing
@@ -8661,7 +8661,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
fatal_insn ("failure trying to reload:", set);
}
/* If IN is a simple operand, use gen_move_insn. */
- else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
+ else if (OBJECT_P (in) || SUBREG_P (in))
{
tem = emit_insn (gen_move_insn (out, in));
/* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
@@ -8714,7 +8714,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
/* Get the raw pseudo-register referred to. */
- while (GET_CODE (reg) == SUBREG)
+ while (SUBREG_P (reg))
reg = SUBREG_REG (reg);
substed = reg_equiv_memory_loc (REGNO (reg));
@@ -8731,7 +8731,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
reg2 = XEXP (rld[k].in_reg, 0);
- while (GET_CODE (reg2) == SUBREG)
+ while (SUBREG_P (reg2))
reg2 = SUBREG_REG (reg2);
if (rtx_equal_p (reg2, reg))
{
diff --git a/gcc/reorg.c b/gcc/reorg.c
index bdfcf8851cd..4ec3d7efea6 100644
--- a/gcc/reorg.c
+++ b/gcc/reorg.c
@@ -894,19 +894,19 @@ get_branch_condition (const rtx_insn *insn, rtx target)
return 0;
src = SET_SRC (pat);
- if (GET_CODE (src) == LABEL_REF && label_ref_label (src) == target)
+ if (LABEL_REF_P (src) && label_ref_label (src) == target)
return const_true_rtx;
else if (GET_CODE (src) == IF_THEN_ELSE
&& XEXP (src, 2) == pc_rtx
- && ((GET_CODE (XEXP (src, 1)) == LABEL_REF
+ && ((LABEL_REF_P (XEXP (src, 1))
&& label_ref_label (XEXP (src, 1)) == target)
|| (ANY_RETURN_P (XEXP (src, 1)) && XEXP (src, 1) == target)))
return XEXP (src, 0);
else if (GET_CODE (src) == IF_THEN_ELSE
&& XEXP (src, 1) == pc_rtx
- && ((GET_CODE (XEXP (src, 2)) == LABEL_REF
+ && ((LABEL_REF_P (XEXP (src, 2))
&& label_ref_label (XEXP (src, 2)) == target)
|| (ANY_RETURN_P (XEXP (src, 2)) && XEXP (src, 2) == target)))
{
@@ -1510,7 +1510,7 @@ redundant_insn (rtx insn, rtx_insn *target, const vec<rtx_insn *> &delay_list)
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (pat))
@@ -1609,7 +1609,7 @@ redundant_insn (rtx insn, rtx_insn *target, const vec<rtx_insn *> &delay_list)
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (pat))
@@ -2047,7 +2047,7 @@ fill_simple_delay_slots (int non_jumps_p)
continue;
/* And DEBUG_INSNs never go into delay slots. */
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* Check for resource conflict first, to avoid unnecessary
@@ -2174,7 +2174,7 @@ fill_simple_delay_slots (int non_jumps_p)
continue;
/* And DEBUG_INSNs do not go in delay slots. */
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* If this already has filled delay slots, get the insn needing
@@ -2442,7 +2442,7 @@ fill_slots_from_thread (rtx_jump_insn *insn, rtx condition,
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* If TRIAL conflicts with the insns ahead of it, we lose. Also,
diff --git a/gcc/resource.c b/gcc/resource.c
index c4bcfd7dc71..3c3d6a1c6e4 100644
--- a/gcc/resource.c
+++ b/gcc/resource.c
@@ -90,10 +90,10 @@ update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
int i;
if (!REG_P (dest)
- && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest))))
+ && (!SUBREG_P (dest) || !REG_P (SUBREG_REG (dest))))
return;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
{
first_regno = subreg_regno (dest);
last_regno = first_regno + subreg_nregs (dest);
@@ -291,7 +291,7 @@ mark_referenced_resources (rtx x, struct resources *res,
if (GET_CODE (x) == ZERO_EXTRACT
|| GET_CODE (x) == STRICT_LOW_PART)
mark_referenced_resources (x, res, false);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
x = SUBREG_REG (x);
if (MEM_P (x))
mark_referenced_resources (XEXP (x, 0), res, false);
diff --git a/gcc/rtl.c b/gcc/rtl.c
index d7b8e9877c3..a1181d1f32e 100644
--- a/gcc/rtl.c
+++ b/gcc/rtl.c
@@ -205,7 +205,7 @@ rtx_size (const_rtx x)
return (RTX_HDR_SIZE
+ sizeof (struct const_poly_int_def)
+ CONST_POLY_INT_COEFFS (x).extra_size ());
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_HAS_BLOCK_INFO_P (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_HAS_BLOCK_INFO_P (x))
return RTX_HDR_SIZE + sizeof (struct block_symbol);
return RTX_CODE_SIZE (GET_CODE (x));
}
@@ -266,13 +266,13 @@ cwi_output_hex (FILE *outfile, const_rtx x)
bool
shared_const_p (const_rtx orig)
{
- gcc_assert (GET_CODE (orig) == CONST);
+ gcc_assert (CONST_P (orig));
/* CONST can be shared if it contains a SYMBOL_REF. If it contains
a LABEL_REF, it isn't sharable. */
poly_int64 offset;
return (GET_CODE (XEXP (orig, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (orig, 0), 0))
&& poly_int_rtx_p (XEXP (XEXP (orig, 0), 1), &offset));
}
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 268a38799d6..a1f9146b7e3 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -649,7 +649,7 @@ rtx_addr_can_trap_p_1 (const_rtx x, poly_int64 offset, poly_int64 size,
/* An address is assumed not to trap if:
- it is the pic register plus a const unspec without offset. */
if (XEXP (x, 0) == pic_offset_table_rtx
- && GET_CODE (XEXP (x, 1)) == CONST
+ && CONST_P (XEXP (x, 1))
&& GET_CODE (XEXP (XEXP (x, 1), 0)) == UNSPEC
&& known_eq (offset, 0))
return 0;
@@ -832,7 +832,7 @@ get_call_rtx_from (rtx x)
HOST_WIDE_INT
get_integer_term (const_rtx x)
{
- if (GET_CODE (x) == CONST)
+ if (CONST_P (x))
x = XEXP (x, 0);
if (GET_CODE (x) == MINUS
@@ -851,7 +851,7 @@ get_integer_term (const_rtx x)
rtx
get_related_value (const_rtx x)
{
- if (GET_CODE (x) != CONST)
+ if (!CONST_P (x))
return 0;
x = XEXP (x, 0);
if (GET_CODE (x) == PLUS
@@ -871,7 +871,7 @@ offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
{
tree decl;
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return false;
if (offset == 0)
@@ -904,7 +904,7 @@ offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
void
split_const (rtx x, rtx *base_out, rtx *offset_out)
{
- if (GET_CODE (x) == CONST)
+ if (CONST_P (x))
{
x = XEXP (x, 0);
if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
@@ -927,7 +927,7 @@ strip_offset (rtx x, poly_int64_pod *offset_out)
{
rtx base = const0_rtx;
rtx test = x;
- if (GET_CODE (test) == CONST)
+ if (CONST_P (test))
test = XEXP (test, 0);
if (GET_CODE (test) == PLUS)
{
@@ -1027,7 +1027,7 @@ unsigned_reg_p (rtx op)
&& TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
return true;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_SIGN (op))
return true;
@@ -1052,7 +1052,7 @@ reg_mentioned_p (const_rtx reg, const_rtx in)
if (reg == in)
return 1;
- if (GET_CODE (in) == LABEL_REF)
+ if (LABEL_REF_P (in))
return reg == label_ref_label (in);
code = GET_CODE (in);
@@ -1155,7 +1155,7 @@ reg_referenced_p (const_rtx x, const_rtx body)
if (GET_CODE (SET_DEST (body)) != CC0
&& GET_CODE (SET_DEST (body)) != PC
&& !REG_P (SET_DEST (body))
- && ! (GET_CODE (SET_DEST (body)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (body))
&& REG_P (SUBREG_REG (SET_DEST (body)))
&& !read_modify_subreg_p (SET_DEST (body)))
&& reg_overlap_mentioned_p (x, SET_DEST (body)))
@@ -1401,7 +1401,7 @@ modified_in_p (const_rtx x, const_rtx insn)
bool
read_modify_subreg_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x));
@@ -1606,7 +1606,7 @@ set_noop_p (const_rtx set)
if (GET_CODE (dst) == STRICT_LOW_PART)
dst = XEXP (dst, 0);
- if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (src) && SUBREG_P (dst))
{
if (maybe_ne (SUBREG_BYTE (src), SUBREG_BYTE (dst)))
return 0;
@@ -1748,7 +1748,7 @@ refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -1912,7 +1912,7 @@ note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data)
{
rtx dest = SET_DEST (x);
- while ((GET_CODE (dest) == SUBREG
+ while ((SUBREG_P (dest)
&& (!REG_P (SUBREG_REG (dest))
|| REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
|| GET_CODE (dest) == ZERO_EXTRACT
@@ -2010,7 +2010,7 @@ note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
(*fun) (&XEXP (dest, 2), data);
}
- while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
+ while (SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
if (MEM_P (dest))
@@ -2072,7 +2072,7 @@ covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
{
unsigned int regno, endregno;
- if (GET_CODE (dest) == SUBREG && !read_modify_subreg_p (dest))
+ if (SUBREG_P (dest) && !read_modify_subreg_p (dest))
dest = SUBREG_REG (dest);
if (!REG_P (dest))
@@ -2850,7 +2850,7 @@ may_trap_p_1 (const_rtx x, unsigned flags)
return flag_trapping_math;
if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
return 1;
- if (GET_CODE (XEXP (x, 1)) == CONST_VECTOR)
+ if (CONST_VECTOR_P (XEXP (x, 1)))
{
/* For CONST_VECTOR, return 1 if any element is or might be zero. */
unsigned int n_elts;
@@ -3090,7 +3090,7 @@ replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
gcc_assert (GET_MODE (x) == GET_MODE (from));
return to;
}
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to, all_regs);
@@ -3177,7 +3177,7 @@ replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
rtx *loc = *iter;
if (rtx x = *loc)
{
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& CONSTANT_POOL_ADDRESS_P (x))
{
rtx c = get_pool_constant (x);
@@ -3196,7 +3196,7 @@ replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
}
}
- if ((GET_CODE (x) == LABEL_REF
+ if ((LABEL_REF_P (x)
|| GET_CODE (x) == INSN_LIST)
&& XEXP (x, 0) == old_label)
{
@@ -3230,7 +3230,7 @@ rtx_referenced_p (const_rtx x, const_rtx body)
if (const_rtx y = *iter)
{
/* Check if a label_ref Y refers to label X. */
- if (GET_CODE (y) == LABEL_REF
+ if (LABEL_REF_P (y)
&& LABEL_P (x)
&& label_ref_label (y) == x)
return true;
@@ -3239,7 +3239,7 @@ rtx_referenced_p (const_rtx x, const_rtx body)
return true;
/* If Y is a reference to pool constant traverse the constant. */
- if (GET_CODE (y) == SYMBOL_REF
+ if (SYMBOL_REF_P (y)
&& CONSTANT_POOL_ADDRESS_P (y))
iter.substitute (get_pool_constant (y));
}
@@ -3296,7 +3296,7 @@ computed_jump_p_1 (const_rtx x)
return 1;
case MEM:
- return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ return ! (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
case IF_THEN_ELSE:
@@ -5804,7 +5804,7 @@ get_condition (rtx_insn *jump, rtx_insn **earliest, int allow_cc_mode,
/* If this branches to JUMP_LABEL when the condition is false, reverse
the condition. */
reverse
- = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ = LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump);
return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX,
@@ -6051,7 +6051,7 @@ split_double (rtx value, rtx *first, rtx *second)
}
}
}
- else if (GET_CODE (value) == CONST_WIDE_INT)
+ else if (CONST_WIDE_INT_P (value))
{
/* All of this is scary code and needs to be converted to
properly work with any size integer. */
@@ -6208,7 +6208,7 @@ get_base_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
@@ -6225,7 +6225,7 @@ get_index_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
@@ -6567,7 +6567,7 @@ contains_symbolic_reference_p (const_rtx x)
{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
- if (SYMBOL_REF_P (*iter) || GET_CODE (*iter) == LABEL_REF)
+ if (SYMBOL_REF_P (*iter) || LABEL_REF_P (*iter))
return true;
return false;
@@ -6597,7 +6597,7 @@ tls_referenced_p (const_rtx x)
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
- if (GET_CODE (*iter) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (*iter) != 0)
+ if (SYMBOL_REF_P (*iter) && SYMBOL_REF_TLS_MODEL (*iter) != 0)
return true;
return false;
}
diff --git a/gcc/rtlhooks.c b/gcc/rtlhooks.c
index 0ce3d1ec637..d410cd55094 100644
--- a/gcc/rtlhooks.c
+++ b/gcc/rtlhooks.c
@@ -51,7 +51,7 @@ gen_lowpart_general (machine_mode mode, rtx x)
return result;
/* Handle SUBREGs and hard REGs that were rejected by
simplify_gen_subreg. */
- else if (REG_P (x) || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || SUBREG_P (x))
{
result = gen_lowpart_common (mode, copy_to_reg (x));
gcc_assert (result != 0);
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index 5cb4a462ce9..2d5073dd79a 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -2089,7 +2089,7 @@ mark_insn_reg_birth (rtx insn, rtx reg, bool clobber_p, bool unused_p)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2148,7 +2148,7 @@ mark_reg_death (rtx reg)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2423,7 +2423,7 @@ sched_analyze_1 (class deps_desc *deps, rtx x, rtx_insn *insn)
return;
}
- while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
+ while (GET_CODE (dest) == STRICT_LOW_PART || SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT)
{
if (GET_CODE (dest) == STRICT_LOW_PART
@@ -3457,7 +3457,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
}
tmp = SET_DEST (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp))
dest_regno = REGNO (tmp);
@@ -3465,7 +3465,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
goto end_call_group;
tmp = SET_SRC (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if ((GET_CODE (tmp) == PLUS
|| GET_CODE (tmp) == MINUS)
@@ -3569,7 +3569,7 @@ call_may_noreturn_p (rtx_insn *insn)
return false;
call = get_call_rtx_from (insn);
- if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (call && SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol)
diff --git a/gcc/sched-rgn.c b/gcc/sched-rgn.c
index 59ee6a0a57c..f30b8d3f94c 100644
--- a/gcc/sched-rgn.c
+++ b/gcc/sched-rgn.c
@@ -1672,7 +1672,7 @@ check_live_1 (int src, rtx x)
if (reg == 0)
return 1;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
@@ -1755,7 +1755,7 @@ update_live_1 (int src, rtx x)
if (reg == 0)
return;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index f127ff74599..e99c9002471 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -811,7 +811,7 @@ count_occurrences_equiv (const_rtx what, const_rtx where)
return 0;
count += 1;
}
- else if (GET_CODE (x) == SUBREG
+ else if (SUBREG_P (x)
&& (!REG_P (SUBREG_REG (x))
|| REGNO (SUBREG_REG (x)) == REGNO (what)))
/* ??? Do not support substituting regs inside subregs. In that case,
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 9359a3cdb4d..9031e929a6d 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -247,7 +247,7 @@ avoid_constant_pool_reference (rtx x)
/* If this is a constant pool reference, we can turn it into its
constant and hope that simplifications happen. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& CONSTANT_POOL_ADDRESS_P (addr))
{
c = get_pool_constant (addr);
@@ -826,7 +826,7 @@ simplify_truncation (machine_mode mode, rtx op,
/* (truncate:A (subreg:B (truncate:C X) 0)) is
(truncate:A X). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& SCALAR_INT_MODE_P (op_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op)), &subreg_mode)
@@ -1242,7 +1242,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* A truncate of a memory is just loading the low part of the memory
if we are not changing the meaning of the address. */
- if (GET_CODE (op) == MEM
+ if (MEM_P (op)
&& !VECTOR_MODE_P (mode)
&& !MEM_VOLATILE_P (op)
&& !mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op)))
@@ -1300,7 +1300,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
is (float_truncate:SF x). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& subreg_lowpart_p (op)
&& GET_CODE (SUBREG_REG (op)) == FLOAT_TRUNCATE)
return SUBREG_REG (op);
@@ -1423,8 +1423,8 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
if (GET_CODE (op) == TRUNCATE
&& GET_MODE (XEXP (op, 0)) == mode
&& GET_CODE (XEXP (op, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (XEXP (op, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (op, 0), 1)))
return XEXP (op, 0);
/* Extending a widening multiplication should be canonicalized to
@@ -1474,7 +1474,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a sign extension of a subreg of a promoted
variable, where the promotion is sign-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_SIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1537,7 +1537,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& ! POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -1557,7 +1557,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a zero extension of a subreg of a promoted
variable, where the promotion is zero-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_UNSIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1667,7 +1667,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& POINTERS_EXTEND_UNSIGNED > 0
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -1736,7 +1736,7 @@ simplify_const_unary_operation (enum rtx_code code, machine_mode mode,
}
if (CONST_SCALAR_INT_P (op) || CONST_DOUBLE_AS_FLOAT_P (op))
return gen_const_vec_duplicate (mode, op);
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& (CONST_VECTOR_DUPLICATE_P (op)
|| CONST_VECTOR_NUNITS (op).is_constant ()))
{
@@ -1752,7 +1752,7 @@ simplify_const_unary_operation (enum rtx_code code, machine_mode mode,
}
if (VECTOR_MODE_P (mode)
- && GET_CODE (op) == CONST_VECTOR
+ && CONST_VECTOR_P (op)
&& known_eq (GET_MODE_NUNITS (mode), CONST_VECTOR_NUNITS (op)))
{
gcc_assert (GET_MODE (op) == op_mode);
@@ -2261,14 +2261,14 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
to CONST_INT since overflow won't be computed properly if wider
than HOST_BITS_PER_WIDE_INT. */
- if ((GET_CODE (op0) == CONST
- || GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF)
+ if ((CONST_P (op0)
+ || SYMBOL_REF_P (op0)
+ || LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, offset);
- else if ((GET_CODE (op1) == CONST
- || GET_CODE (op1) == SYMBOL_REF
- || GET_CODE (op1) == LABEL_REF)
+ else if ((CONST_P (op1)
+ || SYMBOL_REF_P (op1)
+ || LABEL_REF_P (op1))
&& poly_int_rtx_p (op0, &offset))
return plus_constant (mode, op1, offset);
@@ -2540,9 +2540,9 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
return simplify_gen_binary (MINUS, mode, tem, XEXP (op0, 0));
}
- if ((GET_CODE (op0) == CONST
- || GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF)
+ if ((CONST_P (op0)
+ || SYMBOL_REF_P (op0)
+ || LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, trunc_int_for_mode (-offset, mode));
@@ -2791,7 +2791,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
mode size to (rotate A CX). */
if (GET_CODE (op1) == ASHIFT
- || GET_CODE (op1) == SUBREG)
+ || SUBREG_P (op1))
{
opleft = op1;
opright = op0;
@@ -2813,13 +2813,13 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
/* Same, but for ashift that has been "simplified" to a wider mode
by simplify_shift_const. */
- if (GET_CODE (opleft) == SUBREG
+ if (SUBREG_P (opleft)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (opleft)),
&inner_mode)
&& GET_CODE (SUBREG_REG (opleft)) == ASHIFT
&& GET_CODE (opright) == LSHIFTRT
- && GET_CODE (XEXP (opright, 0)) == SUBREG
+ && SUBREG_P (XEXP (opright, 0))
&& known_eq (SUBREG_BYTE (opleft), SUBREG_BYTE (XEXP (opright, 0)))
&& GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode)
&& rtx_equal_p (XEXP (SUBREG_REG (opleft), 0),
@@ -3642,7 +3642,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
if (vec_duplicate_p (trueop0, &elt0))
return elt0;
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP
(trueop1, 0, 0)));
@@ -3725,7 +3725,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
because they are all the same. */
return gen_vec_duplicate (mode, elt0);
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
{
unsigned n_elts = XVECLEN (trueop1, 0);
rtvec v = rtvec_alloc (n_elts);
@@ -3968,10 +3968,10 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
gcc_assert (GET_MODE_INNER (mode) == op1_mode);
unsigned int n_elts, in_n_elts;
- if ((GET_CODE (trueop0) == CONST_VECTOR
+ if ((CONST_VECTOR_P (trueop0)
|| CONST_SCALAR_INT_P (trueop0)
|| CONST_DOUBLE_AS_FLOAT_P (trueop0))
- && (GET_CODE (trueop1) == CONST_VECTOR
+ && (CONST_VECTOR_P (trueop1)
|| CONST_SCALAR_INT_P (trueop1)
|| CONST_DOUBLE_AS_FLOAT_P (trueop1))
&& GET_MODE_NUNITS (mode).is_constant (&n_elts)
@@ -4084,8 +4084,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
{
if (VECTOR_MODE_P (mode)
&& code != VEC_CONCAT
- && GET_CODE (op0) == CONST_VECTOR
- && GET_CODE (op1) == CONST_VECTOR)
+ && CONST_VECTOR_P (op0)
+ && CONST_VECTOR_P (op1))
{
bool step_ok_p;
if (CONST_VECTOR_STEPPED_P (op0)
@@ -4145,8 +4145,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
gcc_assert (n_elts >= 2);
if (n_elts == 2)
{
- gcc_assert (GET_CODE (op0) != CONST_VECTOR);
- gcc_assert (GET_CODE (op1) != CONST_VECTOR);
+ gcc_assert (!CONST_VECTOR_P (op0));
+ gcc_assert (!CONST_VECTOR_P (op1));
RTVEC_ELT (v, 0) = op0;
RTVEC_ELT (v, 1) = op1;
@@ -4157,8 +4157,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
unsigned op1_n_elts = GET_MODE_NUNITS (GET_MODE (op1)).to_constant ();
unsigned i;
- gcc_assert (GET_CODE (op0) == CONST_VECTOR);
- gcc_assert (GET_CODE (op1) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (op0));
+ gcc_assert (CONST_VECTOR_P (op1));
gcc_assert (op0_n_elts + op1_n_elts == n_elts);
for (i = 0; i < op0_n_elts; ++i)
@@ -4714,13 +4714,13 @@ simplify_plus_minus (enum rtx_code code, machine_mode mode, rtx op0,
else if (swap_commutative_operands_p (lhs, rhs))
std::swap (lhs, rhs);
- if ((GET_CODE (lhs) == CONST || CONST_INT_P (lhs))
- && (GET_CODE (rhs) == CONST || CONST_INT_P (rhs)))
+ if ((CONST_P (lhs) || CONST_INT_P (lhs))
+ && (CONST_P (rhs) || CONST_INT_P (rhs)))
{
rtx tem_lhs, tem_rhs;
- tem_lhs = GET_CODE (lhs) == CONST ? XEXP (lhs, 0) : lhs;
- tem_rhs = GET_CODE (rhs) == CONST ? XEXP (rhs, 0) : rhs;
+ tem_lhs = CONST_P (lhs) ? XEXP (lhs, 0) : lhs;
+ tem_rhs = CONST_P (rhs) ? XEXP (rhs, 0) : rhs;
tem = simplify_binary_operation (ncode, mode, tem_lhs,
tem_rhs);
@@ -4740,7 +4740,7 @@ simplify_plus_minus (enum rtx_code code, machine_mode mode, rtx op0,
any more combinations with this rhs: We must have
something like symbol+offset, ie. one of the
trivial CONST expressions we handle later. */
- if (GET_CODE (tem) == CONST
+ if (CONST_P (tem)
&& GET_CODE (XEXP (tem, 0)) == ncode
&& XEXP (XEXP (tem, 0), 0) == lhs
&& XEXP (XEXP (tem, 0), 1) == rhs)
@@ -4852,7 +4852,7 @@ plus_minus_operand_p (const_rtx x)
{
return GET_CODE (x) == PLUS
|| GET_CODE (x) == MINUS
- || (GET_CODE (x) == CONST
+ || (CONST_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS
&& CONSTANT_P (XEXP (XEXP (x, 0), 0))
&& CONSTANT_P (XEXP (XEXP (x, 0), 1)));
@@ -5833,7 +5833,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
if (VECTOR_MODE_P (GET_MODE (op1))
&& GET_CODE (op0) == NE
&& GET_CODE (XEXP (op0, 0)) == NOT
- && GET_CODE (XEXP (op0, 1)) == CONST_VECTOR)
+ && CONST_VECTOR_P (XEXP (op0, 1)))
{
rtx cv = XEXP (op0, 1);
int nunits;
@@ -5937,8 +5937,8 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
rtx trueop0 = avoid_constant_pool_reference (op0);
rtx trueop1 = avoid_constant_pool_reference (op1);
- if (GET_CODE (trueop0) == CONST_VECTOR
- && GET_CODE (trueop1) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0)
+ && CONST_VECTOR_P (trueop1))
{
rtvec v = rtvec_alloc (n_elts);
unsigned int i;
@@ -6001,7 +6001,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat (X) (B)) if N == 1 or
(vec_concat (A) (X)) if N == 2. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == CONST_VECTOR
+ && CONST_VECTOR_P (op1)
&& known_eq (CONST_VECTOR_NUNITS (op1), 2)
&& known_eq (GET_MODE_NUNITS (GET_MODE (op0)), 2)
&& IN_RANGE (sel, 1, 2))
@@ -6046,7 +6046,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
Only applies for vectors of two elements. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == SUBREG
+ && SUBREG_P (op1)
&& GET_MODE (op1) == GET_MODE (op0)
&& GET_MODE (SUBREG_REG (op1)) == GET_MODE (XEXP (op0, 0))
&& paradoxical_subreg_p (op1)
@@ -6070,7 +6070,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat:outer x:inner y:inner) if N == 1,
or (vec_concat:outer y:inner x:inner) if N == 2. */
if (GET_CODE (op1) == VEC_DUPLICATE
- && GET_CODE (op0) == SUBREG
+ && SUBREG_P (op0)
&& GET_MODE (op0) == GET_MODE (op1)
&& GET_MODE (SUBREG_REG (op0)) == GET_MODE (XEXP (op1, 0))
&& paradoxical_subreg_p (op0)
@@ -6177,7 +6177,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
/* Unpack the value. */
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
num_elem = CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode));
elem_bitsize = GET_MODE_UNIT_BITSIZE (innermode);
@@ -6195,7 +6195,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
for (elem = 0; elem < num_elem; elem++)
{
unsigned char * vp;
- rtx el = (GET_CODE (op) == CONST_VECTOR
+ rtx el = (CONST_VECTOR_P (op)
? CONST_VECTOR_ELT (op, first_elem + elem)
: op);
@@ -6511,7 +6511,7 @@ simplify_subreg (machine_mode outermode, rtx op,
if (CONST_SCALAR_INT_P (op)
|| CONST_DOUBLE_AS_FLOAT_P (op)
|| CONST_FIXED_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
{
/* simplify_immed_subreg deconstructs OP into bytes and constructs
the result from bytes, so it only works if the sizes of the modes
@@ -6528,7 +6528,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Handle constant-sized outer modes and variable-sized inner modes. */
unsigned HOST_WIDE_INT first_elem;
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& is_a <fixed_size_mode> (outermode, &fs_outermode)
&& constant_multiple_p (byte, GET_MODE_UNIT_SIZE (innermode),
&first_elem))
@@ -6541,7 +6541,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Changing mode twice with SUBREG => just change it once,
or not at all if changing back op starting mode. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
@@ -6761,7 +6761,7 @@ simplify_gen_subreg (machine_mode outermode, rtx op,
if (newx)
return newx;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
|| GET_CODE (op) == CONCAT
|| GET_MODE (op) == VOIDmode)
return NULL_RTX;
diff --git a/gcc/symtab.c b/gcc/symtab.c
index 63e2820eb93..dbd2221db27 100644
--- a/gcc/symtab.c
+++ b/gcc/symtab.c
@@ -1377,7 +1377,7 @@ symtab_node::make_decl_local (void)
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);
@@ -1432,7 +1432,7 @@ symtab_node::copy_visibility_from (symtab_node *n)
return;
rtx symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 8004951d2e8..2088c98b080 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -150,9 +150,9 @@ gen_addr_rtx (machine_mode address_mode,
if (offset_p)
*offset_p = &XEXP (act_elem, 1);
- if (GET_CODE (symbol) == SYMBOL_REF
- || GET_CODE (symbol) == LABEL_REF
- || GET_CODE (symbol) == CONST)
+ if (SYMBOL_REF_P (symbol)
+ || LABEL_REF_P (symbol)
+ || CONST_P (symbol))
act_elem = gen_rtx_CONST (address_mode, act_elem);
}
@@ -264,13 +264,13 @@ addr_for_mem_ref (struct mem_address *addr, addr_space_t as,
into OFF and clear BSE. Otherwise we may later try to pull a mode from
BSE to generate a REG, which won't work with constants because they
are modeless. */
- if (bse && GET_CODE (bse) == CONST_INT)
+ if (bse && CONST_INT_P (bse))
{
if (off)
off = simplify_gen_binary (PLUS, pointer_mode, bse, off);
else
off = bse;
- gcc_assert (GET_CODE (off) == CONST_INT);
+ gcc_assert (CONST_INT_P (off));
bse = NULL_RTX;
}
gen_addr_rtx (pointer_mode, sym, bse, idx, st, off, &address, NULL, NULL);
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 1f67378a867..19b0b40c2b6 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -320,7 +320,7 @@ dead_debug_global_replace_temp (struct dead_debug_global *global,
dead_debug_global_entry *entry
= dead_debug_global_find (global, *DF_REF_REAL_LOC (use));
- gcc_checking_assert (GET_CODE (entry->reg) == REG
+ gcc_checking_assert (REG_P (entry->reg)
&& REGNO (entry->reg) == uregno);
if (!entry->dtemp)
@@ -420,7 +420,7 @@ dead_debug_promote_uses (struct dead_debug_local *debug)
df_ref ref;
dead_debug_global_entry *entry;
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER)
{
headp = &head->next;
@@ -691,7 +691,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
cleanup_auto_inc_dec (src, VOIDmode),
GET_MODE (dest));
}
- else if (GET_CODE (dest) == SUBREG)
+ else if (SUBREG_P (dest))
{
/* We should be setting REG here. Lose. */
if (REGNO (SUBREG_REG (dest)) != REGNO (reg))
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 67f25c1c795..f14895f0a17 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -975,7 +975,7 @@ use_narrower_mode_test (rtx x, const_rtx subreg)
< GET_MODE_PRECISION (as_a <scalar_int_mode> (op1_mode)))
{
poly_uint64 byte = subreg_lowpart_offset (mode, op1_mode);
- if (GET_CODE (op1) == SUBREG || GET_CODE (op1) == CONCAT)
+ if (SUBREG_P (op1) || GET_CODE (op1) == CONCAT)
{
if (!simplify_subreg (mode, op1, op1_mode, byte))
return false;
@@ -1142,7 +1142,7 @@ adjust_mems (rtx loc, const_rtx old_rtx, void *data)
tem = gen_rtx_raw_SUBREG (GET_MODE (loc), addr, SUBREG_BYTE (loc));
finish_subreg:
if (MAY_HAVE_DEBUG_BIND_INSNS
- && GET_CODE (tem) == SUBREG
+ && SUBREG_P (tem)
&& (GET_CODE (SUBREG_REG (tem)) == PLUS
|| GET_CODE (SUBREG_REG (tem)) == MINUS
|| GET_CODE (SUBREG_REG (tem)) == MULT
@@ -2043,7 +2043,7 @@ vt_get_canonicalize_base (rtx loc)
{
while ((GET_CODE (loc) == PLUS
|| GET_CODE (loc) == AND)
- && GET_CODE (XEXP (loc, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (loc, 1))
&& (GET_CODE (loc) != AND
|| negative_power_of_two_p (INTVAL (XEXP (loc, 1)))))
loc = XEXP (loc, 0);
@@ -2195,7 +2195,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
canonicalize the base and we're done. We'll normally have
only one stack alignment anyway. */
if (GET_CODE (loc) == AND
- && GET_CODE (XEXP (loc, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (loc, 1))
&& negative_power_of_two_p (INTVAL (XEXP (loc, 1))))
{
x = vt_canonicalize_addr (set, XEXP (loc, 0));
@@ -2250,7 +2250,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
static inline bool
vt_canon_true_dep (dataflow_set *set, rtx mloc, rtx maddr, rtx loc)
{
- if (GET_CODE (loc) != MEM)
+ if (!MEM_P (loc))
return false;
rtx addr = vt_canonicalize_addr (set, XEXP (loc, 0));
@@ -2350,7 +2350,7 @@ clobber_overlapping_mems (dataflow_set *set, rtx loc)
{
struct overlapping_mems coms;
- gcc_checking_assert (GET_CODE (loc) == MEM);
+ gcc_checking_assert (MEM_P (loc));
coms.set = set;
coms.loc = canon_rtx (loc);
@@ -2479,7 +2479,7 @@ val_bind (dataflow_set *set, rtx val, rtx loc, bool modified)
dynamic tables. ??? We should test this before emitting the
micro-op in the first place. */
while (l)
- if (GET_CODE (l->loc) == MEM && XEXP (l->loc, 0) == XEXP (loc, 0))
+ if (MEM_P (l->loc) && XEXP (l->loc, 0) == XEXP (loc, 0))
break;
else
l = l->next;
@@ -2609,10 +2609,10 @@ val_reset (dataflow_set *set, decl_or_value dv)
{
if (node->loc == cval)
continue;
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
var_reg_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
- else if (GET_CODE (node->loc) == MEM)
+ else if (MEM_P (node->loc))
var_mem_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
else
@@ -3814,7 +3814,7 @@ canonicalize_values_star (variable **slot, dataflow_set *set)
parent. */
clobber_variable_part (set, cval, ndv, 0, NULL);
}
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *list = set->regs[REGNO (node->loc)], **listp;
@@ -4072,7 +4072,7 @@ variable_merge_over_cur (variable *s1var, struct dfset_merge *dsm)
{
location_chain **nextp = &node->next;
- if (GET_CODE (node->loc) == REG)
+ if (REG_P (node->loc))
{
attrs *list;
@@ -4444,7 +4444,7 @@ variable_post_merge_new_vals (variable **slot, dfset_post_merge *dfpm)
{
if (GET_CODE (node->loc) == VALUE)
gcc_assert (!VALUE_RECURSED_INTO (node->loc));
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *att, **attp, **curp = NULL;
@@ -4735,7 +4735,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
{
/* We want to remove dying MEMs that don't refer to DECL. */
- if (GET_CODE (loc->loc) == MEM
+ if (MEM_P (loc->loc)
&& (MEM_EXPR (loc->loc) != decl
|| int_mem_offset (loc->loc) != 0)
&& mem_dies_at_call (loc->loc))
@@ -4779,7 +4779,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
}
}
- if (GET_CODE (loc->loc) != MEM
+ if (!MEM_P (loc->loc)
|| (MEM_EXPR (loc->loc) == decl
&& int_mem_offset (loc->loc) == 0)
|| !mem_dies_at_call (loc->loc))
@@ -4839,7 +4839,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
if (shared_var_p (var, set->vars))
{
for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
- if (GET_CODE (loc->loc) == MEM
+ if (MEM_P (loc->loc)
&& mem_dies_at_call (loc->loc))
break;
@@ -4859,7 +4859,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
for (locp = &var->var_part[0].loc_chain, loc = *locp;
loc; loc = *locp)
{
- if (GET_CODE (loc->loc) != MEM
+ if (!MEM_P (loc->loc)
|| !mem_dies_at_call (loc->loc))
{
locp = &loc->next;
@@ -5710,7 +5710,7 @@ add_uses (rtx loc, struct count_use_info *cui)
}
if (CONSTANT_P (vloc)
- && (GET_CODE (vloc) != CONST || non_suitable_const (vloc)))
+ && (!CONST_P (vloc) || non_suitable_const (vloc)))
/* For constants don't look up any value. */;
else if (!VAR_LOC_UNKNOWN_P (vloc) && !unsuitable_loc (vloc)
&& (val = find_use_val (vloc, GET_MODE (oloc), cui)))
@@ -5901,7 +5901,7 @@ reverse_op (rtx val, const_rtx expr, rtx_insn *insn)
prefer non-ENTRY_VALUE locations whenever possible. */
for (l = v->locs, count = 0; l; l = l->next, count++)
if (CONSTANT_P (l->loc)
- && (GET_CODE (l->loc) != CONST || !references_value_p (l->loc, 0)))
+ && (!CONST_P (l->loc) || !references_value_p (l->loc, 0)))
return;
/* Avoid creating too large locs lists. */
else if (count == PARAM_VALUE (PARAM_MAX_VARTRACK_REVERSE_OP_SIZE))
@@ -5932,12 +5932,12 @@ reverse_op (rtx val, const_rtx expr, rtx_insn *insn)
if (GET_MODE (v->val_rtx) != GET_MODE (val))
return;
arg = XEXP (src, 1);
- if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
+ if (!CONST_INT_P (arg) && !SYMBOL_REF_P (arg))
{
arg = cselib_expand_value_rtx (arg, scratch_regs, 5);
if (arg == NULL_RTX)
return;
- if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
+ if (!CONST_INT_P (arg) && !SYMBOL_REF_P (arg))
return;
}
ret = simplify_gen_binary (code, GET_MODE (val), val, arg);
@@ -6254,7 +6254,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
call = get_call_rtx_from (insn);
if (call)
{
- if (GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol))
@@ -6470,12 +6470,12 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
/* Try harder, when passing address of a constant
pool integer it can be easily read back. */
item = XEXP (item, 1);
- if (GET_CODE (item) == SUBREG)
+ if (SUBREG_P (item))
item = SUBREG_REG (item);
gcc_assert (GET_CODE (item) == VALUE);
val = CSELIB_VAL_PTR (item);
for (l = val->locs; l; l = l->next)
- if (GET_CODE (l->loc) == SYMBOL_REF
+ if (SYMBOL_REF_P (l->loc)
&& TREE_CONSTANT_POOL_ADDRESS_P (l->loc)
&& SYMBOL_REF_DECL (l->loc)
&& DECL_INITIAL (SYMBOL_REF_DECL (l->loc)))
@@ -6536,7 +6536,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
if (x)
{
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
/* Don't record anything. */;
else if (CONSTANT_P (x))
{
@@ -6832,10 +6832,10 @@ compute_bb_dataflow (basic_block bb)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
- else if (GET_CODE (uloc) == MEM)
+ else if (MEM_P (uloc))
var_mem_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
}
@@ -6885,7 +6885,7 @@ compute_bb_dataflow (basic_block bb)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (out, val, SET_SRC (uloc), insn);
}
@@ -6943,7 +6943,7 @@ compute_bb_dataflow (basic_block bb)
var_regno_delete (out, REGNO (uloc));
else if (MEM_P (uloc))
{
- gcc_checking_assert (GET_CODE (vloc) == MEM);
+ gcc_checking_assert (MEM_P (vloc));
gcc_checking_assert (dstv == vloc);
if (dstv != vloc)
clobber_overlapping_mems (out, vloc);
@@ -8726,7 +8726,7 @@ emit_note_insn_var_location (variable **varp, emit_note_data *data)
continue;
offset = VAR_PART_OFFSET (var, i);
loc2 = var->var_part[i].cur_loc;
- if (loc2 && GET_CODE (loc2) == MEM
+ if (loc2 && MEM_P (loc2)
&& GET_CODE (XEXP (loc2, 0)) == VALUE)
{
rtx depval = XEXP (loc2, 0);
@@ -8998,7 +8998,7 @@ notify_dependents_of_changed_value (rtx val, variable_table_type *htab,
{
rtx loc = ivar->var_part[i].cur_loc;
- if (loc && GET_CODE (loc) == MEM
+ if (loc && MEM_P (loc)
&& XEXP (loc, 0) == val)
{
variable_was_changed (ivar, NULL);
@@ -9330,10 +9330,10 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
- else if (GET_CODE (uloc) == MEM)
+ else if (MEM_P (uloc))
var_mem_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
}
@@ -9385,7 +9385,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (set, val, SET_SRC (uloc), insn);
}
@@ -9437,7 +9437,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
var_regno_delete (set, REGNO (uloc));
else if (MEM_P (uloc))
{
- gcc_checking_assert (GET_CODE (vloc) == MEM);
+ gcc_checking_assert (MEM_P (vloc));
gcc_checking_assert (vloc == dstv);
if (vloc != dstv)
clobber_overlapping_mems (set, vloc);
diff --git a/gcc/varasm.c b/gcc/varasm.c
index e886cdc71b8..036d8e455f2 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -1372,7 +1372,7 @@ make_decl_rtl (tree decl)
/* If the symbol has a SYMBOL_REF_BLOCK field, update it based
on the new decl information. */
if (MEM_P (x)
- && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (x, 0))
&& SYMBOL_REF_HAS_BLOCK_INFO_P (XEXP (x, 0)))
change_symbol_block (XEXP (x, 0), get_block_for_decl (decl));
@@ -1720,7 +1720,7 @@ get_fnname_from_decl (tree decl)
rtx x = DECL_RTL (decl);
gcc_assert (MEM_P (x));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
return XSTR (x, 0);
}
@@ -2247,7 +2247,7 @@ assemble_variable (tree decl, int top_level ATTRIBUTE_UNUSED,
}
gcc_assert (MEM_P (decl_rtl));
- gcc_assert (GET_CODE (XEXP (decl_rtl, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (decl_rtl, 0)));
symbol = XEXP (decl_rtl, 0);
/* If this symbol belongs to the tree constant pool, output the constant
@@ -2433,7 +2433,7 @@ assemble_external_real (tree decl)
{
rtx rtl = DECL_RTL (decl);
- if (MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
+ if (MEM_P (rtl) && SYMBOL_REF_P (XEXP (rtl, 0))
&& !SYMBOL_REF_USED (XEXP (rtl, 0))
&& !incorporeal_function_p (decl))
{
@@ -2813,7 +2813,7 @@ assemble_integer (rtx x, unsigned int size, unsigned int align, int force)
subsize = size > UNITS_PER_WORD? UNITS_PER_WORD : 1;
subalign = MIN (align, subsize * BITS_PER_UNIT);
- if (GET_CODE (x) == CONST_FIXED)
+ if (CONST_FIXED_P (x))
mclass = GET_MODE_CLASS (GET_MODE (x));
else
mclass = MODE_INT;
@@ -3900,7 +3900,7 @@ force_const_mem (machine_mode in_mode, rtx x)
/* If we're dropping a label to the constant pool, make sure we
don't delete it. */
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
LABEL_PRESERVE_P (XEXP (x, 0)) = 1;
return copy_rtx (def);
@@ -3973,7 +3973,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align)
case MODE_VECTOR_BOOL:
{
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
/* Pick the smallest integer mode that contains at least one
whole element. Often this is byte_mode and contains more
@@ -4008,7 +4008,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align)
scalar_mode submode = GET_MODE_INNER (mode);
unsigned int subalign = MIN (align, GET_MODE_BITSIZE (submode));
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
units = GET_MODE_NUNITS (mode);
for (i = 0; i < units; i++)
@@ -4049,7 +4049,7 @@ output_constant_pool_1 (class constant_descriptor_rtx *desc,
{
case CONST:
if (GET_CODE (XEXP (tmp, 0)) != PLUS
- || GET_CODE (XEXP (XEXP (tmp, 0), 0)) != LABEL_REF)
+ || !LABEL_REF_P (XEXP (XEXP (tmp, 0), 0)))
break;
tmp = XEXP (XEXP (tmp, 0), 0);
/* FALLTHRU */
@@ -4130,7 +4130,7 @@ mark_constants_in_pattern (rtx insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (CONSTANT_POOL_ADDRESS_P (x))
{
@@ -5568,7 +5568,7 @@ mark_weak (tree decl)
if (DECL_RTL_SET_P (decl)
&& MEM_P (DECL_RTL (decl))
&& XEXP (DECL_RTL (decl), 0)
- && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (DECL_RTL (decl), 0)))
SYMBOL_REF_WEAK (XEXP (DECL_RTL (decl), 0)) = 1;
}
@@ -6968,7 +6968,7 @@ default_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
if (!MEM_P (rtl))
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
flags = SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_HAS_BLOCK_INFO;
@@ -7494,7 +7494,7 @@ place_block_symbol (rtx symbol)
rtx target = DECL_RTL (snode->ultimate_alias_target ()->decl);
gcc_assert (MEM_P (target)
- && GET_CODE (XEXP (target, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (target, 0))
&& SYMBOL_REF_HAS_BLOCK_INFO_P (XEXP (target, 0)));
target = XEXP (target, 0);
place_block_symbol (target);
diff --git a/gcc/xcoffout.h b/gcc/xcoffout.h
index d8a031268ff..0ab9e5d09c2 100644
--- a/gcc/xcoffout.h
+++ b/gcc/xcoffout.h
@@ -78,7 +78,7 @@ along with GCC; see the file COPYING3. If not see
\
/* If we are writing a function name, we must ensure that \
there is no storage-class suffix on the name. */ \
- if (CODE == N_FUN && GET_CODE (ADDR) == SYMBOL_REF) \
+ if (CODE == N_FUN && SYMBOL_REF_P (ADDR)) \
{ \
const char *_p = XSTR (ADDR, 0); \
if (*_p == '*') \
--
2.21.0
[-- Attachment #4: Touchup --]
[-- Type: text/x-patch, Size: 2073 bytes --]
From 78d09201f5e4ce27a0f1b45386095c864af65954 Mon Sep 17 00:00:00 2001
From: Arvind Sankar <nivedita@alum.mit.edu>
Date: Fri, 2 Aug 2019 12:29:30 -0400
Subject: [PATCH 3/3] Use rtx_code predicates instead of GET_CODE
---
gcc/combine-stack-adj.c | 3 +--
gcc/dwarf2out.c | 3 +--
gcc/rtlanal.c | 3 +--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/gcc/combine-stack-adj.c b/gcc/combine-stack-adj.c
index 3638a1b10ee..f98a0d54c98 100644
--- a/gcc/combine-stack-adj.c
+++ b/gcc/combine-stack-adj.c
@@ -634,8 +634,7 @@ combine_stack_adjustments_for_block (basic_block bb)
&& GET_CODE (XEXP (XEXP (dest, 0), 1)) == PLUS
&& XEXP (XEXP (XEXP (dest, 0), 1), 0)
== stack_pointer_rtx
- && GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
- == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (XEXP (dest, 0), 1), 1))
&& INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1))
== -last_sp_adjust))
&& XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index b81e3ab88b5..724eb60ddba 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -23747,8 +23747,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die)
if (single_element_loc_list_p (loc)
&& loc->expr->dw_loc_opc == DW_OP_addr
&& loc->expr->dw_loc_next == NULL
- && GET_CODE (loc->expr->dw_loc_oprnd1.v.val_addr)
- == SYMBOL_REF)
+ && SYMBOL_REF_P (loc->expr->dw_loc_oprnd1.v.val_addr))
{
rtx x = loc->expr->dw_loc_oprnd1.v.val_addr;
loc->expr->dw_loc_oprnd1.v.val_addr
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index a1f9146b7e3..4716e112a90 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -3347,8 +3347,7 @@ computed_jump_p (const rtx_insn *insn)
for (i = len - 1; i >= 0; i--)
if (GET_CODE (XVECEXP (pat, 0, i)) == USE
- && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))
- == LABEL_REF))
+ && LABEL_REF_P (XEXP (XVECEXP (pat, 0, i), 0)))
{
has_use_labelref = 1;
break;
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-02 17:38 Use predicates for RTL objects Arvind Sankar
@ 2019-08-02 17:50 ` Segher Boessenkool
2019-08-02 17:55 ` Arvind Sankar
0 siblings, 1 reply; 33+ messages in thread
From: Segher Boessenkool @ 2019-08-02 17:50 UTC (permalink / raw)
To: Arvind Sankar; +Cc: gcc-patches
On Fri, Aug 02, 2019 at 01:38:21PM -0400, Arvind Sankar wrote:
> Hi, I have taken a crack at the beginner GCC project mentioned at
> https://gcc.gnu.org/projects/beginner.html to replace uses of GET_CODE
> to check rtx_code with the appropriate predicate macros.
>
> Would someone be able to review/actually apply the changes if they look
> acceptable?
>
> Most of the change is auto-generated using the enclosed script [1]. In
> addition I have added 3 new predicates to rtl.h: CONST_VECTOR_P,
> CONST_STRING_P and CONST_P. After the autogenned patch there is a small
> cleanup for a couple instances where the existing comparison is split
> across source lines and wasn't picked up by the script.
Thank you for doing this!
I don't think there should be a CONST_P like this, the name suggests
too much that the macro returns true for constants, which isn't what it
does (not in either direction; neither more or less than it).
It's worse than SET_P or PLUS_P would be even, imo.
Maybe you can put a script like this in contrib/ ?
Segher
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-02 17:50 ` Segher Boessenkool
@ 2019-08-02 17:55 ` Arvind Sankar
2019-08-02 18:53 ` Segher Boessenkool
0 siblings, 1 reply; 33+ messages in thread
From: Arvind Sankar @ 2019-08-02 17:55 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Arvind Sankar, gcc-patches
On Fri, Aug 02, 2019 at 12:49:56PM -0500, Segher Boessenkool wrote:
> On Fri, Aug 02, 2019 at 01:38:21PM -0400, Arvind Sankar wrote:
> > Hi, I have taken a crack at the beginner GCC project mentioned at
> > https://gcc.gnu.org/projects/beginner.html to replace uses of GET_CODE
> > to check rtx_code with the appropriate predicate macros.
> >
> > Would someone be able to review/actually apply the changes if they look
> > acceptable?
> >
> > Most of the change is auto-generated using the enclosed script [1]. In
> > addition I have added 3 new predicates to rtl.h: CONST_VECTOR_P,
> > CONST_STRING_P and CONST_P. After the autogenned patch there is a small
> > cleanup for a couple instances where the existing comparison is split
> > across source lines and wasn't picked up by the script.
>
> Thank you for doing this!
>
> I don't think there should be a CONST_P like this, the name suggests
> too much that the macro returns true for constants, which isn't what it
> does (not in either direction; neither more or less than it).
>
> It's worse than SET_P or PLUS_P would be even, imo.
>
> Maybe you can put a script like this in contrib/ ?
>
>
> Segher
Yes, I agree CONST_P is a little confusing. There are about 60
occurences of GET_CODE (..) being compared to CONST in generic code.
Should I just leave it out of the conversion or perhaps rename it to
RTL_CONST_P? Though none of the other macros is namespaced, unfortunately.
Thanks.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-02 17:55 ` Arvind Sankar
@ 2019-08-02 18:53 ` Segher Boessenkool
2019-08-02 19:22 ` Arvind Sankar
0 siblings, 1 reply; 33+ messages in thread
From: Segher Boessenkool @ 2019-08-02 18:53 UTC (permalink / raw)
To: Arvind Sankar; +Cc: gcc-patches
On Fri, Aug 02, 2019 at 01:55:04PM -0400, Arvind Sankar wrote:
> On Fri, Aug 02, 2019 at 12:49:56PM -0500, Segher Boessenkool wrote:
> > On Fri, Aug 02, 2019 at 01:38:21PM -0400, Arvind Sankar wrote:
> > > Hi, I have taken a crack at the beginner GCC project mentioned at
> > > https://gcc.gnu.org/projects/beginner.html to replace uses of GET_CODE
> > > to check rtx_code with the appropriate predicate macros.
> > >
> > > Would someone be able to review/actually apply the changes if they look
> > > acceptable?
> > >
> > > Most of the change is auto-generated using the enclosed script [1]. In
> > > addition I have added 3 new predicates to rtl.h: CONST_VECTOR_P,
> > > CONST_STRING_P and CONST_P. After the autogenned patch there is a small
> > > cleanup for a couple instances where the existing comparison is split
> > > across source lines and wasn't picked up by the script.
> >
> > Thank you for doing this!
> >
> > I don't think there should be a CONST_P like this, the name suggests
> > too much that the macro returns true for constants, which isn't what it
> > does (not in either direction; neither more or less than it).
> >
> > It's worse than SET_P or PLUS_P would be even, imo.
>
> Yes, I agree CONST_P is a little confusing. There are about 60
> occurences of GET_CODE (..) being compared to CONST in generic code.
> Should I just leave it out of the conversion
That's shat I would do.
> or perhaps rename it to
> RTL_CONST_P? Though none of the other macros is namespaced, unfortunately.
But please get other people's opinion. Like, people who can actually
approve your patch in the first place ;-)
Segher
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-02 18:53 ` Segher Boessenkool
@ 2019-08-02 19:22 ` Arvind Sankar
2019-08-05 17:18 ` Arvind Sankar
[not found] ` <20190805170908.GA1044536@rani.riverdale.lan>
0 siblings, 2 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-02 19:22 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Arvind Sankar, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1845 bytes --]
On Fri, Aug 02, 2019 at 01:53:11PM -0500, Segher Boessenkool wrote:
> On Fri, Aug 02, 2019 at 01:55:04PM -0400, Arvind Sankar wrote:
> > On Fri, Aug 02, 2019 at 12:49:56PM -0500, Segher Boessenkool wrote:
> > > On Fri, Aug 02, 2019 at 01:38:21PM -0400, Arvind Sankar wrote:
> > > > Hi, I have taken a crack at the beginner GCC project mentioned at
> > > > https://gcc.gnu.org/projects/beginner.html to replace uses of GET_CODE
> > > > to check rtx_code with the appropriate predicate macros.
> > > >
> > > > Would someone be able to review/actually apply the changes if they look
> > > > acceptable?
> > > >
> > > > Most of the change is auto-generated using the enclosed script [1]. In
> > > > addition I have added 3 new predicates to rtl.h: CONST_VECTOR_P,
> > > > CONST_STRING_P and CONST_P. After the autogenned patch there is a small
> > > > cleanup for a couple instances where the existing comparison is split
> > > > across source lines and wasn't picked up by the script.
> > >
> > > Thank you for doing this!
> > >
> > > I don't think there should be a CONST_P like this, the name suggests
> > > too much that the macro returns true for constants, which isn't what it
> > > does (not in either direction; neither more or less than it).
> > >
> > > It's worse than SET_P or PLUS_P would be even, imo.
> >
> > Yes, I agree CONST_P is a little confusing. There are about 60
> > occurences of GET_CODE (..) being compared to CONST in generic code.
> > Should I just leave it out of the conversion
>
> That's shat I would do.
>
> > or perhaps rename it to
> > RTL_CONST_P? Though none of the other macros is namespaced, unfortunately.
>
> But please get other people's opinion. Like, people who can actually
> approve your patch in the first place ;-)
>
>
> Segher
Thanks. Anyway, attaching a version that leaves out CONST_P.
[-- Attachment #2: rtl.h --]
[-- Type: text/x-diff, Size: 1137 bytes --]
From 1bbb0fbaa9a17aaefc1eca86054bbd95719ec691 Mon Sep 17 00:00:00 2001
From: Arvind Sankar <nivedita@alum.mit.edu>
Date: Fri, 2 Aug 2019 14:56:57 -0400
Subject: [PATCH 1/3] Add CONST_VECTOR_P and CONST_STRING_P
---
gcc/rtl.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 039ab05f951..592f141bf22 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -823,10 +823,16 @@ struct GTY(()) rtvec_def {
(CONST_INT_P (X) || CONST_DOUBLE_AS_INT_P (X))
#endif
-/* Predicate yielding true iff X is an rtx for a double-int. */
+/* Predicate yielding true iff X is an rtx for a floating point constant. */
#define CONST_DOUBLE_AS_FLOAT_P(X) \
(GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
+/* Predicate yielding nonzero iff X is an rtx for a constant vector. */
+#define CONST_VECTOR_P(X) (GET_CODE (X) == CONST_VECTOR)
+
+/* Predicate yielding nonzero iff X is an rtx for a constant string */
+#define CONST_STRING_P(X) (GET_CODE (X) == CONST_STRING)
+
/* Predicate yielding nonzero iff X is a label insn. */
#define LABEL_P(X) (GET_CODE (X) == CODE_LABEL)
--
2.21.0
[-- Attachment #3: autogen --]
[-- Type: text/x-diff, Size: 234339 bytes --]
From 5d76b6d68d50974cf51bb823ffab64c6f2477fa9 Mon Sep 17 00:00:00 2001
From: Arvind Sankar <nivedita@alum.mit.edu>
Date: Fri, 2 Aug 2019 14:59:03 -0400
Subject: [PATCH 2/3] Use rtx_code predicates instead of GET_CODE
---
gcc/alias.c | 12 +--
gcc/asan.c | 2 +-
gcc/bb-reorder.c | 2 +-
gcc/bt-load.c | 2 +-
gcc/builtins.c | 2 +-
gcc/caller-save.c | 4 +-
gcc/calls.c | 10 +--
gcc/cfgbuild.c | 4 +-
gcc/cfgcleanup.c | 2 +-
gcc/cfgexpand.c | 8 +-
gcc/cfgrtl.c | 4 +-
gcc/combine.c | 162 ++++++++++++++++++++--------------------
gcc/cprop.c | 2 +-
gcc/cse.c | 80 ++++++++++----------
gcc/cselib.c | 6 +-
gcc/dbxout.c | 20 ++---
gcc/defaults.h | 2 +-
gcc/df-core.c | 4 +-
gcc/df-problems.c | 6 +-
gcc/df-scan.c | 18 ++---
gcc/df.h | 4 +-
gcc/dojump.c | 2 +-
gcc/dse.c | 6 +-
gcc/dwarf2asm.c | 6 +-
gcc/dwarf2out.c | 52 ++++++-------
gcc/emit-rtl.c | 16 ++--
gcc/explow.c | 16 ++--
gcc/expmed.c | 24 +++---
gcc/expr.c | 46 ++++++------
gcc/final.c | 22 +++---
gcc/function.c | 2 +-
gcc/fwprop.c | 16 ++--
gcc/gcse-common.c | 2 +-
gcc/gcse.c | 8 +-
gcc/genattrtab.c | 16 ++--
gcc/genpreds.c | 10 +--
gcc/genrecog.c | 2 +-
gcc/gensupport.c | 8 +-
gcc/ifcvt.c | 20 ++---
gcc/internal-fn.c | 6 +-
gcc/ira-build.c | 2 +-
gcc/ira-conflicts.c | 4 +-
gcc/ira-costs.c | 10 +--
gcc/ira-emit.c | 2 +-
gcc/ira-lives.c | 18 ++---
gcc/ira.c | 12 +--
gcc/jump.c | 36 ++++-----
gcc/loop-doloop.c | 2 +-
gcc/loop-invariant.c | 6 +-
gcc/loop-iv.c | 20 ++---
gcc/loop-unroll.c | 2 +-
gcc/lower-subreg.c | 16 ++--
gcc/lra-constraints.c | 56 +++++++-------
gcc/lra-eliminations.c | 8 +-
gcc/lra.c | 6 +-
gcc/mode-switching.c | 14 ++--
gcc/modulo-sched.c | 2 +-
gcc/optabs.c | 6 +-
gcc/postreload-gcse.c | 4 +-
gcc/postreload.c | 16 ++--
gcc/print-rtl.c | 4 +-
gcc/read-rtl-function.c | 6 +-
gcc/read-rtl.c | 2 +-
gcc/recog.c | 12 +--
gcc/ree.c | 12 +--
gcc/reg-stack.c | 14 ++--
gcc/regcprop.c | 6 +-
gcc/reginfo.c | 18 ++---
gcc/regrename.c | 10 +--
gcc/reload.c | 68 ++++++++---------
gcc/reload1.c | 66 ++++++++--------
gcc/reorg.c | 16 ++--
gcc/resource.c | 6 +-
gcc/rtl.c | 4 +-
gcc/rtlanal.c | 46 ++++++------
gcc/rtlhooks.c | 2 +-
gcc/sched-deps.c | 12 +--
gcc/sched-rgn.c | 4 +-
gcc/sel-sched.c | 2 +-
gcc/simplify-rtx.c | 86 ++++++++++-----------
gcc/symtab.c | 4 +-
gcc/tree-ssa-address.c | 8 +-
gcc/valtrack.c | 6 +-
gcc/var-tracking.c | 64 ++++++++--------
gcc/varasm.c | 26 +++----
gcc/xcoffout.h | 2 +-
86 files changed, 692 insertions(+), 692 deletions(-)
diff --git a/gcc/alias.c b/gcc/alias.c
index 2755df72907..86ada16b6ae 100644
--- a/gcc/alias.c
+++ b/gcc/alias.c
@@ -2222,7 +2222,7 @@ base_alias_check (rtx x, rtx x_base, rtx y, rtx y_base,
return 1;
/* Differing symbols not accessed via AND never alias. */
- if (GET_CODE (x_base) == SYMBOL_REF && GET_CODE (y_base) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x_base) && SYMBOL_REF_P (y_base))
return compare_base_symbol_refs (x_base, y_base) != 0;
if (GET_CODE (x_base) != ADDRESS && GET_CODE (y_base) != ADDRESS)
@@ -2444,7 +2444,7 @@ memrefs_conflict_p (poly_int64 xsize, rtx x, poly_int64 ysize, rtx y,
else
y = addr_side_effect_eval (y, maybe_lt (ysize, 0) ? -ysize : ysize, 0);
- if (GET_CODE (x) == SYMBOL_REF && GET_CODE (y) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_P (y))
{
int cmp = compare_base_symbol_refs (x,y);
@@ -2954,8 +2954,8 @@ true_dependence_1 (const_rtx mem, machine_mode mem_mode, rtx mem_addr,
return 1;
base = find_base_term (x_addr);
- if (base && (GET_CODE (base) == LABEL_REF
- || (GET_CODE (base) == SYMBOL_REF
+ if (base && (LABEL_REF_P (base)
+ || (SYMBOL_REF_P (base)
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
@@ -3063,8 +3063,8 @@ write_dependence_p (const_rtx mem,
base = find_base_term (true_mem_addr);
if (! writep
&& base
- && (GET_CODE (base) == LABEL_REF
- || (GET_CODE (base) == SYMBOL_REF
+ && (LABEL_REF_P (base)
+ || (SYMBOL_REF_P (base)
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
diff --git a/gcc/asan.c b/gcc/asan.c
index a731bd490b4..9976f709a88 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1805,7 +1805,7 @@ asan_protect_global (tree decl, bool ignore_decl_rtl_set_p)
{
rtl = DECL_RTL (decl);
- if (!MEM_P (rtl) || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF)
+ if (!MEM_P (rtl) || !SYMBOL_REF_P (XEXP (rtl, 0)))
return false;
symbol = XEXP (rtl, 0);
diff --git a/gcc/bb-reorder.c b/gcc/bb-reorder.c
index 0ac39140c6c..43623e00d76 100644
--- a/gcc/bb-reorder.c
+++ b/gcc/bb-reorder.c
@@ -2167,7 +2167,7 @@ fix_crossing_conditional_branches (void)
new_label = gen_label_rtx ();
emit_label (new_label);
- gcc_assert (GET_CODE (old_label) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (old_label));
old_jump_target = old_jump_insn->jump_target ();
new_jump = as_a <rtx_jump_insn *>
(emit_jump_insn (targetm.gen_jump (old_jump_target)));
diff --git a/gcc/bt-load.c b/gcc/bt-load.c
index f68879ca49a..11eee41e9d5 100644
--- a/gcc/bt-load.c
+++ b/gcc/bt-load.c
@@ -226,7 +226,7 @@ insn_sets_btr_p (const rtx_insn *insn, int check_const, int *regno)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = XEXP (dest, 0);
if (REG_P (dest)
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 695a9d191af..c01c9d4c789 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -1796,7 +1796,7 @@ expand_builtin_apply (rtx function, rtx arguments, rtx argsize)
/* Ensure address is valid. SYMBOL_REF is already valid, so no need,
and we don't want to load it into a register as an optimization,
because prepare_call_address already did it if it should be done. */
- if (GET_CODE (function) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (function))
function = memory_address (FUNCTION_MODE, function);
/* Generate the actual call instruction and save the return value. */
diff --git a/gcc/caller-save.c b/gcc/caller-save.c
index 7c1de894976..e816d080b82 100644
--- a/gcc/caller-save.c
+++ b/gcc/caller-save.c
@@ -955,7 +955,7 @@ mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data)
int regno, endregno, i;
HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
rtx inner = SUBREG_REG (reg);
if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
@@ -990,7 +990,7 @@ add_stored_regs (rtx reg, const_rtx setter, void *data)
if (GET_CODE (setter) == CLOBBER)
return;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& REG_P (SUBREG_REG (reg))
&& REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/calls.c b/gcc/calls.c
index 7507b698e27..7be7d3b7211 100644
--- a/gcc/calls.c
+++ b/gcc/calls.c
@@ -217,7 +217,7 @@ prepare_call_address (tree fndecl_or_type, rtx funexp, rtx static_chain_value,
{
/* Make a valid memory address and copy constants through pseudo-regs,
but not for a constant address if -fno-function-cse. */
- if (GET_CODE (funexp) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (funexp))
{
/* If it's an indirect call by descriptor, generate code to perform
runtime identification of the pointer and load the descriptor. */
@@ -393,7 +393,7 @@ emit_call_1 (rtx funexp, tree fntree ATTRIBUTE_UNUSED, tree fndecl ATTRIBUTE_UNU
/* Ensure address is valid. SYMBOL_REF is already valid, so no need,
and we don't want to load it into a register as an optimization,
because prepare_call_address already did it if it should be done. */
- if (GET_CODE (funexp) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (funexp))
funexp = memory_address (FUNCTION_MODE, funexp);
funmem = gen_rtx_MEM (FUNCTION_MODE, funexp);
@@ -1004,7 +1004,7 @@ precompute_register_parameters (int num_actuals, struct arg_data *args,
loading the parameters registers. */
else if ((! (REG_P (args[i].value)
- || (GET_CODE (args[i].value) == SUBREG
+ || (SUBREG_P (args[i].value)
&& REG_P (SUBREG_REG (args[i].value)))))
&& args[i].mode != BLKmode
&& (set_src_cost (args[i].value, args[i].mode,
@@ -4286,7 +4286,7 @@ expand_call (tree exp, rtx target, int ignore)
{
datum = XEXP (DECL_RTL (fndecl), 0);
gcc_assert (datum != NULL_RTX
- && GET_CODE (datum) == SYMBOL_REF);
+ && SYMBOL_REF_P (datum));
}
last = last_call_insn ();
add_reg_note (last, REG_CALL_DECL, datum);
@@ -5333,7 +5333,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value,
if (flag_ipa_ra)
{
rtx datum = orgfun;
- gcc_assert (GET_CODE (datum) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (datum));
rtx_call_insn *last = last_call_insn ();
add_reg_note (last, REG_CALL_DECL, datum);
}
diff --git a/gcc/cfgbuild.c b/gcc/cfgbuild.c
index 934325c6538..8ac13b753dd 100644
--- a/gcc/cfgbuild.c
+++ b/gcc/cfgbuild.c
@@ -273,7 +273,7 @@ make_edges (basic_block min, basic_block max, int update_p)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2)))
make_label_edge (edge_cache, bb,
label_ref_label (XEXP (SET_SRC (tmp), 2)), 0);
}
@@ -414,7 +414,7 @@ purge_dead_tablejump_edges (basic_block bb, rtx_jump_table_data *table)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2)))
mark_tablejump_edge (label_ref_label (XEXP (SET_SRC (tmp), 2)));
for (ei = ei_start (bb->succs); (e = ei_safe_edge (ei)); )
diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c
index b9307631e1c..e6d3b00364f 100644
--- a/gcc/cfgcleanup.c
+++ b/gcc/cfgcleanup.c
@@ -1209,7 +1209,7 @@ old_insns_match_p (int mode ATTRIBUTE_UNUSED, rtx_insn *i1, rtx_insn *i2)
if (flag_sanitize & SANITIZE_ADDRESS)
{
rtx call = get_call_rtx_from (i1);
- if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (call && SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol)
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 33af991573f..8f573140d62 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -3786,7 +3786,7 @@ expand_gimple_stmt_1 (gimple *stmt)
bool promoted = false;
target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
promoted = true;
ops.code = gimple_assign_rhs_code (assign_stmt);
@@ -4411,7 +4411,7 @@ expand_debug_expr (tree exp)
op0 = make_decl_rtl_for_debug (exp);
if (!MEM_P (op0)
- || GET_CODE (XEXP (op0, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op0, 0))
|| SYMBOL_REF_DECL (XEXP (op0, 0)) != exp)
return NULL;
}
@@ -5481,8 +5481,8 @@ expand_debug_locations (void)
gcc_assert (mode == GET_MODE (val)
|| (GET_MODE (val) == VOIDmode
&& (CONST_SCALAR_INT_P (val)
- || GET_CODE (val) == CONST_FIXED
- || GET_CODE (val) == LABEL_REF)));
+ || CONST_FIXED_P (val)
+ || LABEL_REF_P (val))));
}
INSN_VAR_LOCATION_LOC (insn) = val;
diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c
index 1f222aea5d1..6e5ccd46c22 100644
--- a/gcc/cfgrtl.c
+++ b/gcc/cfgrtl.c
@@ -1217,7 +1217,7 @@ patch_jump_insn (rtx_insn *insn, rtx_insn *old_label, basic_block new_bb)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2))
&& label_ref_label (XEXP (SET_SRC (tmp), 2)) == old_label)
{
XEXP (SET_SRC (tmp), 2) = gen_rtx_LABEL_REF (Pmode,
@@ -1238,7 +1238,7 @@ patch_jump_insn (rtx_insn *insn, rtx_insn *old_label, basic_block new_bb)
for (i = 0; i < n; ++i)
{
rtx old_ref = ASM_OPERANDS_LABEL (tmp, i);
- gcc_assert (GET_CODE (old_ref) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (old_ref));
if (XEXP (old_ref, 0) == old_label)
{
ASM_OPERANDS_LABEL (tmp, i)
diff --git a/gcc/combine.c b/gcc/combine.c
index f7b1ebc8cc0..1f43dd02dab 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -582,7 +582,7 @@ find_single_use_1 (rtx dest, rtx *loc)
if (GET_CODE (SET_DEST (x)) != CC0
&& GET_CODE (SET_DEST (x)) != PC
&& !REG_P (SET_DEST (x))
- && ! (GET_CODE (SET_DEST (x)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& !read_modify_subreg_p (SET_DEST (x))))
break;
@@ -738,7 +738,7 @@ do_SUBST (rtx *into, rtx newval)
when do_SUBST is called to replace the operand thereof, so we
perform this test on oldval instead, checking whether an
invalid replacement took place before we got here. */
- gcc_assert (!(GET_CODE (oldval) == SUBREG
+ gcc_assert (!(SUBREG_P (oldval)
&& CONST_INT_P (SUBREG_REG (oldval))));
gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
&& CONST_INT_P (XEXP (oldval, 0))));
@@ -2222,7 +2222,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
rtx subdest;
while (GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT)
inner_dest = XEXP (inner_dest, 0);
@@ -2265,7 +2265,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
STACK_POINTER_REGNUM, since these are always considered to be
live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
subdest = dest;
- if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
+ if (SUBREG_P (subdest) && !partial_subreg_p (subdest))
subdest = SUBREG_REG (subdest);
if (pi3dest_killed
&& REG_P (subdest)
@@ -2352,9 +2352,9 @@ cant_combine_insn_p (rtx_insn *insn)
return 0;
src = SET_SRC (set);
dest = SET_DEST (set);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
src = SUBREG_REG (src);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (src) && REG_P (dest)
&& ((HARD_REGISTER_P (src)
@@ -2476,7 +2476,7 @@ adjust_for_new_dest (rtx_insn *insn)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
gcc_assert (REG_P (reg));
@@ -2530,7 +2530,7 @@ reg_subword_p (rtx x, rtx reg)
|| GET_CODE (x) == ZERO_EXTRACT)
x = XEXP (x, 0);
- return GET_CODE (x) == SUBREG
+ return SUBREG_P (x)
&& SUBREG_REG (x) == reg
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
}
@@ -2779,13 +2779,13 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if ((set0 = single_set (i0))
/* Ensure the source of SET0 is a MEM, possibly buried inside
an extension. */
- && (GET_CODE (SET_SRC (set0)) == MEM
+ && (MEM_P (SET_SRC (set0))
|| ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
|| GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
- && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
+ && MEM_P (XEXP (SET_SRC (set0), 0))))
&& (set3 = single_set (i3))
/* Ensure the destination of SET3 is a MEM. */
- && GET_CODE (SET_DEST (set3)) == MEM
+ && MEM_P (SET_DEST (set3))
/* Would it be better to extract the base address for the MEM
in SET3 and look for that? I don't have cases where it matters
but I could envision such cases. */
@@ -3625,7 +3625,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (((REG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
- || (GET_CODE (SET_DEST (set1)) == SUBREG
+ || (SUBREG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set1)))
@@ -3636,14 +3636,14 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (((REG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
- || (GET_CODE (SET_DEST (set0)) == SUBREG
+ || (SUBREG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED,
SUBREG_REG (SET_DEST (set0)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set0)))
{
rtx dest = SET_DEST (set1);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!reg_used_between_p (dest, i2, i3))
{
@@ -3800,12 +3800,12 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
|| GET_CODE (new_i3_dest) == STRICT_LOW_PART
- || GET_CODE (new_i3_dest) == SUBREG)
+ || SUBREG_P (new_i3_dest))
new_i3_dest = XEXP (new_i3_dest, 0);
while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
|| GET_CODE (new_i2_dest) == STRICT_LOW_PART
- || GET_CODE (new_i2_dest) == SUBREG)
+ || SUBREG_P (new_i2_dest))
new_i2_dest = XEXP (new_i2_dest, 0);
if (REG_P (new_i3_dest)
@@ -4037,7 +4037,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
HOST_BITS_PER_INT)
&& (reg_stat[REGNO (temp_expr)].nonzero_bits
!= GET_MODE_MASK (word_mode))))
- && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
+ && ! (SUBREG_P (SET_DEST (XVECEXP (newpat, 0, 1)))
&& (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
(REG_P (temp_expr)
&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
@@ -4112,7 +4112,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (!modified_between_p (SET_SRC (set1), i2, i3)
&& !(REG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
- && !(GET_CODE (SET_DEST (set1)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set1))))
&& !modified_between_p (SET_DEST (set1), i2, i3)
@@ -4128,7 +4128,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (!modified_between_p (SET_SRC (set0), i2, i3)
&& !(REG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
- && !(GET_CODE (SET_DEST (set0)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set0))))
&& !modified_between_p (SET_DEST (set0), i2, i3)
@@ -4971,7 +4971,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
/* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
using LO_SUM and HIGH. */
if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
- || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
+ || SYMBOL_REF_P (XEXP (x, 0))))
{
machine_mode address_mode = get_address_mode (x);
@@ -5045,7 +5045,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 0)))))
{
@@ -5062,7 +5062,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 1)))))
{
@@ -5082,7 +5082,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
This will occur on machines that just support REG + CONST
and have a constant moved through some previous computation. */
if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
}
@@ -5093,7 +5093,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
MEM_ADDR_SPACE (x))
&& ! OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
break;
@@ -5108,7 +5108,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& GET_CODE (SET_SRC (x)) != COMPARE
&& GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
&& !OBJECT_P (SET_SRC (x))
- && ! (GET_CODE (SET_SRC (x)) == SUBREG
+ && ! (SUBREG_P (SET_SRC (x))
&& OBJECT_P (SUBREG_REG (SET_SRC (x)))))
return &SET_SRC (x);
@@ -5313,7 +5313,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (BINARY_P (SET_SRC (x))
&& CONSTANT_P (XEXP (SET_SRC (x), 1))
&& (OBJECT_P (XEXP (SET_SRC (x), 0))
- || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
+ || (SUBREG_P (XEXP (SET_SRC (x), 0))
&& OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
return &XEXP (SET_SRC (x), 1);
@@ -5361,7 +5361,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
constant. It may be better to try splitting (plus (mult B -C) A)
instead if this isn't a multiply by a power of two. */
if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
- && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 1), 1))
&& !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
{
machine_mode mode = GET_MODE (x);
@@ -5382,7 +5382,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (!set_src
&& (GET_CODE (XEXP (x, 0)) == MULT
|| (GET_CODE (XEXP (x, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return loc;
default:
@@ -5626,7 +5626,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
tieable and it is valid if X is a SET that copies
FROM to CC0. */
- if (GET_CODE (to) == SUBREG
+ if (SUBREG_P (to)
&& !targetm.modes_tieable_p (GET_MODE (to),
GET_MODE (SUBREG_REG (to)))
&& ! (code == SUBREG
@@ -5676,7 +5676,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
return new_rtx;
- if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
+ if (SUBREG_P (x) && CONST_SCALAR_INT_P (new_rtx))
{
machine_mode mode = GET_MODE (x);
@@ -5830,14 +5830,14 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
if ((BINARY_P (x)
&& ((!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
|| (!OBJECT_P (XEXP (x, 1))
- && ! (GET_CODE (XEXP (x, 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 1))
&& OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
|| (UNARY_P (x)
&& (!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
{
rtx cond, true_rtx, false_rtx;
@@ -6049,7 +6049,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
complex if it was just a register. */
if (!REG_P (temp)
- && ! (GET_CODE (temp) == SUBREG
+ && ! (SUBREG_P (temp)
&& REG_P (SUBREG_REG (temp)))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
@@ -6151,7 +6151,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
"a = (b & 8) == 0;" */
if (XEXP (x, 1) == constm1_rtx
&& !REG_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& REG_P (SUBREG_REG (XEXP (x, 0))))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& nonzero_bits (XEXP (x, 0), int_mode) == 1)
@@ -6587,7 +6587,7 @@ simplify_if_then_else (rtx x)
&& !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
|| true_rtx == const0_rtx
|| (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
- || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
+ || (SUBREG_P (true_rtx) && OBJECT_P (SUBREG_REG (true_rtx))
&& !OBJECT_P (false_rtx))
|| reg_mentioned_p (true_rtx, false_rtx)
|| rtx_equal_p (false_rtx, XEXP (cond, 0))))
@@ -6712,7 +6712,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6729,7 +6729,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6750,7 +6750,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
@@ -6767,7 +6767,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
@@ -7051,7 +7051,7 @@ simplify_set (rtx x)
be undefined. On machine where it is defined, this transformation is safe
as long as M1 and M2 have the same number of words. */
- if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
+ if (SUBREG_P (src) && subreg_lowpart_p (src)
&& !OBJECT_P (SUBREG_REG (src))
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (src)),
@@ -7063,7 +7063,7 @@ simplify_set (rtx x)
GET_MODE (SUBREG_REG (src)),
GET_MODE (src)))
&& (REG_P (dest)
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest)))))
{
SUBST (SET_DEST (x),
@@ -7387,7 +7387,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& HWI_COMPUTABLE_MODE_P (mode)
@@ -7407,7 +7407,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
@@ -7482,7 +7482,7 @@ expand_field_assignment (const_rtx x)
while (1)
{
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
- && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
+ && SUBREG_P (XEXP (SET_DEST (x), 0)))
{
rtx x0 = XEXP (SET_DEST (x), 0);
if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
@@ -7524,7 +7524,7 @@ expand_field_assignment (const_rtx x)
/* If the destination is a subreg that overwrites the whole of the inner
register, we can move the subreg to the source. */
- else if (GET_CODE (SET_DEST (x)) == SUBREG
+ else if (SUBREG_P (SET_DEST (x))
/* We need SUBREGs to compute nonzero_bits properly. */
&& nonzero_sign_valid
&& !read_modify_subreg_p (SET_DEST (x)))
@@ -7538,7 +7538,7 @@ expand_field_assignment (const_rtx x)
else
break;
- while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
+ while (SUBREG_P (inner) && subreg_lowpart_p (inner))
inner = SUBREG_REG (inner);
/* Don't attempt bitwise arithmetic on non scalar integer modes. */
@@ -7631,7 +7631,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (pos_rtx && CONST_INT_P (pos_rtx))
pos = INTVAL (pos_rtx), pos_rtx = 0;
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& subreg_lowpart_p (inner)
&& (paradoxical_subreg_p (inner)
/* If trying or potentionally trying to extract
@@ -7764,7 +7764,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (in_dest)
return (MEM_P (new_rtx) ? new_rtx
- : (GET_CODE (new_rtx) != SUBREG
+ : (!SUBREG_P (new_rtx)
? gen_rtx_CLOBBER (tmode, const0_rtx)
: gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
@@ -8189,7 +8189,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
}
/* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG
+ else if (SUBREG_P (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0))
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
&inner_mode)
@@ -8294,7 +8294,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
the constant (limited to the smaller mode) has only zero bits where
the sub expression has known zero bits, this can be expressed as
a zero_extend. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG)
+ else if (SUBREG_P (XEXP (x, 0)))
{
rtx sub;
@@ -8365,7 +8365,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
seem worth the effort; the case checked for occurs on Alpha. */
if (!OBJECT_P (lhs)
- && ! (GET_CODE (lhs) == SUBREG
+ && ! (SUBREG_P (lhs)
&& (OBJECT_P (SUBREG_REG (lhs))))
&& CONST_INT_P (rhs)
&& INTVAL (rhs) >= 0
@@ -8410,7 +8410,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
to the recursive make_compound_operation call. */
if (subreg_code == COMPARE
&& (!subreg_lowpart_p (x)
- || GET_CODE (inner) == SUBREG
+ || SUBREG_P (inner)
/* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
is (const_int 0), rather than
(subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
@@ -8440,7 +8440,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* If we have something other than a SUBREG, we might have
done an expansion, so rerun ourselves. */
- if (GET_CODE (newer) != SUBREG)
+ if (!SUBREG_P (newer))
newer = make_compound_operation (newer, in_code);
/* force_to_mode can expand compounds. If it just re-expanded
@@ -8450,7 +8450,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* Likewise if it re-expanded the compound only partially.
This happens for SUBREG of ZERO_EXTRACT if they extract
the same number of bits. */
- || (GET_CODE (newer) == SUBREG
+ || (SUBREG_P (newer)
&& (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
|| GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
&& GET_CODE (inner) == AND
@@ -8777,7 +8777,7 @@ force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
/* We can ignore the effect of a SUBREG if it narrows the mode or
if the constant masks to zero all the bits the mode doesn't have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& (partial_subreg_p (x)
|| (mask
@@ -9711,13 +9711,13 @@ rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
/* Check for a paradoxical SUBREG of a MEM compared with the MEM.
Note that all SUBREGs of MEM are paradoxical; otherwise they
would have been rewritten. */
- if (MEM_P (x) && GET_CODE (y) == SUBREG
+ if (MEM_P (x) && SUBREG_P (y)
&& MEM_P (SUBREG_REG (y))
&& rtx_equal_p (SUBREG_REG (y),
gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
return 1;
- if (MEM_P (y) && GET_CODE (x) == SUBREG
+ if (MEM_P (y) && SUBREG_P (x)
&& MEM_P (SUBREG_REG (x))
&& rtx_equal_p (SUBREG_REG (x),
gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
@@ -9770,7 +9770,7 @@ make_field_assignment (rtx x)
return x;
}
- if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
+ if (GET_CODE (src) == AND && SUBREG_P (XEXP (src, 0))
&& subreg_lowpart_p (XEXP (src, 0))
&& partial_subreg_p (XEXP (src, 0))
&& GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
@@ -9842,7 +9842,7 @@ make_field_assignment (rtx x)
narrowing SUBREG, which we can just strip for the purposes of
identifying the constant-field assignment. */
scalar_int_mode src_mode = mode;
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& subreg_lowpart_p (src)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
src = SUBREG_REG (src);
@@ -11622,7 +11622,7 @@ change_zero_ext (rtx pat)
}
}
else if (GET_CODE (x) == ZERO_EXTEND
- && GET_CODE (XEXP (x, 0)) == SUBREG
+ && SUBREG_P (XEXP (x, 0))
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
&& !paradoxical_subreg_p (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0)))
@@ -11781,7 +11781,7 @@ gen_lowpart_for_combine (machine_mode omode, rtx x)
/* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
won't know what to do. So we will strip off the SUBREG here and
process normally. */
- if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
{
x = SUBREG_REG (x);
@@ -12076,8 +12076,8 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
&& GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
&& GET_CODE (XEXP (op0, 0)) == ASHIFT
&& GET_CODE (XEXP (op1, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
- && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (op0, 0), 0))
+ && SUBREG_P (XEXP (XEXP (op1, 0), 0))
&& is_a <scalar_int_mode> (GET_MODE (op0), &mode)
&& (is_a <scalar_int_mode>
(GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
@@ -12151,7 +12151,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
int changed = 0;
if (paradoxical_subreg_p (inner_op0)
- && GET_CODE (inner_op1) == SUBREG
+ && SUBREG_P (inner_op1)
&& HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
&& (GET_MODE (SUBREG_REG (inner_op0))
== GET_MODE (SUBREG_REG (inner_op1)))
@@ -12729,7 +12729,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
fits in both M1 and M2 and the SUBREG is either paradoxical
or represents the low part, permute the SUBREG and the AND
and try again. */
- if (GET_CODE (XEXP (op0, 0)) == SUBREG
+ if (SUBREG_P (XEXP (op0, 0))
&& CONST_INT_P (XEXP (op0, 1)))
{
unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
@@ -13008,7 +13008,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
op0 = make_compound_operation (op0, op0_mco_code);
op1 = make_compound_operation (op1, SET);
- if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
+ if (SUBREG_P (op0) && subreg_lowpart_p (op0)
&& is_int_mode (GET_MODE (op0), &mode)
&& is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
&& (code == NE || code == EQ))
@@ -13376,7 +13376,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
{
rtx_insn *record_dead_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!record_dead_insn)
@@ -13397,7 +13397,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
else if (GET_CODE (setter) == SET
- && GET_CODE (SET_DEST (setter)) == SUBREG
+ && SUBREG_P (SET_DEST (setter))
&& SUBREG_REG (SET_DEST (setter)) == dest
&& known_le (GET_MODE_PRECISION (GET_MODE (dest)),
BITS_PER_WORD)
@@ -13577,7 +13577,7 @@ record_truncated_value (rtx x)
machine_mode truncated_mode;
reg_stat_type *rsp;
- if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && REG_P (SUBREG_REG (x)))
{
machine_mode original_mode = GET_MODE (SUBREG_REG (x));
truncated_mode = GET_MODE (x);
@@ -13629,7 +13629,7 @@ record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
static void
check_promoted_subreg (rtx_insn *insn, rtx x)
{
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& REG_P (SUBREG_REG (x)))
record_promoted_value (insn, x);
@@ -13775,7 +13775,7 @@ get_last_value (const_rtx x)
/* If this is a non-paradoxical SUBREG, get the value of its operand and
then convert it to the desired mode. If this is a paradoxical SUBREG,
we cannot predict what values the "extra" bits might have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& !paradoxical_subreg_p (x)
&& (value = get_last_value (SUBREG_REG (x))) != 0)
@@ -13982,7 +13982,7 @@ mark_used_regs_combine (rtx x)
the address. */
rtx testreg = SET_DEST (x);
- while (GET_CODE (testreg) == SUBREG
+ while (SUBREG_P (testreg)
|| GET_CODE (testreg) == ZERO_EXTRACT
|| GET_CODE (testreg) == STRICT_LOW_PART)
testreg = XEXP (testreg, 0);
@@ -14162,7 +14162,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
if (GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& !read_modify_subreg_p (dest)))
{
move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
@@ -14171,7 +14171,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
/* If this is some other SUBREG, we know it replaces the entire
value, so use that as the destination. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
/* If this is a MEM, adjust deaths of anything used in the address.
@@ -14225,7 +14225,7 @@ reg_bitfield_target_p (rtx x, rtx body)
else
return 0;
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
target = SUBREG_REG (target);
if (!REG_P (target))
@@ -14483,14 +14483,14 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
/* ??? Ignore the without-reg_equal-note problem for now. */
if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
|| ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
- && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (tem_note, 0))
&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
place = i3;
if (i2
&& (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
|| ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
- && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (tem_note, 0))
&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
{
if (place)
@@ -14624,7 +14624,7 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
if (set != 0)
for (inner_dest = SET_DEST (set);
(GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT);
inner_dest = XEXP (inner_dest, 0))
;
@@ -14892,7 +14892,7 @@ distribute_links (struct insn_link *links)
reg = SET_DEST (set);
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (!REG_P (reg))
@@ -14911,7 +14911,7 @@ distribute_links (struct insn_link *links)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (reg == pc_rtx)
diff --git a/gcc/cprop.c b/gcc/cprop.c
index 65c0130cc07..ecb383487bc 100644
--- a/gcc/cprop.c
+++ b/gcc/cprop.c
@@ -1621,7 +1621,7 @@ bypass_block (basic_block bb, rtx_insn *setcc, rtx_insn *jump)
edest = FALLTHRU_EDGE (bb);
dest = edest->insns.r ? NULL : edest->dest;
}
- else if (GET_CODE (new_rtx) == LABEL_REF)
+ else if (LABEL_REF_P (new_rtx))
{
dest = BLOCK_FOR_INSN (XEXP (new_rtx, 0));
/* Don't bypass edges containing instructions. */
diff --git a/gcc/cse.c b/gcc/cse.c
index 35840a6d5ca..5662dc0eeae 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -722,7 +722,7 @@ static int
notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno)
{
scalar_int_mode int_mode, inner_mode;
- return ((GET_CODE (x) == SUBREG
+ return ((SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& is_int_mode (mode, &int_mode)
&& is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode)
@@ -1171,7 +1171,7 @@ insert_regs (rtx x, struct table_elt *classp, int modified)
not be accessible because its hash code will have changed. So assign
a quantity number now. */
- else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))
+ else if (SUBREG_P (x) && REG_P (SUBREG_REG (x))
&& ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x))))
{
insert_regs (SUBREG_REG (x), NULL, 0);
@@ -1289,7 +1289,7 @@ find_reg_offset_for_const (struct table_elt *anchor_elt, HOST_WIDE_INT offs,
if (REG_P (elt->exp)
|| (GET_CODE (elt->exp) == PLUS
&& REG_P (XEXP (elt->exp, 0))
- && GET_CODE (XEXP (elt->exp, 1)) == CONST_INT))
+ && CONST_INT_P (XEXP (elt->exp, 1))))
{
rtx x;
@@ -1828,7 +1828,7 @@ check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr)
static void
invalidate_reg (rtx x, bool clobber_high)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
/* If X is a register, dependencies on its contents are recorded
through the qty number mechanism. Just change the qty number of
@@ -1984,7 +1984,7 @@ static void
invalidate_dest (rtx dest)
{
if (REG_P (dest)
- || GET_CODE (dest) == SUBREG
+ || SUBREG_P (dest)
|| MEM_P (dest))
invalidate (dest, VOIDmode);
else if (GET_CODE (dest) == STRICT_LOW_PART
@@ -2028,7 +2028,7 @@ remove_invalid_subreg_refs (unsigned int regno, poly_uint64 offset,
next = p->next_same_hash;
if (!REG_P (exp)
- && (GET_CODE (exp) != SUBREG
+ && (!SUBREG_P (exp)
|| !REG_P (SUBREG_REG (exp))
|| REGNO (SUBREG_REG (exp)) != regno
|| ranges_maybe_overlap_p (SUBREG_BYTE (exp),
@@ -2051,7 +2051,7 @@ rehash_using_reg (rtx x)
struct table_elt *p, *next;
unsigned hash;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
/* If X is not a register or if the register is known not to be in any
@@ -3537,13 +3537,13 @@ fold_rtx (rtx x, rtx_insn *insn)
with that LABEL_REF as its second operand. If so, the result is
the first operand of that MINUS. This handles switches with an
ADDR_DIFF_VEC table. */
- if (const_arg1 && GET_CODE (const_arg1) == LABEL_REF)
+ if (const_arg1 && LABEL_REF_P (const_arg1))
{
rtx y
= GET_CODE (folded_arg0) == MINUS ? folded_arg0
: lookup_as_function (folded_arg0, MINUS);
- if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF
+ if (y != 0 && LABEL_REF_P (XEXP (y, 1))
&& label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg1))
return XEXP (y, 0);
@@ -3551,19 +3551,19 @@ fold_rtx (rtx x, rtx_insn *insn)
if ((y = (GET_CODE (folded_arg0) == CONST ? folded_arg0
: lookup_as_function (folded_arg0, CONST))) != 0
&& GET_CODE (XEXP (y, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (y, 0), 1))
&& label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg1))
return XEXP (XEXP (y, 0), 0);
}
/* Likewise if the operands are in the other order. */
- if (const_arg0 && GET_CODE (const_arg0) == LABEL_REF)
+ if (const_arg0 && LABEL_REF_P (const_arg0))
{
rtx y
= GET_CODE (folded_arg1) == MINUS ? folded_arg1
: lookup_as_function (folded_arg1, MINUS);
- if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF
+ if (y != 0 && LABEL_REF_P (XEXP (y, 1))
&& label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg0))
return XEXP (y, 0);
@@ -3571,7 +3571,7 @@ fold_rtx (rtx x, rtx_insn *insn)
if ((y = (GET_CODE (folded_arg1) == CONST ? folded_arg1
: lookup_as_function (folded_arg1, CONST))) != 0
&& GET_CODE (XEXP (y, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (y, 0), 1))
&& label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg0))
return XEXP (XEXP (y, 0), 0);
}
@@ -3811,7 +3811,7 @@ equiv_constant (rtx x)
if (x == 0 || CONSTANT_P (x))
return x;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
machine_mode mode = GET_MODE (x);
machine_mode imode = GET_MODE (SUBREG_REG (x));
@@ -4310,7 +4310,7 @@ find_sets_in_insn (rtx_insn *insn, struct set **psets)
and not be misled by unchanged instructions
that were unconditional jumps to begin with. */
if (SET_DEST (x) == pc_rtx
- && GET_CODE (SET_SRC (x)) == LABEL_REF)
+ && LABEL_REF_P (SET_SRC (x)))
;
/* Don't count call-insns, (set (reg 0) (call ...)), as a set.
The hard function value register is used only once, to copy to
@@ -4334,7 +4334,7 @@ find_sets_in_insn (rtx_insn *insn, struct set **psets)
/* As above, we ignore unconditional jumps and call-insns and
ignore the result of apply_change_group. */
if (SET_DEST (y) == pc_rtx
- && GET_CODE (SET_SRC (y)) == LABEL_REF)
+ && LABEL_REF_P (SET_SRC (y)))
;
else if (GET_CODE (SET_SRC (y)) == CALL)
;
@@ -4517,7 +4517,7 @@ canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets)
canon_reg (XEXP (dest, 2), insn), 1);
}
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -4842,8 +4842,8 @@ cse_insn (rtx_insn *insn)
"constant" here so we will record it. This allows us
to fold switch statements when an ADDR_DIFF_VEC is used. */
|| (GET_CODE (src_folded) == MINUS
- && GET_CODE (XEXP (src_folded, 0)) == LABEL_REF
- && GET_CODE (XEXP (src_folded, 1)) == LABEL_REF)))
+ && LABEL_REF_P (XEXP (src_folded, 0))
+ && LABEL_REF_P (XEXP (src_folded, 1)))))
src_const = src_folded, src_const_elt = elt;
else if (src_const == 0 && src_eqv_here && CONSTANT_P (src_eqv_here))
src_const = src_eqv_here, src_const_elt = src_eqv_elt;
@@ -5029,7 +5029,7 @@ cse_insn (rtx_insn *insn)
if (targetm.const_anchor
&& !src_related
&& src_const
- && GET_CODE (src_const) == CONST_INT)
+ && CONST_INT_P (src_const))
{
src_related = try_const_anchors (src_const, mode);
src_related_is_const_anchor = src_related != NULL_RTX;
@@ -5066,7 +5066,7 @@ cse_insn (rtx_insn *insn)
looking for. */
if (paradoxical_subreg_p (p->exp)
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (p->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (p->exp)))))
@@ -5155,7 +5155,7 @@ cse_insn (rtx_insn *insn)
/* If this was an indirect jump insn, a known label will really be
cheaper even though it looks more expensive. */
- if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF)
+ if (dest == pc_rtx && src_const && LABEL_REF_P (src_const))
src_folded = src_const, src_folded_cost = src_folded_regcost = -1;
/* Terminate loop when replacement made. This must terminate since
@@ -5177,7 +5177,7 @@ cse_insn (rtx_insn *insn)
/* It is okay, though, if the rtx we're trying to match
will ignore any of the bits we can't predict. */
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (elt->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (elt->exp)))))
@@ -5341,11 +5341,11 @@ cse_insn (rtx_insn *insn)
barriers). */
if (n_sets == 1 && dest == pc_rtx
&& (trial == pc_rtx
- || (GET_CODE (trial) == LABEL_REF
+ || (LABEL_REF_P (trial)
&& ! condjump_p (insn))))
{
/* Don't substitute non-local labels, this confuses CFG. */
- if (GET_CODE (trial) == LABEL_REF
+ if (LABEL_REF_P (trial)
&& LABEL_REF_NONLOCAL_P (trial))
continue;
@@ -5380,8 +5380,8 @@ cse_insn (rtx_insn *insn)
/* Likewise on IA-64, except without the
truncate. */
|| (GET_CODE (XEXP (trial, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (trial, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (trial, 0), 1)) == LABEL_REF)))
+ && LABEL_REF_P (XEXP (XEXP (trial, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (trial, 0), 1)))))
/* Do nothing for this case. */
;
@@ -5501,12 +5501,12 @@ cse_insn (rtx_insn *insn)
&& REG_P (dest)
&& src_const
&& !REG_P (src_const)
- && !(GET_CODE (src_const) == SUBREG
+ && !(SUBREG_P (src_const)
&& REG_P (SUBREG_REG (src_const)))
&& !(GET_CODE (src_const) == CONST
&& GET_CODE (XEXP (src_const, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (src_const, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (src_const, 0), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (XEXP (src_const, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (src_const, 0), 1)))
&& !rtx_equal_p (src, src_const))
{
/* Make sure that the rtx is not shared. */
@@ -5522,7 +5522,7 @@ cse_insn (rtx_insn *insn)
do_not_record = 0;
/* Look within any ZERO_EXTRACT to the MEM or REG within it. */
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -5599,7 +5599,7 @@ cse_insn (rtx_insn *insn)
/* If this SET is now setting PC to a label, we know it used to
be a conditional or computed branch. */
- else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF
+ else if (dest == pc_rtx && LABEL_REF_P (src)
&& !LABEL_REF_NONLOCAL_P (src))
{
/* We reemit the jump in as many cases as possible just in
@@ -5853,7 +5853,7 @@ cse_insn (rtx_insn *insn)
previous quantity's chain.
Needed for memory if this is a nonvarying address, unless
we have just done an invalidate_memory that covers even those. */
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
invalidate (dest, VOIDmode);
else if (MEM_P (dest))
invalidate (dest, VOIDmode);
@@ -5975,7 +5975,7 @@ cse_insn (rtx_insn *insn)
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = SUBREG_REG (XEXP (dest, 0));
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
/* Registers must also be inserted into chains for quantities. */
if (insert_regs (dest, sets[i].src_elt, 1))
{
@@ -5998,7 +5998,7 @@ cse_insn (rtx_insn *insn)
if (targetm.const_anchor
&& REG_P (dest)
&& SCALAR_INT_MODE_P (GET_MODE (dest))
- && GET_CODE (sets[i].src_elt->exp) == CONST_INT)
+ && CONST_INT_P (sets[i].src_elt->exp))
insert_const_anchors (dest, sets[i].src_elt->exp, GET_MODE (dest));
elt->in_memory = (MEM_P (sets[i].inner_dest)
@@ -6019,7 +6019,7 @@ cse_insn (rtx_insn *insn)
Note the loop below will find SUBREG_REG (DEST) since we have
already entered SRC and DEST of the SET in the table. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& (known_equal_after_align_down
(GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) - 1,
GET_MODE_SIZE (GET_MODE (dest)) - 1,
@@ -6147,7 +6147,7 @@ invalidate_from_clobbers (rtx_insn *insn)
rtx ref = XEXP (x, 0);
if (ref)
{
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6170,7 +6170,7 @@ invalidate_from_clobbers (rtx_insn *insn)
if (GET_CODE (y) == CLOBBER)
{
rtx ref = XEXP (y, 0);
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6231,7 +6231,7 @@ invalidate_from_sets_and_clobbers (rtx_insn *insn)
rtx clobbered = XEXP (y, 0);
if (REG_P (clobbered)
- || GET_CODE (clobbered) == SUBREG)
+ || SUBREG_P (clobbered))
invalidate (clobbered, VOIDmode);
else if (GET_CODE (clobbered) == STRICT_LOW_PART
|| GET_CODE (clobbered) == ZERO_EXTRACT)
@@ -6582,7 +6582,7 @@ check_for_label_ref (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == LABEL_REF
+ if (LABEL_REF_P (x)
&& !LABEL_REF_NONLOCAL_P (x)
&& (!JUMP_P (insn)
|| !label_is_jump_target_p (label_ref_label (x), insn))
diff --git a/gcc/cselib.c b/gcc/cselib.c
index 7b0545e779c..27be48d2154 100644
--- a/gcc/cselib.c
+++ b/gcc/cselib.c
@@ -1474,7 +1474,7 @@ expand_loc (struct elt_loc_list *p, struct expand_value_data *evd,
fprintf (dump_file, "\n");
}
if (GET_CODE (p->loc) == LO_SUM
- && GET_CODE (XEXP (p->loc, 1)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (p->loc, 1))
&& p->setting_insn
&& (note = find_reg_note (p->setting_insn, REG_EQUAL, NULL_RTX))
&& XEXP (note, 0) == XEXP (p->loc, 1))
@@ -1692,7 +1692,7 @@ cselib_expand_value_rtx_1 (rtx orig, struct expand_value_data *evd,
GET_MODE (SUBREG_REG (orig)),
SUBREG_BYTE (orig));
if (scopy == NULL
- || (GET_CODE (scopy) == SUBREG
+ || (SUBREG_P (scopy)
&& !REG_P (SUBREG_REG (scopy))
&& !MEM_P (SUBREG_REG (scopy))))
return NULL;
@@ -2376,7 +2376,7 @@ cselib_invalidate_mem (rtx mem_rtx)
void
cselib_invalidate_rtx (rtx dest, const_rtx setter)
{
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 81577dfe5cd..2ecca9a7d81 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -2740,7 +2740,7 @@ dbxout_symbol (tree decl, int local ATTRIBUTE_UNUSED)
if (context && DECL_FROM_INLINE (decl))
break;
if (!MEM_P (decl_rtl)
- || GET_CODE (XEXP (decl_rtl, 0)) != SYMBOL_REF)
+ || !SYMBOL_REF_P (XEXP (decl_rtl, 0)))
break;
if (flag_debug_only_used_symbols)
@@ -3000,11 +3000,11 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
If the decl was from an inline function, then its rtl
is not identically the rtl that was used in this
particular compilation. */
- if (GET_CODE (home) == SUBREG)
+ if (SUBREG_P (home))
{
rtx value = home;
- while (GET_CODE (value) == SUBREG)
+ while (SUBREG_P (value))
value = SUBREG_REG (value);
if (REG_P (value))
{
@@ -3033,7 +3033,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
no letter at all, and N_LSYM, for auto variable,
r and N_RSYM for register variable. */
- if (MEM_P (home) && GET_CODE (XEXP (home, 0)) == SYMBOL_REF)
+ if (MEM_P (home) && SYMBOL_REF_P (XEXP (home, 0)))
{
if (TREE_PUBLIC (decl))
{
@@ -3058,13 +3058,13 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
dumped into a constant pool. Alternatively, the symbol
in the constant pool might be referenced by a different
symbol. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& CONSTANT_POOL_ADDRESS_P (addr))
{
bool marked;
rtx tmp = get_pool_constant_mark (addr, &marked);
- if (GET_CODE (tmp) == SYMBOL_REF)
+ if (SYMBOL_REF_P (tmp))
{
addr = tmp;
if (CONSTANT_POOL_ADDRESS_P (addr))
@@ -3072,7 +3072,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
else
marked = true;
}
- else if (GET_CODE (tmp) == LABEL_REF)
+ else if (LABEL_REF_P (tmp))
{
addr = tmp;
marked = true;
@@ -3329,17 +3329,17 @@ dbxout_common_check (tree decl, int *value)
return NULL;
home = DECL_RTL (decl);
- if (home == NULL_RTX || GET_CODE (home) != MEM)
+ if (home == NULL_RTX || !MEM_P (home))
return NULL;
sym_addr = dbxout_expand_expr (DECL_VALUE_EXPR (decl));
- if (sym_addr == NULL_RTX || GET_CODE (sym_addr) != MEM)
+ if (sym_addr == NULL_RTX || !MEM_P (sym_addr))
return NULL;
sym_addr = XEXP (sym_addr, 0);
if (GET_CODE (sym_addr) == CONST)
sym_addr = XEXP (sym_addr, 0);
- if ((GET_CODE (sym_addr) == SYMBOL_REF || GET_CODE (sym_addr) == PLUS)
+ if ((SYMBOL_REF_P (sym_addr) || GET_CODE (sym_addr) == PLUS)
&& DECL_INITIAL (decl) == 0)
{
diff --git a/gcc/defaults.h b/gcc/defaults.h
index af7ea185f1e..f4bdc7b0247 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1170,7 +1170,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
/* For most ports anything that evaluates to a constant symbolic
or integer value is acceptable as a constant address. */
#ifndef CONSTANT_ADDRESS_P
-#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && GET_CODE (X) != CONST_DOUBLE)
+#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && !CONST_DOUBLE_P (X))
#endif
#ifndef MAX_FIXED_MODE_SIZE
diff --git a/gcc/df-core.c b/gcc/df-core.c
index be19aba0f1e..1eae8dba891 100644
--- a/gcc/df-core.c
+++ b/gcc/df-core.c
@@ -1955,7 +1955,7 @@ df_find_def (rtx_insn *insn, rtx reg)
{
df_ref def;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -1984,7 +1984,7 @@ df_find_use (rtx_insn *insn, rtx reg)
{
df_ref use;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
diff --git a/gcc/df-problems.c b/gcc/df-problems.c
index d32c688510c..bc3f38a94bd 100644
--- a/gcc/df-problems.c
+++ b/gcc/df-problems.c
@@ -2811,7 +2811,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
int which_subword = -1;
bool changed = false;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (orig_reg);
regno = REGNO (reg);
reg_mode = GET_MODE (reg);
@@ -2819,7 +2819,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
|| maybe_ne (GET_MODE_SIZE (reg_mode), 2 * UNITS_PER_WORD))
return true;
- if (GET_CODE (orig_reg) == SUBREG
+ if (SUBREG_P (orig_reg)
&& read_modify_subreg_p (orig_reg))
{
gcc_assert (DF_REF_FLAGS_IS_SET (ref, DF_REF_PARTIAL));
@@ -4002,7 +4002,7 @@ find_memory_stores (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
int *pflags = (int *)data;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = XEXP (x, 0);
/* Treat stores to SP as stores to memory, this will prevent problems
when there are references to the stack frame. */
diff --git a/gcc/df-scan.c b/gcc/df-scan.c
index 03294a8a2c3..c3d52be4e49 100644
--- a/gcc/df-scan.c
+++ b/gcc/df-scan.c
@@ -2474,7 +2474,7 @@ df_ref_create_structure (enum df_ref_class cl,
int ref_flags)
{
df_ref this_ref = NULL;
- unsigned int regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ unsigned int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
struct df_scan_problem_data *problem_data
= (struct df_scan_problem_data *) df_scan->problem_data;
@@ -2561,9 +2561,9 @@ df_ref_record (enum df_ref_class cl,
{
unsigned int regno;
- gcc_checking_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
+ gcc_checking_assert (REG_P (reg) || SUBREG_P (reg));
- regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
if (regno < FIRST_PSEUDO_REGISTER)
{
struct df_mw_hardreg *hardreg = NULL;
@@ -2573,7 +2573,7 @@ df_ref_record (enum df_ref_class cl,
unsigned int endregno;
df_ref ref;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno += subreg_regno_offset (regno, GET_MODE (SUBREG_REG (reg)),
SUBREG_BYTE (reg), GET_MODE (reg));
@@ -2590,7 +2590,7 @@ df_ref_record (enum df_ref_class cl,
{
/* Sets to a subreg of a multiword register are partial.
Sets to a non-subreg of a multiword register are not. */
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
ref_flags |= DF_REF_PARTIAL;
ref_flags |= DF_REF_MW_HARDREG;
@@ -2673,7 +2673,7 @@ df_def_record_1 (class df_collection_rec *collection_rec,
df_ref_record (DF_REF_BASE, collection_rec,
dst, NULL, bb, insn_info, DF_REF_REG_USE, flags);
}
- else if (GET_CODE (dst) == SUBREG && REG_P (SUBREG_REG (dst)))
+ else if (SUBREG_P (dst) && REG_P (SUBREG_REG (dst)))
{
if (read_modify_subreg_p (dst))
flags |= DF_REF_READ_WRITE | DF_REF_PARTIAL;
@@ -2753,7 +2753,7 @@ df_find_hard_reg_defs_1 (rtx dst, HARD_REG_SET *defs)
/* At this point if we do not have a reg or a subreg, just return. */
if (REG_P (dst) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (dst));
- else if (GET_CODE (dst) == SUBREG
+ else if (SUBREG_P (dst)
&& REG_P (SUBREG_REG (dst)) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (SUBREG_REG (dst)));
}
@@ -2919,7 +2919,7 @@ df_uses_record (class df_collection_rec *collection_rec,
SUBREG. */
dst = XEXP (dst, 0);
df_uses_record (collection_rec,
- (GET_CODE (dst) == SUBREG) ? &SUBREG_REG (dst) : temp,
+ (SUBREG_P (dst)) ? &SUBREG_REG (dst) : temp,
DF_REF_REG_USE, bb, insn_info,
DF_REF_READ_WRITE | DF_REF_STRICT_LOW_PART);
}
@@ -2930,7 +2930,7 @@ df_uses_record (class df_collection_rec *collection_rec,
DF_REF_REG_USE, bb, insn_info, flags);
df_uses_record (collection_rec, &XEXP (dst, 2),
DF_REF_REG_USE, bb, insn_info, flags);
- if (GET_CODE (XEXP (dst,0)) == MEM)
+ if (MEM_P (XEXP (dst,0)))
df_uses_record (collection_rec, &XEXP (dst, 0),
DF_REF_REG_USE, bb, insn_info,
flags);
diff --git a/gcc/df.h b/gcc/df.h
index 2e3b825065e..039fe9e9b22 100644
--- a/gcc/df.h
+++ b/gcc/df.h
@@ -647,10 +647,10 @@ public:
/* Macros to access the elements within the ref structure. */
-#define DF_REF_REAL_REG(REF) (GET_CODE ((REF)->base.reg) == SUBREG \
+#define DF_REF_REAL_REG(REF) (SUBREG_P ((REF)->base.reg) \
? SUBREG_REG ((REF)->base.reg) : ((REF)->base.reg))
#define DF_REF_REGNO(REF) ((REF)->base.regno)
-#define DF_REF_REAL_LOC(REF) (GET_CODE (*((REF)->regular_ref.loc)) == SUBREG \
+#define DF_REF_REAL_LOC(REF) (SUBREG_P (*((REF)->regular_ref.loc)) \
? &SUBREG_REG (*((REF)->regular_ref.loc)) : ((REF)->regular_ref.loc))
#define DF_REF_REG(REF) ((REF)->base.reg)
#define DF_REF_LOC(REF) (DF_REF_CLASS (REF) == DF_REF_REGULAR ? \
diff --git a/gcc/dojump.c b/gcc/dojump.c
index bac37a357a9..040d2c260fb 100644
--- a/gcc/dojump.c
+++ b/gcc/dojump.c
@@ -610,7 +610,7 @@ do_jump (tree exp, rtx_code_label *if_false_label,
temp = expand_normal (exp);
do_pending_stack_adjust ();
/* The RTL optimizers prefer comparisons against pseudos. */
- if (GET_CODE (temp) == SUBREG)
+ if (SUBREG_P (temp))
{
/* Compare promoted variables in their promoted mode. */
if (SUBREG_PROMOTED_VAR_P (temp)
diff --git a/gcc/dse.c b/gcc/dse.c
index 8d7358d02b4..b7511a320da 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1056,7 +1056,7 @@ const_or_frame_p (rtx x)
if (CONSTANT_P (x))
return true;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* Note that we have to test for the actual rtx used for the frame
and arg pointers and not just the register number in case we have
@@ -1464,7 +1464,7 @@ record_store (rtx body, bb_info_t bb_info)
/* No place to keep the value after ra. */
&& !reload_completed
&& (REG_P (SET_SRC (body))
- || GET_CODE (SET_SRC (body)) == SUBREG
+ || SUBREG_P (SET_SRC (body))
|| CONSTANT_P (SET_SRC (body)))
&& !MEM_VOLATILE_P (mem)
/* Sometimes the store and reload is used for truncation and
@@ -2439,7 +2439,7 @@ scan_insn (bb_info_t bb_info, rtx_insn *insn)
if (!const_call
&& (call = get_call_rtx_from (insn))
&& (sym = XEXP (XEXP (call, 0), 0))
- && GET_CODE (sym) == SYMBOL_REF
+ && SYMBOL_REF_P (sym)
&& SYMBOL_REF_DECL (sym)
&& TREE_CODE (SYMBOL_REF_DECL (sym)) == FUNCTION_DECL
&& fndecl_built_in_p (SYMBOL_REF_DECL (sym), BUILT_IN_MEMSET))
diff --git a/gcc/dwarf2asm.c b/gcc/dwarf2asm.c
index 488e54b72ec..fc655272ed8 100644
--- a/gcc/dwarf2asm.c
+++ b/gcc/dwarf2asm.c
@@ -912,7 +912,7 @@ dw2_force_const_mem (rtx x, bool is_public)
if (! indirect_pool)
indirect_pool = hash_map<const char *, tree>::create_ggc (64);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
key = XSTR (x, 0);
tree *slot = indirect_pool->get (key);
@@ -1078,13 +1078,13 @@ dw2_asm_output_encoded_addr_rtx (int encoding, rtx addr, bool is_public,
#ifdef ASM_OUTPUT_DWARF_DATAREL
case DW_EH_PE_datarel:
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
ASM_OUTPUT_DWARF_DATAREL (asm_out_file, size, XSTR (addr, 0));
break;
#endif
case DW_EH_PE_pcrel:
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
#ifdef ASM_OUTPUT_DWARF_PCREL
ASM_OUTPUT_DWARF_PCREL (asm_out_file, size, XSTR (addr, 0));
#else
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index aa7fd7eb465..b2b4f6d82b2 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -4222,7 +4222,7 @@ static inline int
is_pseudo_reg (const_rtx rtl)
{
return ((REG_P (rtl) && REGNO (rtl) >= FIRST_PSEUDO_REGISTER)
- || (GET_CODE (rtl) == SUBREG
+ || (SUBREG_P (rtl)
&& REGNO (SUBREG_REG (rtl)) >= FIRST_PSEUDO_REGISTER));
}
@@ -6925,7 +6925,7 @@ attr_checksum (dw_attr_node *at, struct md5_ctx *ctx, int *mark)
case dw_val_class_addr:
r = AT_addr (at);
- gcc_assert (GET_CODE (r) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (r));
CHECKSUM_STRING (XSTR (r, 0));
break;
@@ -7225,7 +7225,7 @@ attr_checksum_ordered (enum dwarf_tag tag, dw_attr_node *at,
case dw_val_class_addr:
r = AT_addr (at);
- gcc_assert (GET_CODE (r) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (r));
CHECKSUM_ULEB128 (DW_FORM_string);
CHECKSUM_STRING (XSTR (r, 0));
break;
@@ -14503,7 +14503,7 @@ const_ok_for_output_1 (rtx rtl)
rather than DECL_THREAD_LOCAL_P is not just an optimization. */
if (flag_checking
&& (XVECLEN (rtl, 0) == 0
- || GET_CODE (XVECEXP (rtl, 0, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XVECEXP (rtl, 0, 0))
|| SYMBOL_REF_TLS_MODEL (XVECEXP (rtl, 0, 0)) == TLS_MODEL_NONE))
inform (current_function_decl
? DECL_SOURCE_LOCATION (current_function_decl)
@@ -14619,7 +14619,7 @@ const_ok_for_output_1 (rtx rtl)
static bool
const_ok_for_output (rtx rtl)
{
- if (GET_CODE (rtl) == SYMBOL_REF)
+ if (SYMBOL_REF_P (rtl))
return const_ok_for_output_1 (rtl);
if (GET_CODE (rtl) == CONST)
@@ -15129,7 +15129,7 @@ clz_loc_descriptor (rtx rtl, scalar_int_mode mode,
msb = immed_wide_int_const
(wi::set_bit_in_zero (GET_MODE_PRECISION (mode) - 1,
GET_MODE_PRECISION (mode)), mode);
- if (GET_CODE (msb) == CONST_INT && INTVAL (msb) < 0)
+ if (CONST_INT_P (msb) && INTVAL (msb) < 0)
tmp = new_loc_descr (HOST_BITS_PER_WIDE_INT == 32
? DW_OP_const4u : HOST_BITS_PER_WIDE_INT == 64
? DW_OP_const8u : DW_OP_constu, INTVAL (msb), 0);
@@ -15755,7 +15755,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode,
goto symref;
}
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_TLS_MODEL (rtl) != TLS_MODEL_NONE)
{
dw_loc_descr_ref temp;
@@ -16813,7 +16813,7 @@ loc_descriptor (rtx rtl, machine_mode mode,
if (mode == VOIDmode
|| CONST_SCALAR_INT_P (XEXP (rtl, 0))
|| CONST_DOUBLE_AS_FLOAT_P (XEXP (rtl, 0))
- || GET_CODE (XEXP (rtl, 0)) == CONST_VECTOR)
+ || CONST_VECTOR_P (XEXP (rtl, 0)))
{
loc_result = loc_descriptor (XEXP (rtl, 0), mode, initialized);
break;
@@ -17133,7 +17133,7 @@ dw_sra_loc_expr (tree decl, rtx loc)
|| GET_CODE (varloc) == SIGN_EXTEND
|| GET_CODE (varloc) == ZERO_EXTEND)
varloc = XEXP (varloc, 0);
- else if (GET_CODE (varloc) == SUBREG)
+ else if (SUBREG_P (varloc))
varloc = SUBREG_REG (varloc);
else
break;
@@ -17453,7 +17453,7 @@ cst_pool_loc_descr (tree loc)
gcc_assert (!rtl);
return 0;
}
- gcc_assert (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (rtl, 0)));
/* TODO: We might get more coverage if we was actually delaying expansion
of all expressions till end of compilation when constant pools are fully
@@ -18421,7 +18421,7 @@ loc_list_from_tree_1 (tree loc, int want_address,
val &= GET_MODE_MASK (DECL_MODE (loc));
ret = int_loc_descriptor (val);
}
- else if (GET_CODE (rtl) == CONST_STRING)
+ else if (CONST_STRING_P (rtl))
{
expansion_failed (loc, NULL_RTX, "CONST_STRING");
return 0;
@@ -19687,7 +19687,7 @@ add_const_value_attribute (dw_die_ref die, rtx rtl)
return false;
case MEM:
- if (GET_CODE (XEXP (rtl, 0)) == CONST_STRING
+ if (CONST_STRING_P (XEXP (rtl, 0))
&& MEM_READONLY_P (rtl)
&& GET_MODE (rtl) == BLKmode)
{
@@ -20063,7 +20063,7 @@ rtl_for_decl_location (tree decl)
{
rtl = make_decl_rtl_for_debug (decl);
if (!MEM_P (rtl)
- || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (rtl, 0))
|| SYMBOL_REF_DECL (XEXP (rtl, 0)) != decl)
rtl = NULL_RTX;
}
@@ -20165,7 +20165,7 @@ add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p)
the location. */
rtl = rtl_for_decl_location (decl);
- if (rtl && (CONSTANT_P (rtl) || GET_CODE (rtl) == CONST_STRING)
+ if (rtl && (CONSTANT_P (rtl) || CONST_STRING_P (rtl))
&& add_const_value_attribute (die, rtl))
return true;
@@ -20186,7 +20186,7 @@ add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p)
rtl = NOTE_VAR_LOCATION_LOC (node->loc);
if (GET_CODE (rtl) == EXPR_LIST)
rtl = XEXP (rtl, 0);
- if ((CONSTANT_P (rtl) || GET_CODE (rtl) == CONST_STRING)
+ if ((CONSTANT_P (rtl) || CONST_STRING_P (rtl))
&& add_const_value_attribute (die, rtl))
return true;
}
@@ -21798,7 +21798,7 @@ decl_start_label (tree decl)
gcc_assert (MEM_P (x));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
fnname = XSTR (x, 0);
return fnname;
@@ -23816,7 +23816,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die)
if (single_element_loc_list_p (loc)
&& loc->expr->dw_loc_opc == DW_OP_addr
&& loc->expr->dw_loc_next == NULL
- && GET_CODE (loc->expr->dw_loc_oprnd1.v.val_addr) == SYMBOL_REF)
+ && SYMBOL_REF_P (loc->expr->dw_loc_oprnd1.v.val_addr))
{
rtx x = loc->expr->dw_loc_oprnd1.v.val_addr;
loc->expr->dw_loc_oprnd1.v.val_addr
@@ -27334,7 +27334,7 @@ dwarf2out_var_location (rtx_insn *loc_note)
if (GET_CODE (x) == CALL)
x = XEXP (x, 0);
if (!MEM_P (x)
- || GET_CODE (XEXP (x, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (x, 0))
|| !SYMBOL_REF_DECL (XEXP (x, 0))
|| (TREE_CODE (SYMBOL_REF_DECL (XEXP (x, 0)))
!= FUNCTION_DECL))
@@ -27512,7 +27512,7 @@ create_label:
if (MEM_P (XEXP (x, 0)))
x = XEXP (x, 0);
/* First, look for a memory access to a symbol_ref. */
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& SYMBOL_REF_DECL (XEXP (x, 0))
&& TREE_CODE (SYMBOL_REF_DECL (XEXP (x, 0))) == FUNCTION_DECL)
ca_loc->symbol_ref = XEXP (x, 0);
@@ -29855,7 +29855,7 @@ resolve_one_addr (rtx *addr)
{
rtx rtl = *addr;
- if (GET_CODE (rtl) == CONST_STRING)
+ if (CONST_STRING_P (rtl))
{
size_t len = strlen (XSTR (rtl, 0)) + 1;
tree t = build_string (len, XSTR (rtl, 0));
@@ -29866,7 +29866,7 @@ resolve_one_addr (rtx *addr)
if (!rtl || !MEM_P (rtl))
return false;
rtl = XEXP (rtl, 0);
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_DECL (rtl)
&& !TREE_ASM_WRITTEN (SYMBOL_REF_DECL (rtl)))
return false;
@@ -29875,7 +29875,7 @@ resolve_one_addr (rtx *addr)
return true;
}
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_DECL (rtl))
{
if (TREE_CONSTANT_POOL_ADDRESS_P (rtl))
@@ -29915,7 +29915,7 @@ string_cst_pool_decl (tree t)
if (!rtl || !MEM_P (rtl))
return NULL_RTX;
rtl = XEXP (rtl, 0);
- if (GET_CODE (rtl) != SYMBOL_REF
+ if (!SYMBOL_REF_P (rtl)
|| SYMBOL_REF_DECL (rtl) == NULL_TREE)
return NULL_RTX;
@@ -29960,7 +29960,7 @@ optimize_one_addr_into_implicit_ptr (dw_loc_descr_ref loc)
offset = INTVAL (XEXP (XEXP (rtl, 0), 1));
rtl = XEXP (XEXP (rtl, 0), 0);
}
- if (GET_CODE (rtl) == CONST_STRING)
+ if (CONST_STRING_P (rtl))
{
size_t len = strlen (XSTR (rtl, 0)) + 1;
tree t = build_string (len, XSTR (rtl, 0));
@@ -29972,7 +29972,7 @@ optimize_one_addr_into_implicit_ptr (dw_loc_descr_ref loc)
if (!rtl)
return false;
}
- if (GET_CODE (rtl) == SYMBOL_REF && SYMBOL_REF_DECL (rtl))
+ if (SYMBOL_REF_P (rtl) && SYMBOL_REF_DECL (rtl))
{
decl = SYMBOL_REF_DECL (rtl);
if (VAR_P (decl) && !DECL_EXTERNAL (decl))
@@ -30596,7 +30596,7 @@ resolve_addr (dw_die_ref die)
if (l != NULL
&& l->dw_loc_next == NULL
&& l->dw_loc_opc == DW_OP_addr
- && GET_CODE (l->dw_loc_oprnd1.v.val_addr) == SYMBOL_REF
+ && SYMBOL_REF_P (l->dw_loc_oprnd1.v.val_addr)
&& SYMBOL_REF_DECL (l->dw_loc_oprnd1.v.val_addr)
&& a->dw_attr == DW_AT_location)
{
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index a667cdab94e..13cfd0b00ea 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -1294,7 +1294,7 @@ set_reg_attrs_from_value (rtx reg, rtx x)
while (GET_CODE (x) == SIGN_EXTEND
|| GET_CODE (x) == ZERO_EXTEND
|| GET_CODE (x) == TRUNCATE
- || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x)))
+ || (SUBREG_P (x) && subreg_lowpart_p (x)))
{
#if defined(POINTERS_EXTEND_UNSIGNED)
if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED)
@@ -1377,7 +1377,7 @@ set_reg_attrs_for_decl_rtl (tree t, rtx x)
if (!t)
return;
tree tdecl = t;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
gcc_assert (subreg_lowpart_p (x));
x = SUBREG_REG (x);
@@ -1595,8 +1595,8 @@ gen_lowpart_common (machine_mode mode, rtx x)
else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode))
return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
}
- else if (GET_CODE (x) == SUBREG || REG_P (x)
- || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
+ else if (SUBREG_P (x) || REG_P (x)
+ || GET_CODE (x) == CONCAT || CONST_VECTOR_P (x)
|| CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
|| CONST_POLY_INT_P (x))
return lowpart_subreg (mode, x, innermode);
@@ -1690,7 +1690,7 @@ subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes)
int
subreg_lowpart_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return 1;
else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
return 0;
@@ -3348,7 +3348,7 @@ make_safe_from (rtx x, rtx other)
if ((MEM_P (other)
&& ! CONSTANT_P (x)
&& !REG_P (x)
- && GET_CODE (x) != SUBREG)
+ && !SUBREG_P (x))
|| (REG_P (other)
&& (REGNO (other) < FIRST_PSEUDO_REGISTER
|| reg_mentioned_p (other, x))))
@@ -5416,7 +5416,7 @@ set_for_reg_notes (rtx insn)
reg = XEXP (reg, 0);
/* Check that we have a register. */
- if (!(REG_P (reg) || GET_CODE (reg) == SUBREG))
+ if (!(REG_P (reg) || SUBREG_P (reg)))
return NULL_RTX;
return pat;
@@ -6004,7 +6004,7 @@ gen_vec_duplicate (machine_mode mode, rtx x)
/* A subroutine of const_vec_series_p that handles the case in which:
- (GET_CODE (X) == CONST_VECTOR
+ (CONST_VECTOR_P (X)
&& CONST_VECTOR_NPATTERNS (X) == 1
&& !CONST_VECTOR_DUPLICATE_P (X))
diff --git a/gcc/explow.c b/gcc/explow.c
index 7eb854bca4a..441847d02ba 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -117,12 +117,12 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
/* If this is a reference to the constant pool, try replacing it with
a reference to a new constant. If the resulting address isn't
valid, don't return it because we have no way to validize it. */
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
{
rtx cst = get_pool_constant (XEXP (x, 0));
- if (GET_CODE (cst) == CONST_VECTOR
+ if (CONST_VECTOR_P (cst)
&& GET_MODE_INNER (GET_MODE (cst)) == mode)
{
cst = gen_lowpart (mode, cst);
@@ -197,7 +197,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
if (maybe_ne (c, 0))
x = gen_rtx_PLUS (mode, x, gen_int_mode (c, mode));
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
return x;
else if (all_constant)
return gen_rtx_CONST (mode, x);
@@ -558,7 +558,7 @@ use_anchored_address (rtx x)
}
/* Check whether BASE is suitable for anchors. */
- if (GET_CODE (base) != SYMBOL_REF
+ if (!SYMBOL_REF_P (base)
|| !SYMBOL_REF_HAS_BLOCK_INFO_P (base)
|| SYMBOL_REF_ANCHOR_P (base)
|| SYMBOL_REF_BLOCK (base) == NULL
@@ -680,17 +680,17 @@ force_reg (machine_mode mode, rtx x)
known alignment of that pointer. */
{
unsigned align = 0;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
align = BITS_PER_UNIT;
if (SYMBOL_REF_DECL (x) && DECL_P (SYMBOL_REF_DECL (x)))
align = DECL_ALIGN (SYMBOL_REF_DECL (x));
}
- else if (GET_CODE (x) == LABEL_REF)
+ else if (LABEL_REF_P (x))
align = BITS_PER_UNIT;
else if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))
{
rtx s = XEXP (XEXP (x, 0), 0);
@@ -2178,7 +2178,7 @@ anti_adjust_stack_and_probe (rtx size, bool adjust_back)
if (temp != const0_rtx)
{
/* Manual CSE if the difference is not known at compile-time. */
- if (GET_CODE (temp) != CONST_INT)
+ if (!CONST_INT_P (temp))
temp = gen_rtx_MINUS (Pmode, size, rounded_size_op);
anti_adjust_stack (temp);
emit_stack_probe (stack_pointer_rtx);
diff --git a/gcc/expmed.c b/gcc/expmed.c
index c582f3a1e62..25d19a05794 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -622,7 +622,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
/* If xop0 is a register, we need it in OP_MODE
to make it acceptable to the format of insv. */
- if (GET_CODE (xop0) == SUBREG)
+ if (SUBREG_P (xop0))
/* We can't just change the mode, because this might clobber op0,
and we will need the original value of op0 if insv fails. */
xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
@@ -635,7 +635,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
truncate the result to the original destination. Note that we can't
just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
X) 0)) is (reg:N X). */
- if (GET_CODE (xop0) == SUBREG
+ if (SUBREG_P (xop0)
&& REG_P (SUBREG_REG (xop0))
&& !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
op_mode))
@@ -735,7 +735,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
{
rtx op0 = str_rtx;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += subreg_memory_offset (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -875,7 +875,7 @@ store_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
rtx arg0 = op0;
unsigned HOST_WIDE_INT subreg_off;
- if (GET_CODE (arg0) == SUBREG)
+ if (SUBREG_P (arg0))
{
/* Else we've got some float mode source being extracted into
a different float mode destination -- this combination of
@@ -1330,7 +1330,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -1375,7 +1375,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
&& unit > BITS_PER_UNIT
&& maybe_gt (bitpos + bitsdone - thispos + unit, bitregion_end + 1)
&& !REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
{
unit = unit / 2;
continue;
@@ -1520,7 +1520,7 @@ extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
/* If op0 is a register, we need it in EXT_MODE to make it
acceptable to the format of ext(z)v. */
- if (GET_CODE (op0) == SUBREG && op0_mode.require () != ext_mode)
+ if (SUBREG_P (op0) && op0_mode.require () != ext_mode)
return NULL_RTX;
if (REG_P (op0) && op0_mode.require () != ext_mode)
op0 = gen_lowpart_SUBREG (ext_mode, op0);
@@ -1604,7 +1604,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
if (tmode == VOIDmode)
tmode = mode;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -1764,7 +1764,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
/* If we got a SUBREG, force it into a register since we
aren't going to be able to do another SUBREG on it. */
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (imode, op0);
}
else
@@ -2250,7 +2250,7 @@ extract_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -2477,7 +2477,7 @@ expand_shift_1 (enum tree_code code, machine_mode mode, rtx shifted,
op1 = gen_int_shift_amount (mode,
(unsigned HOST_WIDE_INT) INTVAL (op1)
% GET_MODE_BITSIZE (scalar_mode));
- else if (GET_CODE (op1) == SUBREG
+ else if (SUBREG_P (op1)
&& subreg_lowpart_p (op1)
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1)))
&& SCALAR_INT_MODE_P (GET_MODE (op1)))
@@ -3349,7 +3349,7 @@ expand_mult_const (machine_mode mode, rtx op0, HOST_WIDE_INT val,
we've set the inner register and must properly indicate that. */
tem = op0, nmode = mode;
accum_inner = accum;
- if (GET_CODE (accum) == SUBREG)
+ if (SUBREG_P (accum))
{
accum_inner = SUBREG_REG (accum);
nmode = GET_MODE (accum_inner);
diff --git a/gcc/expr.c b/gcc/expr.c
index 20e3f9ce337..e22b02b8868 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -227,7 +227,7 @@ convert_move (rtx to, rtx from, int unsignedp)
TO here. */
scalar_int_mode to_int_mode;
- if (GET_CODE (from) == SUBREG
+ if (SUBREG_P (from)
&& SUBREG_PROMOTED_VAR_P (from)
&& is_a <scalar_int_mode> (to_mode, &to_int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (from))
@@ -238,7 +238,7 @@ convert_move (rtx to, rtx from, int unsignedp)
from_mode = to_int_mode;
}
- gcc_assert (GET_CODE (to) != SUBREG || !SUBREG_PROMOTED_VAR_P (to));
+ gcc_assert (!SUBREG_P (to) || !SUBREG_PROMOTED_VAR_P (to));
if (to_mode == from_mode
|| (from_mode == VOIDmode && CONSTANT_P (from)))
@@ -437,7 +437,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
so that we always generate the same set of insns for
better cse'ing; if an intermediate assignment occurred,
we won't be doing the operation directly on the SUBREG. */
- if (optimize > 0 && GET_CODE (from) == SUBREG)
+ if (optimize > 0 && SUBREG_P (from))
from = force_reg (from_mode, from);
emit_unop_insn (code, to, from, equiv_code);
return;
@@ -519,7 +519,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
convert_move (to, gen_lowpart (word_mode, from), 0);
return;
@@ -538,7 +538,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
&& !targetm.hard_regno_mode_ok (REGNO (from), to_mode))
@@ -656,7 +656,7 @@ convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp)
/* If FROM is a SUBREG that indicates that we have already done at least
the required extension, strip it. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (x))
@@ -1659,7 +1659,7 @@ rtx
emit_block_move (rtx x, rtx y, rtx size, enum block_op_methods method)
{
unsigned HOST_WIDE_INT max, min = 0;
- if (GET_CODE (size) == CONST_INT)
+ if (CONST_INT_P (size))
min = max = UINTVAL (size);
else
max = GET_MODE_MASK (GET_MODE (size));
@@ -3052,7 +3052,7 @@ rtx
clear_storage (rtx object, rtx size, enum block_op_methods method)
{
unsigned HOST_WIDE_INT max, min = 0;
- if (GET_CODE (size) == CONST_INT)
+ if (CONST_INT_P (size))
min = max = UINTVAL (size);
else
max = GET_MODE_MASK (GET_MODE (size));
@@ -3255,7 +3255,7 @@ read_complex_part (rtx cplx, bool imag_p)
ibitsize = GET_MODE_BITSIZE (imode);
/* Special case reads from complex constants that got spilled to memory. */
- if (MEM_P (cplx) && GET_CODE (XEXP (cplx, 0)) == SYMBOL_REF)
+ if (MEM_P (cplx) && SYMBOL_REF_P (XEXP (cplx, 0)))
{
tree decl = SYMBOL_REF_DECL (XEXP (cplx, 0));
if (decl && TREE_CODE (decl) == COMPLEX_CST)
@@ -3587,7 +3587,7 @@ emit_move_ccmode (machine_mode mode, rtx x, rtx y)
static bool
undefined_operand_subword_p (const_rtx op, int i)
{
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
return false;
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_int64 offset = i * UNITS_PER_WORD + subreg_memory_offset (op);
@@ -3656,7 +3656,7 @@ emit_move_multi_word (machine_mode mode, rtx x, rtx y)
gcc_assert (xpart && ypart);
- need_clobber |= (GET_CODE (xpart) == SUBREG);
+ need_clobber |= (SUBREG_P (xpart));
last_insn = emit_move_insn (xpart, ypart);
}
@@ -4759,7 +4759,7 @@ optimize_bitfield_assignment_op (poly_uint64 pbitsize,
offset1 = (offset1 - bitpos) / BITS_PER_UNIT;
str_rtx = adjust_address (str_rtx, str_mode, offset1);
}
- else if (!REG_P (str_rtx) && GET_CODE (str_rtx) != SUBREG)
+ else if (!REG_P (str_rtx) && !SUBREG_P (str_rtx))
return false;
/* If the bit field covers the whole REG/MEM, store_field
@@ -5554,7 +5554,7 @@ store_expr (tree exp, rtx target, int call_param_p,
return NULL_RTX;
}
- else if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ else if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -6953,7 +6953,7 @@ store_field (rtx target, poly_int64 bitsize, poly_int64 bitpos,
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
|| REG_P (target)
- || GET_CODE (target) == SUBREG
+ || SUBREG_P (target)
/* If the field isn't aligned enough to store as an ordinary memref,
store it as a bit field. */
|| (mode != BLKmode
@@ -7448,8 +7448,8 @@ force_operand (rtx value, rtx target)
/* Check for a PIC address load. */
if ((code == PLUS || code == MINUS)
&& XEXP (value, 0) == pic_offset_table_rtx
- && (GET_CODE (XEXP (value, 1)) == SYMBOL_REF
- || GET_CODE (XEXP (value, 1)) == LABEL_REF
+ && (SYMBOL_REF_P (XEXP (value, 1))
+ || LABEL_REF_P (XEXP (value, 1))
|| GET_CODE (XEXP (value, 1)) == CONST))
{
if (!subtarget)
@@ -7605,7 +7605,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
/* If this is a subreg of a hard register, declare it unsafe, otherwise,
find the underlying pseudo. */
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
x = SUBREG_REG (x);
if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
@@ -7749,7 +7749,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
with it. */
if (exp_rtl)
{
- if (GET_CODE (exp_rtl) == SUBREG)
+ if (SUBREG_P (exp_rtl))
{
exp_rtl = SUBREG_REG (exp_rtl);
if (REG_P (exp_rtl)
@@ -8518,7 +8518,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
a promoted SUBREG, clear that indication since we now
have to do the proper extension. */
if (TYPE_UNSIGNED (TREE_TYPE (treeop0)) != unsignedp
- && GET_CODE (op0) == SUBREG)
+ && SUBREG_P (op0))
SUBREG_PROMOTED_VAR_P (op0) = 0;
return REDUCE_BIT_FIELD (op0);
@@ -10678,7 +10678,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
for (int i = 0; i < 2; i++)
{
rtx op = read_complex_part (op0, i != 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = force_reg (GET_MODE (op), op);
rtx temp = gen_lowpart_common (GET_MODE_INNER (mode1),
op);
@@ -10803,7 +10803,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
(which we know to be the width of a basic mode), then
storing into memory, and changing the mode to BLKmode. */
if (mode1 == VOIDmode
- || REG_P (op0) || GET_CODE (op0) == SUBREG
+ || REG_P (op0) || SUBREG_P (op0)
|| (mode1 != BLKmode && ! direct_load[(int) mode1]
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
@@ -11114,7 +11114,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
GET_MODE_PRECISION (GET_MODE (op0)))
&& !COMPLEX_MODE_P (GET_MODE (op0)))
{
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (GET_MODE (op0), op0);
temp = gen_lowpart_common (mode, op0);
if (temp)
@@ -12271,7 +12271,7 @@ do_tablejump (rtx index, machine_mode mode, rtx range, rtx table_label,
sign-extended subreg, and RANGE does not have the sign bit set, then
we have a value that is valid for both sign and zero extension. In
this case, we get better code if we sign extend. */
- if (GET_CODE (index) == SUBREG
+ if (SUBREG_P (index)
&& SUBREG_PROMOTED_VAR_P (index)
&& SUBREG_PROMOTED_SIGNED_P (index)
&& ((width = GET_MODE_PRECISION (as_a <scalar_int_mode> (mode)))
diff --git a/gcc/final.c b/gcc/final.c
index fefc4874b24..ec396230a3a 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -1611,7 +1611,7 @@ get_some_local_dynamic_name ()
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
return some_local_dynamic_name = XSTR (x, 0);
@@ -2798,17 +2798,17 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
&& insn != last_ignored_compare)
{
rtx src1, src2;
- if (GET_CODE (SET_SRC (set)) == SUBREG)
+ if (SUBREG_P (SET_SRC (set)))
SET_SRC (set) = alter_subreg (&SET_SRC (set), true);
src1 = SET_SRC (set);
src2 = NULL_RTX;
if (GET_CODE (SET_SRC (set)) == COMPARE)
{
- if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 0)))
XEXP (SET_SRC (set), 0)
= alter_subreg (&XEXP (SET_SRC (set), 0), true);
- if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 1)))
XEXP (SET_SRC (set), 1)
= alter_subreg (&XEXP (SET_SRC (set), 1), true);
if (XEXP (SET_SRC (set), 1)
@@ -3093,7 +3093,7 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
{
rtx x = call_from_call_insn (call_insn);
x = XEXP (x, 0);
- if (x && MEM_P (x) && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
+ if (x && MEM_P (x) && SYMBOL_REF_P (XEXP (x, 0)))
{
tree t;
x = XEXP (x, 0);
@@ -3318,7 +3318,7 @@ cleanup_subreg_operands (rtx_insn *insn)
already if we are inside a match_operator expression that
matches the else clause. Instead we test the underlying
expression directly. */
- if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.operand_loc[i]))
{
recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i], true);
changed = true;
@@ -3331,7 +3331,7 @@ cleanup_subreg_operands (rtx_insn *insn)
for (i = 0; i < recog_data.n_dups; i++)
{
- if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.dup_loc[i]))
{
*recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i], true);
changed = true;
@@ -4003,7 +4003,7 @@ output_asm_label (rtx x)
{
char buf[256];
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
x = label_ref_label (x);
if (LABEL_P (x)
|| (NOTE_P (x)
@@ -4024,7 +4024,7 @@ mark_symbol_refs_as_used (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
if (tree t = SYMBOL_REF_DECL (x))
assemble_external (t);
}
@@ -4042,7 +4042,7 @@ mark_symbol_refs_as_used (rtx x)
void
output_operand (rtx x, int code ATTRIBUTE_UNUSED)
{
- if (x && GET_CODE (x) == SUBREG)
+ if (x && SUBREG_P (x))
x = alter_subreg (&x, true);
/* X must not be a pseudo reg. */
@@ -4183,7 +4183,7 @@ output_addr_const (FILE *file, rtx x)
fprintf (file, "-");
if ((CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0)
|| GET_CODE (XEXP (x, 1)) == PC
- || GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ || SYMBOL_REF_P (XEXP (x, 1)))
output_addr_const (file, XEXP (x, 1));
else
{
diff --git a/gcc/function.c b/gcc/function.c
index 2a0061cad35..bd9672e3e44 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -3210,7 +3210,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
/* If op1 is a hard register that is likely spilled, first
force it into a pseudo, otherwise combiner might extend
its lifetime too much. */
- if (GET_CODE (t) == SUBREG)
+ if (SUBREG_P (t))
t = SUBREG_REG (t);
if (REG_P (t)
&& HARD_REGISTER_P (t)
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 137864cb61b..0b16dd2a9af 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -738,7 +738,7 @@ propagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx,
flags = 0;
if (REG_P (new_rtx)
|| CONSTANT_P (new_rtx)
- || (GET_CODE (new_rtx) == SUBREG
+ || (SUBREG_P (new_rtx)
&& REG_P (SUBREG_REG (new_rtx))
&& !paradoxical_subreg_p (new_rtx)))
flags |= PR_CAN_APPEAR;
@@ -1146,7 +1146,7 @@ free_load_extend (rtx src, rtx_insn *insn)
rtx patt = PATTERN (DF_REF_INSN (def));
if (GET_CODE (patt) == SET
- && GET_CODE (SET_SRC (patt)) == MEM
+ && MEM_P (SET_SRC (patt))
&& rtx_equal_p (SET_DEST (patt), reg))
return true;
}
@@ -1165,7 +1165,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
/* Only consider subregs... */
machine_mode use_mode = GET_MODE (use_reg);
- if (GET_CODE (use_reg) != SUBREG
+ if (!SUBREG_P (use_reg)
|| !REG_P (SET_DEST (def_set)))
return false;
@@ -1178,7 +1178,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
these SUBREGs just say how to treat the register. */
use_insn = DF_REF_INSN (use);
src = SET_SRC (def_set);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& REG_P (SUBREG_REG (src))
&& REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER
&& GET_MODE (SUBREG_REG (src)) == use_mode
@@ -1327,17 +1327,17 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
/* If def and use are subreg, check if they match. */
reg = DF_REF_REG (use);
- if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ if (SUBREG_P (reg) && SUBREG_P (SET_DEST (def_set)))
{
if (maybe_ne (SUBREG_BYTE (SET_DEST (def_set)), SUBREG_BYTE (reg)))
return false;
}
/* Check if the def had a subreg, but the use has the whole reg. */
- else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ else if (REG_P (reg) && SUBREG_P (SET_DEST (def_set)))
return false;
/* Check if the use has a subreg, but the def had the whole reg. Unlike the
previous case, the optimization is possible and often useful indeed. */
- else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set)))
+ else if (SUBREG_P (reg) && REG_P (SET_DEST (def_set)))
reg = SUBREG_REG (reg);
/* Make sure that we can treat REG as having the same mode as the
@@ -1406,7 +1406,7 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
set_reg_equal = (note == NULL_RTX
&& REG_P (SET_DEST (use_set))
&& !REG_P (src)
- && !(GET_CODE (src) == SUBREG
+ && !(SUBREG_P (src)
&& REG_P (SUBREG_REG (src)))
&& !reg_mentioned_p (SET_DEST (use_set),
SET_SRC (use_set))
diff --git a/gcc/gcse-common.c b/gcc/gcse-common.c
index e6e4b642b58..0e40adb44af 100644
--- a/gcc/gcse-common.c
+++ b/gcc/gcse-common.c
@@ -40,7 +40,7 @@ canon_list_insert (rtx dest, const_rtx x ATTRIBUTE_UNUSED, void *data)
int bb;
modify_pair pair;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/gcse.c b/gcc/gcse.c
index ff2771bdc04..357f8a2ddb2 100644
--- a/gcc/gcse.c
+++ b/gcc/gcse.c
@@ -984,7 +984,7 @@ mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
struct mem_conflict_info *mci = (struct mem_conflict_info *) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -1478,7 +1478,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
@@ -1735,7 +1735,7 @@ prune_expressions (bool pre_p)
of the tables. */
if (MEM_P (x))
{
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
continue;
@@ -3381,7 +3381,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
const_rtx set = single_set_gcse (insn);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c
index cdf0b5c12dc..912d6b4f594 100644
--- a/gcc/genattrtab.c
+++ b/gcc/genattrtab.c
@@ -739,7 +739,7 @@ check_attr_test (file_location loc, rtx exp, attr_desc *attr)
else
{
for (av = attr2->first_value; av; av = av->next)
- if (GET_CODE (av->value) == CONST_STRING
+ if (CONST_STRING_P (av->value)
&& ! strcmp (XSTR (exp, 1), XSTR (av->value, 0)))
break;
@@ -813,8 +813,8 @@ check_attr_test (file_location loc, rtx exp, attr_desc *attr)
case LE: case LT: case GT: case GE:
case LEU: case LTU: case GTU: case GEU:
case NE: case EQ:
- if (GET_CODE (XEXP (exp, 0)) == SYMBOL_REF
- && GET_CODE (XEXP (exp, 1)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (exp, 0))
+ && SYMBOL_REF_P (XEXP (exp, 1)))
exp = attr_rtx (GET_CODE (exp),
attr_rtx (SYMBOL_REF, XSTR (XEXP (exp, 0), 0)),
attr_rtx (SYMBOL_REF, XSTR (XEXP (exp, 1), 0)));
@@ -892,7 +892,7 @@ check_attr_value (file_location loc, rtx exp, class attr_desc *attr)
}
for (av = attr->first_value; av; av = av->next)
- if (GET_CODE (av->value) == CONST_STRING
+ if (CONST_STRING_P (av->value)
&& ! strcmp (XSTR (av->value, 0), XSTR (exp, 0)))
break;
@@ -3715,7 +3715,7 @@ write_test_expr (FILE *outf, rtx exp, unsigned int attrs_cached, int flags,
/* The address of the branch target. */
case MATCH_DUP:
fprintf (outf,
- "INSN_ADDRESSES_SET_P () ? INSN_ADDRESSES (INSN_UID (GET_CODE (operands[%d]) == LABEL_REF ? XEXP (operands[%d], 0) : operands[%d])) : 0",
+ "INSN_ADDRESSES_SET_P () ? INSN_ADDRESSES (INSN_UID (LABEL_REF_P (operands[%d]) ? XEXP (operands[%d], 0) : operands[%d])) : 0",
XINT (exp, 0), XINT (exp, 0), XINT (exp, 0));
break;
@@ -5000,7 +5000,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (dfa_file,
"extern int internal_dfa_insn_code_%s (rtx_insn *);\n",
XSTR (val->value, 0));
@@ -5012,7 +5012,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (latency_file,
"extern int insn_default_latency_%s (rtx_insn *);\n",
XSTR (val->value, 0));
@@ -5024,7 +5024,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (attr_file,
"extern int internal_dfa_insn_code_%s (rtx_insn *);\n"
"extern int insn_default_latency_%s (rtx_insn *);\n",
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 556c4bdd869..1d9baea9f44 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -103,7 +103,7 @@ process_define_predicate (md_rtx_info *info)
(define_predicate "basereg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
})
@@ -112,7 +112,7 @@ process_define_predicate (md_rtx_info *info)
static inline int basereg_operand_1(rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
}
@@ -1247,14 +1247,14 @@ write_tm_constrs_h (void)
error ("you can't use lval or hval");
#else
if (needs_hval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode == VOIDmode)"
" hval = CONST_DOUBLE_HIGH (op);");
if (needs_lval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode == VOIDmode)"
" lval = CONST_DOUBLE_LOW (op);");
#endif
if (needs_rval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode != VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode != VOIDmode)"
" rval = CONST_DOUBLE_REAL_VALUE (op);");
write_predicate_stmts (c->exp);
diff --git a/gcc/genrecog.c b/gcc/genrecog.c
index f20089eeee8..82b00fde9ed 100644
--- a/gcc/genrecog.c
+++ b/gcc/genrecog.c
@@ -1687,7 +1687,7 @@ simplify_tests (state *s)
for (decision *d = s->first; d; d = d->next)
{
uint64_t label;
- /* Convert checks for GET_CODE (x) == CONST_INT and XWINT (x, 0) == N
+ /* Convert checks for CONST_INT_P (x) and XWINT (x, 0) == N
into checks for const_int_rtx[N'], if N is suitably small. */
if (d->test.kind == rtx_test::CODE
&& d->if_statement_p (&label)
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index 1aab7119901..8bdd0ae7502 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -683,7 +683,7 @@ is_predicable (class queue_elem *elem)
|| strcmp (XSTR (SET_DEST (sub), 0), "predicable") != 0)
break;
sub = SET_SRC (sub);
- if (GET_CODE (sub) == CONST_STRING)
+ if (CONST_STRING_P (sub))
{
value = XSTR (sub, 0);
goto found;
@@ -775,7 +775,7 @@ has_subst_attribute (class queue_elem *elem, class queue_elem *subst_elem)
|| strcmp (XSTR (SET_DEST (cur_attr), 0), subst_name) != 0)
break;
cur_attr = SET_SRC (cur_attr);
- if (GET_CODE (cur_attr) == CONST_STRING)
+ if (CONST_STRING_P (cur_attr))
{
value = XSTR (cur_attr, 0);
goto found;
@@ -1415,7 +1415,7 @@ alter_attrs_for_insn (rtx insn)
if (strcmp (XSTR (SET_DEST (sub), 0), "predicable") == 0)
{
sub = SET_SRC (sub);
- if (GET_CODE (sub) == CONST_STRING)
+ if (CONST_STRING_P (sub))
{
predicable_idx = i;
XSTR (sub, 0) = "ce_enabled";
@@ -3156,7 +3156,7 @@ needs_barrier_p (rtx x)
{
return (GET_CODE (x) == SET
&& GET_CODE (SET_DEST (x)) == PC
- && GET_CODE (SET_SRC (x)) == LABEL_REF);
+ && LABEL_REF_P (SET_SRC (x)));
}
#define NS "NULL"
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index e0c9522057a..a62b1265599 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -310,7 +310,7 @@ rtx_interchangeable_p (const_rtx a, const_rtx b)
if (!rtx_equal_p (a, b))
return false;
- if (GET_CODE (a) != MEM)
+ if (!MEM_P (a))
return true;
/* A dead type-unsafe memory reference is legal, but a live type-unsafe memory
@@ -438,7 +438,7 @@ cond_exec_get_condition (rtx_insn *jump)
/* If this branches to JUMP_LABEL when the condition is false,
reverse the condition. */
- if (GET_CODE (XEXP (test_if, 2)) == LABEL_REF
+ if (LABEL_REF_P (XEXP (test_if, 2))
&& label_ref_label (XEXP (test_if, 2)) == JUMP_LABEL (jump))
{
enum rtx_code rev = reversed_comparison_code (cond, jump);
@@ -832,7 +832,7 @@ noce_emit_store_flag (struct noce_if_info *if_info, rtx x, int reversep,
{
rtx set = pc_set (if_info->jump);
cond = XEXP (SET_SRC (set), 0);
- if (GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ if (LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (if_info->jump))
reversep = !reversep;
if (if_info->then_else_reversed)
@@ -905,7 +905,7 @@ noce_emit_move_insn (rtx x, rtx y)
start_sequence ();
/* Check that the SET_SRC is reasonable before calling emit_move_insn,
otherwise construct a suitable SET pattern ourselves. */
- insn = (OBJECT_P (y) || CONSTANT_P (y) || GET_CODE (y) == SUBREG)
+ insn = (OBJECT_P (y) || CONSTANT_P (y) || SUBREG_P (y))
? emit_move_insn (x, y)
: emit_insn (gen_rtx_SET (x, y));
seq = get_insns ();
@@ -1720,7 +1720,7 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code,
if (reload_completed)
return NULL_RTX;
- if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG)
+ if (SUBREG_P (vtrue) && SUBREG_P (vfalse))
{
rtx reg_vtrue = SUBREG_REG (vtrue);
rtx reg_vfalse = SUBREG_REG (vfalse);
@@ -2316,7 +2316,7 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
set = pc_set (if_info->jump);
cond = XEXP (SET_SRC (set), 0);
reverse
- = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ = LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (if_info->jump);
if (if_info->then_else_reversed)
reverse = !reverse;
@@ -2630,7 +2630,7 @@ noce_try_abs (struct noce_if_info *if_info)
return FALSE;
}
if (MEM_P (c)
- && GET_CODE (XEXP (c, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (c, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (c, 0)))
c = get_pool_constant (XEXP (c, 0));
@@ -2928,7 +2928,7 @@ noce_get_condition (rtx_insn *jump, rtx_insn **earliest, bool then_else_reversed
/* If this branches to JUMP_LABEL when the condition is false,
reverse the condition. */
- reverse = (GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ reverse = (LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump));
/* We may have to reverse because the caller's if block is not canonical,
@@ -3335,7 +3335,7 @@ bb_ok_for_noce_convert_multiple_sets (basic_block test_bb)
return false;
if (!(REG_P (src)
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& subreg_lowpart_p (src))))
return false;
@@ -3710,7 +3710,7 @@ check_cond_move_block (basic_block bb,
modified earlier in the block. */
if ((REG_P (src)
&& vals->get (src))
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& vals->get (SUBREG_REG (src))))
return FALSE;
diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
index 10673769958..58fcc5de017 100644
--- a/gcc/internal-fn.c
+++ b/gcc/internal-fn.c
@@ -658,7 +658,7 @@ expand_arith_overflow_result_store (tree lhs, rtx target,
static void
expand_ubsan_result_store (rtx target, rtx res)
{
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -2898,7 +2898,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
guarantee that the instruction will leave the upper bits of the
register in the state required by SUBREG_PROMOTED_SIGN. */
rtx dest = lhs_rtx;
- if (dest && GET_CODE (dest) == SUBREG && SUBREG_PROMOTED_VAR_P (dest))
+ if (dest && SUBREG_P (dest) && SUBREG_PROMOTED_VAR_P (dest))
dest = NULL_RTX;
create_output_operand (&ops[0], dest, insn_data[icode].operand[0].mode);
@@ -2926,7 +2926,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
If the return value has a nonintegral type, its mode must match
the instruction result. */
- if (GET_CODE (lhs_rtx) == SUBREG && SUBREG_PROMOTED_VAR_P (lhs_rtx))
+ if (SUBREG_P (lhs_rtx) && SUBREG_PROMOTED_VAR_P (lhs_rtx))
{
/* If this is a scalar in a register that is stored in a wider
mode than the declared mode, compute the result into its
diff --git a/gcc/ira-build.c b/gcc/ira-build.c
index c7457fa4431..200ed52ad55 100644
--- a/gcc/ira-build.c
+++ b/gcc/ira-build.c
@@ -1850,7 +1850,7 @@ create_insn_allocnos (rtx x, rtx outer, bool output_p)
if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
{
a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
- if (outer != NULL && GET_CODE (outer) == SUBREG)
+ if (outer != NULL && SUBREG_P (outer))
{
machine_mode wmode = GET_MODE (outer);
if (partial_subreg_p (ALLOCNO_WMODE (a), wmode))
diff --git a/gcc/ira-conflicts.c b/gcc/ira-conflicts.c
index 813a6d4103c..fc471bb8770 100644
--- a/gcc/ira-conflicts.c
+++ b/gcc/ira-conflicts.c
@@ -207,7 +207,7 @@ allocnos_conflict_for_copy_p (ira_allocno_t a1, ira_allocno_t a2)
/* Check that X is REG or SUBREG of REG. */
#define REG_SUBREG_P(x) \
- (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))))
+ (REG_P (x) || (SUBREG_P (x) && REG_P (SUBREG_REG (x))))
/* Return X if X is a REG, otherwise it should be SUBREG of REG and
the function returns the reg in this case. *OFFSET will be set to
@@ -220,7 +220,7 @@ go_through_subreg (rtx x, int *offset)
*offset = 0;
if (REG_P (x))
return x;
- ira_assert (GET_CODE (x) == SUBREG);
+ ira_assert (SUBREG_P (x));
reg = SUBREG_REG (x);
ira_assert (REG_P (reg));
if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index c7feaba3718..1838a0ea538 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1297,11 +1297,11 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& known_eq (GET_MODE_SIZE (GET_MODE (dest)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
dest = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& known_eq (GET_MODE_SIZE (GET_MODE (src)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
src = SUBREG_REG (src);
@@ -1404,7 +1404,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
{
memcpy (op_costs[i], init_cost, struct_costs_size);
- if (GET_CODE (recog_data.operand[i]) == SUBREG)
+ if (SUBREG_P (recog_data.operand[i]))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
if (MEM_P (recog_data.operand[i]))
@@ -1475,7 +1475,7 @@ scan_one_insn (rtx_insn *insn)
if (pat_code == USE || pat_code == CLOBBER)
{
rtx x = XEXP (PATTERN (insn), 0);
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
&& have_regs_of_mode[GET_MODE (x)])
ira_init_register_move_cost_if_necessary (GET_MODE (x));
@@ -1542,7 +1542,7 @@ scan_one_insn (rtx_insn *insn)
{
rtx op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/ira-emit.c b/gcc/ira-emit.c
index 255af307b3c..846dd5d501b 100644
--- a/gcc/ira-emit.c
+++ b/gcc/ira-emit.c
@@ -941,7 +941,7 @@ emit_move_list (move_t list, int freq)
if ((set = single_set (insn)) != NULL_RTX)
{
dest = SET_DEST (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
ira_assert (REG_P (dest));
regno = REGNO (dest);
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index 2029027125a..f1fae3c1ec7 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -416,7 +416,7 @@ mark_ref_live (df_ref ref)
rtx reg = DF_REF_REG (ref);
rtx orig_reg = reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -545,11 +545,11 @@ mark_ref_dead (df_ref def)
if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
- && (GET_CODE (orig_reg) != SUBREG
+ && (!SUBREG_P (orig_reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER
|| !read_modify_subreg_p (orig_reg)))
return;
@@ -573,7 +573,7 @@ make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
rtx orig_reg = reg;
ira_allocno_t a;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
@@ -646,7 +646,7 @@ check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
if (def_cl == NO_REGS)
return;
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
@@ -766,7 +766,7 @@ mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
{
rtx dreg = DF_REF_REG (def);
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
continue;
@@ -875,7 +875,7 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
{
op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == SCRATCH
@@ -934,7 +934,7 @@ process_single_reg_class_operands (bool in_p, int freq)
operand_a = NULL;
- if (GET_CODE (operand) == SUBREG)
+ if (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand)
@@ -1337,7 +1337,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
{
rtx ureg = DF_REF_REG (use);
- if (GET_CODE (ureg) == SUBREG)
+ if (SUBREG_P (ureg))
ureg = SUBREG_REG (ureg);
if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
continue;
diff --git a/gcc/ira.c b/gcc/ira.c
index c58daba6e79..9f7a72e3fe5 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -2206,7 +2206,7 @@ ira_bad_reload_regno_1 (int regno, rtx x)
enum reg_class pref;
/* We only deal with pseudo regs. */
- if (! x || GET_CODE (x) != REG)
+ if (! x || !REG_P (x))
return false;
x_regno = REGNO (x);
@@ -3323,7 +3323,7 @@ set_paradoxical_subreg (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
{
const_rtx subreg = *iter;
- if (GET_CODE (subreg) == SUBREG)
+ if (SUBREG_P (subreg))
{
const_rtx reg = SUBREG_REG (subreg);
if (REG_P (reg) && paradoxical_subreg_p (subreg))
@@ -3933,12 +3933,12 @@ indirect_jump_optimize (void)
rtx_insn *def_insn = DF_REF_INSN (def);
rtx lab = NULL_RTX;
rtx set = single_set (def_insn);
- if (set && GET_CODE (SET_SRC (set)) == LABEL_REF)
+ if (set && LABEL_REF_P (SET_SRC (set)))
lab = SET_SRC (set);
else
{
rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX);
- if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF)
+ if (eqnote && LABEL_REF_P (XEXP (eqnote, 0)))
lab = XEXP (eqnote, 0);
}
if (lab && validate_replace_rtx (SET_SRC (x), lab, insn))
@@ -4225,7 +4225,7 @@ build_insn_chain (void)
conservative and treat the definition as a partial
definition of the full register rather than a full
definition of a specific part of the register. */
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)
&& get_subreg_tracking_sizes (reg, &outer_size,
&inner_size, &start))
@@ -4321,7 +4321,7 @@ build_insn_chain (void)
|| pseudo_for_reload_consideration_p (regno))
{
HOST_WIDE_INT outer_size, inner_size, start;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (use,
DF_REF_SIGN_EXTRACT
| DF_REF_ZERO_EXTRACT)
diff --git a/gcc/jump.c b/gcc/jump.c
index ce5cee523c3..2ec071a6235 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -263,7 +263,7 @@ maybe_propagate_label_ref (rtx_insn *jump_insn, rtx_insn *prev_nonjump_insn)
if (label_set != NULL
/* The source must be the direct LABEL_REF, not a
PLUS, UNSPEC, IF_THEN_ELSE etc. */
- && GET_CODE (SET_SRC (label_set)) == LABEL_REF
+ && LABEL_REF_P (SET_SRC (label_set))
&& (rtx_equal_p (label_dest, pc_src)
|| (GET_CODE (pc_src) == IF_THEN_ELSE
&& (rtx_equal_p (label_dest, XEXP (pc_src, 1))
@@ -773,7 +773,7 @@ simplejump_p (const rtx_insn *insn)
return (JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (SET_DEST (PATTERN (insn))) == PC
- && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF);
+ && LABEL_REF_P (SET_SRC (PATTERN (insn))));
}
/* Return nonzero if INSN is a (possibly) conditional jump
@@ -792,15 +792,15 @@ condjump_p (const rtx_insn *insn)
return 0;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return 1;
else
return (GET_CODE (x) == IF_THEN_ELSE
&& ((GET_CODE (XEXP (x, 2)) == PC
- && (GET_CODE (XEXP (x, 1)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (x, 1))
|| ANY_RETURN_P (XEXP (x, 1))))
|| (GET_CODE (XEXP (x, 1)) == PC
- && (GET_CODE (XEXP (x, 2)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (x, 2))
|| ANY_RETURN_P (XEXP (x, 2))))));
}
@@ -824,16 +824,16 @@ condjump_in_parallel_p (const rtx_insn *insn)
return 0;
if (GET_CODE (SET_DEST (x)) != PC)
return 0;
- if (GET_CODE (SET_SRC (x)) == LABEL_REF)
+ if (LABEL_REF_P (SET_SRC (x)))
return 1;
if (GET_CODE (SET_SRC (x)) != IF_THEN_ELSE)
return 0;
if (XEXP (SET_SRC (x), 2) == pc_rtx
- && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (SET_SRC (x), 1))
|| ANY_RETURN_P (XEXP (SET_SRC (x), 1))))
return 1;
if (XEXP (SET_SRC (x), 1) == pc_rtx
- && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (SET_SRC (x), 2))
|| ANY_RETURN_P (XEXP (SET_SRC (x), 2))))
return 1;
return 0;
@@ -868,7 +868,7 @@ any_uncondjump_p (const rtx_insn *insn)
const_rtx x = pc_set (insn);
if (!x)
return 0;
- if (GET_CODE (SET_SRC (x)) != LABEL_REF)
+ if (!LABEL_REF_P (SET_SRC (x)))
return 0;
if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
return 0;
@@ -911,13 +911,13 @@ condjump_label (const rtx_insn *insn)
if (!x)
return NULL_RTX;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return x;
if (GET_CODE (x) != IF_THEN_ELSE)
return NULL_RTX;
- if (XEXP (x, 2) == pc_rtx && GET_CODE (XEXP (x, 1)) == LABEL_REF)
+ if (XEXP (x, 2) == pc_rtx && LABEL_REF_P (XEXP (x, 1)))
return XEXP (x, 1);
- if (XEXP (x, 1) == pc_rtx && GET_CODE (XEXP (x, 2)) == LABEL_REF)
+ if (XEXP (x, 1) == pc_rtx && LABEL_REF_P (XEXP (x, 2)))
return XEXP (x, 2);
return NULL_RTX;
}
@@ -1438,7 +1438,7 @@ redirect_exp_1 (rtx *loc, rtx olabel, rtx nlabel, rtx_insn *insn)
|| x == olabel)
{
x = redirect_target (nlabel);
- if (GET_CODE (x) == LABEL_REF && loc == &PATTERN (insn))
+ if (LABEL_REF_P (x) && loc == &PATTERN (insn))
x = gen_rtx_SET (pc_rtx, x);
validate_change (insn, loc, x, 1);
return;
@@ -1446,7 +1446,7 @@ redirect_exp_1 (rtx *loc, rtx olabel, rtx nlabel, rtx_insn *insn)
if (code == SET && SET_DEST (x) == pc_rtx
&& ANY_RETURN_P (nlabel)
- && GET_CODE (SET_SRC (x)) == LABEL_REF
+ && LABEL_REF_P (SET_SRC (x))
&& label_ref_label (SET_SRC (x)) == olabel)
{
validate_change (insn, loc, nlabel, 1);
@@ -1690,7 +1690,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int reg_x = -1, reg_y = -1;
@@ -1728,7 +1728,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
reg_x = reg_renumber[reg_x];
}
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
reg_y = REGNO (SUBREG_REG (y));
byte_y = SUBREG_BYTE (y);
@@ -1900,7 +1900,7 @@ true_regnum (const_rtx x)
return reg_renumber[REGNO (x)];
return REGNO (x);
}
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
int base = true_regnum (SUBREG_REG (x));
if (base >= 0
@@ -1924,7 +1924,7 @@ true_regnum (const_rtx x)
unsigned int
reg_or_subregno (const_rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
return REGNO (reg);
diff --git a/gcc/loop-doloop.c b/gcc/loop-doloop.c
index 0efe7b449ff..e30d17be3ef 100644
--- a/gcc/loop-doloop.c
+++ b/gcc/loop-doloop.c
@@ -190,7 +190,7 @@ doloop_condition_get (rtx_insn *doloop_pat)
if (GET_CODE (cmp) != SET
|| SET_DEST (cmp) != pc_rtx
|| GET_CODE (SET_SRC (cmp)) != IF_THEN_ELSE
- || GET_CODE (XEXP (SET_SRC (cmp), 1)) != LABEL_REF
+ || !LABEL_REF_P (XEXP (SET_SRC (cmp), 1))
|| XEXP (SET_SRC (cmp), 2) != pc_rtx)
return 0;
diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
index 644ecfc6fbb..a69eec6cda5 100644
--- a/gcc/loop-invariant.c
+++ b/gcc/loop-invariant.c
@@ -1269,7 +1269,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
/* Considered invariant insns have only one set. */
gcc_assert (set != NULL_RTX);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
@@ -1793,7 +1793,7 @@ move_invariant_reg (class loop *loop, unsigned invno)
need to create a temporary register. */
set = single_set (inv->insn);
reg = dest = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
regno = REGNO (reg);
@@ -2060,7 +2060,7 @@ static void
mark_reg_store (rtx reg, const_rtx setter ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c
index 2274cc3075b..5c39106170b 100644
--- a/gcc/loop-iv.c
+++ b/gcc/loop-iv.c
@@ -219,7 +219,7 @@ simple_reg_p (rtx reg)
{
unsigned r;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
if (!subreg_lowpart_p (reg))
return false;
@@ -338,7 +338,7 @@ iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def)
*def = NULL;
if (!simple_reg_p (reg))
return GRD_INVALID;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -680,7 +680,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
(set x':DI (plus:DI y:DI 1))
(set x:SI (subreg:SI (x':DI)). */
- if (GET_CODE (op0) != SUBREG)
+ if (!SUBREG_P (op0))
return false;
if (GET_MODE (SUBREG_REG (op0)) != outer_mode)
return false;
@@ -705,7 +705,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
return false;
}
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
if (!subreg_lowpart_p (next))
return false;
@@ -737,7 +737,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
outer_step))
return false;
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
scalar_int_mode amode;
if (!is_a <scalar_int_mode> (GET_MODE (next), &amode)
@@ -1119,7 +1119,7 @@ iv_analyze_op (rtx_insn *insn, scalar_int_mode mode, rtx op, class rtx_iv *iv)
if (function_invariant_p (op))
res = GRD_INVARIANT;
- else if (GET_CODE (op) == SUBREG)
+ else if (SUBREG_P (op))
{
scalar_int_mode inner_mode;
if (!subreg_lowpart_p (op)
@@ -1175,7 +1175,7 @@ iv_analyze (rtx_insn *insn, scalar_int_mode mode, rtx val, class rtx_iv *iv)
following insns. */
if (simple_reg_p (val))
{
- if (GET_CODE (val) == SUBREG)
+ if (SUBREG_P (val))
reg = SUBREG_REG (val);
else
reg = val;
@@ -1321,7 +1321,7 @@ altered_reg_used (const_rtx x, bitmap alt)
static void
mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt)
{
- if (GET_CODE (expr) == SUBREG)
+ if (SUBREG_P (expr))
expr = SUBREG_REG (expr);
if (!REG_P (expr))
return;
@@ -1502,7 +1502,7 @@ implies_p (rtx a, rtx b)
op1 = XEXP (a, 1);
if (REG_P (op0)
- || (GET_CODE (op0) == SUBREG
+ || (SUBREG_P (op0)
&& REG_P (SUBREG_REG (op0))))
{
rtx r = simplify_replace_rtx (b, op0, op1);
@@ -1511,7 +1511,7 @@ implies_p (rtx a, rtx b)
}
if (REG_P (op1)
- || (GET_CODE (op1) == SUBREG
+ || (SUBREG_P (op1)
&& REG_P (SUBREG_REG (op1))))
{
rtx r = simplify_replace_rtx (b, op1, op0);
diff --git a/gcc/loop-unroll.c b/gcc/loop-unroll.c
index 63fccd23fae..b75d13492c5 100644
--- a/gcc/loop-unroll.c
+++ b/gcc/loop-unroll.c
@@ -1419,7 +1419,7 @@ analyze_insn_to_expand_var (class loop *loop, rtx_insn *insn)
return NULL;
if (!REG_P (dest)
- && !(GET_CODE (dest) == SUBREG
+ && !(SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest))))
return NULL;
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index e1418e5ec51..54a8f78cd7b 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -300,14 +300,14 @@ init_lower_subreg (void)
static bool
simple_move_operand (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!OBJECT_P (x))
return false;
- if (GET_CODE (x) == LABEL_REF
- || GET_CODE (x) == SYMBOL_REF
+ if (LABEL_REF_P (x)
+ || SYMBOL_REF_P (x)
|| GET_CODE (x) == HIGH
|| GET_CODE (x) == CONST)
return false;
@@ -492,7 +492,7 @@ find_decomposable_subregs (rtx *loc, enum classify_move_insn *pcmi)
FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
{
rtx x = *iter;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx inner = SUBREG_REG (x);
unsigned int regno, outer_size, inner_size, outer_words, inner_words;
@@ -698,7 +698,7 @@ simplify_gen_subreg_concatn (machine_mode outermode, rtx op,
If OP is a SUBREG of a CONCATN, then it must be a simple mode
change with the same size and offset 0, or it must extract a
part. We shouldn't see anything else here. */
- if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN)
+ if (SUBREG_P (op) && GET_CODE (SUBREG_REG (op)) == CONCATN)
{
rtx op2;
@@ -757,7 +757,7 @@ resolve_reg_p (rtx x)
static bool
resolve_subreg_p (rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
return resolve_reg_p (SUBREG_REG (x));
}
@@ -933,7 +933,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
}
}
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& resolve_reg_p (SUBREG_REG (src))
&& (maybe_ne (SUBREG_BYTE (src), 0)
|| maybe_ne (orig_size, GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))))
@@ -947,7 +947,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
/* Similarly if we are copying to a SUBREG of a decomposed reg where
the SUBREG is larger than word size. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& resolve_reg_p (SUBREG_REG (dest))
&& (maybe_ne (SUBREG_BYTE (dest), 0)
|| maybe_ne (orig_size,
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index f2584075937..65ccbf3798f 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -162,7 +162,7 @@ static int new_insn_uid_start;
static inline rtx *
strip_subreg (rtx *loc)
{
- return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
+ return loc && SUBREG_P (*loc) ? &SUBREG_REG (*loc) : loc;
}
/* Return hard regno of REGNO or if it is was not assigned to a hard
@@ -269,7 +269,7 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
&& curr_insn_set != NULL
&& ((OBJECT_P (SET_SRC (curr_insn_set))
&& ! CONSTANT_P (SET_SRC (curr_insn_set)))
- || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ || (SUBREG_P (SET_SRC (curr_insn_set))
&& OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
&& ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
/* When we don't know what class will be used finally for reload
@@ -601,7 +601,7 @@ get_reload_reg (enum op_type type, machine_mode mode, rtx original,
GET_MODE_SIZE (mode)))
continue;
reg = lowpart_subreg (mode, reg, GET_MODE (reg));
- if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
+ if (reg == NULL_RTX || !SUBREG_P (reg))
continue;
}
*result_reg = reg;
@@ -680,7 +680,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (x == y)
return true;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
+ && (REG_P (y) || (SUBREG_P (y) && REG_P (SUBREG_REG (y)))))
{
int j;
@@ -717,10 +717,10 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (code == REG && REG_P (y))
return REGNO (x) == REGNO (y);
- if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
+ if (code == REG && SUBREG_P (y) && REG_P (SUBREG_REG (y))
&& x == SUBREG_REG (y))
return true;
- if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
+ if (REG_P (y) && code == SUBREG && REG_P (SUBREG_REG (x))
&& SUBREG_REG (x) == y)
return true;
@@ -829,7 +829,7 @@ narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
registers for several reloads of one insn. */
if (INSN_UID (curr_insn) >= new_insn_uid_start)
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
return;
@@ -946,7 +946,7 @@ match_reload (signed char out, signed char *ins, signed char *outs,
rtx_insn *clobber = emit_clobber (new_out_reg);
LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
LRA_SUBREG_P (new_in_reg) = 1;
- if (GET_CODE (in_rtx) == SUBREG)
+ if (SUBREG_P (in_rtx))
{
rtx subreg_reg = SUBREG_REG (in_rtx);
@@ -1125,7 +1125,7 @@ emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
if (! MEM_P (val))
{
val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
- GET_CODE (val) == SUBREG
+ SUBREG_P (val)
? SUBREG_REG (val) : val);
LRA_SUBREG_P (val) = 1;
}
@@ -1156,9 +1156,9 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
lra_assert (curr_insn_set != NULL_RTX);
dreg = dest = SET_DEST (curr_insn_set);
sreg = src = SET_SRC (curr_insn_set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dreg = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
sreg = SUBREG_REG (src);
if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
return false;
@@ -1355,7 +1355,7 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
machine_mode mode;
bool subreg_p, before_p = false;
- subreg_p = GET_CODE (*loc) == SUBREG;
+ subreg_p = SUBREG_P (*loc);
if (subreg_p)
{
reg = SUBREG_REG (*loc);
@@ -1483,7 +1483,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode)
before = after = NULL;
- if (GET_CODE (operand) != SUBREG)
+ if (!SUBREG_P (operand))
return false;
mode = GET_MODE (operand);
@@ -1961,7 +1961,7 @@ process_alt_operands (int only_alternative)
operand_reg[nop] = reg = op;
biggest_mode[nop] = GET_MODE (op);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
biggest_mode[nop] = wider_subreg_mode (op);
operand_reg[nop] = reg = SUBREG_REG (op);
@@ -2600,7 +2600,7 @@ process_alt_operands (int only_alternative)
if (curr_static_id->operand[nop].strict_low
&& REG_P (op)
&& hard_regno[nop] < 0
- && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
+ && SUBREG_P (*curr_id->operand_loc[nop])
&& ira_class_hard_regs_num[this_alternative] > 0
&& (!targetm.hard_regno_mode_ok
(ira_class_hard_regs[this_alternative][0],
@@ -2904,7 +2904,7 @@ process_alt_operands (int only_alternative)
if (curr_insn_set != NULL_RTX && n_operands == 2
/* Prevent processing non-move insns. */
- && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ && (SUBREG_P (SET_SRC (curr_insn_set))
|| SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
&& ((! curr_alt_win[0] && ! curr_alt_win[1]
&& REG_P (no_subreg_reg_operand[0])
@@ -3338,7 +3338,7 @@ process_address_1 (int nop, bool check_only_p,
&& get_constraint_type (cn) == CT_FIXED_FORM
&& constraint_satisfied_p (op, cn)))
decompose_mem_address (&ad, op);
- else if (GET_CODE (op) == SUBREG
+ else if (SUBREG_P (op)
&& MEM_P (SUBREG_REG (op)))
decompose_mem_address (&ad, SUBREG_REG (op));
else
@@ -3886,7 +3886,7 @@ curr_insn_transform (bool check_only_p)
continue;
old = op = *curr_id->operand_loc[i];
- if (GET_CODE (old) == SUBREG)
+ if (SUBREG_P (old))
old = SUBREG_REG (old);
subst = get_equiv_with_elimination (old, curr_insn);
original_subreg_reg_mode[i] = VOIDmode;
@@ -3896,7 +3896,7 @@ curr_insn_transform (bool check_only_p)
equiv_substition_p[i] = true;
subst = copy_rtx (subst);
lra_assert (REG_P (old));
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
*curr_id->operand_loc[i] = subst;
else
{
@@ -4154,7 +4154,7 @@ curr_insn_transform (bool check_only_p)
enum reg_class new_class;
rtx reg = *curr_id->operand_loc[i];
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
@@ -4176,7 +4176,7 @@ curr_insn_transform (bool check_only_p)
rtx subreg = NULL_RTX;
machine_mode mode = curr_operand_mode[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4272,10 +4272,10 @@ curr_insn_transform (bool check_only_p)
&& (curr_insn_set == NULL_RTX
|| !((REG_P (SET_SRC (curr_insn_set))
|| MEM_P (SET_SRC (curr_insn_set))
- || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
+ || SUBREG_P (SET_SRC (curr_insn_set)))
&& (REG_P (SET_DEST (curr_insn_set))
|| MEM_P (SET_DEST (curr_insn_set))
- || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
+ || SUBREG_P (SET_DEST (curr_insn_set))))))
optional_p = true;
else if (goal_alt_matched[i][0] != -1
&& curr_static_id->operand[i].type == OP_OUT
@@ -4355,7 +4355,7 @@ curr_insn_transform (bool check_only_p)
loc = curr_id->operand_loc[i];
mode = curr_operand_mode[i];
- if (GET_CODE (*loc) == SUBREG)
+ if (SUBREG_P (*loc))
{
reg = SUBREG_REG (*loc);
poly_int64 byte = SUBREG_BYTE (*loc);
@@ -4485,7 +4485,7 @@ curr_insn_transform (bool check_only_p)
lra_assert (REG_P (reg));
regno = REGNO (reg);
op = *curr_id->operand_loc[i]; /* Substitution. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
@@ -4948,7 +4948,7 @@ lra_constraints (bool first_p)
/* The equivalence pseudo could be set up as SUBREG in a
case when it is a call restore insn in a mode
different from the pseudo mode. */
- if (GET_CODE (dest_reg) == SUBREG)
+ if (SUBREG_P (dest_reg))
dest_reg = SUBREG_REG (dest_reg);
if ((REG_P (dest_reg)
&& (x = get_equiv (dest_reg)) != dest_reg
@@ -6765,7 +6765,7 @@ fix_bb_live_info (bitmap live, bitmap removed_pseudos)
static int
get_regno (rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
return REGNO (reg);
@@ -6950,7 +6950,7 @@ remove_inheritance_pseudos (bitmap remove_pseudos)
&& (restore_rtx
= lra_reg_info[dregno].restore_rtx) != NULL_RTX)
{
- if (GET_CODE (SET_DEST (set)) == SUBREG)
+ if (SUBREG_P (SET_DEST (set)))
SUBREG_REG (SET_DEST (set)) = restore_rtx;
else
SET_DEST (set) = restore_rtx;
diff --git a/gcc/lra-eliminations.c b/gcc/lra-eliminations.c
index 943da888848..a9d650dab7e 100644
--- a/gcc/lra-eliminations.c
+++ b/gcc/lra-eliminations.c
@@ -287,7 +287,7 @@ move_plus_up (rtx x)
rtx subreg_reg;
machine_mode x_mode, subreg_reg_mode;
- if (GET_CODE (x) != SUBREG || !subreg_lowpart_p (x))
+ if (!SUBREG_P (x) || !subreg_lowpart_p (x))
return x;
subreg_reg = SUBREG_REG (x);
x_mode = GET_MODE (x);
@@ -932,7 +932,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -943,7 +943,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (ep = get_elimination (reg)) != NULL)
@@ -964,7 +964,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
}
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx);
/* If we have a nonzero offset, and the source is already a
simple REG, the following transformation would increase
diff --git a/gcc/lra.c b/gcc/lra.c
index d7593998f97..f7790f2e154 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -384,9 +384,9 @@ lra_emit_add (rtx x, rtx y, rtx z)
base = a1;
index = a2;
}
- if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
+ if ((base != NULL_RTX && ! (REG_P (base) || SUBREG_P (base)))
|| (index != NULL_RTX
- && ! (REG_P (index) || GET_CODE (index) == SUBREG))
+ && ! (REG_P (index) || SUBREG_P (index)))
|| (disp != NULL_RTX && ! CONSTANT_P (disp))
|| (scale != NULL_RTX && ! CONSTANT_P (scale)))
{
@@ -1459,7 +1459,7 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
code = GET_CODE (x);
mode = GET_MODE (x);
subreg_p = false;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
mode = wider_subreg_mode (x);
if (read_modify_subreg_p (x))
diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index 2ff21a40081..5e3bacb1e18 100644
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -212,7 +212,7 @@ reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -266,7 +266,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
&& EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
&& NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
&& GET_CODE (PATTERN (last_insn)) == USE
- && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
+ && REG_P ((ret_reg = XEXP (PATTERN (last_insn), 0))))
{
int ret_start = REGNO (ret_reg);
int nregs = REG_NREGS (ret_reg);
@@ -302,7 +302,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
case USE:
/* Skip USEs of multiple return registers.
__builtin_apply pattern is also handled here. */
- if (GET_CODE (XEXP (return_copy_pat, 0)) == REG
+ if (REG_P (XEXP (return_copy_pat, 0))
&& (targetm.calls.function_value_regno_p
(REGNO (XEXP (return_copy_pat, 0)))))
{
@@ -344,7 +344,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
the previous insn is the clobber for
the return register. */
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG
+ if (REG_P (copy_reg)
&& !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
{
if (INSN_P (PREV_INSN (return_copy)))
@@ -358,10 +358,10 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
}
}
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG)
+ if (REG_P (copy_reg))
copy_start = REGNO (copy_reg);
- else if (GET_CODE (copy_reg) == SUBREG
- && GET_CODE (SUBREG_REG (copy_reg)) == REG)
+ else if (SUBREG_P (copy_reg)
+ && REG_P (SUBREG_REG (copy_reg)))
copy_start = REGNO (SUBREG_REG (copy_reg));
else
{
diff --git a/gcc/modulo-sched.c b/gcc/modulo-sched.c
index c355594bb6b..4ebd514daed 100644
--- a/gcc/modulo-sched.c
+++ b/gcc/modulo-sched.c
@@ -1477,7 +1477,7 @@ sms_schedule (void)
&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
&& !reg_mentioned_p (count_reg, insn))
|| (INSN_P (insn) && (set = single_set (insn))
- && GET_CODE (SET_DEST (set)) == SUBREG))
+ && SUBREG_P (SET_DEST (set))))
break;
}
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 06bcaab1f55..77a58bdde2c 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -208,7 +208,7 @@ widen_operand (rtx op, machine_mode mode, machine_mode oldmode,
a promoted object differs from our extension. */
if (! no_extend
|| !is_a <scalar_int_mode> (mode, &int_mode)
- || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)
+ || (SUBREG_P (op) && SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_CHECK_PROMOTED_SIGN (op, unsignedp)))
return convert_modes (mode, oldmode, op, unsignedp);
@@ -5276,7 +5276,7 @@ debug_optab_libfuncs (void)
rtx l = optab_libfunc ((optab) i, (machine_mode) j);
if (l)
{
- gcc_assert (GET_CODE (l) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (l));
fprintf (stderr, "%s\t%s:\t%s\n",
GET_RTX_NAME (optab_to_code ((optab) i)),
GET_MODE_NAME (j),
@@ -5293,7 +5293,7 @@ debug_optab_libfuncs (void)
(machine_mode) k);
if (l)
{
- gcc_assert (GET_CODE (l) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (l));
fprintf (stderr, "%s\t%s\t%s:\t%s\n",
GET_RTX_NAME (optab_to_code ((optab) i)),
GET_MODE_NAME (j),
diff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c
index e4737670883..429a44a4762 100644
--- a/gcc/postreload-gcse.c
+++ b/gcc/postreload-gcse.c
@@ -618,7 +618,7 @@ find_mem_conflicts (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
rtx mem_op = (rtx) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -733,7 +733,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 728aa9b0ed5..f1951b305ff 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -1418,7 +1418,7 @@ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
int i;
machine_mode mode = GET_MODE (dst);
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
{
regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
GET_MODE (SUBREG_REG (dst)),
@@ -1670,7 +1670,7 @@ move2add_record_mode (rtx reg)
int regno, nregs;
machine_mode mode = GET_MODE (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno = subreg_regno (reg);
nregs = subreg_nregs (reg);
@@ -2053,16 +2053,16 @@ reload_cse_move2add (rtx_insn *first)
(set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
...
(set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
- if ((GET_CODE (src) == SYMBOL_REF
+ if ((SYMBOL_REF_P (src)
|| (GET_CODE (src) == CONST
&& GET_CODE (XEXP (src, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (src, 0), 0))
&& CONST_INT_P (XEXP (XEXP (src, 0), 1))))
&& dbg_cnt (cse2_move2add))
{
rtx sym, off;
- if (GET_CODE (src) == SYMBOL_REF)
+ if (SYMBOL_REF_P (src))
{
sym = src;
off = const0_rtx;
@@ -2188,7 +2188,7 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
return;
}
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
regno = subreg_regno (dst);
else if (REG_P (dst))
regno = REGNO (dst);
@@ -2204,14 +2204,14 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
rtx off;
note = find_reg_equal_equiv_note (insn);
- if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
+ if (note && SYMBOL_REF_P (XEXP (note, 0)))
{
sym = XEXP (note, 0);
off = const0_rtx;
}
else if (note && GET_CODE (XEXP (note, 0)) == CONST
&& GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (XEXP (note, 0), 0), 0))
&& CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
{
sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index 10948efddd9..53212ce878f 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -215,7 +215,7 @@ rtx_writer::print_rtx_operand_code_0 (const_rtx in_rtx ATTRIBUTE_UNUSED,
int idx ATTRIBUTE_UNUSED)
{
#ifndef GENERATOR_FILE
- if (idx == 1 && GET_CODE (in_rtx) == SYMBOL_REF)
+ if (idx == 1 && SYMBOL_REF_P (in_rtx))
{
int flags = SYMBOL_REF_FLAGS (in_rtx);
if (flags)
@@ -573,7 +573,7 @@ rtx_writer::print_rtx_operand_code_u (const_rtx in_rtx, int idx)
rtx sub = XEXP (in_rtx, idx);
enum rtx_code subc = GET_CODE (sub);
- if (GET_CODE (in_rtx) == LABEL_REF)
+ if (LABEL_REF_P (in_rtx))
{
if (subc == NOTE
&& NOTE_KIND (sub) == NOTE_INSN_DELETED_LABEL)
diff --git a/gcc/read-rtl-function.c b/gcc/read-rtl-function.c
index f41f54a0d4a..0a3f79c8c36 100644
--- a/gcc/read-rtl-function.c
+++ b/gcc/read-rtl-function.c
@@ -955,7 +955,7 @@ function_reader::read_rtx_operand_u (rtx x, int idx)
{
/* In compact mode, the PREV/NEXT insn uids are not dumped, so skip
the "uu" when reading. */
- if (is_compact () && GET_CODE (x) != LABEL_REF)
+ if (is_compact () && !LABEL_REF_P (x))
return;
struct md_name name;
@@ -1446,7 +1446,7 @@ ensure_regno (int regno)
static rtx
consolidate_reg (rtx x)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
unsigned int regno = REGNO (x);
@@ -1463,7 +1463,7 @@ consolidate_reg (rtx x)
if (regno_reg_rtx[regno] == NULL)
regno_reg_rtx[regno] = x;
/* Use it. */
- gcc_assert (GET_CODE (regno_reg_rtx[regno]) == REG);
+ gcc_assert (REG_P (regno_reg_rtx[regno]));
gcc_assert (REGNO (regno_reg_rtx[regno]) == regno);
if (GET_MODE (x) == GET_MODE (regno_reg_rtx[regno]))
return regno_reg_rtx[regno];
diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c
index 3b5d9997603..3dcf35b8f17 100644
--- a/gcc/read-rtl.c
+++ b/gcc/read-rtl.c
@@ -255,7 +255,7 @@ find_int (const char *name)
static void
apply_int_iterator (rtx x, unsigned int index, int value)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
SUBREG_BYTE (x) = value;
else
XINT (x, index) = value;
diff --git a/gcc/recog.c b/gcc/recog.c
index a9f584bc0dc..5b6e957b2b4 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -123,7 +123,7 @@ asm_labels_ok (rtx body)
return true;
for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
- if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
+ if (!LABEL_REF_P (ASM_OPERANDS_LABEL (asmop, i)))
return false;
return true;
@@ -1087,7 +1087,7 @@ address_operand (rtx op, machine_mode mode)
int
register_operand (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
rtx sub = SUBREG_REG (op);
@@ -1213,7 +1213,7 @@ const_scalar_int_operand (rtx op, machine_mode mode)
int
const_double_operand (rtx op, machine_mode mode)
{
- return (GET_CODE (op) == CONST_DOUBLE)
+ return (CONST_DOUBLE_P (op))
&& (GET_MODE (op) == mode || mode == VOIDmode);
}
#else
@@ -1360,7 +1360,7 @@ memory_operand (rtx op, machine_mode mode)
return 0;
inner = op;
- if (GET_CODE (inner) == SUBREG)
+ if (SUBREG_P (inner))
inner = SUBREG_REG (inner);
return (MEM_P (inner) && general_operand (op, mode));
@@ -1374,7 +1374,7 @@ indirect_operand (rtx op, machine_mode mode)
{
/* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
if (! reload_completed
- && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
+ && SUBREG_P (op) && MEM_P (SUBREG_REG (op)))
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
@@ -2603,7 +2603,7 @@ constrain_operands (int strict, alternative_mask alternatives)
if (UNARY_P (op))
op = XEXP (op, 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (REG_P (SUBREG_REG (op))
&& REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ree.c b/gcc/ree.c
index c63e1591ae3..ddd31ab6c06 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -268,7 +268,7 @@ update_reg_equal_equiv_notes (rtx_insn *insn, machine_mode new_mode,
rtx orig_src = XEXP (*loc, 0);
/* Update equivalency constants. Recall that RTL constants are
sign-extended. */
- if (GET_CODE (orig_src) == CONST_INT
+ if (CONST_INT_P (orig_src)
&& HWI_COMPUTABLE_MODE_P (new_mode))
{
if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
@@ -336,7 +336,7 @@ combine_set_extension (ext_cand *cand, rtx_insn *curr_insn, rtx *orig_set)
/* Merge constants by directly moving the constant into the register under
some conditions. Recall that RTL constants are sign-extended. */
- if (GET_CODE (orig_src) == CONST_INT
+ if (CONST_INT_P (orig_src)
&& HWI_COMPUTABLE_MODE_P (cand->mode))
{
if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
@@ -467,7 +467,7 @@ get_defs (rtx_insn *insn, rtx reg, vec<rtx_insn *> *dest)
FOR_EACH_INSN_USE (use, insn)
{
- if (GET_CODE (DF_REF_REG (use)) == SUBREG)
+ if (SUBREG_P (DF_REF_REG (use)))
return NULL;
if (REGNO (DF_REF_REG (use)) == REGNO (reg))
break;
@@ -541,10 +541,10 @@ is_cond_copy_insn (rtx_insn *insn, rtx *reg1, rtx *reg2)
if (expr != NULL_RTX
&& GET_CODE (expr) == SET
- && GET_CODE (SET_DEST (expr)) == REG
+ && REG_P (SET_DEST (expr))
&& GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG
- && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG)
+ && REG_P (XEXP (SET_SRC (expr), 1))
+ && REG_P (XEXP (SET_SRC (expr), 2)))
{
*reg1 = XEXP (SET_SRC (expr), 1);
*reg2 = XEXP (SET_SRC (expr), 2);
diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index 710f14a9544..45b0b35160a 100644
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -492,7 +492,7 @@ check_asm_stack_operands (rtx_insn *insn)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
@@ -510,7 +510,7 @@ check_asm_stack_operands (rtx_insn *insn)
rtx clobber = XVECEXP (body, 0, i);
rtx reg = XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
reg = SUBREG_REG (reg);
if (STACK_REG_P (reg))
@@ -908,7 +908,7 @@ emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg)
i1src = XEXP (i1src, 0);
if (REG_P (i1dest)
&& REGNO (i1dest) == FIRST_STACK_REG
- && (MEM_P (i1src) || GET_CODE (i1src) == CONST_DOUBLE)
+ && (MEM_P (i1src) || CONST_DOUBLE_P (i1src))
&& !side_effects_p (i1src)
&& hard_regno == FIRST_STACK_REG + 1
&& i1 != BB_HEAD (current_block))
@@ -949,7 +949,7 @@ emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg)
%st to %st(1), consider swapping them. */
if (REG_P (i2dest)
&& REGNO (i2dest) == FIRST_STACK_REG
- && (MEM_P (i2src) || GET_CODE (i2src) == CONST_DOUBLE)
+ && (MEM_P (i2src) || CONST_DOUBLE_P (i2src))
/* Ensure i2 doesn't have other side-effects. */
&& !side_effects_p (i2src)
/* And that the two instructions can actually be
@@ -2139,7 +2139,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
{
recog_data.operand_loc[i] = & SUBREG_REG (recog_data.operand[i]);
@@ -2163,7 +2163,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (note, 0);
rtx *loc = & XEXP (note, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
@@ -2196,7 +2196,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (clobber, 0);
rtx *loc = & XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
diff --git a/gcc/regcprop.c b/gcc/regcprop.c
index a18c24f4797..680cf15e719 100644
--- a/gcc/regcprop.c
+++ b/gcc/regcprop.c
@@ -189,7 +189,7 @@ kill_value_regno (unsigned int regno, unsigned int nregs,
static void
kill_value (const_rtx x, struct value_data *vd)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx tmp = simplify_subreg (GET_MODE (x), SUBREG_REG (x),
GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
@@ -541,13 +541,13 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reginfo.c b/gcc/reginfo.c
index 4832affd436..a3d16005d91 100644
--- a/gcc/reginfo.c
+++ b/gcc/reginfo.c
@@ -1109,7 +1109,7 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
case SET:
/* Count a set of the destination if it is a register. */
for (dest = SET_DEST (x);
- GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
+ SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART
|| GET_CODE (dest) == ZERO_EXTRACT;
dest = XEXP (dest, 0))
;
@@ -1144,21 +1144,21 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
&& REG_P (XEXP (SET_SRC (x), 0))
&& REG_POINTER (XEXP (SET_SRC (x), 0)))
|| GET_CODE (SET_SRC (x)) == CONST
- || GET_CODE (SET_SRC (x)) == SYMBOL_REF
- || GET_CODE (SET_SRC (x)) == LABEL_REF
+ || SYMBOL_REF_P (SET_SRC (x))
+ || LABEL_REF_P (SET_SRC (x))
|| (GET_CODE (SET_SRC (x)) == HIGH
&& (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
- || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
+ || SYMBOL_REF_P (XEXP (SET_SRC (x), 0))
+ || LABEL_REF_P (XEXP (SET_SRC (x), 0))))
|| ((GET_CODE (SET_SRC (x)) == PLUS
|| GET_CODE (SET_SRC (x)) == LO_SUM)
&& (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
- || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
- || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
+ || SYMBOL_REF_P (XEXP (SET_SRC (x), 1))
+ || LABEL_REF_P (XEXP (SET_SRC (x), 1))))
|| ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
&& (GET_CODE (XEXP (note, 0)) == CONST
- || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
+ || SYMBOL_REF_P (XEXP (note, 0))
+ || LABEL_REF_P (XEXP (note, 0))))))
REG_POINTER (SET_DEST (x)) = 1;
/* If this is setting a register from a register or from a simple
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 73c0ceda341..0ce4d180880 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1055,7 +1055,7 @@ note_sets_clobbers (rtx x, const_rtx set, void *data)
enum rtx_code code = *(enum rtx_code *)data;
class du_head *chain;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!REG_P (x) || GET_CODE (set) != code)
return;
@@ -1088,8 +1088,8 @@ scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions act
a single output. */
if (recog_data.n_operands == 2
&& GET_CODE (pat) == SET
- && GET_CODE (SET_DEST (pat)) == REG
- && GET_CODE (SET_SRC (pat)) == REG
+ && REG_P (SET_DEST (pat))
+ && REG_P (SET_SRC (pat))
&& terminated_this_insn
&& terminated_this_insn->nregs
== REG_NREGS (recog_data.operand[1]))
@@ -1291,13 +1291,13 @@ scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reload.c b/gcc/reload.c
index 72cc38a0e09..52233eb55e1 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -840,7 +840,7 @@ reload_inner_reg_of_subreg (rtx x, machine_mode mode, bool output)
rtx inner;
/* Only SUBREGs are problematical. */
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
inner = SUBREG_REG (x);
@@ -1051,7 +1051,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
no choice, so we hope we do get the right register class there. */
scalar_int_mode inner_mode;
- if (in != 0 && GET_CODE (in) == SUBREG
+ if (in != 0 && SUBREG_P (in)
&& (subreg_lowpart_p (in) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (in)),
inmode, rclass)
@@ -1149,7 +1149,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
entitled to clobber it all (except in the case of a word mode subreg
or of a STRICT_LOW_PART, in that latter case the constraint should
label it input-output.) */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& (subreg_lowpart_p (out) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (out)),
outmode, rclass)
@@ -1232,13 +1232,13 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
/* If IN is a SUBREG of a hard register, make a new REG. This
simplifies some of the cases below. */
- if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
+ if (in != 0 && SUBREG_P (in) && REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
/* Similarly for OUT. */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
@@ -1270,12 +1270,12 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
#ifdef LIMIT_RELOAD_CLASS
if (in_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (inmode, rclass);
- else if (in != 0 && GET_CODE (in) == SUBREG)
+ else if (in != 0 && SUBREG_P (in))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass);
if (out_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (outmode, rclass);
- if (out != 0 && GET_CODE (out) == SUBREG)
+ if (out != 0 && SUBREG_P (out))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass);
#endif
@@ -1351,7 +1351,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (subreg_in_class == NO_REGS
&& in != 0
&& (REG_P (in)
- || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
+ || (SUBREG_P (in) && REG_P (SUBREG_REG (in))))
&& reg_or_subregno (in) < FIRST_PSEUDO_REGISTER)
subreg_in_class = REGNO_REG_CLASS (reg_or_subregno (in));
/* If a memory location is needed for the copy, make one. */
@@ -1383,7 +1383,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (out != 0
&& (REG_P (out)
- || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
+ || (SUBREG_P (out) && REG_P (SUBREG_REG (out))))
&& reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
&& (targetm.secondary_memory_needed
(outmode, rclass, REGNO_REG_CLASS (reg_or_subregno (out)))))
@@ -1597,7 +1597,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
Is there any simple coherent way to describe the two together?
What's going on here. */
&& (in != out
- || (GET_CODE (in) == SUBREG
+ || (SUBREG_P (in)
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (in)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))),
@@ -1951,7 +1951,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
respectively refers to a hard register. */
/* Find the inside of any subregs. */
- while (GET_CODE (out) == SUBREG)
+ while (SUBREG_P (out))
{
if (REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
@@ -1961,7 +1961,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
GET_MODE (out));
out = SUBREG_REG (out);
}
- while (GET_CODE (in) == SUBREG)
+ while (SUBREG_P (in))
{
if (REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
@@ -2134,7 +2134,7 @@ hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
{
rtx op0 = SET_DEST (x);
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
op0 = SUBREG_REG (op0);
if (REG_P (op0))
{
@@ -2204,7 +2204,7 @@ operands_match_p (rtx x, rtx y)
if (x == y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int j;
@@ -2222,7 +2222,7 @@ operands_match_p (rtx x, rtx y)
else
i = REGNO (x);
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
j = REGNO (SUBREG_REG (y));
if (j >= FIRST_PSEUDO_REGISTER)
@@ -2836,7 +2836,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we now have a simple operand where we used to have a
PLUS or MULT, re-recognize and try again. */
if ((OBJECT_P (*recog_data.operand_loc[i])
- || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ || SUBREG_P (*recog_data.operand_loc[i]))
&& (GET_CODE (recog_data.operand[i]) == MULT
|| GET_CODE (recog_data.operand[i]) == PLUS))
{
@@ -3073,7 +3073,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
the REG or MEM (or maybe even a constant) within.
(Constants can occur as a result of reg_equiv_constant.) */
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
{
/* Offset only matters when operand is a REG and
it is a hard reg. This is because it is passed
@@ -3692,7 +3692,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
it's costly to reload it, so reload the input instead. */
if (small_register_class_p (this_alternative[i])
&& (REG_P (recog_data.operand[j])
- || GET_CODE (recog_data.operand[j]) == SUBREG))
+ || SUBREG_P (recog_data.operand[j])))
{
losers++;
this_alternative_win[j] = 0;
@@ -3907,7 +3907,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* Reloads of SUBREGs of CONSTANT RTXs are handled later in
push_reload so we have to let them pass here. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4086,7 +4086,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -4136,7 +4136,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
{
operand = *recog_data.operand_loc[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand))
{
@@ -4163,7 +4163,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -4200,7 +4200,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we're replacing an operand with a LABEL_REF, we need to
make sure that there's a REG_LABEL_OPERAND note attached to
this instruction. */
- if (GET_CODE (substitution) == LABEL_REF
+ if (LABEL_REF_P (substitution)
&& !find_reg_note (insn, REG_LABEL_OPERAND,
label_ref_label (substitution))
/* For a JUMP_P, if it was a branch target it must have
@@ -5035,7 +5035,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
taken care of above. */
if (ind_levels == 0
- || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
+ || (SYMBOL_REF_P (XEXP (tem, 0)) && ! indirect_symref_ok)
|| MEM_P (XEXP (tem, 0))
|| ! (REG_P (XEXP (tem, 0))
|| (GET_CODE (XEXP (tem, 0)) == PLUS
@@ -5229,7 +5229,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
/* If AD is an address in the constant pool, the MEM rtx may be shared.
Unshare it so we can safely alter it. */
- if (memrefloc && GET_CODE (ad) == SYMBOL_REF
+ if (memrefloc && SYMBOL_REF_P (ad)
&& CONSTANT_POOL_ADDRESS_P (ad))
{
*memrefloc = copy_rtx (*memrefloc);
@@ -5505,7 +5505,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
rtx op0 = orig_op0;
rtx op1 = orig_op1;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
@@ -5518,7 +5518,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
GET_MODE (orig_op0))));
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
@@ -6266,7 +6266,7 @@ subst_reloads (rtx_insn *insn)
/* If we're replacing a LABEL_REF with a register, there must
already be an indication (to e.g. flow) which label this
register refers to. */
- gcc_assert (GET_CODE (*r->where) != LABEL_REF
+ gcc_assert (!LABEL_REF_P (*r->where)
|| !JUMP_P (insn)
|| find_reg_note (insn,
REG_LABEL_OPERAND,
@@ -6362,7 +6362,7 @@ find_replacement (rtx *loc)
return reloadreg;
}
- else if (reloadreg && GET_CODE (*loc) == SUBREG
+ else if (reloadreg && SUBREG_P (*loc)
&& r->where == &SUBREG_REG (*loc))
{
if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
@@ -6455,7 +6455,7 @@ refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -6531,9 +6531,9 @@ reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
/* If either argument is a constant, then modifying X cannot affect IN. */
if (CONSTANT_P (x) || CONSTANT_P (in))
return 0;
- else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ else if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
return refers_to_mem_for_reload_p (in);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
regno = REGNO (SUBREG_REG (x));
if (regno < FIRST_PSEUDO_REGISTER)
@@ -6942,7 +6942,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
{
rtx dest = SET_DEST (pat);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -6981,7 +6981,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
{
rtx dest = SET_DEST (v1);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 38ee356a791..d30badc0c4f 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2436,13 +2436,13 @@ set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
case IF_THEN_ELSE:
tem = XEXP (SET_SRC (x), 1);
- if (GET_CODE (tem) == LABEL_REF)
+ if (LABEL_REF_P (tem))
set_label_offsets (label_ref_label (tem), insn, initial_p);
else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
break;
tem = XEXP (SET_SRC (x), 2);
- if (GET_CODE (tem) == LABEL_REF)
+ if (LABEL_REF_P (tem))
set_label_offsets (label_ref_label (tem), insn, initial_p);
else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
break;
@@ -2850,7 +2850,7 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
|| known_eq (x_size, new_size))
)
return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
- else if (insn && GET_CODE (insn) == DEBUG_INSN)
+ else if (insn && DEBUG_INSN_P (insn))
return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
else
return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
@@ -3270,7 +3270,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
if (plus_cst_src)
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -3282,7 +3282,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
rtx reg = XEXP (plus_cst_src, 0);
poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
@@ -3292,7 +3292,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
offset += ep->offset;
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
to_rtx);
/* If we have a nonzero offset, and the source is already
@@ -3721,7 +3721,7 @@ mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
/* A SUBREG of a hard register here is just changing its mode. We should
not see a SUBREG of an eliminable hard register, but check just in
case. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (dest == hard_frame_pointer_rtx)
@@ -4422,7 +4422,7 @@ strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
rather than simplifying it to another hard register, then the
mode change cannot be properly represented. For example, OTHER
might be valid in its current mode, but not in the new one. */
- if (GET_CODE (tem) == SUBREG
+ if (SUBREG_P (tem)
&& REG_P (other)
&& HARD_REGISTER_P (other))
return false;
@@ -4829,7 +4829,7 @@ forget_old_reloads_1 (rtx x, const_rtx setter,
/* note_stores does give us subregs of hard regs,
subreg_regno_offset requires a hard reg. */
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
{
/* We ignore the subreg offset when calculating the regno,
because we are using the entire underlying hard register
@@ -5589,10 +5589,10 @@ gen_reload_chain_without_interm_reg_p (int r1, int r2)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -5994,7 +5994,7 @@ function_invariant_p (const_rtx x)
return 1;
if (GET_CODE (x) == PLUS
&& (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 1)))
return 1;
return 0;
}
@@ -6281,7 +6281,7 @@ choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
static rtx
replaced_subreg (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
return find_replacement (&SUBREG_REG (x));
return x;
}
@@ -6467,7 +6467,7 @@ choose_reload_regs (class insn_chain *chain)
regno = REGNO (rld[r].in_reg);
mode = GET_MODE (rld[r].in_reg);
}
- else if (GET_CODE (rld[r].in_reg) == SUBREG
+ else if (SUBREG_P (rld[r].in_reg)
&& REG_P (SUBREG_REG (rld[r].in_reg)))
{
regno = REGNO (SUBREG_REG (rld[r].in_reg));
@@ -6493,7 +6493,7 @@ choose_reload_regs (class insn_chain *chain)
/* This won't work, since REGNO can be a pseudo reg number.
Also, it takes much more hair to keep track of all the things
that can invalidate an inherited reload of part of a pseudoreg. */
- else if (GET_CODE (rld[r].in) == SUBREG
+ else if (SUBREG_P (rld[r].in)
&& REG_P (SUBREG_REG (rld[r].in)))
regno = subreg_regno (rld[r].in);
#endif
@@ -6663,7 +6663,7 @@ choose_reload_regs (class insn_chain *chain)
Make a new REG since this might be used in an
address and not all machines support SUBREGs
there. */
- gcc_assert (GET_CODE (equiv) == SUBREG);
+ gcc_assert (SUBREG_P (equiv));
regno = subreg_regno (equiv);
equiv = gen_rtx_REG (rld[r].mode, regno);
/* If we choose EQUIV as the reload register, but the
@@ -6914,7 +6914,7 @@ choose_reload_regs (class insn_chain *chain)
check_reg = rld[r].reg_rtx;
else if (reload_override_in[r]
&& (REG_P (reload_override_in[r])
- || GET_CODE (reload_override_in[r]) == SUBREG))
+ || SUBREG_P (reload_override_in[r])))
check_reg = reload_override_in[r];
else
continue;
@@ -7131,7 +7131,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
determine whether a secondary reload is needed. */
if (reload_override_in[j]
&& (REG_P (rl->in_reg)
- || (GET_CODE (rl->in_reg) == SUBREG
+ || (SUBREG_P (rl->in_reg)
&& REG_P (SUBREG_REG (rl->in_reg)))))
{
oldequiv = old;
@@ -7141,7 +7141,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
oldequiv = old;
else if (REG_P (oldequiv))
oldequiv_reg = oldequiv;
- else if (GET_CODE (oldequiv) == SUBREG)
+ else if (SUBREG_P (oldequiv))
oldequiv_reg = SUBREG_REG (oldequiv);
reloadreg = reload_reg_rtx_for_input[j];
@@ -7163,7 +7163,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
/* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
OLDEQUIV. */
- while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
+ while (SUBREG_P (oldequiv) && GET_MODE (oldequiv) != mode)
oldequiv = SUBREG_REG (oldequiv);
if (GET_MODE (oldequiv) != VOIDmode
&& mode != GET_MODE (oldequiv))
@@ -7342,7 +7342,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
not in the right mode. */
tmp = oldequiv;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7351,14 +7351,14 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (oldequiv) == SUBREG)
+ || SUBREG_P (oldequiv))
real_oldequiv = rl->in;
else
real_oldequiv = reg_equiv_mem (REGNO (tmp));
}
tmp = old;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7367,7 +7367,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (old) == SUBREG)
+ || SUBREG_P (old))
real_old = rl->in;
else
real_old = reg_equiv_mem (REGNO (tmp));
@@ -7542,7 +7542,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
&& REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
&& (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
|| reg_equiv_constant (REGNO (oldequiv)) != 0))
- || (GET_CODE (oldequiv) == SUBREG
+ || (SUBREG_P (oldequiv)
&& REG_P (SUBREG_REG (oldequiv))
&& (REGNO (SUBREG_REG (oldequiv))
>= FIRST_PSEUDO_REGISTER)
@@ -7949,7 +7949,7 @@ do_output_reload (class insn_chain *chain, struct reload *rl, int j)
return;
}
/* Likewise for a SUBREG of an operand that dies. */
- else if (GET_CODE (old) == SUBREG
+ else if (SUBREG_P (old)
&& REG_P (SUBREG_REG (old))
&& (note = find_reg_note (insn, REG_UNUSED,
SUBREG_REG (old))) != 0)
@@ -8098,7 +8098,7 @@ emit_reload_insns (class insn_chain *chain)
{
rtx reg = rld[r].in_reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg)
@@ -8507,10 +8507,10 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -8569,7 +8569,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
code = optab_handler (add_optab, GET_MODE (out));
- if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
+ if (CONSTANT_P (op1) || MEM_P (op1) || SUBREG_P (op1)
|| (REG_P (op1)
&& REGNO (op1) >= FIRST_PSEUDO_REGISTER)
|| (code != CODE_FOR_nothing
@@ -8661,7 +8661,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
fatal_insn ("failure trying to reload:", set);
}
/* If IN is a simple operand, use gen_move_insn. */
- else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
+ else if (OBJECT_P (in) || SUBREG_P (in))
{
tem = emit_insn (gen_move_insn (out, in));
/* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
@@ -8714,7 +8714,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
/* Get the raw pseudo-register referred to. */
- while (GET_CODE (reg) == SUBREG)
+ while (SUBREG_P (reg))
reg = SUBREG_REG (reg);
substed = reg_equiv_memory_loc (REGNO (reg));
@@ -8731,7 +8731,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
reg2 = XEXP (rld[k].in_reg, 0);
- while (GET_CODE (reg2) == SUBREG)
+ while (SUBREG_P (reg2))
reg2 = SUBREG_REG (reg2);
if (rtx_equal_p (reg2, reg))
{
diff --git a/gcc/reorg.c b/gcc/reorg.c
index bdfcf8851cd..4ec3d7efea6 100644
--- a/gcc/reorg.c
+++ b/gcc/reorg.c
@@ -894,19 +894,19 @@ get_branch_condition (const rtx_insn *insn, rtx target)
return 0;
src = SET_SRC (pat);
- if (GET_CODE (src) == LABEL_REF && label_ref_label (src) == target)
+ if (LABEL_REF_P (src) && label_ref_label (src) == target)
return const_true_rtx;
else if (GET_CODE (src) == IF_THEN_ELSE
&& XEXP (src, 2) == pc_rtx
- && ((GET_CODE (XEXP (src, 1)) == LABEL_REF
+ && ((LABEL_REF_P (XEXP (src, 1))
&& label_ref_label (XEXP (src, 1)) == target)
|| (ANY_RETURN_P (XEXP (src, 1)) && XEXP (src, 1) == target)))
return XEXP (src, 0);
else if (GET_CODE (src) == IF_THEN_ELSE
&& XEXP (src, 1) == pc_rtx
- && ((GET_CODE (XEXP (src, 2)) == LABEL_REF
+ && ((LABEL_REF_P (XEXP (src, 2))
&& label_ref_label (XEXP (src, 2)) == target)
|| (ANY_RETURN_P (XEXP (src, 2)) && XEXP (src, 2) == target)))
{
@@ -1510,7 +1510,7 @@ redundant_insn (rtx insn, rtx_insn *target, const vec<rtx_insn *> &delay_list)
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (pat))
@@ -1609,7 +1609,7 @@ redundant_insn (rtx insn, rtx_insn *target, const vec<rtx_insn *> &delay_list)
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (pat))
@@ -2047,7 +2047,7 @@ fill_simple_delay_slots (int non_jumps_p)
continue;
/* And DEBUG_INSNs never go into delay slots. */
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* Check for resource conflict first, to avoid unnecessary
@@ -2174,7 +2174,7 @@ fill_simple_delay_slots (int non_jumps_p)
continue;
/* And DEBUG_INSNs do not go in delay slots. */
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* If this already has filled delay slots, get the insn needing
@@ -2442,7 +2442,7 @@ fill_slots_from_thread (rtx_jump_insn *insn, rtx condition,
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* If TRIAL conflicts with the insns ahead of it, we lose. Also,
diff --git a/gcc/resource.c b/gcc/resource.c
index c4bcfd7dc71..3c3d6a1c6e4 100644
--- a/gcc/resource.c
+++ b/gcc/resource.c
@@ -90,10 +90,10 @@ update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
int i;
if (!REG_P (dest)
- && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest))))
+ && (!SUBREG_P (dest) || !REG_P (SUBREG_REG (dest))))
return;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
{
first_regno = subreg_regno (dest);
last_regno = first_regno + subreg_nregs (dest);
@@ -291,7 +291,7 @@ mark_referenced_resources (rtx x, struct resources *res,
if (GET_CODE (x) == ZERO_EXTRACT
|| GET_CODE (x) == STRICT_LOW_PART)
mark_referenced_resources (x, res, false);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
x = SUBREG_REG (x);
if (MEM_P (x))
mark_referenced_resources (XEXP (x, 0), res, false);
diff --git a/gcc/rtl.c b/gcc/rtl.c
index d7b8e9877c3..3a678e46236 100644
--- a/gcc/rtl.c
+++ b/gcc/rtl.c
@@ -205,7 +205,7 @@ rtx_size (const_rtx x)
return (RTX_HDR_SIZE
+ sizeof (struct const_poly_int_def)
+ CONST_POLY_INT_COEFFS (x).extra_size ());
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_HAS_BLOCK_INFO_P (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_HAS_BLOCK_INFO_P (x))
return RTX_HDR_SIZE + sizeof (struct block_symbol);
return RTX_CODE_SIZE (GET_CODE (x));
}
@@ -272,7 +272,7 @@ shared_const_p (const_rtx orig)
a LABEL_REF, it isn't sharable. */
poly_int64 offset;
return (GET_CODE (XEXP (orig, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (orig, 0), 0))
&& poly_int_rtx_p (XEXP (XEXP (orig, 0), 1), &offset));
}
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 268a38799d6..3ce8c1bb03e 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -871,7 +871,7 @@ offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
{
tree decl;
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return false;
if (offset == 0)
@@ -1027,7 +1027,7 @@ unsigned_reg_p (rtx op)
&& TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
return true;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_SIGN (op))
return true;
@@ -1052,7 +1052,7 @@ reg_mentioned_p (const_rtx reg, const_rtx in)
if (reg == in)
return 1;
- if (GET_CODE (in) == LABEL_REF)
+ if (LABEL_REF_P (in))
return reg == label_ref_label (in);
code = GET_CODE (in);
@@ -1155,7 +1155,7 @@ reg_referenced_p (const_rtx x, const_rtx body)
if (GET_CODE (SET_DEST (body)) != CC0
&& GET_CODE (SET_DEST (body)) != PC
&& !REG_P (SET_DEST (body))
- && ! (GET_CODE (SET_DEST (body)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (body))
&& REG_P (SUBREG_REG (SET_DEST (body)))
&& !read_modify_subreg_p (SET_DEST (body)))
&& reg_overlap_mentioned_p (x, SET_DEST (body)))
@@ -1401,7 +1401,7 @@ modified_in_p (const_rtx x, const_rtx insn)
bool
read_modify_subreg_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x));
@@ -1606,7 +1606,7 @@ set_noop_p (const_rtx set)
if (GET_CODE (dst) == STRICT_LOW_PART)
dst = XEXP (dst, 0);
- if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (src) && SUBREG_P (dst))
{
if (maybe_ne (SUBREG_BYTE (src), SUBREG_BYTE (dst)))
return 0;
@@ -1748,7 +1748,7 @@ refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -1912,7 +1912,7 @@ note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data)
{
rtx dest = SET_DEST (x);
- while ((GET_CODE (dest) == SUBREG
+ while ((SUBREG_P (dest)
&& (!REG_P (SUBREG_REG (dest))
|| REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
|| GET_CODE (dest) == ZERO_EXTRACT
@@ -2010,7 +2010,7 @@ note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
(*fun) (&XEXP (dest, 2), data);
}
- while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
+ while (SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
if (MEM_P (dest))
@@ -2072,7 +2072,7 @@ covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
{
unsigned int regno, endregno;
- if (GET_CODE (dest) == SUBREG && !read_modify_subreg_p (dest))
+ if (SUBREG_P (dest) && !read_modify_subreg_p (dest))
dest = SUBREG_REG (dest);
if (!REG_P (dest))
@@ -2850,7 +2850,7 @@ may_trap_p_1 (const_rtx x, unsigned flags)
return flag_trapping_math;
if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
return 1;
- if (GET_CODE (XEXP (x, 1)) == CONST_VECTOR)
+ if (CONST_VECTOR_P (XEXP (x, 1)))
{
/* For CONST_VECTOR, return 1 if any element is or might be zero. */
unsigned int n_elts;
@@ -3090,7 +3090,7 @@ replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
gcc_assert (GET_MODE (x) == GET_MODE (from));
return to;
}
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to, all_regs);
@@ -3177,7 +3177,7 @@ replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
rtx *loc = *iter;
if (rtx x = *loc)
{
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& CONSTANT_POOL_ADDRESS_P (x))
{
rtx c = get_pool_constant (x);
@@ -3196,7 +3196,7 @@ replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
}
}
- if ((GET_CODE (x) == LABEL_REF
+ if ((LABEL_REF_P (x)
|| GET_CODE (x) == INSN_LIST)
&& XEXP (x, 0) == old_label)
{
@@ -3230,7 +3230,7 @@ rtx_referenced_p (const_rtx x, const_rtx body)
if (const_rtx y = *iter)
{
/* Check if a label_ref Y refers to label X. */
- if (GET_CODE (y) == LABEL_REF
+ if (LABEL_REF_P (y)
&& LABEL_P (x)
&& label_ref_label (y) == x)
return true;
@@ -3239,7 +3239,7 @@ rtx_referenced_p (const_rtx x, const_rtx body)
return true;
/* If Y is a reference to pool constant traverse the constant. */
- if (GET_CODE (y) == SYMBOL_REF
+ if (SYMBOL_REF_P (y)
&& CONSTANT_POOL_ADDRESS_P (y))
iter.substitute (get_pool_constant (y));
}
@@ -3296,7 +3296,7 @@ computed_jump_p_1 (const_rtx x)
return 1;
case MEM:
- return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ return ! (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
case IF_THEN_ELSE:
@@ -5804,7 +5804,7 @@ get_condition (rtx_insn *jump, rtx_insn **earliest, int allow_cc_mode,
/* If this branches to JUMP_LABEL when the condition is false, reverse
the condition. */
reverse
- = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ = LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump);
return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX,
@@ -6051,7 +6051,7 @@ split_double (rtx value, rtx *first, rtx *second)
}
}
}
- else if (GET_CODE (value) == CONST_WIDE_INT)
+ else if (CONST_WIDE_INT_P (value))
{
/* All of this is scary code and needs to be converted to
properly work with any size integer. */
@@ -6208,7 +6208,7 @@ get_base_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
@@ -6225,7 +6225,7 @@ get_index_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
@@ -6567,7 +6567,7 @@ contains_symbolic_reference_p (const_rtx x)
{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
- if (SYMBOL_REF_P (*iter) || GET_CODE (*iter) == LABEL_REF)
+ if (SYMBOL_REF_P (*iter) || LABEL_REF_P (*iter))
return true;
return false;
@@ -6597,7 +6597,7 @@ tls_referenced_p (const_rtx x)
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
- if (GET_CODE (*iter) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (*iter) != 0)
+ if (SYMBOL_REF_P (*iter) && SYMBOL_REF_TLS_MODEL (*iter) != 0)
return true;
return false;
}
diff --git a/gcc/rtlhooks.c b/gcc/rtlhooks.c
index 0ce3d1ec637..d410cd55094 100644
--- a/gcc/rtlhooks.c
+++ b/gcc/rtlhooks.c
@@ -51,7 +51,7 @@ gen_lowpart_general (machine_mode mode, rtx x)
return result;
/* Handle SUBREGs and hard REGs that were rejected by
simplify_gen_subreg. */
- else if (REG_P (x) || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || SUBREG_P (x))
{
result = gen_lowpart_common (mode, copy_to_reg (x));
gcc_assert (result != 0);
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index 5cb4a462ce9..2d5073dd79a 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -2089,7 +2089,7 @@ mark_insn_reg_birth (rtx insn, rtx reg, bool clobber_p, bool unused_p)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2148,7 +2148,7 @@ mark_reg_death (rtx reg)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2423,7 +2423,7 @@ sched_analyze_1 (class deps_desc *deps, rtx x, rtx_insn *insn)
return;
}
- while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
+ while (GET_CODE (dest) == STRICT_LOW_PART || SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT)
{
if (GET_CODE (dest) == STRICT_LOW_PART
@@ -3457,7 +3457,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
}
tmp = SET_DEST (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp))
dest_regno = REGNO (tmp);
@@ -3465,7 +3465,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
goto end_call_group;
tmp = SET_SRC (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if ((GET_CODE (tmp) == PLUS
|| GET_CODE (tmp) == MINUS)
@@ -3569,7 +3569,7 @@ call_may_noreturn_p (rtx_insn *insn)
return false;
call = get_call_rtx_from (insn);
- if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (call && SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol)
diff --git a/gcc/sched-rgn.c b/gcc/sched-rgn.c
index 59ee6a0a57c..f30b8d3f94c 100644
--- a/gcc/sched-rgn.c
+++ b/gcc/sched-rgn.c
@@ -1672,7 +1672,7 @@ check_live_1 (int src, rtx x)
if (reg == 0)
return 1;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
@@ -1755,7 +1755,7 @@ update_live_1 (int src, rtx x)
if (reg == 0)
return;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index f127ff74599..e99c9002471 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -811,7 +811,7 @@ count_occurrences_equiv (const_rtx what, const_rtx where)
return 0;
count += 1;
}
- else if (GET_CODE (x) == SUBREG
+ else if (SUBREG_P (x)
&& (!REG_P (SUBREG_REG (x))
|| REGNO (SUBREG_REG (x)) == REGNO (what)))
/* ??? Do not support substituting regs inside subregs. In that case,
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 9359a3cdb4d..2d3ec52bd93 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -247,7 +247,7 @@ avoid_constant_pool_reference (rtx x)
/* If this is a constant pool reference, we can turn it into its
constant and hope that simplifications happen. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& CONSTANT_POOL_ADDRESS_P (addr))
{
c = get_pool_constant (addr);
@@ -826,7 +826,7 @@ simplify_truncation (machine_mode mode, rtx op,
/* (truncate:A (subreg:B (truncate:C X) 0)) is
(truncate:A X). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& SCALAR_INT_MODE_P (op_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op)), &subreg_mode)
@@ -1242,7 +1242,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* A truncate of a memory is just loading the low part of the memory
if we are not changing the meaning of the address. */
- if (GET_CODE (op) == MEM
+ if (MEM_P (op)
&& !VECTOR_MODE_P (mode)
&& !MEM_VOLATILE_P (op)
&& !mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op)))
@@ -1300,7 +1300,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
is (float_truncate:SF x). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& subreg_lowpart_p (op)
&& GET_CODE (SUBREG_REG (op)) == FLOAT_TRUNCATE)
return SUBREG_REG (op);
@@ -1423,8 +1423,8 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
if (GET_CODE (op) == TRUNCATE
&& GET_MODE (XEXP (op, 0)) == mode
&& GET_CODE (XEXP (op, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (XEXP (op, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (op, 0), 1)))
return XEXP (op, 0);
/* Extending a widening multiplication should be canonicalized to
@@ -1474,7 +1474,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a sign extension of a subreg of a promoted
variable, where the promotion is sign-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_SIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1537,7 +1537,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& ! POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -1557,7 +1557,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a zero extension of a subreg of a promoted
variable, where the promotion is zero-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_UNSIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1667,7 +1667,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& POINTERS_EXTEND_UNSIGNED > 0
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -1736,7 +1736,7 @@ simplify_const_unary_operation (enum rtx_code code, machine_mode mode,
}
if (CONST_SCALAR_INT_P (op) || CONST_DOUBLE_AS_FLOAT_P (op))
return gen_const_vec_duplicate (mode, op);
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& (CONST_VECTOR_DUPLICATE_P (op)
|| CONST_VECTOR_NUNITS (op).is_constant ()))
{
@@ -1752,7 +1752,7 @@ simplify_const_unary_operation (enum rtx_code code, machine_mode mode,
}
if (VECTOR_MODE_P (mode)
- && GET_CODE (op) == CONST_VECTOR
+ && CONST_VECTOR_P (op)
&& known_eq (GET_MODE_NUNITS (mode), CONST_VECTOR_NUNITS (op)))
{
gcc_assert (GET_MODE (op) == op_mode);
@@ -2262,13 +2262,13 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
than HOST_BITS_PER_WIDE_INT. */
if ((GET_CODE (op0) == CONST
- || GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF)
+ || SYMBOL_REF_P (op0)
+ || LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, offset);
else if ((GET_CODE (op1) == CONST
- || GET_CODE (op1) == SYMBOL_REF
- || GET_CODE (op1) == LABEL_REF)
+ || SYMBOL_REF_P (op1)
+ || LABEL_REF_P (op1))
&& poly_int_rtx_p (op0, &offset))
return plus_constant (mode, op1, offset);
@@ -2541,8 +2541,8 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
}
if ((GET_CODE (op0) == CONST
- || GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF)
+ || SYMBOL_REF_P (op0)
+ || LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, trunc_int_for_mode (-offset, mode));
@@ -2791,7 +2791,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
mode size to (rotate A CX). */
if (GET_CODE (op1) == ASHIFT
- || GET_CODE (op1) == SUBREG)
+ || SUBREG_P (op1))
{
opleft = op1;
opright = op0;
@@ -2813,13 +2813,13 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
/* Same, but for ashift that has been "simplified" to a wider mode
by simplify_shift_const. */
- if (GET_CODE (opleft) == SUBREG
+ if (SUBREG_P (opleft)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (opleft)),
&inner_mode)
&& GET_CODE (SUBREG_REG (opleft)) == ASHIFT
&& GET_CODE (opright) == LSHIFTRT
- && GET_CODE (XEXP (opright, 0)) == SUBREG
+ && SUBREG_P (XEXP (opright, 0))
&& known_eq (SUBREG_BYTE (opleft), SUBREG_BYTE (XEXP (opright, 0)))
&& GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode)
&& rtx_equal_p (XEXP (SUBREG_REG (opleft), 0),
@@ -3642,7 +3642,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
if (vec_duplicate_p (trueop0, &elt0))
return elt0;
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP
(trueop1, 0, 0)));
@@ -3725,7 +3725,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
because they are all the same. */
return gen_vec_duplicate (mode, elt0);
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
{
unsigned n_elts = XVECLEN (trueop1, 0);
rtvec v = rtvec_alloc (n_elts);
@@ -3968,10 +3968,10 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
gcc_assert (GET_MODE_INNER (mode) == op1_mode);
unsigned int n_elts, in_n_elts;
- if ((GET_CODE (trueop0) == CONST_VECTOR
+ if ((CONST_VECTOR_P (trueop0)
|| CONST_SCALAR_INT_P (trueop0)
|| CONST_DOUBLE_AS_FLOAT_P (trueop0))
- && (GET_CODE (trueop1) == CONST_VECTOR
+ && (CONST_VECTOR_P (trueop1)
|| CONST_SCALAR_INT_P (trueop1)
|| CONST_DOUBLE_AS_FLOAT_P (trueop1))
&& GET_MODE_NUNITS (mode).is_constant (&n_elts)
@@ -4084,8 +4084,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
{
if (VECTOR_MODE_P (mode)
&& code != VEC_CONCAT
- && GET_CODE (op0) == CONST_VECTOR
- && GET_CODE (op1) == CONST_VECTOR)
+ && CONST_VECTOR_P (op0)
+ && CONST_VECTOR_P (op1))
{
bool step_ok_p;
if (CONST_VECTOR_STEPPED_P (op0)
@@ -4145,8 +4145,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
gcc_assert (n_elts >= 2);
if (n_elts == 2)
{
- gcc_assert (GET_CODE (op0) != CONST_VECTOR);
- gcc_assert (GET_CODE (op1) != CONST_VECTOR);
+ gcc_assert (!CONST_VECTOR_P (op0));
+ gcc_assert (!CONST_VECTOR_P (op1));
RTVEC_ELT (v, 0) = op0;
RTVEC_ELT (v, 1) = op1;
@@ -4157,8 +4157,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
unsigned op1_n_elts = GET_MODE_NUNITS (GET_MODE (op1)).to_constant ();
unsigned i;
- gcc_assert (GET_CODE (op0) == CONST_VECTOR);
- gcc_assert (GET_CODE (op1) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (op0));
+ gcc_assert (CONST_VECTOR_P (op1));
gcc_assert (op0_n_elts + op1_n_elts == n_elts);
for (i = 0; i < op0_n_elts; ++i)
@@ -5833,7 +5833,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
if (VECTOR_MODE_P (GET_MODE (op1))
&& GET_CODE (op0) == NE
&& GET_CODE (XEXP (op0, 0)) == NOT
- && GET_CODE (XEXP (op0, 1)) == CONST_VECTOR)
+ && CONST_VECTOR_P (XEXP (op0, 1)))
{
rtx cv = XEXP (op0, 1);
int nunits;
@@ -5937,8 +5937,8 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
rtx trueop0 = avoid_constant_pool_reference (op0);
rtx trueop1 = avoid_constant_pool_reference (op1);
- if (GET_CODE (trueop0) == CONST_VECTOR
- && GET_CODE (trueop1) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0)
+ && CONST_VECTOR_P (trueop1))
{
rtvec v = rtvec_alloc (n_elts);
unsigned int i;
@@ -6001,7 +6001,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat (X) (B)) if N == 1 or
(vec_concat (A) (X)) if N == 2. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == CONST_VECTOR
+ && CONST_VECTOR_P (op1)
&& known_eq (CONST_VECTOR_NUNITS (op1), 2)
&& known_eq (GET_MODE_NUNITS (GET_MODE (op0)), 2)
&& IN_RANGE (sel, 1, 2))
@@ -6046,7 +6046,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
Only applies for vectors of two elements. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == SUBREG
+ && SUBREG_P (op1)
&& GET_MODE (op1) == GET_MODE (op0)
&& GET_MODE (SUBREG_REG (op1)) == GET_MODE (XEXP (op0, 0))
&& paradoxical_subreg_p (op1)
@@ -6070,7 +6070,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat:outer x:inner y:inner) if N == 1,
or (vec_concat:outer y:inner x:inner) if N == 2. */
if (GET_CODE (op1) == VEC_DUPLICATE
- && GET_CODE (op0) == SUBREG
+ && SUBREG_P (op0)
&& GET_MODE (op0) == GET_MODE (op1)
&& GET_MODE (SUBREG_REG (op0)) == GET_MODE (XEXP (op1, 0))
&& paradoxical_subreg_p (op0)
@@ -6177,7 +6177,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
/* Unpack the value. */
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
num_elem = CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode));
elem_bitsize = GET_MODE_UNIT_BITSIZE (innermode);
@@ -6195,7 +6195,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
for (elem = 0; elem < num_elem; elem++)
{
unsigned char * vp;
- rtx el = (GET_CODE (op) == CONST_VECTOR
+ rtx el = (CONST_VECTOR_P (op)
? CONST_VECTOR_ELT (op, first_elem + elem)
: op);
@@ -6511,7 +6511,7 @@ simplify_subreg (machine_mode outermode, rtx op,
if (CONST_SCALAR_INT_P (op)
|| CONST_DOUBLE_AS_FLOAT_P (op)
|| CONST_FIXED_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
{
/* simplify_immed_subreg deconstructs OP into bytes and constructs
the result from bytes, so it only works if the sizes of the modes
@@ -6528,7 +6528,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Handle constant-sized outer modes and variable-sized inner modes. */
unsigned HOST_WIDE_INT first_elem;
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& is_a <fixed_size_mode> (outermode, &fs_outermode)
&& constant_multiple_p (byte, GET_MODE_UNIT_SIZE (innermode),
&first_elem))
@@ -6541,7 +6541,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Changing mode twice with SUBREG => just change it once,
or not at all if changing back op starting mode. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
@@ -6761,7 +6761,7 @@ simplify_gen_subreg (machine_mode outermode, rtx op,
if (newx)
return newx;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
|| GET_CODE (op) == CONCAT
|| GET_MODE (op) == VOIDmode)
return NULL_RTX;
diff --git a/gcc/symtab.c b/gcc/symtab.c
index 63e2820eb93..dbd2221db27 100644
--- a/gcc/symtab.c
+++ b/gcc/symtab.c
@@ -1377,7 +1377,7 @@ symtab_node::make_decl_local (void)
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);
@@ -1432,7 +1432,7 @@ symtab_node::copy_visibility_from (symtab_node *n)
return;
rtx symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 8004951d2e8..8432a98bd47 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -150,8 +150,8 @@ gen_addr_rtx (machine_mode address_mode,
if (offset_p)
*offset_p = &XEXP (act_elem, 1);
- if (GET_CODE (symbol) == SYMBOL_REF
- || GET_CODE (symbol) == LABEL_REF
+ if (SYMBOL_REF_P (symbol)
+ || LABEL_REF_P (symbol)
|| GET_CODE (symbol) == CONST)
act_elem = gen_rtx_CONST (address_mode, act_elem);
}
@@ -264,13 +264,13 @@ addr_for_mem_ref (struct mem_address *addr, addr_space_t as,
into OFF and clear BSE. Otherwise we may later try to pull a mode from
BSE to generate a REG, which won't work with constants because they
are modeless. */
- if (bse && GET_CODE (bse) == CONST_INT)
+ if (bse && CONST_INT_P (bse))
{
if (off)
off = simplify_gen_binary (PLUS, pointer_mode, bse, off);
else
off = bse;
- gcc_assert (GET_CODE (off) == CONST_INT);
+ gcc_assert (CONST_INT_P (off));
bse = NULL_RTX;
}
gen_addr_rtx (pointer_mode, sym, bse, idx, st, off, &address, NULL, NULL);
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 1f67378a867..19b0b40c2b6 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -320,7 +320,7 @@ dead_debug_global_replace_temp (struct dead_debug_global *global,
dead_debug_global_entry *entry
= dead_debug_global_find (global, *DF_REF_REAL_LOC (use));
- gcc_checking_assert (GET_CODE (entry->reg) == REG
+ gcc_checking_assert (REG_P (entry->reg)
&& REGNO (entry->reg) == uregno);
if (!entry->dtemp)
@@ -420,7 +420,7 @@ dead_debug_promote_uses (struct dead_debug_local *debug)
df_ref ref;
dead_debug_global_entry *entry;
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER)
{
headp = &head->next;
@@ -691,7 +691,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
cleanup_auto_inc_dec (src, VOIDmode),
GET_MODE (dest));
}
- else if (GET_CODE (dest) == SUBREG)
+ else if (SUBREG_P (dest))
{
/* We should be setting REG here. Lose. */
if (REGNO (SUBREG_REG (dest)) != REGNO (reg))
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 67f25c1c795..d978e62cf1a 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -975,7 +975,7 @@ use_narrower_mode_test (rtx x, const_rtx subreg)
< GET_MODE_PRECISION (as_a <scalar_int_mode> (op1_mode)))
{
poly_uint64 byte = subreg_lowpart_offset (mode, op1_mode);
- if (GET_CODE (op1) == SUBREG || GET_CODE (op1) == CONCAT)
+ if (SUBREG_P (op1) || GET_CODE (op1) == CONCAT)
{
if (!simplify_subreg (mode, op1, op1_mode, byte))
return false;
@@ -1142,7 +1142,7 @@ adjust_mems (rtx loc, const_rtx old_rtx, void *data)
tem = gen_rtx_raw_SUBREG (GET_MODE (loc), addr, SUBREG_BYTE (loc));
finish_subreg:
if (MAY_HAVE_DEBUG_BIND_INSNS
- && GET_CODE (tem) == SUBREG
+ && SUBREG_P (tem)
&& (GET_CODE (SUBREG_REG (tem)) == PLUS
|| GET_CODE (SUBREG_REG (tem)) == MINUS
|| GET_CODE (SUBREG_REG (tem)) == MULT
@@ -2043,7 +2043,7 @@ vt_get_canonicalize_base (rtx loc)
{
while ((GET_CODE (loc) == PLUS
|| GET_CODE (loc) == AND)
- && GET_CODE (XEXP (loc, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (loc, 1))
&& (GET_CODE (loc) != AND
|| negative_power_of_two_p (INTVAL (XEXP (loc, 1)))))
loc = XEXP (loc, 0);
@@ -2195,7 +2195,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
canonicalize the base and we're done. We'll normally have
only one stack alignment anyway. */
if (GET_CODE (loc) == AND
- && GET_CODE (XEXP (loc, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (loc, 1))
&& negative_power_of_two_p (INTVAL (XEXP (loc, 1))))
{
x = vt_canonicalize_addr (set, XEXP (loc, 0));
@@ -2250,7 +2250,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
static inline bool
vt_canon_true_dep (dataflow_set *set, rtx mloc, rtx maddr, rtx loc)
{
- if (GET_CODE (loc) != MEM)
+ if (!MEM_P (loc))
return false;
rtx addr = vt_canonicalize_addr (set, XEXP (loc, 0));
@@ -2350,7 +2350,7 @@ clobber_overlapping_mems (dataflow_set *set, rtx loc)
{
struct overlapping_mems coms;
- gcc_checking_assert (GET_CODE (loc) == MEM);
+ gcc_checking_assert (MEM_P (loc));
coms.set = set;
coms.loc = canon_rtx (loc);
@@ -2479,7 +2479,7 @@ val_bind (dataflow_set *set, rtx val, rtx loc, bool modified)
dynamic tables. ??? We should test this before emitting the
micro-op in the first place. */
while (l)
- if (GET_CODE (l->loc) == MEM && XEXP (l->loc, 0) == XEXP (loc, 0))
+ if (MEM_P (l->loc) && XEXP (l->loc, 0) == XEXP (loc, 0))
break;
else
l = l->next;
@@ -2609,10 +2609,10 @@ val_reset (dataflow_set *set, decl_or_value dv)
{
if (node->loc == cval)
continue;
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
var_reg_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
- else if (GET_CODE (node->loc) == MEM)
+ else if (MEM_P (node->loc))
var_mem_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
else
@@ -3814,7 +3814,7 @@ canonicalize_values_star (variable **slot, dataflow_set *set)
parent. */
clobber_variable_part (set, cval, ndv, 0, NULL);
}
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *list = set->regs[REGNO (node->loc)], **listp;
@@ -4072,7 +4072,7 @@ variable_merge_over_cur (variable *s1var, struct dfset_merge *dsm)
{
location_chain **nextp = &node->next;
- if (GET_CODE (node->loc) == REG)
+ if (REG_P (node->loc))
{
attrs *list;
@@ -4444,7 +4444,7 @@ variable_post_merge_new_vals (variable **slot, dfset_post_merge *dfpm)
{
if (GET_CODE (node->loc) == VALUE)
gcc_assert (!VALUE_RECURSED_INTO (node->loc));
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *att, **attp, **curp = NULL;
@@ -4735,7 +4735,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
{
/* We want to remove dying MEMs that don't refer to DECL. */
- if (GET_CODE (loc->loc) == MEM
+ if (MEM_P (loc->loc)
&& (MEM_EXPR (loc->loc) != decl
|| int_mem_offset (loc->loc) != 0)
&& mem_dies_at_call (loc->loc))
@@ -4779,7 +4779,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
}
}
- if (GET_CODE (loc->loc) != MEM
+ if (!MEM_P (loc->loc)
|| (MEM_EXPR (loc->loc) == decl
&& int_mem_offset (loc->loc) == 0)
|| !mem_dies_at_call (loc->loc))
@@ -4839,7 +4839,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
if (shared_var_p (var, set->vars))
{
for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
- if (GET_CODE (loc->loc) == MEM
+ if (MEM_P (loc->loc)
&& mem_dies_at_call (loc->loc))
break;
@@ -4859,7 +4859,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
for (locp = &var->var_part[0].loc_chain, loc = *locp;
loc; loc = *locp)
{
- if (GET_CODE (loc->loc) != MEM
+ if (!MEM_P (loc->loc)
|| !mem_dies_at_call (loc->loc))
{
locp = &loc->next;
@@ -5932,12 +5932,12 @@ reverse_op (rtx val, const_rtx expr, rtx_insn *insn)
if (GET_MODE (v->val_rtx) != GET_MODE (val))
return;
arg = XEXP (src, 1);
- if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
+ if (!CONST_INT_P (arg) && !SYMBOL_REF_P (arg))
{
arg = cselib_expand_value_rtx (arg, scratch_regs, 5);
if (arg == NULL_RTX)
return;
- if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
+ if (!CONST_INT_P (arg) && !SYMBOL_REF_P (arg))
return;
}
ret = simplify_gen_binary (code, GET_MODE (val), val, arg);
@@ -6254,7 +6254,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
call = get_call_rtx_from (insn);
if (call)
{
- if (GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol))
@@ -6470,12 +6470,12 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
/* Try harder, when passing address of a constant
pool integer it can be easily read back. */
item = XEXP (item, 1);
- if (GET_CODE (item) == SUBREG)
+ if (SUBREG_P (item))
item = SUBREG_REG (item);
gcc_assert (GET_CODE (item) == VALUE);
val = CSELIB_VAL_PTR (item);
for (l = val->locs; l; l = l->next)
- if (GET_CODE (l->loc) == SYMBOL_REF
+ if (SYMBOL_REF_P (l->loc)
&& TREE_CONSTANT_POOL_ADDRESS_P (l->loc)
&& SYMBOL_REF_DECL (l->loc)
&& DECL_INITIAL (SYMBOL_REF_DECL (l->loc)))
@@ -6536,7 +6536,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
if (x)
{
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
/* Don't record anything. */;
else if (CONSTANT_P (x))
{
@@ -6832,10 +6832,10 @@ compute_bb_dataflow (basic_block bb)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
- else if (GET_CODE (uloc) == MEM)
+ else if (MEM_P (uloc))
var_mem_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
}
@@ -6885,7 +6885,7 @@ compute_bb_dataflow (basic_block bb)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (out, val, SET_SRC (uloc), insn);
}
@@ -6943,7 +6943,7 @@ compute_bb_dataflow (basic_block bb)
var_regno_delete (out, REGNO (uloc));
else if (MEM_P (uloc))
{
- gcc_checking_assert (GET_CODE (vloc) == MEM);
+ gcc_checking_assert (MEM_P (vloc));
gcc_checking_assert (dstv == vloc);
if (dstv != vloc)
clobber_overlapping_mems (out, vloc);
@@ -8726,7 +8726,7 @@ emit_note_insn_var_location (variable **varp, emit_note_data *data)
continue;
offset = VAR_PART_OFFSET (var, i);
loc2 = var->var_part[i].cur_loc;
- if (loc2 && GET_CODE (loc2) == MEM
+ if (loc2 && MEM_P (loc2)
&& GET_CODE (XEXP (loc2, 0)) == VALUE)
{
rtx depval = XEXP (loc2, 0);
@@ -8998,7 +8998,7 @@ notify_dependents_of_changed_value (rtx val, variable_table_type *htab,
{
rtx loc = ivar->var_part[i].cur_loc;
- if (loc && GET_CODE (loc) == MEM
+ if (loc && MEM_P (loc)
&& XEXP (loc, 0) == val)
{
variable_was_changed (ivar, NULL);
@@ -9330,10 +9330,10 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
- else if (GET_CODE (uloc) == MEM)
+ else if (MEM_P (uloc))
var_mem_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
}
@@ -9385,7 +9385,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (set, val, SET_SRC (uloc), insn);
}
@@ -9437,7 +9437,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
var_regno_delete (set, REGNO (uloc));
else if (MEM_P (uloc))
{
- gcc_checking_assert (GET_CODE (vloc) == MEM);
+ gcc_checking_assert (MEM_P (vloc));
gcc_checking_assert (vloc == dstv);
if (vloc != dstv)
clobber_overlapping_mems (set, vloc);
diff --git a/gcc/varasm.c b/gcc/varasm.c
index e886cdc71b8..036d8e455f2 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -1372,7 +1372,7 @@ make_decl_rtl (tree decl)
/* If the symbol has a SYMBOL_REF_BLOCK field, update it based
on the new decl information. */
if (MEM_P (x)
- && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (x, 0))
&& SYMBOL_REF_HAS_BLOCK_INFO_P (XEXP (x, 0)))
change_symbol_block (XEXP (x, 0), get_block_for_decl (decl));
@@ -1720,7 +1720,7 @@ get_fnname_from_decl (tree decl)
rtx x = DECL_RTL (decl);
gcc_assert (MEM_P (x));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
return XSTR (x, 0);
}
@@ -2247,7 +2247,7 @@ assemble_variable (tree decl, int top_level ATTRIBUTE_UNUSED,
}
gcc_assert (MEM_P (decl_rtl));
- gcc_assert (GET_CODE (XEXP (decl_rtl, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (decl_rtl, 0)));
symbol = XEXP (decl_rtl, 0);
/* If this symbol belongs to the tree constant pool, output the constant
@@ -2433,7 +2433,7 @@ assemble_external_real (tree decl)
{
rtx rtl = DECL_RTL (decl);
- if (MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
+ if (MEM_P (rtl) && SYMBOL_REF_P (XEXP (rtl, 0))
&& !SYMBOL_REF_USED (XEXP (rtl, 0))
&& !incorporeal_function_p (decl))
{
@@ -2813,7 +2813,7 @@ assemble_integer (rtx x, unsigned int size, unsigned int align, int force)
subsize = size > UNITS_PER_WORD? UNITS_PER_WORD : 1;
subalign = MIN (align, subsize * BITS_PER_UNIT);
- if (GET_CODE (x) == CONST_FIXED)
+ if (CONST_FIXED_P (x))
mclass = GET_MODE_CLASS (GET_MODE (x));
else
mclass = MODE_INT;
@@ -3900,7 +3900,7 @@ force_const_mem (machine_mode in_mode, rtx x)
/* If we're dropping a label to the constant pool, make sure we
don't delete it. */
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
LABEL_PRESERVE_P (XEXP (x, 0)) = 1;
return copy_rtx (def);
@@ -3973,7 +3973,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align)
case MODE_VECTOR_BOOL:
{
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
/* Pick the smallest integer mode that contains at least one
whole element. Often this is byte_mode and contains more
@@ -4008,7 +4008,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align)
scalar_mode submode = GET_MODE_INNER (mode);
unsigned int subalign = MIN (align, GET_MODE_BITSIZE (submode));
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
units = GET_MODE_NUNITS (mode);
for (i = 0; i < units; i++)
@@ -4049,7 +4049,7 @@ output_constant_pool_1 (class constant_descriptor_rtx *desc,
{
case CONST:
if (GET_CODE (XEXP (tmp, 0)) != PLUS
- || GET_CODE (XEXP (XEXP (tmp, 0), 0)) != LABEL_REF)
+ || !LABEL_REF_P (XEXP (XEXP (tmp, 0), 0)))
break;
tmp = XEXP (XEXP (tmp, 0), 0);
/* FALLTHRU */
@@ -4130,7 +4130,7 @@ mark_constants_in_pattern (rtx insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (CONSTANT_POOL_ADDRESS_P (x))
{
@@ -5568,7 +5568,7 @@ mark_weak (tree decl)
if (DECL_RTL_SET_P (decl)
&& MEM_P (DECL_RTL (decl))
&& XEXP (DECL_RTL (decl), 0)
- && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (DECL_RTL (decl), 0)))
SYMBOL_REF_WEAK (XEXP (DECL_RTL (decl), 0)) = 1;
}
@@ -6968,7 +6968,7 @@ default_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
if (!MEM_P (rtl))
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
flags = SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_HAS_BLOCK_INFO;
@@ -7494,7 +7494,7 @@ place_block_symbol (rtx symbol)
rtx target = DECL_RTL (snode->ultimate_alias_target ()->decl);
gcc_assert (MEM_P (target)
- && GET_CODE (XEXP (target, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (target, 0))
&& SYMBOL_REF_HAS_BLOCK_INFO_P (XEXP (target, 0)));
target = XEXP (target, 0);
place_block_symbol (target);
diff --git a/gcc/xcoffout.h b/gcc/xcoffout.h
index d8a031268ff..0ab9e5d09c2 100644
--- a/gcc/xcoffout.h
+++ b/gcc/xcoffout.h
@@ -78,7 +78,7 @@ along with GCC; see the file COPYING3. If not see
\
/* If we are writing a function name, we must ensure that \
there is no storage-class suffix on the name. */ \
- if (CODE == N_FUN && GET_CODE (ADDR) == SYMBOL_REF) \
+ if (CODE == N_FUN && SYMBOL_REF_P (ADDR)) \
{ \
const char *_p = XSTR (ADDR, 0); \
if (*_p == '*') \
--
2.21.0
[-- Attachment #4: touchup --]
[-- Type: text/x-diff, Size: 2073 bytes --]
From 3ad93997b70d9b5fc575cf35f6e30852270a82f5 Mon Sep 17 00:00:00 2001
From: Arvind Sankar <nivedita@alum.mit.edu>
Date: Fri, 2 Aug 2019 15:00:08 -0400
Subject: [PATCH 3/3] Use rtx_code predicates instead of GET_CODE
---
gcc/combine-stack-adj.c | 3 +--
gcc/dwarf2out.c | 3 +--
gcc/rtlanal.c | 3 +--
3 files changed, 3 insertions(+), 6 deletions(-)
diff --git a/gcc/combine-stack-adj.c b/gcc/combine-stack-adj.c
index 3638a1b10ee..f98a0d54c98 100644
--- a/gcc/combine-stack-adj.c
+++ b/gcc/combine-stack-adj.c
@@ -634,8 +634,7 @@ combine_stack_adjustments_for_block (basic_block bb)
&& GET_CODE (XEXP (XEXP (dest, 0), 1)) == PLUS
&& XEXP (XEXP (XEXP (dest, 0), 1), 0)
== stack_pointer_rtx
- && GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
- == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (XEXP (dest, 0), 1), 1))
&& INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1))
== -last_sp_adjust))
&& XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index b2b4f6d82b2..ea38963d177 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -23747,8 +23747,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die)
if (single_element_loc_list_p (loc)
&& loc->expr->dw_loc_opc == DW_OP_addr
&& loc->expr->dw_loc_next == NULL
- && GET_CODE (loc->expr->dw_loc_oprnd1.v.val_addr)
- == SYMBOL_REF)
+ && SYMBOL_REF_P (loc->expr->dw_loc_oprnd1.v.val_addr))
{
rtx x = loc->expr->dw_loc_oprnd1.v.val_addr;
loc->expr->dw_loc_oprnd1.v.val_addr
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 3ce8c1bb03e..adb0929a1aa 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -3347,8 +3347,7 @@ computed_jump_p (const rtx_insn *insn)
for (i = len - 1; i >= 0; i--)
if (GET_CODE (XVECEXP (pat, 0, i)) == USE
- && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))
- == LABEL_REF))
+ && LABEL_REF_P (XEXP (XVECEXP (pat, 0, i), 0)))
{
has_use_labelref = 1;
break;
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-02 19:22 ` Arvind Sankar
@ 2019-08-05 17:18 ` Arvind Sankar
[not found] ` <20190805170908.GA1044536@rani.riverdale.lan>
1 sibling, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-05 17:18 UTC (permalink / raw)
To: Arvind Sankar; +Cc: Segher Boessenkool, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 9157 bytes --]
Updated patchset now including target subdirs. I have tested all of them
by building cross-compilers and comparing object files (except for
tilegx which doesn't appear to build any more in trunk).
Patches are attached as tar.gz as its too big otherwise.
gcc/ChangeLog:
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
* rtl.h: Add CONST_VECTOR_P and CONST_STRING_P.
* gcc/alias.c, gcc/asan.c, gcc/bb-reorder.c, gcc/bt-load.c: Use predicate macros for rtx_code comparisons.
* gcc/builtins.c, gcc/caller-save.c, gcc/calls.c, gcc/cfgbuild.c: Likewise.
* gcc/cfgcleanup.c, gcc/cfgexpand.c, gcc/cfgrtl.c, gcc/combine-stack-adj.c: Likewise.
* gcc/combine.c, gcc/common.md, gcc/cprop.c, gcc/cse.c, gcc/cselib.c: Likewise.
* gcc/dbxout.c, gcc/defaults.h, gcc/df-core.c, gcc/df-problems.c, gcc/df-scan.c: Likewise.
* gcc/df.h, gcc/dojump.c, gcc/dse.c, gcc/dwarf2asm.c, gcc/dwarf2out.c: Likewise.
* gcc/emit-rtl.c, gcc/explow.c, gcc/expmed.c, gcc/expr.c, gcc/final.c: Likewise.
* gcc/function.c, gcc/fwprop.c, gcc/gcse-common.c, gcc/gcse.c, gcc/genattrtab.c: Likewise.
* gcc/genpreds.c, gcc/genrecog.c, gcc/gensupport.c, gcc/ifcvt.c: Likewise.
* gcc/internal-fn.c, gcc/ira-build.c, gcc/ira-conflicts.c, gcc/ira-costs.c: Likewise.
* gcc/ira-emit.c, gcc/ira-lives.c, gcc/ira.c, gcc/jump.c, gcc/loop-doloop.c: Likewise.
* gcc/loop-invariant.c, gcc/loop-iv.c, gcc/loop-unroll.c, gcc/lower-subreg.c: Likewise.
* gcc/lra-constraints.c, gcc/lra-eliminations.c, gcc/lra.c, gcc/mode-switching.c: Likewise.
* gcc/modulo-sched.c, gcc/optabs.c, gcc/postreload-gcse.c, gcc/postreload.c: Likewise.
* gcc/print-rtl.c, gcc/read-rtl-function.c, gcc/read-rtl.c, gcc/recog.c: Likewise.
* gcc/ree.c, gcc/reg-stack.c, gcc/regcprop.c, gcc/reginfo.c, gcc/regrename.c: Likewise.
* gcc/reload.c, gcc/reload1.c, gcc/reorg.c, gcc/resource.c, gcc/rtl.c: Likewise.
* gcc/rtlanal.c, gcc/rtlhooks.c, gcc/sched-deps.c, gcc/sched-rgn.c: Likewise.
* gcc/sel-sched.c, gcc/simplify-rtx.c, gcc/symtab.c, gcc/tree-ssa-address.c: Likewise.
* gcc/valtrack.c, gcc/var-tracking.c, gcc/varasm.c, gcc/xcoffout.h: Likewise.
* gcc/config/aarch64/aarch64-simd.md, gcc/config/aarch64/aarch64-sve.md: Likewise.
* gcc/config/aarch64/aarch64.c, gcc/config/aarch64/aarch64.md: Likewise.
* gcc/config/aarch64/predicates.md: Likewise.
* gcc/config/alpha/alpha.c, gcc/config/alpha/alpha.md, gcc/config/alpha/predicates.md,
* gcc/config/arc/arc.c, gcc/config/arc/arc.h, gcc/config/arc/arc.md: Likewise.
* gcc/config/arc/fpx.md, gcc/config/arc/predicates.md, gcc/config/arc/simdext.md,
* gcc/config/arm/aarch-common.c, gcc/config/arm/arm.c, gcc/config/arm/arm.h: Likewise.
* gcc/config/arm/arm.md, gcc/config/arm/predicates.md, gcc/config/arm/thumb1.md,
* gcc/config/avr/avr.c: Likewise.
* gcc/config/bfin/bfin.c, gcc/config/bfin/bfin.h, gcc/config/bfin/bfin.md: Likewise.
* gcc/config/bfin/predicates.md: Likewise.
* gcc/config/c6x/c6x.c, gcc/config/c6x/c6x.h, gcc/config/c6x/c6x.md: Likewise.
* gcc/config/c6x/predicates.md: Likewise.
* gcc/config/cr16/cr16.c, gcc/config/cr16/cr16.h, gcc/config/cr16/cr16.md: Likewise.
* gcc/config/cr16/predicates.md: Likewise.
* gcc/config/cris/cris.c, gcc/config/cris/cris.h, gcc/config/cris/cris.md,
* gcc/config/csky/constraints.md, gcc/config/csky/csky.c, gcc/config/csky/csky.h: Likewise.
* gcc/config/csky/csky.md, gcc/config/csky/predicates.md: Likewise.
* gcc/config/darwin.c, gcc/config/darwin.h: Likewise.
* gcc/config/epiphany/epiphany.c, gcc/config/epiphany/epiphany.h: Likewise.
* gcc/config/epiphany/epiphany.md, gcc/config/epiphany/predicates.md: Likewise.
* gcc/config/fr30/fr30.c, gcc/config/fr30/fr30.h, gcc/config/fr30/fr30.md: Likewise.
* gcc/config/fr30/predicates.md: Likewise.
* gcc/config/frv/frv.c, gcc/config/frv/frv.h, gcc/config/frv/frv.md: Likewise.
* gcc/config/frv/predicates.md,
* gcc/config/ft32/constraints.md, gcc/config/ft32/ft32.c: Likewise.
* gcc/config/ft32/ft32.md, gcc/config/ft32/predicates.md,
* gcc/config/gcn/gcn-valu.md, gcc/config/gcn/gcn.c,
* gcc/config/gcn/gcn.md, gcc/config/gcn/predicates.md,
* gcc/config/h8300/h8300.c, gcc/config/h8300/h8300.h,
* gcc/config/h8300/h8300.md, gcc/config/h8300/predicates.md,
* gcc/config/i386/i386-expand.c, gcc/config/i386/i386-features.c: Likewise.
* gcc/config/i386/i386.c, gcc/config/i386/i386.h, gcc/config/i386/i386.md: Likewise.
* gcc/config/i386/predicates.md, gcc/config/i386/sse.md, gcc/config/i386/winnt.c: Likewise.
* gcc/config/ia64/ia64.c, gcc/config/ia64/ia64.md, gcc/config/ia64/predicates.md: Likewise.
* gcc/config/ia64/vect.md, gcc/config/iq2000/iq2000.c: Likewise.
* gcc/config/iq2000/iq2000.h, gcc/config/iq2000/iq2000.md: Likewise.
* gcc/config/iq2000/predicates.md: Likewise.
* gcc/config/lm32/lm32.c, gcc/config/lm32/lm32.h, gcc/config/lm32/lm32.md,
* gcc/config/m32c/addsub.md, gcc/config/m32c/m32c.c,
* gcc/config/m32c/muldiv.md, gcc/config/m32c/predicates.md,
* gcc/config/m32r/constraints.md, gcc/config/m32r/m32r.c, gcc/config/m32r/m32r.h: Likewise.
* gcc/config/m32r/m32r.md, gcc/config/m32r/predicates.md,
* gcc/config/m68k/constraints.md, gcc/config/m68k/m68k.c, gcc/config/m68k/m68k.h: Likewise.
* gcc/config/m68k/m68k.md, gcc/config/m68k/predicates.md,
* gcc/config/mcore/constraints.md, gcc/config/mcore/mcore.c: Likewise.
* gcc/config/mcore/mcore.h, gcc/config/mcore/mcore.md: Likewise.
* gcc/config/mcore/predicates.md,
* gcc/config/microblaze/constraints.md, gcc/config/microblaze/microblaze.c: Likewise.
* gcc/config/microblaze/microblaze.h, gcc/config/microblaze/microblaze.md: Likewise.
* gcc/config/microblaze/predicates.md,
* gcc/config/mips/mips.c, gcc/config/mips/mips.md, gcc/config/mips/predicates.md: Likewise.
* gcc/config/mmix/mmix.c, gcc/config/mmix/mmix.md, gcc/config/mmix/predicates.md,
* gcc/config/mn10300/constraints.md, gcc/config/mn10300/mn10300.c: Likewise.
* gcc/config/mn10300/mn10300.h, gcc/config/mn10300/mn10300.md: Likewise.
* gcc/config/mn10300/predicates.md,
* gcc/config/moxie/constraints.md, gcc/config/moxie/moxie.c,
* gcc/config/moxie/moxie.md, gcc/config/moxie/predicates.md,
* gcc/config/msp430/msp430.c, gcc/config/msp430/msp430.md,
* gcc/config/nds32/constraints.md, gcc/config/nds32/nds32-cost.c: Likewise.
* gcc/config/nds32/nds32-dspext.md, gcc/config/nds32/nds32-fp-as-gp.c: Likewise.
* gcc/config/nds32/nds32-intrinsic.c, gcc/config/nds32/nds32-md-auxiliary.c: Likewise.
* gcc/config/nds32/nds32-memory-manipulation.c: Likewise.
* gcc/config/nds32/nds32-multiple.md: Likewise.
* gcc/config/nds32/nds32-pipelines-auxiliary.c: Likewise.
* gcc/config/nds32/nds32-predicates.c, gcc/config/nds32/nds32-relax-opt.c: Likewise.
* gcc/config/nds32/nds32-utils.c, gcc/config/nds32/nds32.c: Likewise.
* gcc/config/nds32/nds32.h, gcc/config/nds32/nds32.md: Likewise.
* gcc/config/nds32/predicates.md: Likewise.
* gcc/config/nios2/nios2.c, gcc/config/nios2/predicates.md: Likewise.
* gcc/config/nvptx/nvptx.c, gcc/config/nvptx/nvptx.md: Likewise.
* gcc/config/or1k/or1k.c,
* gcc/config/pa/pa.c, gcc/config/pa/pa.h,
* gcc/config/pa/pa.md, gcc/config/pa/predicates.md,
* gcc/config/pdp11/pdp11.c, gcc/config/pdp11/pdp11.md,
* gcc/config/pru/predicates.md, gcc/config/pru/pru.c, gcc/config/pru/pru.md: Likewise.
* gcc/config/riscv/constraints.md, gcc/config/riscv/riscv.c, gcc/config/riscv/riscv.md,
* gcc/config/rl78/constraints.md, gcc/config/rl78/rl78-expand.md: Likewise.
* gcc/config/rl78/rl78.c, gcc/config/rl78/rl78.h: Likewise.
* gcc/config/rs6000/freebsd64.h, gcc/config/rs6000/linux64.h: Likewise.
* gcc/config/rs6000/predicates.md, gcc/config/rs6000/rs6000-p8swap.c: Likewise.
* gcc/config/rs6000/rs6000.c, gcc/config/rs6000/rs6000.h: Likewise.
* gcc/config/rs6000/rtems.h, gcc/config/rs6000/sysv4.h: Likewise.
* gcc/config/rs6000/xcoff.h: Likewise.
* gcc/config/rx/constraints.md, gcc/config/rx/rx.c, gcc/config/rx/rx.h: Likewise.
* gcc/config/rx/rx.md: Likewise.
* gcc/config/s390/predicates.md, gcc/config/s390/s390.c: Likewise.
* gcc/config/s390/s390.h, gcc/config/s390/s390.md: Likewise.
* gcc/config/sh/predicates.md, gcc/config/sh/sh.c: Likewise.
* gcc/config/sh/sh.h, gcc/config/sh/sh.md: Likewise.
* gcc/config/sparc/predicates.md, gcc/config/sparc/sparc.c, gcc/config/sparc/sparc.md,
* gcc/config/spu/constraints.md, gcc/config/spu/predicates.md: Likewise.
* gcc/config/spu/spu-builtins.md, gcc/config/spu/spu.c: Likewise.
* gcc/config/spu/spu.h, gcc/config/spu/spu.md,
* gcc/config/stormy16/predicates.md, gcc/config/stormy16/stormy16.c,
* gcc/config/tilegx/predicates.md,
* gcc/config/tilegx/tilegx.c, gcc/config/tilegx/tilegx.md,
* gcc/config/tilepro/predicates.md, gcc/config/tilepro/tilepro.c,
* gcc/config/v850/constraints.md, gcc/config/v850/predicates.md: Likewise.
* gcc/config/v850/v850.c, gcc/config/v850/v850.md: Likewise.
* gcc/config/vax/predicates.md, gcc/config/vax/vax.c, gcc/config/vax/vax.md,
* gcc/config/visium/predicates.md,
* gcc/config/visium/visium.c, gcc/config/visium/visium.md,
* gcc/config/xtensa/predicates.md, gcc/config/xtensa/xtensa.c: Likewise.
* gcc/config/xtensa/xtensa.h, gcc/config/xtensa/xtensa.md: Likewise.
[-- Attachment #2: rtl-predicate.tar.gz --]
[-- Type: application/octet-stream, Size: 263158 bytes --]
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
[not found] ` <20190805170908.GA1044536@rani.riverdale.lan>
@ 2019-08-05 17:49 ` Segher Boessenkool
2019-08-05 18:14 ` Arvind Sankar
0 siblings, 1 reply; 33+ messages in thread
From: Segher Boessenkool @ 2019-08-05 17:49 UTC (permalink / raw)
To: Arvind Sankar; +Cc: gcc-patches
Hi Arvind,
First: do you have a copyright assignment? See
https://gcc.gnu.org/contribute.html
for instructions.
This is easier to review, and even to commit as obvious, if you did a
patch per macro, certainly for the new macros; and, put the script in
contrib/, and then say with every patch that is just the output of the
script that that is the case.
Some (mostly changelog) comments:
On Mon, Aug 05, 2019 at 01:09:10PM -0400, Arvind Sankar wrote:
> * gcc/alias.c, gcc/asan.c, gcc/bb-reorder.c, gcc/bt-load.c: Use predicate macros for rtx_code comparisons.
Many of your changelog lines are much too long. Don't use more than 80
columns (including the leading tab, which is 8 columns).
Please mention the exact macros you now use, and/or the actual rtx codes.
Filenames are relative to the directory containing the changelog file
itself, so you shouldn't have the gcc/ in those filenames.
> * gcc/config/microblaze/predicates.md,
There shouldn't be trailing spaces.
> * gcc/config/rx/constraints.md, gcc/config/rx/rx.c, gcc/config/rx/rx.h: Likewise.
And you normally have a separate entry for every file.
> -/* Predicate yielding true iff X is an rtx for a double-int. */
> +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> #define CONST_DOUBLE_AS_FLOAT_P(X) \
> (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
Is const_double really only used for floating point these days?
Segher
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-05 17:49 ` Segher Boessenkool
@ 2019-08-05 18:14 ` Arvind Sankar
2019-08-05 18:29 ` Segher Boessenkool
2019-08-06 3:11 ` Arvind Sankar
0 siblings, 2 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-05 18:14 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Arvind Sankar, gcc-patches
On Mon, Aug 05, 2019 at 12:48:46PM -0500, Segher Boessenkool wrote:
> Hi Arvind,
>
> First: do you have a copyright assignment? See
> https://gcc.gnu.org/contribute.html
> for instructions.
Nope, is this really substantial enough to warrant one?
>
> This is easier to review, and even to commit as obvious, if you did a
> patch per macro, certainly for the new macros; and, put the script in
> contrib/, and then say with every patch that is just the output of the
> script that that is the case.
Ok, I can split it up that way.
>
> Some (mostly changelog) comments:
>
> On Mon, Aug 05, 2019 at 01:09:10PM -0400, Arvind Sankar wrote:
> > * gcc/alias.c, gcc/asan.c, gcc/bb-reorder.c, gcc/bt-load.c: Use predicate macros for rtx_code comparisons.
>
> Many of your changelog lines are much too long. Don't use more than 80
> columns (including the leading tab, which is 8 columns).
>
> Please mention the exact macros you now use, and/or the actual rtx codes.
That'll be easier once its split up by macro. I'll combine the backend +
target code into one patch per macro.
>
> Filenames are relative to the directory containing the changelog file
> itself, so you shouldn't have the gcc/ in those filenames.
>
> > * gcc/config/microblaze/predicates.md,
>
> There shouldn't be trailing spaces.
>
> > * gcc/config/rx/constraints.md, gcc/config/rx/rx.c, gcc/config/rx/rx.h: Likewise.
>
> And you normally have a separate entry for every file.
>
I tried to make the changelog a bit shorter by combining filenames into
the same line-- should be easier all around to generate that with one entry per file.
> > -/* Predicate yielding true iff X is an rtx for a double-int. */
> > +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> > #define CONST_DOUBLE_AS_FLOAT_P(X) \
> > (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
>
> Is const_double really only used for floating point these days?
>
>
> Segher
Are you asking if the CONST_DOUBLE_AS_INT_P possibility is dead code
now? That's beyond my current level of understanding of the code,
hopefully someone else will chime in.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-05 18:14 ` Arvind Sankar
@ 2019-08-05 18:29 ` Segher Boessenkool
2019-08-05 18:34 ` Arvind Sankar
2019-08-08 16:48 ` Jeff Law
2019-08-06 3:11 ` Arvind Sankar
1 sibling, 2 replies; 33+ messages in thread
From: Segher Boessenkool @ 2019-08-05 18:29 UTC (permalink / raw)
To: Arvind Sankar; +Cc: gcc-patches
On Mon, Aug 05, 2019 at 02:14:50PM -0400, Arvind Sankar wrote:
> On Mon, Aug 05, 2019 at 12:48:46PM -0500, Segher Boessenkool wrote:
> > First: do you have a copyright assignment? See
> > https://gcc.gnu.org/contribute.html
> > for instructions.
>
> Nope, is this really substantial enough to warrant one?
Some might say it is, the sheer amount of code changed :-) If some
maintainer okays it without assignment, that is fine with me of course.
This is also easier if it is all machine-generated and nice simple
patches :-)
> > This is easier to review, and even to commit as obvious, if you did a
> > patch per macro, certainly for the new macros; and, put the script in
> > contrib/, and then say with every patch that is just the output of the
> > script that that is the case.
>
> Ok, I can split it up that way.
Thanks!
> > Please mention the exact macros you now use, and/or the actual rtx codes.
> That'll be easier once its split up by macro. I'll combine the backend +
> target code into one patch per macro.
Looking forward to it.
In general, writing changelogs for simpler patches is easier :-)
> > > * gcc/config/rx/constraints.md, gcc/config/rx/rx.c, gcc/config/rx/rx.h: Likewise.
> >
> > And you normally have a separate entry for every file.
>
> I tried to make the changelog a bit shorter by combining filenames into
> the same line-- should be easier all around to generate that with one entry per file.
Yeah.
> > > -/* Predicate yielding true iff X is an rtx for a double-int. */
> > > +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> > > #define CONST_DOUBLE_AS_FLOAT_P(X) \
> > > (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
> >
> > Is const_double really only used for floating point these days?
> Are you asking if the CONST_DOUBLE_AS_INT_P possibility is dead code
> now? That's beyond my current level of understanding of the code,
> hopefully someone else will chime in.
I am asking if the change to this comment is correct.
Thanks,
Segher
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-05 18:29 ` Segher Boessenkool
@ 2019-08-05 18:34 ` Arvind Sankar
2019-08-08 16:48 ` Jeff Law
1 sibling, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-05 18:34 UTC (permalink / raw)
To: Segher Boessenkool; +Cc: Arvind Sankar, gcc-patches
On Mon, Aug 05, 2019 at 01:29:26PM -0500, Segher Boessenkool wrote:
> On Mon, Aug 05, 2019 at 02:14:50PM -0400, Arvind Sankar wrote:
> > On Mon, Aug 05, 2019 at 12:48:46PM -0500, Segher Boessenkool wrote:
> > > > -/* Predicate yielding true iff X is an rtx for a double-int. */
> > > > +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> > > > #define CONST_DOUBLE_AS_FLOAT_P(X) \
> > > > (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
> > >
> > > Is const_double really only used for floating point these days?
>
> > Are you asking if the CONST_DOUBLE_AS_INT_P possibility is dead code
> > now? That's beyond my current level of understanding of the code,
> > hopefully someone else will chime in.
>
> I am asking if the change to this comment is correct.
>
Ah. The comment was originally copy-pasted from the one for
CONST_DOUBLE_AS_INT_P, and it seemed clearly wrong. The comment for
CONST_DOUBLE_P (which only checks the code and not the machine mode)
says it can either be a double-int or a floating point constant.
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-05 18:14 ` Arvind Sankar
2019-08-05 18:29 ` Segher Boessenkool
@ 2019-08-06 3:11 ` Arvind Sankar
2019-08-06 3:11 ` [PATCH v2 03/18] Use CONST_INT_P macro Arvind Sankar
` (17 more replies)
1 sibling, 18 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:11 UTC (permalink / raw)
To: gcc-patches
Here's the patches split up. The ones that say autogenerated were
generated from the script below.
I haven't included that as a patch yet since not sure about the
copyright/licensing boilerplate to insert in it.
contrib/rtl-pred.sh:
#!/bin/sh
# codes="CONST_INT|CONST_WIDE_INT|CONST_FIXED|CONST_DOUBLE|CONST_VECTOR|CONST_STRING|REG|SUBREG|MEM|LABEL_REF|SYMBOL_REF|DEBUG_INSN"
if test $# != 1 -a $# != 2; then
echo "Usage: $0 <RTX_CODE> [<RTX_PREDICATE>]" >&2
exit 1
fi
rtx_code="$1"
rtx_pred="$2"
if [ "x${rtx_pred}" == "x" ]; then
rtx_pred=${rtx_code}
fi
find . -path ./testsuite -prune -o -type f -regex '.*\.\(c\|cc\|h\|md\)' \! -path ./rtl.h -print | xargs \
perl -pi -e 's/\bGET_CODE[ ]?(\((?:(?>[^()]+)|(?1))*\)) (?|(!)=|==) ('${rtx_code}')\b/$2'${rtx_pred}'_P $1/g'
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 03/18] Use CONST_INT_P macro.
2019-08-06 3:11 ` Arvind Sankar
@ 2019-08-06 3:11 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 01/18] Fix CONST_DOUBLE_AS_FLOAT_P comment Arvind Sankar
` (16 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:11 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* combine-stack-adj.c: Convert GET_CODE (..) == CONST_INT
to CONST_INT_P (..).
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/combine-stack-adj.c b/gcc/combine-stack-adj.c
index 3638a1b10ee..f98a0d54c98 100644
--- a/gcc/combine-stack-adj.c
+++ b/gcc/combine-stack-adj.c
@@ -634,8 +634,7 @@ combine_stack_adjustments_for_block (basic_block bb)
&& GET_CODE (XEXP (XEXP (dest, 0), 1)) == PLUS
&& XEXP (XEXP (XEXP (dest, 0), 1), 0)
== stack_pointer_rtx
- && GET_CODE (XEXP (XEXP (XEXP (dest, 0), 1), 1))
- == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (XEXP (dest, 0), 1), 1))
&& INTVAL (XEXP (XEXP (XEXP (dest, 0), 1), 1))
== -last_sp_adjust))
&& XEXP (XEXP (dest, 0), 0) == stack_pointer_rtx
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 13/18] Use MEM_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh MEM
2019-08-06 3:11 ` Arvind Sankar
` (5 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 12/18] Use SUBREG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SUBREG Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 08/18] Use CONST_VECTOR_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_VECTOR Arvind Sankar
` (10 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* combine.c: Convert GET_CODE (..) == MEM to MEM_P (..).
* config/aarch64/aarch64-simd.md: Likewise.
* config/aarch64/aarch64-sve.md: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/aarch64/aarch64.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/predicates.md: Likewise.
* config/arc/simdext.md: Likewise.
* config/arm/arm.c: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/bfin.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cr16/cr16.h: Likewise.
* config/cr16/predicates.md: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.md: Likewise.
* config/csky/predicates.md: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/fr30/fr30.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/frv.md: Likewise.
* config/frv/predicates.md: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/i386/i386-expand.c: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/ia64.md: Likewise.
* config/ia64/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/iq2000/iq2000.md: Likewise.
* config/iq2000/predicates.md: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32c/predicates.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.md: Likewise.
* config/m68k/predicates.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/microblaze/microblaze.md: Likewise.
* config/mmix/mmix.md: Likewise.
* config/msp430/msp430.c: Likewise.
* config/nds32/nds32-fp-as-gp.c: Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nios2/nios2.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c: Likewise.
* config/pru/predicates.md: Likewise.
* config/pru/pru.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rx/rx.c: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.md: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/spu/spu.c: Likewise.
* config/spu/spu.md: Likewise.
* config/stormy16/predicates.md: Likewise.
* config/v850/predicates.md: Likewise.
* config/v850/v850.c: Likewise.
* config/visium/visium.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* dbxout.c: Likewise.
* df-scan.c: Likewise.
* fwprop.c: Likewise.
* ifcvt.c: Likewise.
* simplify-rtx.c: Likewise.
* var-tracking.c: Likewise.
80 files changed, 478 insertions(+), 478 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index b175ed9c4a0..a7af1ace40b 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -2779,13 +2779,13 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if ((set0 = single_set (i0))
/* Ensure the source of SET0 is a MEM, possibly buried inside
an extension. */
- && (GET_CODE (SET_SRC (set0)) == MEM
+ && (MEM_P (SET_SRC (set0))
|| ((GET_CODE (SET_SRC (set0)) == ZERO_EXTEND
|| GET_CODE (SET_SRC (set0)) == SIGN_EXTEND)
- && GET_CODE (XEXP (SET_SRC (set0), 0)) == MEM))
+ && MEM_P (XEXP (SET_SRC (set0), 0))))
&& (set3 = single_set (i3))
/* Ensure the destination of SET3 is a MEM. */
- && GET_CODE (SET_DEST (set3)) == MEM
+ && MEM_P (SET_DEST (set3))
/* Would it be better to extract the base address for the MEM
in SET3 and look for that? I don't have cases where it matters
but I could envision such cases. */
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index 0fe7ef60d33..b36cfce0d92 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -29,7 +29,7 @@
a stp in DI mode, so we check the validity of that.
If the mode is 8 bytes wide, then we will do doing a
normal str, so the check need not apply. */
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& !(aarch64_simd_imm_zero (operands[1], <MODE>mode)
&& ((known_eq (GET_MODE_SIZE (<MODE>mode), 16)
&& aarch64_mem_pair_operand (operands[0], DImode))
diff --git a/gcc/config/aarch64/aarch64-sve.md b/gcc/config/aarch64/aarch64-sve.md
index e489afbdde9..3f65d5f6604 100644
--- a/gcc/config/aarch64/aarch64-sve.md
+++ b/gcc/config/aarch64/aarch64-sve.md
@@ -438,7 +438,7 @@
(match_operand:PRED_ALL 1 "general_operand"))]
"TARGET_SVE"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
}
)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 70cac11c257..f54a0d462a8 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2099,7 +2099,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
/* The operand is expected to be MEM. Whenever the related insn
pattern changed, above code which calculate mem should be
updated. */
- gcc_assert (GET_CODE (mem) == MEM);
+ gcc_assert (MEM_P (mem));
MEM_READONLY_P (mem) = 1;
MEM_NOTRAP_P (mem) = 1;
emit_insn (insn);
@@ -2142,7 +2142,7 @@ aarch64_load_symref_appropriately (rtx dest, rtx imm,
mem = XVECEXP (XEXP (SET_SRC (insn), 0), 0, 0);
}
- gcc_assert (GET_CODE (mem) == MEM);
+ gcc_assert (MEM_P (mem));
MEM_READONLY_P (mem) = 1;
MEM_NOTRAP_P (mem) = 1;
emit_insn (insn);
@@ -8084,7 +8084,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
{
machine_mode mode = GET_MODE (x);
- if (GET_CODE (x) != MEM
+ if (!MEM_P (x)
|| (code == 'y' && maybe_ne (GET_MODE_SIZE (mode), 16)))
{
output_operand_lossage ("invalid operand for '%%%c'", code);
@@ -18118,20 +18118,20 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset)
{
fusion = SCHED_FUSION_LD_SIGN_EXTEND;
src = XEXP (src, 0);
- if (GET_CODE (src) != MEM || GET_MODE (src) != SImode)
+ if (!MEM_P (src) || GET_MODE (src) != SImode)
return SCHED_FUSION_NONE;
}
else if (GET_CODE (src) == ZERO_EXTEND)
{
fusion = SCHED_FUSION_LD_ZERO_EXTEND;
src = XEXP (src, 0);
- if (GET_CODE (src) != MEM || GET_MODE (src) != SImode)
+ if (!MEM_P (src) || GET_MODE (src) != SImode)
return SCHED_FUSION_NONE;
}
- if (GET_CODE (src) == MEM && REG_P (dest))
+ if (MEM_P (src) && REG_P (dest))
extract_base_offset_in_addr (src, base, offset);
- else if (GET_CODE (dest) == MEM && (REG_P (src) || src == const0_rtx))
+ else if (MEM_P (dest) && (REG_P (src) || src == const0_rtx))
{
fusion = SCHED_FUSION_ST;
extract_base_offset_in_addr (dest, base, offset);
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 1fe96d5f772..ff3addfe615 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1020,7 +1020,7 @@
(match_operand:SHORT 1 "general_operand"))]
""
"
- if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+ if (MEM_P (operands[0]) && operands[1] != const0_rtx)
operands[1] = force_reg (<MODE>mode, operands[1]);
if (GET_CODE (operands[1]) == CONST_POLY_INT)
@@ -1082,7 +1082,7 @@
&& aarch64_split_dimode_const_store (operands[0], operands[1]))
DONE;
- if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+ if (MEM_P (operands[0]) && operands[1] != const0_rtx)
operands[1] = force_reg (<MODE>mode, operands[1]);
/* FIXME: RR we still need to fix up what we are doing with
@@ -1184,7 +1184,7 @@
(match_operand:TI 1 "general_operand"))]
""
"
- if (GET_CODE (operands[0]) == MEM && operands[1] != const0_rtx)
+ if (MEM_P (operands[0]) && operands[1] != const0_rtx)
operands[1] = force_reg (TImode, operands[1]);
if (GET_CODE (operands[1]) == CONST_POLY_INT)
@@ -1245,7 +1245,7 @@
FAIL;
}
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! (CONST_DOUBLE_P (operands[1])
&& aarch64_float_const_zero_rtx_p (operands[1])))
operands[1] = force_reg (<MODE>mode, operands[1]);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 5a06d94d5f7..e79f36761b2 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -925,7 +925,7 @@ arc_secondary_reload_conv (rtx reg, rtx mem, rtx scratch, bool store_p)
{
rtx addr;
- gcc_assert (GET_CODE (mem) == MEM);
+ gcc_assert (MEM_P (mem));
addr = XEXP (mem, 0);
/* Large offset: use a move. FIXME: ld ops accepts limms as
@@ -4595,7 +4595,7 @@ arc_print_operand (FILE *file, rtx x, int code)
register or memory. */
if (REG_P (x))
fputs (reg_names[REGNO (x)+1], file);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
{
fputc ('[', file);
@@ -4721,7 +4721,7 @@ arc_print_operand (FILE *file, rtx x, int code)
}
case 'U' :
/* Output a load/store with update indicator if appropriate. */
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
{
rtx addr = XEXP (x, 0);
switch (GET_CODE (addr))
@@ -4779,7 +4779,7 @@ arc_print_operand (FILE *file, rtx x, int code)
case 'V' :
/* Output cache bypass indicator for a load/store insn. Volatile memory
refs are defined to use the cache bypass mechanism. */
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
{
if ((MEM_VOLATILE_P (x) && !TARGET_VOLATILE_CACHE_SET)
|| arc_is_uncached_mem_p (x))
@@ -8701,7 +8701,7 @@ compact_sda_memory_operand (rtx op, machine_mode mode, bool short_p)
int mask = 0;
/* Eliminate non-memory operations. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return false;
if (mode == VOIDmode)
@@ -10920,7 +10920,7 @@ compact_memory_operand_p (rtx op, machine_mode mode,
int size, off;
/* Eliminate non-memory operations. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return 0;
/* .di instructions have no 16-bit form. */
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 01bfc1b9547..a5537ec73e4 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -291,7 +291,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
- if (GET_CODE (SUBREG_REG (op)) == MEM)
+ if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else
return register_operand (op, mode);
@@ -315,7 +315,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
- if (GET_CODE (SUBREG_REG (op)) == MEM)
+ if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else
return register_operand (op, mode);
@@ -355,7 +355,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
- if (GET_CODE (SUBREG_REG (op)) == MEM)
+ if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else
return dest_reg_operand (op, mode);
@@ -398,7 +398,7 @@
;; and only the standard movXX patterns are set up to handle them.
(define_predicate "nonvol_nonimm_operand"
(and (match_code "subreg, reg, mem")
- (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)")
+ (match_test "(!MEM_P (op) || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)")
(match_test "!arc_is_uncached_mem_p (op)"))
)
@@ -652,7 +652,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- if ((GET_CODE (op) == MEM)
+ if ((MEM_P (op))
&& (mode == V8HImode)
&& REG_P (XEXP (op,0)))
return 1;
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 53a0a90ef3b..9a450fbe446 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -163,7 +163,7 @@
{
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
operands[1] = force_reg (V8HImode, operands[1]);
}")
@@ -213,7 +213,7 @@
(define_insn "movv8hi_insn"
[(set (match_operand:V8HI 0 "vector_register_or_memory_operand" "=v,m,v")
(match_operand:V8HI 1 "vector_register_or_memory_operand" "m,v,v"))]
- "TARGET_SIMD_SET && !(GET_CODE (operands[0]) == MEM && GET_CODE(operands[1]) == MEM)"
+ "TARGET_SIMD_SET && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
"@
vld128r %0, %1
vst128r %1, %0
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 2a5359c26ec..fd18f92b6ec 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -31207,12 +31207,12 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset, bool *is_load)
src = SET_SRC (x);
dest = SET_DEST (x);
- if (REG_P (src) && GET_CODE (dest) == MEM)
+ if (REG_P (src) && MEM_P (dest))
{
*is_load = false;
extract_base_offset_in_addr (dest, base, offset);
}
- else if (GET_CODE (src) == MEM && REG_P (dest))
+ else if (MEM_P (src) && REG_P (dest))
{
*is_load = true;
extract_base_offset_in_addr (src, base, offset);
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 716e7345d50..7ae604716e6 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -1217,7 +1217,7 @@ bfin_delegitimize_address (rtx orig_x)
{
rtx x = orig_x;
- if (GET_CODE (x) != MEM)
+ if (!MEM_P (x))
return orig_x;
x = XEXP (x, 0);
@@ -1324,7 +1324,7 @@ print_address_operand (FILE *file, rtx x)
break;
default:
- gcc_assert (GET_CODE (x) != MEM);
+ gcc_assert (!MEM_P (x));
print_operand (file, x, 0);
break;
}
@@ -1915,7 +1915,7 @@ emit_pic_move (rtx *operands, machine_mode mode ATTRIBUTE_UNUSED)
rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
gcc_assert (!TARGET_FDPIC || !(reload_in_progress || reload_completed));
- if (GET_CODE (operands[0]) == MEM && SYMBOLIC_CONST (operands[1]))
+ if (MEM_P (operands[0]) && SYMBOLIC_CONST (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
else
operands[1] = legitimize_pic_address (operands[1], temp,
@@ -1947,7 +1947,7 @@ expand_move (rtx *operands, machine_mode mode)
op1 = XEXP (op, 1);
if (!insn_data[CODE_FOR_addsi3].operand[2].predicate (op1, mode))
op1 = force_reg (mode, op1);
- if (GET_CODE (dest) == MEM)
+ if (MEM_P (dest))
dest = gen_reg_rtx (mode);
emit_insn (gen_addsi3 (dest, op0, op1));
if (dest == operands[0])
@@ -1957,7 +1957,7 @@ expand_move (rtx *operands, machine_mode mode)
/* Don't generate memory->memory or constant->memory moves, go through a
register */
else if ((reload_in_progress | reload_completed) == 0
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& !REG_P (operands[1]))
operands[1] = force_reg (mode, operands[1]);
return false;
@@ -1978,7 +1978,7 @@ split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
/* simplify_subreg refuse to split volatile memory addresses,
but we still have to handle it. */
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
lo_half[num] = adjust_address (op, SImode, 0);
hi_half[num] = adjust_address (op, SImode, 4);
@@ -3045,7 +3045,7 @@ analyze_push_multiple_operation (rtx op)
src = SET_SRC (t);
dest = SET_DEST (t);
- if (GET_CODE (dest) != MEM || ! REG_P (src))
+ if (!MEM_P (dest) || ! REG_P (src))
return 0;
dest = XEXP (dest, 0);
if (GET_CODE (dest) != PLUS
@@ -3114,7 +3114,7 @@ analyze_pop_multiple_operation (rtx op)
src = SET_SRC (t);
dest = SET_DEST (t);
- if (GET_CODE (src) != MEM || ! REG_P (dest))
+ if (!MEM_P (src) || ! REG_P (dest))
return 0;
src = XEXP (src, 0);
@@ -4297,7 +4297,7 @@ indirect_call_p (rtx pat)
pat = SET_SRC (pat);
gcc_assert (GET_CODE (pat) == CALL);
pat = XEXP (pat, 0);
- gcc_assert (GET_CODE (pat) == MEM);
+ gcc_assert (MEM_P (pat));
pat = XEXP (pat, 0);
return REG_P (pat);
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 2c70db8b39b..627b5a4b47c 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -505,7 +505,7 @@
(define_insn_and_split "movdi_insn"
[(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
(match_operand:DI 1 "general_operand" "iFx,r,mx"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"#"
"reload_completed"
[(set (match_dup 2) (match_dup 3))
@@ -607,7 +607,7 @@
(define_insn "*movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
(match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"@
%0 = %1;
%0 = %1;
@@ -647,7 +647,7 @@
[(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
(match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"@
#
%0 = %1;
@@ -669,7 +669,7 @@
(define_insn "*movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
(match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
{
static const char *templates[] = {
"%0 = %1;",
@@ -693,7 +693,7 @@
(define_insn "*movqi_insn"
[(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
(match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"@
%0 = %1;
%0 = %1 (X);
@@ -706,7 +706,7 @@
(define_insn "*movsf_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
(match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"@
%0 = %1;
#
@@ -717,7 +717,7 @@
(define_insn_and_split "movdf_insn"
[(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
(match_operand:DF 1 "general_operand" "iFx,r,mx"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"#"
"reload_completed"
[(set (match_dup 2) (match_dup 3))
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index dab63cb3011..938e42f24d6 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1375,7 +1375,7 @@ expand_move (rtx *operands, machine_mode mode)
rtx op = operands[1];
if ((reload_in_progress | reload_completed) == 0
- && GET_CODE (dest) == MEM && !REG_P (op))
+ && MEM_P (dest) && !REG_P (op))
operands[1] = force_reg (mode, op);
else if (mode == SImode && symbolic_operand (op, SImode))
{
@@ -1973,7 +1973,7 @@ c6x_print_address_operand (FILE *file, rtx x, machine_mode mem_mode)
break;
default:
- gcc_assert (GET_CODE (x) != MEM);
+ gcc_assert (!MEM_P (x));
c6x_print_operand (file, x, 0);
break;
}
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 1404363f8f8..f108c671796 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -602,7 +602,7 @@
"=a,b, a, b, ab, ab,a,?a, b,?b, Q, R, R, Q")
(match_operand:QIHIM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,Q, R, R, Q, a,?a, b,?b"))]
- "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
+ "!MEM_P (operands[0]) || REG_P (operands[1])"
"@
%|%.\\tmv\\t%$\\t%1, %0
%|%.\\tmv\\t%$\\t%1, %0
@@ -631,7 +631,7 @@
"=a,b, a, b, ab, ab,a,b,ab,a,?a, b,?b, Q, R, R, Q")
(match_operand:SISFVM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,S0,S0,Si,Q, R, R, Q, a,?a, b,?b"))]
- "(GET_CODE (operands[0]) != MEM || REG_P (operands[1])
+ "(!MEM_P (operands[0]) || REG_P (operands[1])
|| (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))"
"@
%|%.\\tmv\\t%$\\t%1, %0
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 0dc9435078d..fbc2b5cf67a 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -2109,14 +2109,14 @@ notice_update_cc (rtx exp)
the RTX's which we remember the cc's came from.
(Note that moving a constant 0 or 1 MAY set the cc's). */
if (REG_P (SET_DEST (exp))
- && (REG_P (SET_SRC (exp)) || GET_CODE (SET_SRC (exp)) == MEM))
+ && (REG_P (SET_SRC (exp)) || MEM_P (SET_SRC (exp))))
{
return;
}
/* Moving register into memory doesn't alter the cc's.
It may invalidate the RTX's which we remember the cc's came from. */
- if (GET_CODE (SET_DEST (exp)) == MEM && REG_P (SET_SRC (exp)))
+ if (MEM_P (SET_DEST (exp)) && REG_P (SET_SRC (exp)))
{
return;
}
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index 227b536d1c9..dbc012a197d 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -340,9 +340,9 @@ enum reg_class
/* This check is for sbit/cbit instruction. */
#define OK_FOR_Z(OP) \
- ((GET_CODE (OP) == MEM && CONST_INT_P (XEXP (OP, 0))) \
- || (GET_CODE (OP) == MEM && REG_P (XEXP (OP, 0))) \
- || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
+ ((MEM_P (OP) && CONST_INT_P (XEXP (OP, 0))) \
+ || (MEM_P (OP) && REG_P (XEXP (OP, 0))) \
+ || (MEM_P (OP) && GET_CODE (XEXP (OP, 0)) == PLUS \
&& REG_P (XEXP ((XEXP (OP, 0)), 0)) \
&& CONST_INT_P (XEXP ((XEXP (OP, 0)), 1))))
diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md
index b1e3193889f..5800123c558 100644
--- a/gcc/config/cr16/predicates.md
+++ b/gcc/config/cr16/predicates.md
@@ -25,7 +25,7 @@
(define_predicate "bit_operand"
(match_code "mem")
{
- return ((GET_CODE (op) == MEM && OK_FOR_Z (op)));
+ return ((MEM_P (op) && OK_FOR_Z (op)));
})
;; Unsigned 4-bits constant int or double value.
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index fd2291f176c..2cd0630ac88 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -1408,7 +1408,7 @@ csky_minipool_load_p (rtx_insn *insn)
/* Constant pool loads are label_refs. */
if (GET_CODE (op1) == ZERO_EXTEND || GET_CODE (op1) == SIGN_EXTEND)
op1 = XEXP (op1, 0);
- if (GET_CODE (op1) != MEM)
+ if (!MEM_P (op1))
return false;
addr = XEXP (op1, 0);
if (GET_CODE (addr) == PLUS && CONST_INT_P (XEXP (addr, 1)))
@@ -3966,7 +3966,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
return "mov\t%0, %1";
}
/* The situation mov memory to reg. */
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
decompose_csky_address (XEXP (src, 0), &op1);
@@ -4048,7 +4048,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "lrw\t%0, %1";
}
- else if (GET_CODE (dst) == MEM)
+ else if (MEM_P (dst))
{
decompose_csky_address (XEXP (dst, 0), &op0);
@@ -4104,7 +4104,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
{
if (REG_P (src))
return "mov\t%0, %1";
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
decompose_csky_address (XEXP (src, 0), &op1);
@@ -4166,7 +4166,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "lrw\t%0, %1";
}
- else if (GET_CODE (dst) == MEM)
+ else if (MEM_P (dst))
switch (GET_MODE (dst))
{
case E_HImode:
@@ -4246,7 +4246,7 @@ csky_output_movedouble (rtx operands[],
else
return "mov\t%0, %1\n\tmov\t%R0, %R1";
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
rtx memexp = XEXP (src, 0);
int dstreg = REGNO (dst);
@@ -4318,7 +4318,7 @@ csky_output_movedouble (rtx operands[],
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && REG_P (src))
+ else if (MEM_P (dst) && REG_P (src))
{
rtx memexp = XEXP (dst, 0);
int srcreg = REGNO (src);
@@ -4381,7 +4381,7 @@ csky_output_ck801_movedouble (rtx operands[],
else
return "mov\t%0, %1\n\tmov\t%R0, %R1";
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
rtx memexp = XEXP (src, 0);
int dstreg = REGNO (dst);
@@ -4440,7 +4440,7 @@ csky_output_ck801_movedouble (rtx operands[],
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && REG_P (src))
+ else if (MEM_P (dst) && REG_P (src))
{
rtx memexp = XEXP (dst, 0);
int srcreg = REGNO (src);
@@ -5942,7 +5942,7 @@ csky_valid_fpuv2_mem_operand (rtx op)
{
struct csky_address addr;
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return false;
if (!decompose_csky_address (XEXP (op, 0), &addr))
@@ -6523,7 +6523,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
enum rtx_code code = GET_CODE (addr);
if (code == ZERO_EXTEND || code == SIGN_EXTEND)
addr = XEXP (addr, 0);
- gcc_assert (GET_CODE (addr) == MEM);
+ gcc_assert (MEM_P (addr));
rtx base = XEXP (addr, 0);
rtx reg = NULL_RTX;
@@ -6554,7 +6554,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
enum rtx_code code = GET_CODE (addr);
if (code == ZERO_EXTEND || code == SIGN_EXTEND)
addr = XEXP (addr, 0);
- gcc_assert (GET_CODE (addr) == MEM);
+ gcc_assert (MEM_P (addr));
rtx base = XEXP (addr, 0);
rtx reg = NULL_RTX;
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 2dd1452eb3b..6e680c14ac2 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -259,7 +259,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
else if (CONSTANT_P (operands[1])
&& (!CONST_INT_P (operands[1])
@@ -300,7 +300,7 @@
""
"
{
- if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM)
+ if (can_create_pseudo_p () && MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]);
else if (CONSTANT_P (operands[1])
&& (!CONST_INT_P (operands[1])
@@ -339,7 +339,7 @@
[(set (match_operand:DI 0 "general_operand" "")
(match_operand:DI 1 "general_operand" ""))]
""
- "if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM)
+ "if (can_create_pseudo_p () && MEM_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);"
)
@@ -428,7 +428,7 @@
(match_operand:SF 1 "general_operand" ""))]
""
"
- if (GET_CODE (operands[0]) == MEM && can_create_pseudo_p ())
+ if (MEM_P (operands[0]) && can_create_pseudo_p ())
operands[1] = force_reg (SFmode, operands[1]);
"
)
@@ -467,7 +467,7 @@
(match_operand:DF 1 "general_operand" ""))]
""
"
- if (GET_CODE (operands[0]) == MEM && can_create_pseudo_p ())
+ if (MEM_P (operands[0]) && can_create_pseudo_p ())
operands[1] = force_reg (DFmode, operands[1]);
"
)
@@ -2057,7 +2057,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
- || GET_CODE (operands[1]) != MEM
+ || !MEM_P (operands[1])
|| !REG_P (XEXP (operands[1], 0))
|| XEXP (operands[1], 0) != stack_pointer_rtx
|| !REG_P (operands[0])
@@ -2095,7 +2095,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
- || GET_CODE (operands[0]) != MEM
+ || !MEM_P (operands[0])
|| !REG_P (XEXP (operands[0], 0))
|| XEXP (operands[0], 0) != stack_pointer_rtx
|| !REG_P (operands[1])
@@ -3250,7 +3250,7 @@
operands[0] = gen_rtx_MEM (GET_MODE (pic_ref), pic_ref);
}
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! register_operand (XEXP (operands[0], 0), SImode)
&& ! csky_symbolic_address_p (XEXP (operands[0], 0))
&& ! (flag_pic
@@ -3301,7 +3301,7 @@
operands[1] = gen_rtx_MEM (GET_MODE (pic_ref), pic_ref);
}
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& ! register_operand (XEXP (operands[1], 0), SImode)
&& ! csky_symbolic_address_p (XEXP (operands[1], 0))
&& ! (flag_pic
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index 93725f15209..c2dadba3d27 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -32,7 +32,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM
+ || !MEM_P (SET_SRC (XVECEXP (op, 0, 0)))
|| !REG_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0))
|| XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx)
return 0;
@@ -48,7 +48,7 @@
|| !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
- || GET_CODE (SET_SRC (elt)) != MEM
+ || !MEM_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
@@ -72,7 +72,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+ || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
|| !REG_P (XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0))
|| XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx
|| !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
@@ -89,7 +89,7 @@
|| !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
- || GET_CODE (SET_DEST (elt)) != MEM
+ || !MEM_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 8dea5b9f33c..ef6e27ff34c 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -347,7 +347,7 @@ machopic_define_symbol (rtx mem)
{
rtx sym_ref;
- gcc_assert (GET_CODE (mem) == MEM);
+ gcc_assert (MEM_P (mem));
sym_ref = XEXP (mem, 0);
SYMBOL_REF_FLAGS (sym_ref) |= MACHO_SYMBOL_FLAG_DEFINED;
}
@@ -730,7 +730,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
else
return orig;
}
- else if (GET_CODE (orig) == MEM)
+ else if (MEM_P (orig))
{
XEXP (ptr_ref, 0) =
machopic_indirect_data_reference (XEXP (orig, 0), reg);
@@ -764,7 +764,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
else
result = gen_rtx_PLUS (Pmode, base, orig);
- if (MACHOPIC_JUST_INDIRECT && GET_CODE (base) == MEM)
+ if (MACHOPIC_JUST_INDIRECT && MEM_P (base))
{
if (reg)
{
@@ -791,7 +791,7 @@ machopic_indirect_call_target (rtx target)
if (! darwin_picsymbol_stubs)
return target;
- if (GET_CODE (target) != MEM)
+ if (!MEM_P (target))
return target;
if (MACHOPIC_INDIRECT
@@ -838,7 +838,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
return reg;
}
- if (GET_CODE (orig) == MEM)
+ if (MEM_P (orig))
{
if (reg == 0)
{
@@ -1023,7 +1023,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
}
}
else if (GET_CODE (orig) == PLUS
- && (GET_CODE (XEXP (orig, 0)) == MEM
+ && (MEM_P (XEXP (orig, 0))
|| GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (orig, 0)) == LABEL_REF)
&& XEXP (orig, 0) != pic_offset_table_rtx
@@ -1031,7 +1031,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
{
rtx base;
- int is_complex = (GET_CODE (XEXP (orig, 0)) == MEM);
+ int is_complex = (MEM_P (XEXP (orig, 0)));
base = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
orig = machopic_legitimize_pic_address (XEXP (orig, 1),
@@ -1055,7 +1055,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
{
return machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
}
- else if (GET_CODE (orig) == MEM
+ else if (MEM_P (orig)
&& GET_CODE (XEXP (orig, 0)) == SYMBOL_REF)
{
rtx addr = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md
index 354a21f5c41..83b8e76062e 100644
--- a/gcc/config/epiphany/epiphany.md
+++ b/gcc/config/epiphany/epiphany.md
@@ -121,7 +121,7 @@
emit_insn (gen_movsi (operands[0], operands[1]));
DONE;
}
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
if (<MODE>mode == SImode
&& (operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx))
@@ -333,7 +333,7 @@
subregs. */
if (epiphany_vect_align != 4 /* == 8 */
&& !reload_in_progress
- && (GET_CODE (operands[0]) == MEM || GET_CODE (operands[1]) == MEM)
+ && (MEM_P (operands[0]) || MEM_P (operands[1]))
&& !misaligned_operand (operands[1], <MODE>mode)
&& (!SUBREG_P (operands[0])
|| (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
@@ -350,7 +350,7 @@
}
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
}")
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index 1d881a22d50..07b44b5ec65 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -144,7 +144,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
- if (GET_CODE (SUBREG_REG (op)) == MEM)
+ if (MEM_P (SUBREG_REG (op)))
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
else
return register_operand (op, mode);
@@ -162,7 +162,7 @@
(define_predicate "move_double_src_operand"
(match_code "reg,subreg,mem,const_int,const_double,const_vector")
{
- if (GET_CODE (op) == MEM && misaligned_operand (op, mode)
+ if (MEM_P (op) && misaligned_operand (op, mode)
&& !address_operand (plus_constant (Pmode, XEXP (op, 0), 4), SImode))
return 0;
return general_operand (op, mode);
@@ -180,7 +180,7 @@
case SUBREG :
/* (subreg (mem ...) ...) can occur here if the inner part was once a
pseudo-reg and is now a stack slot. */
- if (GET_CODE (SUBREG_REG (op)) == MEM)
+ if (MEM_P (SUBREG_REG (op)))
{
return address_operand (XEXP (SUBREG_REG (op), 0), mode);
}
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index f19dbdabd81..3413eaaedc5 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -166,8 +166,8 @@
{
if (!reload_in_progress
&& !reload_completed
- && GET_CODE (operands[0]) == MEM
- && (GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[0])
+ && (MEM_P (operands[1])
|| immediate_operand (operands[1], QImode)))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
}")
@@ -212,8 +212,8 @@
{
if (!reload_in_progress
&& !reload_completed
- && GET_CODE (operands[0]) == MEM
- && (GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[0])
+ && (MEM_P (operands[1])
|| immediate_operand (operands[1], HImode)))
operands[1] = copy_to_mode_reg (HImode, operands[1]);
}")
@@ -262,8 +262,8 @@
"{
if (!reload_in_progress
&& !reload_completed
- && GET_CODE(operands[0]) == MEM
- && (GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[0])
+ && (MEM_P (operands[1])
|| immediate_operand (operands[1], SImode)))
operands[1] = copy_to_mode_reg (SImode, operands[1]);
}"
@@ -386,7 +386,7 @@
"
/* Everything except mem = const or mem = mem can be done easily. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);
"
)
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 330a74523a5..1fa5f167f27 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -56,7 +56,7 @@
(define_predicate "call_operand"
(match_code "mem")
{
- return (GET_CODE (op) == MEM
+ return (MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| REG_P (XEXP (op, 0))));
})
@@ -103,7 +103,7 @@
if (SUBREG_P (op))
op = SUBREG_REG (op);
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
return memory_address_p (DImode, XEXP (op, 0));
return FALSE;
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index a1df8153a22..e16508dba44 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -2466,7 +2466,7 @@ frv_index_memory (rtx memref, machine_mode mode, int index)
static void
frv_print_operand_address (FILE * stream, machine_mode /* mode */, rtx x)
{
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
x = XEXP (x, 0);
switch (GET_CODE (x))
@@ -2858,7 +2858,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'I':
/* Print 'i' if the operand is a constant, or is a memory reference that
adds a constant. */
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
x = ((GET_CODE (XEXP (x, 0)) == PLUS)
? XEXP (XEXP (x, 0), 1)
: XEXP (x, 0));
@@ -2958,7 +2958,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'U':
/* Print 'u' if the operand is a update load/store. */
- if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
+ if (MEM_P (x) && GET_CODE (XEXP (x, 0)) == PRE_MODIFY)
fputs ("u", file);
break;
@@ -2995,7 +2995,7 @@ frv_print_operand (FILE * file, rtx x, int code)
else if (frv_const_unspec_p (x, &unspec))
frv_output_const_unspec (file, &unspec);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
frv_print_operand_address (file, GET_MODE (x), XEXP (x, 0));
else if (CONSTANT_ADDRESS_P (x))
@@ -3733,7 +3733,7 @@ int
frv_legitimate_memory_operand (rtx op, machine_mode mode, int condexec_p)
{
return ((GET_MODE (op) == mode || mode == VOIDmode)
- && GET_CODE (op) == MEM
+ && MEM_P (op)
&& frv_legitimate_address_p_1 (mode, XEXP (op, 0),
reload_completed, condexec_p, FALSE));
}
@@ -3891,7 +3891,7 @@ condexec_memory_operand (rtx op, machine_mode mode)
break;
}
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
addr = XEXP (op, 0);
@@ -4232,7 +4232,7 @@ output_move_single (rtx operands[], rtx insn)
return "movsg %1, %0";
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
/* gpr <- memory */
switch (mode)
@@ -4306,7 +4306,7 @@ output_move_single (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
/* fpr <- memory */
switch (mode)
@@ -4345,7 +4345,7 @@ output_move_single (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (dest) == MEM)
+ else if (MEM_P (dest))
{
if (REG_P (src))
{
@@ -4449,7 +4449,7 @@ output_move_double (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
/* gpr <- memory */
if (dbl_memory_one_insn_operand (src, mode))
@@ -4490,7 +4490,7 @@ output_move_double (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
/* fpr <- memory */
if (dbl_memory_one_insn_operand (src, mode))
@@ -4504,7 +4504,7 @@ output_move_double (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (dest) == MEM)
+ else if (MEM_P (dest))
{
if (REG_P (src))
{
@@ -4574,7 +4574,7 @@ output_condmove_single (rtx operands[], rtx insn)
return "cmovfg %3, %2, %1, %e0";
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
/* gpr <- memory */
switch (mode)
@@ -4617,7 +4617,7 @@ output_condmove_single (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
/* fpr <- memory */
if (mode == SImode || mode == SFmode)
@@ -4629,7 +4629,7 @@ output_condmove_single (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (dest) == MEM)
+ else if (MEM_P (dest))
{
if (REG_P (src))
{
@@ -6002,7 +6002,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
}
/* See if we need to fix up stores */
- if (GET_CODE (dest) == MEM)
+ if (MEM_P (dest))
{
rtx new_mem = frv_ifcvt_rewrite_mem (dest, mode, insn);
@@ -6017,7 +6017,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
}
/* See if we need to fix up loads */
- if (GET_CODE (src) == MEM)
+ if (MEM_P (src))
{
rtx new_mem = frv_ifcvt_rewrite_mem (src, mode, insn);
@@ -7081,7 +7081,7 @@ frv_registers_conflict_p_1 (rtx pat, regstate_t cond)
if (frv_regstate_conflict_p (frv_packet.regstate[regno], cond))
return true;
}
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
{
/* If we ran out of memory slots, assume a conflict. */
if (frv_packet.num_mems > ARRAY_SIZE (frv_packet.mems))
@@ -7141,7 +7141,7 @@ frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
FOR_EACH_REGNO (regno, x)
frv_packet.regstate[regno] |= *(regstate_t *) data;
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
{
if (frv_packet.num_mems < ARRAY_SIZE (frv_packet.mems))
{
@@ -7822,7 +7822,7 @@ frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
if (GET_CODE (src) == ZERO_EXTEND)
src = XEXP (src, 0);
- if (GET_CODE (src) == MEM
+ if (MEM_P (src)
&& rtx_equal_p (XEXP (src, 0), next_io->var_address))
{
if (dump_file)
@@ -8815,7 +8815,7 @@ frv_expand_voidbinop_builtin (enum insn_code icode, tree call)
machine_mode mode0 = insn_data[icode].operand[0].mode;
rtx addr;
- if (GET_CODE (op0) != MEM)
+ if (!MEM_P (op0))
{
rtx reg = op0;
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index d365476ef0a..cac99227522 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -2185,7 +2185,7 @@
rtx addr;
rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0);
@@ -4874,7 +4874,7 @@
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
addr = XEXP (operands[0], 0);
if (! call_operand (addr, Pmode))
@@ -4959,7 +4959,7 @@
{
rtx addr;
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
addr = XEXP (operands[0], 0);
if (! sibcall_operand (addr, Pmode))
@@ -5026,7 +5026,7 @@
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0);
if (! call_operand (addr, Pmode))
@@ -5092,7 +5092,7 @@
{
rtx addr;
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0);
if (! sibcall_operand (addr, Pmode))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index bbe55939a62..fb4f13b32e6 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -455,7 +455,7 @@
if (gpr_or_memory_operand (op, mode))
return TRUE;
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
if (GET_MODE (op) != mode)
@@ -1004,7 +1004,7 @@
if (! TARGET_DWORD)
return FALSE;
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
@@ -1049,7 +1049,7 @@
(define_predicate "dbl_memory_two_insn_operand"
(match_code "mem")
{
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
if (mode != VOIDmode && GET_MODE_SIZE (mode) != 2*UNITS_PER_WORD)
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 5e1fe1b682b..d9d69e4791e 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -756,7 +756,7 @@ h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
if (GET_CODE (x) == SET
&& REG_P (XEXP (x, regindex))
- && GET_CODE (XEXP (x, memindex)) == MEM
+ && MEM_P (XEXP (x, memindex))
&& h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
return REGNO (XEXP (x, regindex));
@@ -2324,7 +2324,7 @@ h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
return size;
}
- else if (GET_CODE (op) == MEM)
+ else if (MEM_P (op))
{
op = XEXP (op, 0);
if (CONSTANT_P (op))
@@ -2484,7 +2484,7 @@ h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
rtx addr;
unsigned int size;
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return false;
addr = XEXP (op, 0);
@@ -2611,7 +2611,7 @@ h8300_insn_length_from_table (rtx_insn *insn, rtx * operands)
bool
h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs)
{
- if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM)
+ if (MEM_P (rhs) && MEM_P (lhs))
{
rhs = XEXP (rhs, 0);
lhs = XEXP (lhs, 0);
@@ -2797,9 +2797,9 @@ compute_mov_length (rtx *operands)
rtx src = operands[1];
rtx addr;
- if (GET_CODE (src) == MEM)
+ if (MEM_P (src))
addr = XEXP (src, 0);
- else if (GET_CODE (dest) == MEM)
+ else if (MEM_P (dest))
addr = XEXP (dest, 0);
else
addr = NULL_RTX;
@@ -5228,7 +5228,7 @@ fix_bit_operand (rtx *operands, enum rtx_code code)
: single_one_operand (operands[2], QImode))
{
/* OK to have a memory dest. */
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& !satisfies_constraint_U (operands[0]))
{
rtx mem = gen_rtx_MEM (GET_MODE (operands[0]),
@@ -5238,7 +5238,7 @@ fix_bit_operand (rtx *operands, enum rtx_code code)
operands[0] = mem;
}
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& !satisfies_constraint_U (operands[1]))
{
rtx mem = gen_rtx_MEM (GET_MODE (operands[1]),
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 082ef9a7f74..401420c42f1 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -327,7 +327,7 @@
return "mov.w %f1,%f0\;mov.w %e1,%e0";
case 2:
/* Make sure we don't trample the register we index with. */
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
{
rtx inside = XEXP (operands[1], 0);
if (REG_P (inside))
@@ -662,7 +662,7 @@
return "mov.w %f1,%f0\;mov.w %e1,%e0";
case 2:
/* Make sure we don't trample the register we index with. */
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
{
rtx inside = XEXP (operands[1], 0);
if (REG_P (inside))
@@ -2990,8 +2990,8 @@
FAIL;
/* For now, we don't allow memory operands. */
- if (GET_CODE (operands[0]) == MEM
- || GET_CODE (operands[3]) == MEM)
+ if (MEM_P (operands[0])
+ || MEM_P (operands[3]))
FAIL;
if (!REG_P (operands[3]))
@@ -3060,7 +3060,7 @@
FAIL;
/* For now, we don't allow memory operands. */
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
FAIL;
})
@@ -4654,8 +4654,8 @@
(const_int 255)))]
"(TARGET_H8300H || TARGET_H8300S)
&& !reg_overlap_mentioned_p (operands[0], operands[1])
- && !(GET_CODE (operands[1]) == MEM && !offsettable_memref_p (operands[1]))
- && !(GET_CODE (operands[1]) == MEM && MEM_VOLATILE_P (operands[1]))"
+ && !(MEM_P (operands[1]) && !offsettable_memref_p (operands[1]))
+ && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))"
[(set (match_dup 0)
(const_int 0))
(set (strict_low_part (match_dup 2))
@@ -4679,10 +4679,10 @@
&& REGNO (operands[0]) == REGNO (operands[2])
&& !reg_overlap_mentioned_p (operands[2], operands[1])
&& !(GET_MODE (operands[1]) != QImode
- && GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[1])
&& !offsettable_memref_p (operands[1]))
&& !(GET_MODE (operands[1]) != QImode
- && GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[1])
&& MEM_VOLATILE_P (operands[1]))"
[(set (match_dup 2)
(const_int 0))
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 4eeb34bb75d..b71bdde6de8 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -24,7 +24,7 @@
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
{
if (GET_MODE (op) == mode
- && GET_CODE (op) == MEM
+ && MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == POST_INC)
return 1;
return general_operand (op, mode);
@@ -37,7 +37,7 @@
(match_code "subreg,reg,mem")
{
if (GET_MODE (op) == mode
- && GET_CODE (op) == MEM
+ && MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PRE_DEC)
return 1;
return general_operand (op, mode);
@@ -219,7 +219,7 @@
(define_predicate "call_expander_operand"
(match_code "mem")
{
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
rtx inside = XEXP (op, 0);
if (register_operand (inside, Pmode))
@@ -267,7 +267,7 @@
if (REG_P (op))
return GET_MODE (op) == Pmode;
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
rtx inside = XEXP (op, 0);
if (register_operand (inside, Pmode))
@@ -349,7 +349,7 @@
return 1;
if (SUBREG_P (op))
return 1;
- return (GET_CODE (op) == MEM
+ return (MEM_P (op)
&& satisfies_constraint_U (op));
})
@@ -358,7 +358,7 @@
(define_predicate "bit_memory_operand"
(match_code "mem")
{
- return (GET_CODE (op) == MEM
+ return (MEM_P (op)
&& satisfies_constraint_U (op));
})
@@ -368,7 +368,7 @@
(define_predicate "bit_register_indirect_operand"
(match_code "mem")
{
- return (GET_CODE (op) == MEM
+ return (MEM_P (op)
&& (REG_P (XEXP (op, 0))
|| CONST_INT_P (XEXP (op, 0))));
})
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index f6ab07de01b..e83ab66a598 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -258,13 +258,13 @@ ix86_expand_move (machine_mode mode, rtx operands[])
op1 = machopic_legitimize_pic_address (op1, mode,
temp == op1 ? 0 : temp);
}
- if (op0 != op1 && GET_CODE (op0) != MEM)
+ if (op0 != op1 && !MEM_P (op0))
{
rtx insn = gen_rtx_SET (op0, op1);
emit_insn (insn);
return;
}
- if (GET_CODE (op0) == MEM)
+ if (MEM_P (op0))
op1 = force_reg (Pmode, op1);
else
{
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index a5813a80bfa..86ef8bc0078 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -877,7 +877,7 @@ ia64_encode_section_info (tree decl, rtx rtl, int first)
/* Careful not to prod global register variables. */
if (TREE_CODE (decl) == VAR_DECL
- && GET_CODE (DECL_RTL (decl)) == MEM
+ && MEM_P (DECL_RTL (decl))
&& GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
&& (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
ia64_encode_addr_area (decl, XEXP (rtl, 0));
@@ -892,9 +892,9 @@ ia64_move_ok (rtx dst, rtx src)
memory_operand. So check the code directly and don't worry about
the validity of the underlying address, which should have been
checked elsewhere anyway. */
- if (GET_CODE (dst) != MEM)
+ if (!MEM_P (dst))
return 1;
- if (GET_CODE (src) == MEM)
+ if (MEM_P (src))
return 0;
if (register_operand (src, VOIDmode))
return 1;
@@ -917,7 +917,7 @@ ia64_load_pair_ok (rtx dst, rtx src)
if (!REG_P (dst)
|| !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
return 0;
- if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
+ if (!MEM_P (src) || MEM_VOLATILE_P (src))
return 0;
switch (GET_CODE (XEXP (src, 0)))
{
@@ -1586,7 +1586,7 @@ ia64_split_tmode_move (rtx operands[])
load, or rws_access_regno will die. And we must not generate a
postmodify for the second load if the destination register
overlaps with the base register. */
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& reg_overlap_mentioned_p (operands[0], operands[1]))
{
rtx base = XEXP (operands[1], 0);
@@ -1612,7 +1612,7 @@ ia64_split_tmode_move (rtx operands[])
fixup[1] = ia64_split_tmode (out, operands[0], reversed, dead);
#define MAYBE_ADD_REG_INC_NOTE(INSN, EXP) \
- if (GET_CODE (EXP) == MEM \
+ if (MEM_P (EXP) \
&& (GET_CODE (XEXP (EXP, 0)) == POST_MODIFY \
|| GET_CODE (XEXP (EXP, 0)) == POST_INC \
|| GET_CODE (XEXP (EXP, 0)) == POST_DEC)) \
@@ -1725,7 +1725,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
if (register_operand (operands[1], mode))
operands[1] = spill_xfmode_rfmode_operand (operands[1], 1, mode);
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
/* Don't word-swap when reading in the value. */
out[0] = gen_rtx_REG (DImode, REGNO (op0));
@@ -1757,7 +1757,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
{
rtx in[2];
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
/* Don't word-swap when writing out the value. */
in[0] = gen_rtx_REG (DImode, REGNO (operands[1]));
@@ -1778,7 +1778,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
rtx memt, memx, in = operands[1];
if (CONSTANT_P (in))
in = validize_mem (force_const_mem (mode, in));
- if (GET_CODE (in) == MEM)
+ if (MEM_P (in))
memt = adjust_address (in, TImode, 0);
else
{
@@ -5923,7 +5923,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
/* This is needed if a pseudo used as a call_operand gets spilled to a
stack slot. */
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
return GR_REGS;
break;
@@ -5940,7 +5940,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
register_operand when INSN_SCHEDULING is defined. Or alternatively,
stop the paradoxical subreg stupidity in the *_operand functions
in recog.c. */
- if (GET_CODE (x) == MEM
+ if (MEM_P (x)
&& (GET_MODE (x) == SImode || GET_MODE (x) == HImode
|| GET_MODE (x) == QImode))
return GR_REGS;
@@ -5964,7 +5964,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
crtl->has_nonlocal_goto is true. This is relatively
common for C++ programs that use exceptions. To reproduce,
return NO_REGS and compile libstdc++. */
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
return GR_REGS;
/* This can happen when we take a BImode subreg of a DImode value,
@@ -9633,7 +9633,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
dest = ia64_single_set (consumer);
gcc_assert (dest);
mem = SET_DEST (dest);
- gcc_assert (mem && GET_CODE (mem) == MEM);
+ gcc_assert (mem && MEM_P (mem));
return reg_mentioned_p (reg, mem);
}
@@ -9681,7 +9681,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
}
/* Note that LO_SUM is used for GOT loads. */
- gcc_assert (GET_CODE (mem) == LO_SUM || GET_CODE (mem) == MEM);
+ gcc_assert (GET_CODE (mem) == LO_SUM || MEM_P (mem));
return reg_mentioned_p (reg, mem);
}
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 5322e66e1be..d22817af05b 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -4587,7 +4587,7 @@
element into a register without bothering to see whether that
is necessary given the operand predicate. Check for MEM just
in case someone fixes this. */
- if (GET_CODE (op0) == MEM)
+ if (MEM_P (op0))
addr = XEXP (op0, 0);
else
{
@@ -4604,7 +4604,7 @@
set = single_set (last);
gcc_assert (rtx_equal_p (SET_DEST (set), op0)
- && GET_CODE (SET_SRC (set)) == MEM);
+ && MEM_P (SET_SRC (set)));
addr = XEXP (SET_SRC (set), 0);
gcc_assert (!rtx_equal_p (addr, op0));
}
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index c1f3e09322c..4b78dcf4971 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -308,14 +308,14 @@
;; POST_MODIFY with a REG as displacement.
(define_predicate "destination_operand"
(and (match_operand 0 "nonimmediate_operand")
- (match_test "GET_CODE (op) != MEM
+ (match_test "!MEM_P (op)
|| GET_CODE (XEXP (op, 0)) != POST_MODIFY
|| !REG_P (XEXP (XEXP (XEXP (op, 0), 1), 1))")))
;; Like destination_operand, but don't allow any post-increments.
(define_predicate "not_postinc_destination_operand"
(and (match_operand 0 "nonimmediate_operand")
- (match_test "GET_CODE (op) != MEM
+ (match_test "!MEM_P (op)
|| GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
;; Like memory_operand, but don't allow post-increments.
@@ -372,7 +372,7 @@
;; Like move_operand but don't allow post-increments.
(define_predicate "not_postinc_move_operand"
(and (match_operand 0 "move_operand")
- (match_test "GET_CODE (op) != MEM
+ (match_test "!MEM_P (op)
|| GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC")))
;; True if OP is a register operand that is (or could be) a GR reg.
@@ -419,7 +419,7 @@
{
unsigned int regno;
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
return true;
if (SUBREG_P (op))
op = SUBREG_REG (op);
@@ -434,7 +434,7 @@
{
unsigned int regno;
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
return true;
if (SUBREG_P (op))
op = SUBREG_REG (op);
@@ -449,7 +449,7 @@
{
unsigned int regno;
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
return true;
if (SUBREG_P (op))
op = SUBREG_REG (op);
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index 2092093b877..74e52a16c7b 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -469,7 +469,7 @@ iq2000_count_memory_refs (rtx op, int num)
}
/* Skip MEM if passed, otherwise handle movsi of address. */
- addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
+ addr = (!MEM_P (op)) ? op : XEXP (op, 0);
/* Loop, going through the address RTL. */
do
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index 0ff9d01998a..ac34adf4c0f 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -510,10 +510,10 @@
""
"
{
- if (optimize && GET_CODE (operands[1]) == MEM)
+ if (optimize && MEM_P (operands[1]))
operands[1] = force_not_mem (operands[1]);
- if (GET_CODE (operands[1]) != MEM)
+ if (!MEM_P (operands[1]))
{
rtx op1 = gen_lowpart (SImode, operands[1]);
rtx temp = gen_reg_rtx (SImode);
@@ -540,10 +540,10 @@
""
"
{
- if (optimize && GET_CODE (operands[1]) == MEM)
+ if (optimize && MEM_P (operands[1]))
operands[1] = force_not_mem (operands[1]);
- if (GET_CODE (operands[1]) != MEM)
+ if (!MEM_P (operands[1]))
{
rtx op0 = gen_lowpart (SImode, operands[0]);
rtx op1 = gen_lowpart (SImode, operands[1]);
@@ -572,10 +572,10 @@
""
"
{
- if (optimize && GET_CODE (operands[1]) == MEM)
+ if (optimize && MEM_P (operands[1]))
operands[1] = force_not_mem (operands[1]);
- if (GET_CODE (operands[1]) != MEM)
+ if (!MEM_P (operands[1]))
{
rtx op1 = gen_lowpart (SImode, operands[1]);
rtx temp = gen_reg_rtx (SImode);
@@ -828,8 +828,8 @@
{
if (!reload_in_progress
&& !reload_completed
- && GET_CODE (operands[0]) == MEM
- && (GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[0])
+ && (MEM_P (operands[1])
|| CONST_DOUBLE_P (operands[1])))
operands[1] = copy_to_mode_reg (SFmode, operands[1]);
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index c8f4ef37fc8..e75fb05cac7 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -118,7 +118,7 @@
rtx addr, plus0, plus1;
/* Eliminate non-memory operations. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return 0;
/* Dword operations really put out 2 instructions, so eliminate them. */
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index e52354eb8d8..76fe95bbf18 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -105,7 +105,7 @@
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operand0) == MEM)
+ if (MEM_P (operand0))
{
/* Source operand for store must be in a register. */
operands[1] = force_reg (QImode, operands[1]);
@@ -121,7 +121,7 @@
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
/* Source operand for store must be in a register. */
operands[1] = force_reg (HImode, operands[1]);
@@ -137,9 +137,9 @@
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
|| (SUBREG_P (operands[0])
- && GET_CODE (SUBREG_REG (operands[0])) == MEM))
+ && MEM_P (SUBREG_REG (operands[0]))))
{
/* Source operand for store must be in a register. */
operands[1] = force_reg (SImode, operands[1]);
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 922ea03ce80..4a122a76908 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -131,7 +131,7 @@ static GTY(()) rtx patternr[30];
static int
far_addr_space_p (rtx x)
{
- if (GET_CODE (x) != MEM)
+ if (!MEM_P (x))
return 0;
#if DEBUG0
fprintf(stderr, "\033[35mfar_addr_space: "); debug_rtx(x);
@@ -694,7 +694,7 @@ m32c_preferred_reload_class (rtx x, reg_class_t rclass)
fprintf (stderr, "%s\n", class_names[rclass]);
debug_rtx (x);
- if (GET_CODE (x) == MEM
+ if (MEM_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
fprintf (stderr, "Glorm!\n");
@@ -754,7 +754,7 @@ m32c_secondary_reload_class (int rclass, machine_mode mode, rtx x)
debug_rtx (x);
#endif
if (mode == QImode
- && GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
+ && MEM_P (x) && (cc & ~class_contents[R23_REGS][0]) == 0)
return QI_REGS;
if (reg_classes_intersect_p (rclass, CR_REGS)
&& REG_P (x)
@@ -875,7 +875,7 @@ m32c_matches_constraint_p (rtx value, int constraint)
{
/* This is the common "src/dest" address */
rtx r;
- if (GET_CODE (value) == MEM && CONSTANT_P (XEXP (value, 0)))
+ if (MEM_P (value) && CONSTANT_P (XEXP (value, 0)))
return true;
if (RTX_IS ("ms") || RTX_IS ("m+si"))
return true;
@@ -1680,7 +1680,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
/* This is the double indirection detection, but it currently
doesn't work as cleanly as this code implies, so until we've had
a chance to debug it, leave it disabled. */
- if (TARGET_A24 && GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) != PLUS)
+ if (TARGET_A24 && MEM_P (x) && GET_CODE (XEXP (x, 0)) != PLUS)
{
#if DEBUG_DOUBLE
fprintf (stderr, "double indirect\n");
@@ -2809,7 +2809,7 @@ m32c_print_operand_punct_valid_p (unsigned char c)
static void
m32c_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx address)
{
- if (GET_CODE (address) == MEM)
+ if (MEM_P (address))
address = XEXP (address, 0);
else
/* cf: gcc.dg/asm-4.c. */
@@ -3132,7 +3132,7 @@ m32c_illegal_subreg_p (rtx op)
unsigned int i;
machine_mode src_mode, dest_mode;
- if (GET_CODE (op) == MEM
+ if (MEM_P (op)
&& ! m32c_legitimate_address_p (Pmode, XEXP (op, 0), false))
{
return true;
@@ -3204,8 +3204,8 @@ m32c_mov_ok (rtx * operands, machine_mode mode ATTRIBUTE_UNUSED)
if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
- if (GET_CODE (op0) == MEM
- && GET_CODE (op1) == MEM
+ if (MEM_P (op0)
+ && MEM_P (op1)
&& ! reload_completed)
{
#if DEBUG_MOV_OK
@@ -3246,7 +3246,7 @@ m32c_subreg (machine_mode outer,
just rewrite them. */
if (SUBREG_P (x)
&& SUBREG_BYTE (x) == 0
- && GET_CODE (SUBREG_REG (x)) == MEM
+ && MEM_P (SUBREG_REG (x))
&& (GET_MODE_SIZE (GET_MODE (x))
== GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)))))
{
@@ -3256,12 +3256,12 @@ m32c_subreg (machine_mode outer,
}
/* Push/pop get done as smaller push/pops. */
- if (GET_CODE (x) == MEM
+ if (MEM_P (x)
&& (GET_CODE (XEXP (x, 0)) == PRE_DEC
|| GET_CODE (XEXP (x, 0)) == POST_INC))
return gen_rtx_MEM (outer, XEXP (x, 0));
if (SUBREG_P (x)
- && GET_CODE (XEXP (x, 0)) == MEM
+ && MEM_P (XEXP (x, 0))
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
@@ -3270,7 +3270,7 @@ m32c_subreg (machine_mode outer,
{
rtx r = simplify_gen_subreg (outer, x, inner, byte);
if (SUBREG_P (r)
- && GET_CODE (x) == MEM
+ && MEM_P (x)
&& MEM_VOLATILE_P (x))
{
/* Volatile MEMs don't get simplified, but we need them to
@@ -3334,7 +3334,7 @@ m32c_prepare_move (rtx * operands, machine_mode mode)
}
if (TARGET_A16 && mode == PSImode)
return m32c_split_move (operands, mode, 1);
- if ((GET_CODE (operands[0]) == MEM)
+ if ((MEM_P (operands[0]))
&& (GET_CODE (XEXP (operands[0], 0)) == PRE_MODIFY))
{
rtx pmv = XEXP (operands[0], 0);
@@ -3369,7 +3369,7 @@ m32c_split_psi_p (rtx * operands)
#endif
return 1;
}
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == POST_INC)
{
#if DEBUG_SPLIT
@@ -3446,7 +3446,7 @@ m32c_split_move (rtx * operands, machine_mode mode, int split_all)
if (TARGET_A24
&& split_all != 3
&& (mode == SImode || mode == PSImode)
- && !(GET_CODE (operands[1]) == MEM
+ && !(MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == POST_INC))
return 0;
@@ -3462,7 +3462,7 @@ m32c_split_move (rtx * operands, machine_mode mode, int split_all)
}
/* Split pushes by emitting a sequence of smaller pushes. */
- if (GET_CODE (d[0]) == MEM && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
+ if (MEM_P (d[0]) && GET_CODE (XEXP (d[0], 0)) == PRE_DEC)
{
for (si = parts - 1; si >= 0; si--)
{
@@ -3476,7 +3476,7 @@ m32c_split_move (rtx * operands, machine_mode mode, int split_all)
rv = 1;
}
/* Likewise for pops. */
- else if (GET_CODE (s[0]) == MEM && GET_CODE (XEXP (s[0], 0)) == POST_INC)
+ else if (MEM_P (s[0]) && GET_CODE (XEXP (s[0], 0)) == POST_INC)
{
for (di = 0; di < parts; di++)
{
@@ -3915,7 +3915,7 @@ m32c_expand_insv (rtx *operands)
}
if (!can_create_pseudo_p ()
- || (GET_CODE (op0) == MEM && MEM_VOLATILE_P (op0)))
+ || (MEM_P (op0) && MEM_VOLATILE_P (op0)))
src0 = op0;
else
{
@@ -3925,7 +3925,7 @@ m32c_expand_insv (rtx *operands)
if (GET_MODE (op0) == HImode
&& INTVAL (operands[2]) >= 8
- && GET_CODE (op0) == MEM)
+ && MEM_P (op0))
{
/* We are little endian. */
rtx new_mem = gen_rtx_MEM (QImode, plus_constant (Pmode,
@@ -4364,8 +4364,8 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
/* Check for comparisons against memory - between volatiles and
aliases, we just can't risk this one. */
- if (GET_CODE (operands[0]) == MEM
- || GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0])
+ || MEM_P (operands[0]))
{
#if DEBUG_CMP
fprintf(stderr, "comparisons with memory:\n");
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index 2c66da5f284..48e9ee1f5af 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -151,7 +151,7 @@
(define_predicate "mra_nopp_operand"
(match_operand 0 "mra_operand" "")
{
- if (GET_CODE (op) == MEM
+ if (MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == PRE_DEC
|| (GET_CODE (XEXP (op, 0)) == POST_INC)))
return 0;
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 0fb4b059daa..0f4c1f4fda9 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -3082,10 +3082,10 @@ output_move_himode (rtx *operands)
{
if (operands[1] == const0_rtx
&& (DATA_REG_P (operands[0])
- || GET_CODE (operands[0]) == MEM)
+ || MEM_P (operands[0]))
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM
+ || !(MEM_P (operands[0])
&& MEM_VOLATILE_P (operands[0]))))
return "clr%.w %0";
else if (operands[1] == const0_rtx
@@ -3111,7 +3111,7 @@ output_move_qimode (rtx *operands)
byte pushes. The 5200 (ColdFire) does not do this. */
/* This case is generated by pushqi1 pattern now. */
- gcc_assert (!(GET_CODE (operands[0]) == MEM
+ gcc_assert (!(MEM_P (operands[0])
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
&& ! ADDRESS_REG_P (operands[1])
@@ -3120,7 +3120,7 @@ output_move_qimode (rtx *operands)
/* clr and st insns on 68000 read before writing. */
if (!ADDRESS_REG_P (operands[0])
&& ((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+ || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
{
if (operands[1] == const0_rtx)
return "clr%.b %0";
@@ -3154,7 +3154,7 @@ output_move_stricthi (rtx *operands)
if (operands[1] == const0_rtx
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+ || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
return "clr%.w %0";
return "move%.w %1,%0";
}
@@ -3165,7 +3165,7 @@ output_move_strictqi (rtx *operands)
if (operands[1] == const0_rtx
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+ || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
return "clr%.b %0";
return "move%.b %1,%0";
}
@@ -3219,7 +3219,7 @@ handle_move_double (rtx operands[2],
optype0 = POPOP;
else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
optype0 = PUSHOP;
- else if (GET_CODE (operands[0]) == MEM)
+ else if (MEM_P (operands[0]))
optype0 = MEMOP;
else
optype0 = RNDOP;
@@ -3234,7 +3234,7 @@ handle_move_double (rtx operands[2],
optype1 = POPOP;
else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
optype1 = PUSHOP;
- else if (GET_CODE (operands[1]) == MEM)
+ else if (MEM_P (operands[1]))
optype1 = MEMOP;
else
optype1 = RNDOP;
@@ -3714,11 +3714,11 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
operand1 = alter_subreg (&temp, true);
}
- if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
+ if (scratch_reg && reload_in_progress && MEM_P (operand0)
&& ((tem = find_replacement (&XEXP (operand0, 0)))
!= XEXP (operand0, 0)))
operand0 = gen_rtx_MEM (GET_MODE (operand0), tem);
- if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
+ if (scratch_reg && reload_in_progress && MEM_P (operand1)
&& ((tem = find_replacement (&XEXP (operand1, 0)))
!= XEXP (operand1, 0)))
operand1 = gen_rtx_MEM (GET_MODE (operand1), tem);
@@ -3726,10 +3726,10 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* Handle secondary reloads for loads/stores of FP registers where
the address is symbolic by using the scratch register */
if (fp_reg_operand (operand0, mode)
- && ((GET_CODE (operand1) == MEM
+ && ((MEM_P (operand1)
&& ! memory_address_p (DFmode, XEXP (operand1, 0)))
|| ((SUBREG_P (operand1)
- && GET_CODE (XEXP (operand1, 0)) == MEM
+ && MEM_P (XEXP (operand1, 0))
&& !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
&& scratch_reg)
{
@@ -3757,10 +3757,10 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
return 1;
}
else if (fp_reg_operand (operand1, mode)
- && ((GET_CODE (operand0) == MEM
+ && ((MEM_P (operand0)
&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
|| ((SUBREG_P (operand0))
- && GET_CODE (XEXP (operand0, 0)) == MEM
+ && MEM_P (XEXP (operand0, 0))
&& !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
&& scratch_reg)
{
@@ -3839,7 +3839,7 @@ split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
/* simplify_subreg refuses to split volatile memory addresses,
but we still have to handle it. */
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
lo_half[num] = adjust_address (op, SImode, 4);
hi_half[num] = adjust_address (op, SImode, 0);
@@ -4184,7 +4184,7 @@ notice_update_cc (rtx exp, rtx insn)
&& !FP_REG_P (SET_SRC (exp))
&& GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
&& (REG_P (SET_SRC (exp))
- || GET_CODE (SET_SRC (exp)) == MEM
+ || MEM_P (SET_SRC (exp))
|| CONST_DOUBLE_P (SET_SRC (exp))))
CC_STATUS_INIT;
else if (SET_DEST (exp) != pc_rtx)
@@ -4245,7 +4245,7 @@ notice_update_cc (rtx exp, rtx insn)
&& reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
cc_status.value2 = 0;
/* Check for PRE_DEC in dest modifying a register used in src. */
- if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM
+ if (cc_status.value1 && MEM_P (cc_status.value1)
&& GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC
&& cc_status.value2
&& reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0),
@@ -4498,7 +4498,7 @@ print_operand (FILE *file, rtx op, int letter)
else
fputs (M68K_REGNAME(REGNO (op)), file);
}
- else if (GET_CODE (op) == MEM)
+ else if (MEM_P (op))
{
output_address (GET_MODE (op), XEXP (op, 0));
if (letter == 'd' && ! TARGET_68020
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index ce4f39c953b..c995f4469c3 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -504,10 +504,10 @@
(match_operand:SI 1 "general_operand" "mr,ma,KTr,Ksr,>")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
return "cmpm%.l %1,%0";
if (REG_P (operands[1])
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+ || (!REG_P (operands[0]) && !MEM_P (operands[0])))
{
cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.l %d0,%d1";
@@ -527,7 +527,7 @@
"TARGET_COLDFIRE"
{
if (REG_P (operands[1])
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+ || (!REG_P (operands[0]) && !MEM_P (operands[0])))
{
cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.l %d0,%d1";
@@ -564,10 +564,10 @@
(match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
return "cmpm%.w %1,%0";
if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+ || (!REG_P (operands[0]) && !MEM_P (operands[0])))
{
cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.w %d0,%d1";
@@ -603,10 +603,10 @@
(match_operand:QI 1 "general_operand" "dm,nd,>")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[0]) && MEM_P (operands[1]))
return "cmpm%.b %1,%0";
if (REG_P (operands[1])
- || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
+ || (!REG_P (operands[0]) && !MEM_P (operands[0])))
{
cc_status.flags |= CC_REVERSED; /*|*/
return "cmp%.b %d0,%d1";
@@ -770,7 +770,7 @@
"!TARGET_COLDFIRE
&& !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
operands[0] = adjust_address (operands[0], QImode,
INTVAL (operands[1]) / 8);
@@ -794,7 +794,7 @@
"TARGET_COLDFIRE
&& !(REG_P (operands[0]) && !IN_RANGE (INTVAL (operands[1]), 0, 31))"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
operands[0] = adjust_address (operands[0], QImode,
INTVAL (operands[1]) / 8);
@@ -936,7 +936,7 @@
the m68k doesn't consider PC-relative addresses to be writable. */
if (symbolic_operand (operands[0], SImode))
operands[0] = force_reg (SImode, XEXP (operands[0], 0));
- else if (GET_CODE (operands[0]) == MEM
+ else if (MEM_P (operands[0])
&& symbolic_operand (XEXP (operands[0], 0), SImode))
operands[0] = gen_rtx_MEM (SImode,
force_reg (SImode, XEXP (operands[0], 0)));
@@ -1184,7 +1184,7 @@
if (operands[1] == CONST0_RTX (SFmode)
/* clr insns on 68000 read before writing. */
&& ((TARGET_68010 || TARGET_COLDFIRE)
- || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
+ || !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))))
{
if (ADDRESS_REG_P (operands[0]))
{
@@ -1231,7 +1231,7 @@
else
output_asm_insn ("clr%.l %0", xoperands);
} else
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& symbolic_operand (XEXP (operands[0], 0), SImode))
output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands);
else
@@ -1416,7 +1416,7 @@
{
/* Don't allow writes to memory except via a register; the
m68k doesn't consider PC-relative addresses to be writable. */
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& symbolic_operand (XEXP (operands[0], 0), SImode))
operands[0] = gen_rtx_MEM (XFmode,
force_reg (SImode, XEXP (operands[0], 0)));
@@ -1588,7 +1588,7 @@
CC_STATUS_INIT;
return "move%.l %1,%0";
}
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
operands[1] = adjust_address (operands[1], QImode, 3);
return "move%.b %1,%0";
})
@@ -1600,7 +1600,7 @@
"!TARGET_COLDFIRE"
{
if (REG_P (operands[0])
- && (GET_CODE (operands[1]) == MEM
+ && (MEM_P (operands[1])
|| CONST_INT_P (operands[1])))
{
/* Must clear condition codes, since the move.w bases them on
@@ -1615,7 +1615,7 @@
CC_STATUS_INIT;
return "move%.l %1,%0";
}
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
operands[1] = adjust_address (operands[1], QImode, 1);
return "move%.b %1,%0";
})
@@ -1633,7 +1633,7 @@
CC_STATUS_INIT;
return "move%.l %1,%0";
}
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
operands[1] = adjust_address (operands[1], QImode, 2);
return "move%.w %1,%0";
})
@@ -1709,15 +1709,15 @@
(zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
""
{
- if (GET_CODE (operands[0]) == MEM
- && GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[0])
+ && MEM_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
})
(define_insn_and_split "*zero_extendsidi2"
[(set (match_operand:DI 0 "nonimmediate_operand" "")
(zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
+ "!MEM_P (operands[0]) || !MEM_P (operands[1])"
"#"
""
[(set (match_dup 2)
@@ -2278,7 +2278,7 @@
operands[4] = operands[1];
else
operands[4] = adjust_address (operands[1], SImode, 4);
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
output_asm_insn ("move%.l %4,%3", operands);
output_asm_insn ("move%.l %1,%0\;smi %2", operands);
@@ -2286,7 +2286,7 @@
output_asm_insn ("extb%.l %2", operands);
else
output_asm_insn ("ext%.w %2\;ext%.l %2", operands);
- if (GET_CODE (operands[1]) != MEM
+ if (!MEM_P (operands[1])
|| GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
output_asm_insn ("move%.l %4,%3", operands);
return "sub%.l %2,%3\;subx%.l %2,%0";
@@ -2366,7 +2366,7 @@
{
if (DATA_REG_P (operands[2]))
return "add%.l %R2,%R0\;addx%.l %2,%0";
- else if (GET_CODE (operands[2]) == MEM
+ else if (MEM_P (operands[2])
&& GET_CODE (XEXP (operands[2], 0)) == POST_INC)
return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0";
else
@@ -2411,7 +2411,7 @@
}
else
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
CC_STATUS_INIT;
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
@@ -2442,7 +2442,7 @@
{
operands[2] = operands[0];
operands[3] = gen_label_rtx();
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
@@ -2863,7 +2863,7 @@
{
if (DATA_REG_P (operands[2]))
return "sub%.l %R2,%R0\;subx%.l %2,%0";
- else if (GET_CODE (operands[2]) == MEM
+ else if (MEM_P (operands[2])
&& GET_CODE (XEXP (operands[2], 0)) == POST_INC)
{
return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0";
@@ -2910,7 +2910,7 @@
}
else
{
- gcc_assert (GET_CODE (operands[0]) == MEM);
+ gcc_assert (MEM_P (operands[0]));
CC_STATUS_INIT;
if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
{
@@ -3724,7 +3724,7 @@
if (GET_MODE (operands[1]) == SImode)
return "or%.l %1,%0";
byte_mode = (GET_MODE (operands[1]) == QImode);
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
byte_mode ? 3 : 2);
if (byte_mode)
@@ -3829,7 +3829,7 @@
CC_STATUS_INIT;
byte_mode = (GET_MODE (operands[1]) == QImode);
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode,
byte_mode ? 3 : 2);
if (byte_mode)
@@ -4380,7 +4380,7 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0";
@@ -6782,7 +6782,7 @@
CC_STATUS_INIT;
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1";
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
return "subq%.w #1,%0\;jcc %l1";
return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
})
@@ -6802,7 +6802,7 @@
CC_STATUS_INIT;
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
return "subq%.l #1,%0\;jcc %l1";
return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
})
@@ -6825,7 +6825,7 @@
CC_STATUS_INIT;
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1";
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
return "subq%.w #1,%0\;jcc %l1";
return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1";
})
@@ -6860,7 +6860,7 @@
CC_STATUS_INIT;
if (DATA_REG_P (operands[0]))
return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1";
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
return "subq%.l #1,%0\;jcc %l1";
return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1";
})
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index a90bf61a948..3238211a0de 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -25,7 +25,7 @@
(match_code "const_int,const_double,const,symbol_ref,label_ref,subreg,reg,mem")
{
if (TARGET_PCREL
- && GET_CODE (op) == MEM
+ && MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF
|| GET_CODE (XEXP (op, 0)) == CONST))
@@ -40,7 +40,7 @@
(define_predicate "nonimmediate_src_operand"
(match_code "subreg,reg,mem")
{
- if (TARGET_PCREL && GET_CODE (op) == MEM
+ if (TARGET_PCREL && MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF
|| GET_CODE (XEXP (op, 0)) == CONST))
@@ -54,7 +54,7 @@
(define_predicate "memory_src_operand"
(match_code "subreg,mem")
{
- if (TARGET_PCREL && GET_CODE (op) == MEM
+ if (TARGET_PCREL && MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF
|| GET_CODE (XEXP (op, 0)) == CONST))
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 4df4551fd95..30d8c8b7c58 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -1291,7 +1291,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "mov\t%0,%1"; /* r-r*/
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
return "lrw\t%0,[%1]"; /* a-R */
@@ -1326,7 +1326,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "lrw\t%0, %1"; /* Into the literal pool. */
}
- else if (GET_CODE (dst) == MEM) /* m-r */
+ else if (MEM_P (dst)) /* m-r */
switch (GET_MODE (dst))
{
case E_SImode:
@@ -1365,7 +1365,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
else
return "mov %0,%1\n\tmov %R0,%R1";
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
{
rtx memexp = XEXP (src, 0);
int dstreg = REGNO (dst);
@@ -1437,7 +1437,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && REG_P (src))
+ else if (MEM_P (dst) && REG_P (src))
return "stw\t%1,%0\n\tstw\t%R1,%R0";
else
gcc_unreachable ();
@@ -1987,7 +1987,7 @@ mcore_expand_prolog (void)
x = DECL_RTL (current_function_decl);
- gcc_assert (GET_CODE (x) == MEM);
+ gcc_assert (MEM_P (x));
x = XEXP (x, 0);
@@ -2911,7 +2911,7 @@ mcore_mark_dllexport (tree decl)
rtlname = XEXP (DECL_RTL (decl), 0);
- if (GET_CODE (rtlname) == MEM)
+ if (MEM_P (rtlname))
rtlname = XEXP (rtlname, 0);
gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
oldname = XSTR (rtlname, 0);
@@ -2946,7 +2946,7 @@ mcore_mark_dllimport (tree decl)
rtlname = XEXP (DECL_RTL (decl), 0);
- if (GET_CODE (rtlname) == MEM)
+ if (MEM_P (rtlname))
rtlname = XEXP (rtlname, 0);
gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
oldname = XSTR (rtlname, 0);
@@ -3032,8 +3032,8 @@ mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIB
else if ((TREE_CODE (decl) == FUNCTION_DECL
|| TREE_CODE (decl) == VAR_DECL)
&& DECL_RTL (decl) != NULL_RTX
- && GET_CODE (DECL_RTL (decl)) == MEM
- && GET_CODE (XEXP (DECL_RTL (decl), 0)) == MEM
+ && MEM_P (DECL_RTL (decl))
+ && MEM_P (XEXP (DECL_RTL (decl), 0))
&& GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
&& mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
{
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index c71cb67fdb6..dab98beca28 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -1185,7 +1185,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
}")
@@ -1207,7 +1207,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
else if (CONSTANT_P (operands[1])
&& (!CONST_INT_P (operands[1])
@@ -1240,7 +1240,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]);
else if (CONSTANT_P (operands[1])
&& (!CONST_INT_P (operands[1])
@@ -1272,7 +1272,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);
else if (CONST_INT_P (operands[1])
&& ! CONST_OK_FOR_I (INTVAL (operands[1]))
@@ -1302,7 +1302,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}")
@@ -1324,7 +1324,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}")
@@ -1365,7 +1365,7 @@
only if at least two registers. The last register must be r15. */
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[1]) != MEM
+ || !MEM_P (operands[1])
|| XEXP (operands[1], 0) != stack_pointer_rtx
|| !REG_P (operands[0])
|| REGNO (operands[0]) + INTVAL (operands[2]) != 16)
@@ -1403,7 +1403,7 @@
only if at least two registers. The last register must be r15. */
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[0]) != MEM
+ || !MEM_P (operands[0])
|| XEXP (operands[0], 0) != stack_pointer_rtx
|| !REG_P (operands[1])
|| REGNO (operands[1]) + INTVAL (operands[2]) != 16)
@@ -1529,7 +1529,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! register_operand (XEXP (operands[0], 0), SImode)
&& ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
@@ -1551,7 +1551,7 @@
""
"
{
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& ! register_operand (XEXP (operands[0], 0), SImode)
&& ! mcore_symbolic_address_p (XEXP (operands[0], 0)))
operands[1] = gen_rtx_MEM (GET_MODE (operands[1]),
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index 5bc901e55ea..d34f9f7125b 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -40,7 +40,7 @@
(match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
{
/* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
- if (GET_CODE (op) == MEM && GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == LABEL_REF)
return 1;
return general_operand (op, mode);
@@ -69,7 +69,7 @@
if (! reload_in_progress)
return 0;
- return GET_CODE (op) == MEM;
+ return MEM_P (op);
})
;; Nonzero if OP is a valid source operand for an arithmetic insn.
@@ -263,7 +263,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+ || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
return 0;
dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -302,7 +302,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+ || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
|| !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return 0;
@@ -317,7 +317,7 @@
|| !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
- || GET_CODE (SET_DEST (elt)) != MEM
+ || !MEM_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 800baefc070..e89c527cc41 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -288,7 +288,7 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
rtx addr, plus0, plus1;
/* Eliminate non-memory operations. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return 0;
/* dword operations really put out 2 instructions, so eliminate them. */
@@ -348,7 +348,7 @@ double_memory_operand (rtx op, machine_mode mode)
{
rtx addr;
- if (GET_CODE (op) != MEM || !memory_operand (op, mode))
+ if (!MEM_P (op) || !memory_operand (op, mode))
{
/* During reload, we accept a pseudo register if it has an
appropriate memory address. If we don't do this, we will
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index a4ffb50797f..a83d7ff2d80 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -1218,7 +1218,7 @@
""
{
if (flag_pic == 2) {
- if (GET_CODE (operands[1]) == MEM
+ if (MEM_P (operands[1])
&& !microblaze_legitimate_address_p (DFmode, XEXP (operands[1],0), 0))
{
rtx ptr_reg;
diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md
index bf28b63a16b..70ac4997705 100644
--- a/gcc/config/mmix/mmix.md
+++ b/gcc/config/mmix/mmix.md
@@ -521,7 +521,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
""
"
{
- if (GET_CODE (operands[0]) != MEM)
+ if (!MEM_P (operands[0]))
{
rtx stack_slot;
@@ -555,7 +555,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
""
"
{
- if (GET_CODE (operands[0]) != MEM)
+ if (!MEM_P (operands[0]))
{
rtx stack_slot;
@@ -630,7 +630,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
""
"
{
- if (GET_CODE (operands[0]) != MEM)
+ if (!MEM_P (operands[0]))
{
/* FIXME: There should be a way to say: 'put this in operands[0]
but *after* the expanded insn'. */
@@ -665,7 +665,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
""
"
{
- if (GET_CODE (operands[1]) != MEM)
+ if (!MEM_P (operands[1]))
{
rtx stack_slot;
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index 40796b45883..0d3421a0121 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3168,7 +3168,7 @@ msp430_fixup_compare_operands (machine_mode my_mode, rtx * operands)
const_op_idx = 2;
if (!REG_P (operands[const_op_idx])
- && GET_CODE (operands[const_op_idx]) != MEM)
+ && !MEM_P (operands[const_op_idx]))
operands[const_op_idx] = copy_to_mode_reg (my_mode, operands[const_op_idx]);
}
@@ -3194,7 +3194,7 @@ msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
else
rv = simplify_gen_subreg (mode, ireg, imode, byte);
}
- else if (GET_CODE (r) == MEM)
+ else if (MEM_P (r))
rv = adjust_address (r, mode, byte);
else if (GET_CODE (r) == SYMBOL_REF
&& (byte == 0 || byte == 2)
diff --git a/gcc/config/nds32/nds32-fp-as-gp.c b/gcc/config/nds32/nds32-fp-as-gp.c
index b8b038aaa7a..6b5b84fa3d8 100644
--- a/gcc/config/nds32/nds32-fp-as-gp.c
+++ b/gcc/config/nds32/nds32-fp-as-gp.c
@@ -84,7 +84,7 @@ nds32_get_symbol_count (void)
so don't count any other than SImode.
MEM for QImode and HImode will wrap by ZERO_EXTEND
or SIGN_EXTEND */
- if (GET_CODE (mem) == MEM)
+ if (MEM_P (mem))
symbol_count++;
}
}
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index 7a767e7e426..96fae88d2cf 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -60,7 +60,7 @@
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| !REG_P (operands[0])
- || GET_CODE (operands[1]) != MEM
+ || !MEM_P (operands[1])
|| MEM_VOLATILE_P (operands[1])
|| REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
FAIL;
@@ -1908,7 +1908,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[0]) != MEM
+ || !MEM_P (operands[0])
|| !REG_P (operands[1])
|| MEM_VOLATILE_P (operands[0])
|| REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index 649b34d3c5b..7cfa77eb5cd 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -76,7 +76,7 @@ nds32_consecutive_registers_load_store_p (rtx op,
if (!REG_P (elt_reg) || GET_MODE (elt_reg) != SImode)
return false;
/* If elt_mem is not a expected mem rtx, return false. */
- if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
+ if (!MEM_P (elt_mem) || GET_MODE (elt_mem) != SImode)
return false;
/* The consecutive registers should be in (Rb,Rb+1...Re) order. */
@@ -136,7 +136,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
if (load_p)
{
if (!REG_P (SET_DEST (elt))
- || GET_CODE (SET_SRC (elt)) != MEM)
+ || !MEM_P (SET_SRC (elt)))
return false;
first_elt_regno = REGNO (SET_DEST (elt));
@@ -144,7 +144,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
else
{
if (!REG_P (SET_SRC (elt))
- || GET_CODE (SET_DEST (elt)) != MEM)
+ || !MEM_P (SET_DEST (elt)))
return false;
first_elt_regno = REGNO (SET_SRC (elt));
@@ -302,7 +302,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
index++;
- if (GET_CODE (elt_mem) != MEM
+ if (!MEM_P (elt_mem)
|| !REG_P (elt_reg)
|| REGNO (elt_reg) != FP_REGNUM)
return false;
@@ -314,7 +314,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
index++;
- if (GET_CODE (elt_mem) != MEM
+ if (!MEM_P (elt_mem)
|| !REG_P (elt_reg)
|| REGNO (elt_reg) != GP_REGNUM)
return false;
@@ -326,7 +326,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
elt_reg = push_p ? SET_SRC (elt) : SET_DEST (elt);
index++;
- if (GET_CODE (elt_mem) != MEM
+ if (!MEM_P (elt_mem)
|| !REG_P (elt_reg)
|| REGNO (elt_reg) != LP_REGNUM)
return false;
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 74c80bbd1e3..6378b7567a5 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -2253,7 +2253,7 @@ nios2_large_constant_memory_operand_p (rtx x)
{
rtx addr;
- if (GET_CODE (x) != MEM)
+ if (!MEM_P (x))
return false;
addr = XEXP (x, 0);
@@ -2904,7 +2904,7 @@ nios2_print_operand (FILE *file, rtx op, int letter)
return;
case 'o':
- if (GET_CODE (op) == MEM
+ if (MEM_P (op)
&& ((MEM_VOLATILE_P (op) && TARGET_BYPASS_CACHE_VOLATILE)
|| TARGET_BYPASS_CACHE))
{
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 39050c5e492..dd3b14c515a 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -2500,7 +2500,7 @@ nvptx_print_address_operand (FILE *file, rtx x, machine_mode)
break;
default:
- gcc_assert (GET_CODE (x) != MEM);
+ gcc_assert (!MEM_P (x));
nvptx_print_operand (file, x, 0);
break;
}
@@ -2907,7 +2907,7 @@ nvptx_call_insn_is_syscall_p (rtx_insn *insn)
if (GET_CODE (pat) == SET)
pat = SET_SRC (pat);
gcc_checking_assert (GET_CODE (pat) == CALL
- && GET_CODE (XEXP (pat, 0)) == MEM);
+ && MEM_P (XEXP (pat, 0)));
rtx addr = XEXP (XEXP (pat, 0), 0);
if (GET_CODE (addr) != SYMBOL_REF)
return false;
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index cdd2e031bf7..1df00c00dbf 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1640,7 +1640,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* We can only handle indexed addresses in the destination operand
of floating point stores. Thus, we need to break out indexed
addresses from the destination operand. */
- if (GET_CODE (operand0) == MEM && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
+ if (MEM_P (operand0) && IS_INDEX_ADDR_P (XEXP (operand0, 0)))
{
gcc_assert (can_create_pseudo_p ());
@@ -1657,7 +1657,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
unscaled indexed addresses. */
if (!TARGET_NO_SPACE_REGS
&& !cse_not_expected
- && GET_CODE (operand1) == MEM
+ && MEM_P (operand1)
&& GET_CODE (XEXP (operand1, 0)) == PLUS
&& REG_P (XEXP (XEXP (operand1, 0), 0))
&& REG_P (XEXP (XEXP (operand1, 0), 1)))
@@ -1699,12 +1699,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
operand1 = alter_subreg (&temp, true);
}
- if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM
+ if (scratch_reg && reload_in_progress && MEM_P (operand0)
&& ((tem = find_replacement (&XEXP (operand0, 0)))
!= XEXP (operand0, 0)))
operand0 = replace_equiv_address (operand0, tem);
- if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM
+ if (scratch_reg && reload_in_progress && MEM_P (operand1)
&& ((tem = find_replacement (&XEXP (operand1, 0)))
!= XEXP (operand1, 0)))
operand1 = replace_equiv_address (operand1, tem);
@@ -1855,11 +1855,11 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REG_P (operand0)
&& REGNO (operand0) < FIRST_PSEUDO_REGISTER
&& REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
- && (GET_CODE (operand1) == MEM || CONST_INT_P (operand1)))
+ && (MEM_P (operand1) || CONST_INT_P (operand1)))
{
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
- if (GET_CODE (operand1) == MEM
+ if (MEM_P (operand1)
&& !memory_address_p (GET_MODE (operand0), XEXP (operand1, 0)))
{
/* We are reloading the address into the scratch register, so we
@@ -1914,7 +1914,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
|| (GET_CODE (operand1) == HIGH
&& !symbolic_operand (XEXP (operand1, 0), VOIDmode))
/* Only `general_operands' can come here, so MEM is ok. */
- || GET_CODE (operand1) == MEM)
+ || MEM_P (operand1))
{
/* Various sets are created during RTL generation which don't
have the REG_POINTER flag correctly set. After the CSE pass,
@@ -1934,7 +1934,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
get set. In some cases, we can set the REG_POINTER flag
from the declaration for the MEM. */
if (REG_P (operand0)
- && GET_CODE (operand1) == MEM
+ && MEM_P (operand1)
&& !REG_POINTER (operand0))
{
tree decl = MEM_EXPR (operand1);
@@ -1963,7 +1963,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
return 1;
}
}
- else if (GET_CODE (operand0) == MEM)
+ else if (MEM_P (operand0))
{
if (mode == DFmode && operand1 == CONST0_RTX (mode)
&& !(reload_in_progress || reload_completed))
@@ -2380,9 +2380,9 @@ pa_singlemove_string (rtx *operands)
{
HOST_WIDE_INT intval;
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
return "stw %r1,%0";
- if (GET_CODE (operands[1]) == MEM)
+ if (MEM_P (operands[1]))
return "ldw %1,%0";
if (CONST_DOUBLE_P (operands[1]))
{
@@ -2512,7 +2512,7 @@ pa_output_move_double (rtx *operands)
optype0 = REGOP;
else if (offsettable_memref_p (operands[0]))
optype0 = OFFSOP;
- else if (GET_CODE (operands[0]) == MEM)
+ else if (MEM_P (operands[0]))
optype0 = MEMOP;
else
optype0 = RNDOP;
@@ -2523,7 +2523,7 @@ pa_output_move_double (rtx *operands)
optype1 = CNSTOP;
else if (offsettable_memref_p (operands[1]))
optype1 = OFFSOP;
- else if (GET_CODE (operands[1]) == MEM)
+ else if (MEM_P (operands[1]))
optype1 = MEMOP;
else
optype1 = RNDOP;
@@ -5056,8 +5056,8 @@ pa_adjust_insn_length (rtx_insn *insn, int length)
if (NONJUMP_INSN_P (insn)
&& GET_CODE (pat) == PARALLEL
&& GET_CODE (XVECEXP (pat, 0, 0)) == SET
- && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
- && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 1)) == MEM
+ && MEM_P (XEXP (XVECEXP (pat, 0, 0), 0))
+ && MEM_P (XEXP (XVECEXP (pat, 0, 0), 1))
&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode
&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 1)) == BLKmode)
length += compute_cpymem_length (insn) - 4;
@@ -5065,7 +5065,7 @@ pa_adjust_insn_length (rtx_insn *insn, int length)
else if (NONJUMP_INSN_P (insn)
&& GET_CODE (pat) == PARALLEL
&& GET_CODE (XVECEXP (pat, 0, 0)) == SET
- && GET_CODE (XEXP (XVECEXP (pat, 0, 0), 0)) == MEM
+ && MEM_P (XEXP (XVECEXP (pat, 0, 0), 0))
&& XEXP (XVECEXP (pat, 0, 0), 1) == const0_rtx
&& GET_MODE (XEXP (XVECEXP (pat, 0, 0), 0)) == BLKmode)
length += compute_clrmem_length (insn) - 4;
@@ -5437,7 +5437,7 @@ pa_print_operand (FILE *file, rtx x, int code)
&& (REGNO (x) & 1) == 0)
fputs ("L", file);
}
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
{
int size = GET_MODE_SIZE (GET_MODE (x));
rtx base = NULL_RTX;
@@ -6046,7 +6046,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
/* If we have something like (mem (mem (...)), we can safely assume the
inner MEM will end up in a general register after reloading, so there's
no need for a secondary reload. */
- if (GET_CODE (x) == MEM && GET_CODE (XEXP (x, 0)) == MEM)
+ if (MEM_P (x) && MEM_P (XEXP (x, 0)))
return NO_REGS;
/* Trying to load a constant into a FP register during PIC code
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 01c778368cd..f0e498e2782 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3269,9 +3269,9 @@
(use (match_operand:SI 4 "arith14_operand" ""))
(use (match_operand:SI 5 "const_int_operand" ""))])]
"!TARGET_64BIT && reload_completed && !flag_peephole2
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), SImode)
- && GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[1])
&& register_operand (XEXP (operands[1], 0), SImode)"
[(set (match_dup 7) (match_dup 9))
(set (match_dup 8) (match_dup 10))
@@ -3303,9 +3303,9 @@
(use (match_operand:SI 4 "arith14_operand" ""))
(use (match_operand:SI 5 "const_int_operand" ""))])]
"!TARGET_64BIT
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), SImode)
- && GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[1])
&& register_operand (XEXP (operands[1], 0), SImode)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))
@@ -3457,9 +3457,9 @@
(use (match_operand:DI 4 "arith14_operand" ""))
(use (match_operand:DI 5 "const_int_operand" ""))])]
"TARGET_64BIT && reload_completed && !flag_peephole2
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), DImode)
- && GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[1])
&& register_operand (XEXP (operands[1], 0), DImode)"
[(set (match_dup 7) (match_dup 9))
(set (match_dup 8) (match_dup 10))
@@ -3491,9 +3491,9 @@
(use (match_operand:DI 4 "arith14_operand" ""))
(use (match_operand:DI 5 "const_int_operand" ""))])]
"TARGET_64BIT
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), DImode)
- && GET_CODE (operands[1]) == MEM
+ && MEM_P (operands[1])
&& register_operand (XEXP (operands[1], 0), DImode)"
[(parallel [(set (match_dup 0) (match_dup 1))
(clobber (match_dup 2))
@@ -3599,7 +3599,7 @@
(use (match_operand:SI 2 "arith14_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))])]
"!TARGET_64BIT && reload_completed && !flag_peephole2
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), SImode)"
[(set (match_dup 4) (match_dup 5))
(parallel [(set (match_dup 0) (const_int 0))
@@ -3622,7 +3622,7 @@
(use (match_operand:SI 2 "arith14_operand" ""))
(use (match_operand:SI 3 "const_int_operand" ""))])]
"!TARGET_64BIT
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), SImode)"
[(parallel [(set (match_dup 0) (const_int 0))
(clobber (match_dup 1))
@@ -3713,7 +3713,7 @@
(use (match_operand:DI 2 "arith14_operand" ""))
(use (match_operand:DI 3 "const_int_operand" ""))])]
"TARGET_64BIT && reload_completed && !flag_peephole2
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), DImode)"
[(set (match_dup 4) (match_dup 5))
(parallel [(set (match_dup 0) (const_int 0))
@@ -3736,7 +3736,7 @@
(use (match_operand:DI 2 "arith14_operand" ""))
(use (match_operand:DI 3 "const_int_operand" ""))])]
"TARGET_64BIT
- && GET_CODE (operands[0]) == MEM
+ && MEM_P (operands[0])
&& register_operand (XEXP (operands[0], 0), DImode)"
[(parallel [(set (match_dup 0) (const_int 0))
(clobber (match_dup 1))
@@ -3838,7 +3838,7 @@
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
&& !(CONST_DOUBLE_P (operands[1])
- && GET_CODE (operands[0]) == MEM)
+ && MEM_P (operands[0]))
&& !TARGET_64BIT
&& !TARGET_SOFT_FLOAT"
"*
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 7a3e24a1b1f..53211af53f7 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -490,16 +490,16 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
useorder = either;
if (opcount == 2)
{
- if (GET_CODE (operands[0]) == MEM &&
- GET_CODE (operands[1]) == MEM &&
+ if (MEM_P (operands[0]) &&
+ MEM_P (operands[1]) &&
((GET_CODE (XEXP (operands[0], 0)) == POST_INC &&
GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) ||
(GET_CODE (XEXP (operands[0], 0)) == PRE_DEC &&
GET_CODE (XEXP (operands[1], 0)) == POST_INC)))
useorder = big;
- else if ((GET_CODE (operands[0]) == MEM &&
+ else if ((MEM_P (operands[0]) &&
GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) ||
- (GET_CODE (operands[1]) == MEM &&
+ (MEM_P (operands[1]) &&
GET_CODE (XEXP (operands[1], 0)) == PRE_DEC))
useorder = little;
else if (REG_P (operands[0]) && REG_P (operands[1]) &&
@@ -545,7 +545,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
optype = PUSHOP;
else if (!reload_in_progress || offsettable_memref_p (operands[op]))
optype = OFFSOP;
- else if (GET_CODE (operands[op]) == MEM)
+ else if (MEM_P (operands[op]))
optype = MEMOP;
else
optype = RNDOP;
@@ -799,7 +799,7 @@ pdp11_asm_print_operand (FILE *file, rtx x, int code)
}
else if (REG_P (x))
fprintf (file, "%s", reg_names[REGNO (x)]);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
output_address (GET_MODE (x), XEXP (x, 0));
else if (CONST_DOUBLE_P (x) && FLOAT_MODE_P (GET_MODE (x)))
{
@@ -866,13 +866,13 @@ print_operand_address (FILE *file, register rtx addr)
breg = 0;
offset = 0;
if (CONSTANT_ADDRESS_P (XEXP (addr, 0))
- || GET_CODE (XEXP (addr, 0)) == MEM)
+ || MEM_P (XEXP (addr, 0)))
{
offset = XEXP (addr, 0);
addr = XEXP (addr, 1);
}
else if (CONSTANT_ADDRESS_P (XEXP (addr, 1))
- || GET_CODE (XEXP (addr, 1)) == MEM)
+ || MEM_P (XEXP (addr, 1)))
{
offset = XEXP (addr, 1);
addr = XEXP (addr, 0);
@@ -1349,7 +1349,7 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
rtx addr;
/* Eliminate non-memory operations */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
/* Decode the address now. */
@@ -1407,7 +1407,7 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
rtx addr;
/* Eliminate non-memory operations */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
/* Decode the address now. */
@@ -1464,13 +1464,13 @@ pushpop_regeq (rtx op, int regno)
rtx addr;
/* False if not memory reference. */
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
/* Get the address of the memory reference. */
addr = XEXP (op, 0);
- if (GET_CODE (addr) == MEM)
+ if (MEM_P (addr))
addr = XEXP (addr, 0);
switch (GET_CODE (addr))
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index eae67483f63..adead56621b 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -199,7 +199,7 @@
/* Perform a quick check so we don't blow up below. */
if (GET_CODE (XVECEXP (op, 0, 0)) != SET
|| !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+ || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -220,7 +220,7 @@
|| !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| REGNO (SET_DEST (elt)) != dest_regno + i * GET_MODE_SIZE (elt_mode)
- || GET_CODE (SET_SRC (elt)) != MEM
+ || !MEM_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode)
return false;
@@ -250,7 +250,7 @@
/* Perform a quick check so we don't blow up below. */
if (GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+ || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
|| !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
@@ -272,7 +272,7 @@
|| !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| REGNO (SET_SRC (elt)) != src_regno + i * GET_MODE_SIZE (elt_mode)
- || GET_CODE (SET_DEST (elt)) != MEM
+ || !MEM_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode)
return false;
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index c1cb98f5001..4e500d5ea13 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -231,7 +231,7 @@
/* Support only loading a constant number of fixed-point registers from
memory. */
if (!CONST_INT_P (operands[2])
- || GET_CODE (operands[1]) != MEM
+ || !MEM_P (operands[1])
|| !REG_P (operands[0]))
FAIL;
@@ -289,7 +289,7 @@
/* Support only storing a constant number of fixed-point registers to
memory. */
if (!CONST_INT_P (operands[2])
- || GET_CODE (operands[0]) != MEM
+ || !MEM_P (operands[0])
|| !REG_P (operands[1]))
FAIL;
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index 779c94e038f..a667ac8f543 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -522,7 +522,7 @@ rl78_modes_tieable_p (machine_mode mode1, machine_mode mode2)
static rtx
rl78_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
{
- if (GET_CODE (r) == MEM)
+ if (MEM_P (r))
return adjust_address (r, mode, byte);
else
return simplify_gen_subreg (mode, r, omode, byte);
@@ -2233,7 +2233,7 @@ rl78_trampoline_adjust_address (rtx m_tramp)
void
rl78_expand_compare (rtx *operands)
{
- if (GET_CODE (operands[2]) == MEM)
+ if (MEM_P (operands[2]))
operands[2] = copy_to_mode_reg (GET_MODE (operands[2]), operands[2]);
}
@@ -2268,7 +2268,7 @@ rl78_peep_movhi_p (rtx *operands)
#endif
/* You can move a constant to memory as QImode, but not HImode. */
- if (GET_CODE (operands[0]) == MEM
+ if (MEM_P (operands[0])
&& !REG_P (operands[1]))
{
#if DEBUG_PEEP
@@ -2688,7 +2688,7 @@ already_contains (rtx loc, rtx value)
bool
rl78_es_addr (rtx addr)
{
- if (GET_CODE (addr) == MEM)
+ if (MEM_P (addr))
addr = XEXP (addr, 0);
if (GET_CODE (addr) != UNSPEC)
return false;
@@ -2700,7 +2700,7 @@ rl78_es_addr (rtx addr)
rtx
rl78_es_base (rtx addr)
{
- if (GET_CODE (addr) == MEM)
+ if (MEM_P (addr))
addr = XEXP (addr, 0);
addr = XVECEXP (addr, 0, 1);
if (GET_CODE (addr) == CONST
@@ -2737,7 +2737,7 @@ insn_ok_now (rtx_insn * insn)
/* We need to detect far addresses that haven't been
converted to es/lo16 format. */
for (i=0; i<recog_data.n_operands; i++)
- if (GET_CODE (OP (i)) == MEM
+ if (MEM_P (OP (i))
&& GET_MODE (XEXP (OP (i), 0)) == SImode
&& GET_CODE (XEXP (OP (i), 0)) != UNSPEC)
goto not_ok;
@@ -3901,7 +3901,7 @@ rl78_note_reg_set (char *dead, rtx d, rtx insn)
{
int r, i;
bool is_dead;
- if (GET_CODE (d) == MEM)
+ if (MEM_P (d))
rl78_note_reg_uses (dead, XEXP (d, 0), insn);
if (!REG_P (d))
@@ -4567,7 +4567,7 @@ rl78_encode_section_info (tree decl, rtx rtl, int first)
if (GET_CODE (rtlname) == SYMBOL_REF)
oldname = XSTR (rtlname, 0);
- else if (GET_CODE (rtlname) == MEM
+ else if (MEM_P (rtlname)
&& GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
oldname = XSTR (XEXP (rtlname, 0), 0);
else
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index ea04eb6b836..e529f8b173e 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -80,7 +80,7 @@ rx_pid_base_regnum (void)
static tree
rx_decl_for_addr (rtx op)
{
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
op = XEXP (op, 0);
if (GET_CODE (op) == CONST)
op = XEXP (op, 0);
@@ -940,7 +940,7 @@ rx_maybe_pidify_operand (rtx op, int copy_to_reg)
{
if (rx_pid_data_operand (op) == PID_UNENCODED)
{
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
rtx a = gen_pid_addr (gen_rtx_REG (SImode, rx_pid_base_regnum ()), XEXP (op, 0));
op = replace_equiv_address (op, a);
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index b05e8ed6ed0..e7ce44dbb43 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -66,10 +66,10 @@
after reload. */
if (reload_completed
&& SUBREG_P (op)
- && GET_CODE (SUBREG_REG (op)) == MEM)
+ && MEM_P (SUBREG_REG (op)))
op = SUBREG_REG (op);
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return false;
if (!s390_legitimate_address_without_index_p (op))
return false;
@@ -394,7 +394,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
+ || !MEM_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
dest_regno = REGNO (SET_DEST (XVECEXP (op, 0, 0)));
@@ -423,7 +423,7 @@
|| !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| REGNO (SET_DEST (elt)) != dest_regno + i
- || GET_CODE (SET_SRC (elt)) != MEM
+ || !MEM_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
@@ -496,7 +496,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
+ || !MEM_P (SET_DEST (XVECEXP (op, 0, 0)))
|| !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
@@ -526,7 +526,7 @@
|| !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| REGNO (SET_SRC (elt)) != src_regno + i
- || GET_CODE (SET_DEST (elt)) != MEM
+ || !MEM_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index d38cf3aad12..acec764bc42 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2562,8 +2562,8 @@ s390_split_ok_p (rtx dst, rtx src, machine_mode mode, int first_subword)
return false;
/* Non-offsettable memory references cannot be split. */
- if ((GET_CODE (src) == MEM && !offsettable_memref_p (src))
- || (GET_CODE (dst) == MEM && !offsettable_memref_p (dst)))
+ if ((MEM_P (src) && !offsettable_memref_p (src))
+ || (MEM_P (dst) && !offsettable_memref_p (dst)))
return false;
/* Moving the first subword must not clobber a register
@@ -2588,7 +2588,7 @@ s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
rtx addr1, addr2, addr_delta;
HOST_WIDE_INT delta;
- if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
+ if (!MEM_P (mem1) || !MEM_P (mem2))
return true;
if (size == 0)
@@ -2629,7 +2629,7 @@ s390_offset_p (rtx mem1, rtx mem2, rtx delta)
{
rtx addr1, addr2, addr_delta;
- if (GET_CODE (mem1) != MEM || GET_CODE (mem2) != MEM)
+ if (!MEM_P (mem1) || !MEM_P (mem2))
return false;
addr1 = XEXP (mem1, 0);
@@ -2660,7 +2660,7 @@ s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
/* QImode and HImode patterns make sense only if we have a destination
in memory. Otherwise perform the operation in SImode. */
- if ((mode == QImode || mode == HImode) && GET_CODE (dst) != MEM)
+ if ((mode == QImode || mode == HImode) && !MEM_P (dst))
wmode = SImode;
/* Widen operands if required. */
@@ -2705,7 +2705,7 @@ s390_logical_operator_ok_p (rtx *operands)
/* If the destination operand is in memory, it needs to coincide
with one of the source operands. After reload, it has to be
the first source operand. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
return rtx_equal_p (operands[0], operands[1])
|| (!reload_completed && rtx_equal_p (operands[0], operands[2]));
@@ -2722,7 +2722,7 @@ s390_narrow_logical_operator (enum rtx_code code, rtx *memop, rtx *immop)
HOST_WIDE_INT mask;
int part;
- gcc_assert (GET_CODE (*memop) == MEM);
+ gcc_assert (MEM_P (*memop));
gcc_assert (!MEM_VOLATILE_P (*memop));
mask = s390_extract_part (*immop, QImode, def);
@@ -3359,7 +3359,7 @@ s390_mem_constraint (const char *str, rtx op)
case 'R':
case 'S':
case 'T':
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return 0;
return s390_check_qrst_address (c, XEXP (op, 0), true);
case 'Y':
@@ -5292,7 +5292,7 @@ emit_symbolic_move (rtx *operands)
{
rtx temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode);
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
operands[1] = force_reg (Pmode, operands[1]);
else if (TLS_SYMBOLIC_CONST (operands[1]))
operands[1] = legitimize_tls_address (operands[1], temp);
@@ -7429,7 +7429,7 @@ s390_delegitimize_address (rtx orig_x)
return plus_constant (Pmode, XVECEXP (y, 0, 0), offset);
}
- if (GET_CODE (x) != MEM)
+ if (!MEM_P (x))
return orig_x;
x = XEXP (x, 0);
@@ -7966,7 +7966,7 @@ print_operand (FILE *file, rtx x, int code)
case 'N':
if (REG_P (x))
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
x = change_address (x, VOIDmode,
plus_constant (Pmode, XEXP (x, 0), 4));
else
@@ -7977,7 +7977,7 @@ print_operand (FILE *file, rtx x, int code)
case 'M':
if (REG_P (x))
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
x = change_address (x, VOIDmode,
plus_constant (Pmode, XEXP (x, 0), 8));
else
@@ -8332,7 +8332,7 @@ annotate_constant_pool_refs_1 (rtx *x)
|| !CONSTANT_POOL_ADDRESS_P (*x));
/* Literal pool references can only occur inside a MEM ... */
- if (GET_CODE (*x) == MEM)
+ if (MEM_P (*x))
{
rtx memref = XEXP (*x, 0);
@@ -9464,7 +9464,7 @@ s390_regs_ever_clobbered (char regs_ever_clobbered[])
continue;
/* l / lg */
- if (GET_CODE (SET_SRC (pat)) == MEM)
+ if (MEM_P (SET_SRC (pat)))
continue;
}
@@ -13742,7 +13742,7 @@ s390_optimize_prologue (void)
if (cfun_frame_layout.first_save_gpr == -1
&& GET_CODE (pat) == SET
&& GENERAL_REG_P (SET_SRC (pat))
- && GET_CODE (SET_DEST (pat)) == MEM)
+ && MEM_P (SET_DEST (pat)))
{
set = pat;
first = REGNO (SET_SRC (set));
@@ -13813,7 +13813,7 @@ s390_optimize_prologue (void)
if (cfun_frame_layout.first_restore_gpr == -1
&& GET_CODE (pat) == SET
&& GENERAL_REG_P (SET_DEST (pat))
- && GET_CODE (SET_SRC (pat)) == MEM)
+ && MEM_P (SET_SRC (pat)))
{
set = pat;
first = REGNO (SET_DEST (set));
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 0f2cc5a7752..3305d9fdf73 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2258,7 +2258,7 @@
always sign-extends (at least) to SImode. */
if (optimize && can_create_pseudo_p ()
&& register_operand (operands[0], VOIDmode)
- && GET_CODE (operands[1]) == MEM)
+ && MEM_P (operands[1]))
{
rtx tmp = gen_reg_rtx (SImode);
rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]);
@@ -2324,7 +2324,7 @@
is just as fast as a QImode load. */
if (TARGET_ZARCH && optimize && can_create_pseudo_p ()
&& register_operand (operands[0], VOIDmode)
- && GET_CODE (operands[1]) == MEM)
+ && MEM_P (operands[1]))
{
rtx tmp = gen_reg_rtx (DImode);
rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]);
@@ -2840,7 +2840,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
- || GET_CODE (operands[1]) != MEM
+ || !MEM_P (operands[1])
|| !REG_P (operands[0])
|| REGNO (operands[0]) >= 16)
FAIL;
@@ -2931,7 +2931,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
- || GET_CODE (operands[0]) != MEM
+ || !MEM_P (operands[0])
|| !REG_P (operands[1])
|| REGNO (operands[1]) >= 16)
FAIL;
@@ -7714,7 +7714,7 @@
(clobber (reg:CC CC_REGNUM))]
"!TARGET_ARCH13
&& ! reload_completed
- && (GET_CODE (operands[0]) != MEM
+ && (!MEM_P (operands[0])
/* Ensure that s390_logical_operator_ok_p will succeed even
on the split xor if (b & a) is stored into a pseudo. */
|| rtx_equal_p (operands[0], operands[2]))"
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index d947736e933..b1c2059dd43 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -415,7 +415,7 @@
op = SUBREG_REG (op);
/* Check for valid MEM forms. */
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
/* Except when LRA is precisely working hard to make them valid
and relying entirely on the constraints. */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 523f2851d31..f3f61bdb947 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2224,7 +2224,7 @@ bool
sparc_expand_move (machine_mode mode, rtx *operands)
{
/* Handle sets of MEM first. */
- if (GET_CODE (operands[0]) == MEM)
+ if (MEM_P (operands[0]))
{
/* 0 is a register (or a pair of registers) on SPARC. */
if (register_or_zero_operand (operands[1], mode))
@@ -3638,7 +3638,7 @@ emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands)
if (TARGET_BUGGY_QP_LIB && i == 0)
force_stack_temp = 1;
- if (GET_CODE (this_arg) == MEM
+ if (MEM_P (this_arg)
&& ! force_stack_temp)
{
tree expr = MEM_EXPR (this_arg);
@@ -4504,7 +4504,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& !REG_P (rs2)
&& !SUBREG_P (rs2)
&& GET_CODE (rs2) != LO_SUM
- && GET_CODE (rs2) != MEM
+ && !MEM_P (rs2)
&& !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
&& (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
&& (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
@@ -5160,7 +5160,7 @@ mem_min_alignment (rtx mem, int desired)
rtx addr, base, offset;
/* If it's not a MEM we can't accept it. */
- if (GET_CODE (mem) != MEM)
+ if (!MEM_P (mem))
return 0;
/* Obviously... */
@@ -9587,7 +9587,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
case 'f':
/* Operand must be a MEM; write its address. */
- if (GET_CODE (x) != MEM)
+ if (!MEM_P (x))
output_operand_lossage ("invalid %%f operand");
output_address (GET_MODE (x), XEXP (x, 0));
return;
@@ -9619,7 +9619,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
if (REG_P (x))
fputs (reg_names[REGNO (x)], file);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
{
fputc ('[', file);
/* Poor Sun assembler doesn't understand absolute addressing. */
@@ -10141,8 +10141,8 @@ hypersparc_adjust_cost (rtx_insn *insn, int dtype, rtx_insn *dep_insn,
if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE)
{
if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET
- || GET_CODE (SET_DEST (dep_pat)) != MEM
- || GET_CODE (SET_SRC (pat)) != MEM
+ || !MEM_P (SET_DEST (dep_pat))
+ || !MEM_P (SET_SRC (pat))
|| ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0),
XEXP (SET_SRC (pat), 0)))
return cost + 2;
@@ -13402,7 +13402,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
a paradoxical subreg in a float/fix conversion insn. */
if (FP_REG_CLASS_P (rclass)
&& (mode == HImode || mode == QImode)
- && (GET_CODE (x) == MEM
+ && (MEM_P (x)
|| ((REG_P (x) || SUBREG_P (x))
&& true_regnum (x) == -1)))
return GENERAL_REGS;
@@ -13412,7 +13412,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
if (TARGET_ARCH32
&& rclass == EXTRA_FP_REGS
&& mode == DFmode
- && GET_CODE (x) == MEM
+ && MEM_P (x)
&& ! mem_min_alignment (x, 8))
return FP_REGS;
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 668a1950c9a..4527842e8b6 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -482,7 +482,7 @@ spu_expand_insv (rtx ops[])
int shift;
- if (GET_CODE (ops[0]) == MEM)
+ if (MEM_P (ops[0]))
dst = gen_reg_rtx (TImode);
else
dst = adjust_operand (dst, &start);
@@ -554,7 +554,7 @@ spu_expand_insv (rtx ops[])
default:
abort ();
}
- if (GET_CODE (ops[0]) == MEM)
+ if (MEM_P (ops[0]))
{
rtx low = gen_reg_rtx (SImode);
rtx rotl = gen_reg_rtx (SImode);
@@ -2687,8 +2687,8 @@ uses_ls_unit(rtx_insn *insn)
{
rtx set = single_set (insn);
if (set != 0
- && (GET_CODE (SET_DEST (set)) == MEM
- || GET_CODE (SET_SRC (set)) == MEM))
+ && (MEM_P (SET_DEST (set))
+ || MEM_P (SET_SRC (set))))
return 1;
return 0;
}
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index 47705c65067..58459210cfd 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -4831,7 +4831,7 @@ selb\t%0,%4,%0,%3"
emit_move_insn (offset, array_to_constant (V8HImode, arr));
emit_move_insn (splatqi, array_to_constant (TImode, arr2));
- gcc_assert (GET_CODE (operands[1]) == MEM);
+ gcc_assert (MEM_P (operands[1]));
addr = force_reg (Pmode, XEXP (operands[1], 0));
emit_insn (gen_andsi3 (addr_bits, addr, GEN_INT (0xF)));
emit_insn (gen_shufb (addr_bits_vec, addr_bits, addr_bits, splatqi));
diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md
index 9f9edcb4b1b..3398efe91d8 100644
--- a/gcc/config/stormy16/predicates.md
+++ b/gcc/config/stormy16/predicates.md
@@ -65,10 +65,10 @@
{
if (GET_MODE (op) != mode)
return 0;
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
op = XEXP (op, 0);
else if (SUBREG_P (op)
- && GET_CODE (XEXP (op, 0)) == MEM
+ && MEM_P (XEXP (op, 0))
&& !MEM_VOLATILE_P (XEXP (op, 0)))
op = XEXP (XEXP (op, 0), 0);
else
@@ -95,7 +95,7 @@
(define_predicate "xstormy16_splittable_below100_or_register"
(match_code "mem,reg,subreg")
{
- if (GET_CODE (op) == MEM && MEM_VOLATILE_P (op))
+ if (MEM_P (op) && MEM_VOLATILE_P (op))
return 0;
return (xstormy16_below100_operand (op, mode)
|| register_operand (op, mode));
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index a1821a3bc29..f6cbdaabcaf 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -196,7 +196,7 @@
dest = SET_DEST (vector_element);
src = SET_SRC (vector_element);
- if (GET_CODE (dest) != MEM
+ if (!MEM_P (dest)
|| GET_MODE (dest) != SImode
|| !REG_P (src)
|| GET_MODE (src) != SImode
@@ -286,7 +286,7 @@
if (!REG_P (dest)
|| GET_MODE (dest) != SImode
|| ! register_is_ok_for_epilogue (dest, SImode)
- || GET_CODE (src) != MEM
+ || !MEM_P (src)
|| GET_MODE (src) != SImode)
return 0;
@@ -358,7 +358,7 @@
if ( !REG_P (dest)
|| GET_MODE (dest) != SImode
|| ! register_is_ok_for_epilogue (dest, SImode)
- || GET_CODE (src) != MEM
+ || !MEM_P (src)
|| GET_MODE (src) != SImode)
return 0;
@@ -419,7 +419,7 @@
dest = SET_DEST (vector_element);
src = SET_SRC (vector_element);
- if ( GET_CODE (dest) != MEM
+ if ( !MEM_P (dest)
|| GET_MODE (dest) != SImode
|| !REG_P (src)
|| GET_MODE (src) != SImode
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 3412e69563b..001b1baa8ec 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -583,7 +583,7 @@ v850_print_operand (FILE * file, rtx x, int code)
case 'S':
{
/* If it's a reference to a TDA variable, use sst/sld vs. st/ld. */
- if (GET_CODE (x) == MEM && ep_memory_operand (x, GET_MODE (x), FALSE))
+ if (MEM_P (x) && ep_memory_operand (x, GET_MODE (x), FALSE))
fputs ("s", file);
break;
@@ -591,7 +591,7 @@ v850_print_operand (FILE * file, rtx x, int code)
case 'T':
{
/* Like an 'S' operand above, but for unsigned loads only. */
- if (GET_CODE (x) == MEM && ep_memory_operand (x, GET_MODE (x), TRUE))
+ if (MEM_P (x) && ep_memory_operand (x, GET_MODE (x), TRUE))
fputs ("s", file);
break;
@@ -866,7 +866,7 @@ output_move_single (rtx * operands)
return "movhi hi(%F1),%.,%0\n\tmovea lo(%F1),%0,%0";
}
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
return "%S1ld%W1 %1,%0";
else if (special_symbolref_operand (src, VOIDmode))
@@ -893,7 +893,7 @@ output_move_single (rtx * operands)
}
}
- else if (GET_CODE (dst) == MEM)
+ else if (MEM_P (dst))
{
if (REG_P (src))
return "%S0st%W0 %1,%0";
@@ -1066,7 +1066,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
if (!TARGET_EP)
return FALSE;
- if (GET_CODE (op) != MEM)
+ if (!MEM_P (op))
return FALSE;
max_offset = ep_memory_offset (mode, unsigned_load);
@@ -1153,22 +1153,22 @@ Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, end
/* Memory operands are signed by default. */
int unsignedp = FALSE;
- if (GET_CODE (SET_DEST (pattern)) == MEM
- && GET_CODE (SET_SRC (pattern)) == MEM)
+ if (MEM_P (SET_DEST (pattern))
+ && MEM_P (SET_SRC (pattern)))
p_mem = (rtx *)0;
- else if (GET_CODE (SET_DEST (pattern)) == MEM)
+ else if (MEM_P (SET_DEST (pattern)))
p_mem = &SET_DEST (pattern);
- else if (GET_CODE (SET_SRC (pattern)) == MEM)
+ else if (MEM_P (SET_SRC (pattern)))
p_mem = &SET_SRC (pattern);
else if (GET_CODE (SET_SRC (pattern)) == SIGN_EXTEND
- && GET_CODE (XEXP (SET_SRC (pattern), 0)) == MEM)
+ && MEM_P (XEXP (SET_SRC (pattern), 0)))
p_mem = &XEXP (SET_SRC (pattern), 0);
else if (GET_CODE (SET_SRC (pattern)) == ZERO_EXTEND
- && GET_CODE (XEXP (SET_SRC (pattern), 0)) == MEM)
+ && MEM_P (XEXP (SET_SRC (pattern), 0)))
{
p_mem = &XEXP (SET_SRC (pattern), 0);
unsignedp = TRUE;
@@ -1301,29 +1301,29 @@ v850_reorg (void)
/* We might have (SUBREG (MEM)) here, so just get rid of the
subregs to make this code simpler. */
if (SUBREG_P (dest)
- && (GET_CODE (SUBREG_REG (dest)) == MEM
+ && (MEM_P (SUBREG_REG (dest))
|| REG_P (SUBREG_REG (dest))))
alter_subreg (&dest, false);
if (SUBREG_P (src)
- && (GET_CODE (SUBREG_REG (src)) == MEM
+ && (MEM_P (SUBREG_REG (src))
|| REG_P (SUBREG_REG (src))))
alter_subreg (&src, false);
- if (GET_CODE (dest) == MEM && GET_CODE (src) == MEM)
+ if (MEM_P (dest) && MEM_P (src))
mem = NULL_RTX;
- else if (GET_CODE (dest) == MEM)
+ else if (MEM_P (dest))
mem = dest;
- else if (GET_CODE (src) == MEM)
+ else if (MEM_P (src))
mem = src;
else if (GET_CODE (src) == SIGN_EXTEND
- && GET_CODE (XEXP (src, 0)) == MEM)
+ && MEM_P (XEXP (src, 0)))
mem = XEXP (src, 0);
else if (GET_CODE (src) == ZERO_EXTEND
- && GET_CODE (XEXP (src, 0)) == MEM)
+ && MEM_P (XEXP (src, 0)))
{
mem = XEXP (src, 0);
unsignedp = TRUE;
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 1621f4a6403..694456b5069 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -919,7 +919,7 @@ void
prepare_move_operands (rtx *operands, machine_mode mode)
{
/* If the output is not a register, the input must be. */
- if (GET_CODE (operands[0]) == MEM && !reg_or_0_operand (operands[1], mode))
+ if (MEM_P (operands[0]) && !reg_or_0_operand (operands[1], mode))
operands[1] = force_reg (mode, operands[1]);
}
@@ -1046,7 +1046,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
/* Should be no stall/hazard if OUT_INSN is MEM := ???. This only
occurs prior to reload. */
- if (GET_CODE (dest) == MEM)
+ if (MEM_P (dest))
return 0;
if (GET_CODE (dest) == STRICT_LOW_PART)
@@ -1058,7 +1058,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
in_set = single_set_and_flags (in_insn);
/* If IN_INSN is MEM := MEM, it's the source that counts. */
- if (GET_CODE (SET_SRC (in_set)) == MEM)
+ if (MEM_P (SET_SRC (in_set)))
memexpr = XEXP (SET_SRC (in_set), 0);
else
memexpr = XEXP (SET_DEST (in_set), 0);
@@ -1150,7 +1150,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
const bool double_p = GET_MODE_SIZE (GET_MODE (dest)) > UNITS_PER_WORD;
rtx memrtx = NULL;
- if (GET_CODE (SET_SRC (set)) == MEM)
+ if (MEM_P (SET_SRC (set)))
{
memrtx = XEXP (SET_SRC (set), 0);
if (GET_CODE (dest) == STRICT_LOW_PART)
@@ -1183,7 +1183,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
}
}
- else if (GET_CODE (dest) == MEM)
+ else if (MEM_P (dest))
memrtx = XEXP (dest, 0);
else if (GET_MODE_CLASS (GET_MODE (dest)) != MODE_CC)
@@ -2120,7 +2120,7 @@ visium_split_double_move (rtx *operands, machine_mode mode)
swap = true;
/* Check memory to register where the base reg overlaps the destination. */
- if (REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
+ if (REG_P (operands[0]) && MEM_P (operands[1]))
{
rtx op = XEXP (operands[1], 0);
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 505b86397b9..85b4777a91d 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -525,7 +525,7 @@ xtensa_valid_move (machine_mode mode, rtx *operands)
int
smalloffset_mem_p (rtx op)
{
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
{
rtx addr = XEXP (op, 0);
if (REG_P (addr))
@@ -582,7 +582,7 @@ constantpool_mem_p (rtx op)
{
if (SUBREG_P (op))
op = SUBREG_REG (op);
- if (GET_CODE (op) == MEM)
+ if (MEM_P (op))
return constantpool_address_p (XEXP (op, 0));
return FALSE;
}
@@ -2376,7 +2376,7 @@ print_operand (FILE *file, rtx x, int letter)
break;
case 'v':
- if (GET_CODE (x) == MEM)
+ if (MEM_P (x))
{
/* For a volatile memory reference, emit a MEMW before the
load or store. */
@@ -2388,7 +2388,7 @@ print_operand (FILE *file, rtx x, int letter)
break;
case 'N':
- if (GET_CODE (x) == MEM
+ if (MEM_P (x)
&& (GET_MODE (x) == DFmode || GET_MODE (x) == DImode))
{
x = adjust_address (x, GET_MODE (x) == DFmode ? E_SFmode : E_SImode,
@@ -2503,7 +2503,7 @@ print_operand (FILE *file, rtx x, int letter)
default:
if (REG_P (x) || SUBREG_P (x))
fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
- else if (GET_CODE (x) == MEM)
+ else if (MEM_P (x))
output_address (GET_MODE (x), XEXP (x, 0));
else if (CONST_INT_P (x))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 1d487a5475e..24672f62635 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -3329,11 +3329,11 @@ dbxout_common_check (tree decl, int *value)
return NULL;
home = DECL_RTL (decl);
- if (home == NULL_RTX || GET_CODE (home) != MEM)
+ if (home == NULL_RTX || !MEM_P (home))
return NULL;
sym_addr = dbxout_expand_expr (DECL_VALUE_EXPR (decl));
- if (sym_addr == NULL_RTX || GET_CODE (sym_addr) != MEM)
+ if (sym_addr == NULL_RTX || !MEM_P (sym_addr))
return NULL;
sym_addr = XEXP (sym_addr, 0);
diff --git a/gcc/df-scan.c b/gcc/df-scan.c
index 57d6efd709f..c3d52be4e49 100644
--- a/gcc/df-scan.c
+++ b/gcc/df-scan.c
@@ -2930,7 +2930,7 @@ df_uses_record (class df_collection_rec *collection_rec,
DF_REF_REG_USE, bb, insn_info, flags);
df_uses_record (collection_rec, &XEXP (dst, 2),
DF_REF_REG_USE, bb, insn_info, flags);
- if (GET_CODE (XEXP (dst,0)) == MEM)
+ if (MEM_P (XEXP (dst,0)))
df_uses_record (collection_rec, &XEXP (dst, 0),
DF_REF_REG_USE, bb, insn_info,
flags);
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 4d5b72e70e1..0b16dd2a9af 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -1146,7 +1146,7 @@ free_load_extend (rtx src, rtx_insn *insn)
rtx patt = PATTERN (DF_REF_INSN (def));
if (GET_CODE (patt) == SET
- && GET_CODE (SET_SRC (patt)) == MEM
+ && MEM_P (SET_SRC (patt))
&& rtx_equal_p (SET_DEST (patt), reg))
return true;
}
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index b93b692cb43..8ccf523c859 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -310,7 +310,7 @@ rtx_interchangeable_p (const_rtx a, const_rtx b)
if (!rtx_equal_p (a, b))
return false;
- if (GET_CODE (a) != MEM)
+ if (!MEM_P (a))
return true;
/* A dead type-unsafe memory reference is legal, but a live type-unsafe memory
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 02f37535b0d..d1cb817df44 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1242,7 +1242,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* A truncate of a memory is just loading the low part of the memory
if we are not changing the meaning of the address. */
- if (GET_CODE (op) == MEM
+ if (MEM_P (op)
&& !VECTOR_MODE_P (mode)
&& !MEM_VOLATILE_P (op)
&& !mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op)))
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 1d425d1acd9..e0ee278e044 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -2250,7 +2250,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
static inline bool
vt_canon_true_dep (dataflow_set *set, rtx mloc, rtx maddr, rtx loc)
{
- if (GET_CODE (loc) != MEM)
+ if (!MEM_P (loc))
return false;
rtx addr = vt_canonicalize_addr (set, XEXP (loc, 0));
@@ -2350,7 +2350,7 @@ clobber_overlapping_mems (dataflow_set *set, rtx loc)
{
struct overlapping_mems coms;
- gcc_checking_assert (GET_CODE (loc) == MEM);
+ gcc_checking_assert (MEM_P (loc));
coms.set = set;
coms.loc = canon_rtx (loc);
@@ -2479,7 +2479,7 @@ val_bind (dataflow_set *set, rtx val, rtx loc, bool modified)
dynamic tables. ??? We should test this before emitting the
micro-op in the first place. */
while (l)
- if (GET_CODE (l->loc) == MEM && XEXP (l->loc, 0) == XEXP (loc, 0))
+ if (MEM_P (l->loc) && XEXP (l->loc, 0) == XEXP (loc, 0))
break;
else
l = l->next;
@@ -2612,7 +2612,7 @@ val_reset (dataflow_set *set, decl_or_value dv)
else if (REG_P (node->loc))
var_reg_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
- else if (GET_CODE (node->loc) == MEM)
+ else if (MEM_P (node->loc))
var_mem_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
else
@@ -4735,7 +4735,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
{
/* We want to remove dying MEMs that don't refer to DECL. */
- if (GET_CODE (loc->loc) == MEM
+ if (MEM_P (loc->loc)
&& (MEM_EXPR (loc->loc) != decl
|| int_mem_offset (loc->loc) != 0)
&& mem_dies_at_call (loc->loc))
@@ -4779,7 +4779,7 @@ dataflow_set_preserve_mem_locs (variable **slot, dataflow_set *set)
}
}
- if (GET_CODE (loc->loc) != MEM
+ if (!MEM_P (loc->loc)
|| (MEM_EXPR (loc->loc) == decl
&& int_mem_offset (loc->loc) == 0)
|| !mem_dies_at_call (loc->loc))
@@ -4839,7 +4839,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
if (shared_var_p (var, set->vars))
{
for (loc = var->var_part[0].loc_chain; loc; loc = loc->next)
- if (GET_CODE (loc->loc) == MEM
+ if (MEM_P (loc->loc)
&& mem_dies_at_call (loc->loc))
break;
@@ -4859,7 +4859,7 @@ dataflow_set_remove_mem_locs (variable **slot, dataflow_set *set)
for (locp = &var->var_part[0].loc_chain, loc = *locp;
loc; loc = *locp)
{
- if (GET_CODE (loc->loc) != MEM
+ if (!MEM_P (loc->loc)
|| !mem_dies_at_call (loc->loc))
{
locp = &loc->next;
@@ -6835,7 +6835,7 @@ compute_bb_dataflow (basic_block bb)
if (REG_P (uloc))
var_reg_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
- else if (GET_CODE (uloc) == MEM)
+ else if (MEM_P (uloc))
var_mem_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
}
@@ -6943,7 +6943,7 @@ compute_bb_dataflow (basic_block bb)
var_regno_delete (out, REGNO (uloc));
else if (MEM_P (uloc))
{
- gcc_checking_assert (GET_CODE (vloc) == MEM);
+ gcc_checking_assert (MEM_P (vloc));
gcc_checking_assert (dstv == vloc);
if (dstv != vloc)
clobber_overlapping_mems (out, vloc);
@@ -8726,7 +8726,7 @@ emit_note_insn_var_location (variable **varp, emit_note_data *data)
continue;
offset = VAR_PART_OFFSET (var, i);
loc2 = var->var_part[i].cur_loc;
- if (loc2 && GET_CODE (loc2) == MEM
+ if (loc2 && MEM_P (loc2)
&& GET_CODE (XEXP (loc2, 0)) == VALUE)
{
rtx depval = XEXP (loc2, 0);
@@ -8998,7 +8998,7 @@ notify_dependents_of_changed_value (rtx val, variable_table_type *htab,
{
rtx loc = ivar->var_part[i].cur_loc;
- if (loc && GET_CODE (loc) == MEM
+ if (loc && MEM_P (loc)
&& XEXP (loc, 0) == val)
{
variable_was_changed (ivar, NULL);
@@ -9333,7 +9333,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
if (REG_P (uloc))
var_reg_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
- else if (GET_CODE (uloc) == MEM)
+ else if (MEM_P (uloc))
var_mem_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
}
@@ -9437,7 +9437,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
var_regno_delete (set, REGNO (uloc));
else if (MEM_P (uloc))
{
- gcc_checking_assert (GET_CODE (vloc) == MEM);
+ gcc_checking_assert (MEM_P (vloc));
gcc_checking_assert (vloc == dstv);
if (vloc != dstv)
clobber_overlapping_mems (set, vloc);
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 14/18] Use LABEL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh LABEL_REF
2019-08-06 3:11 ` Arvind Sankar
2019-08-06 3:11 ` [PATCH v2 03/18] Use CONST_INT_P macro Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 01/18] Fix CONST_DOUBLE_AS_FLOAT_P comment Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 15/18] Use LABEL_REF_P macro Arvind Sankar
` (14 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* alias.c: Convert GET_CODE (..) == LABEL_REF to
LABEL_REF_P (..).
* bb-reorder.c: Likewise.
* cfgbuild.c: Likewise.
* cfgexpand.c: Likewise.
* cfgrtl.c: Likewise.
* combine.c: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/alpha/predicates.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/arc.h: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/thumb1.md: Likewise.
* config/avr/avr.c: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/bfin.h: Likewise.
* config/bfin/predicates.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/c6x/predicates.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cr16/cr16.h: Likewise.
* config/cris/cris.c: Likewise.
* config/cris/cris.md: Likewise.
* config/csky/constraints.md: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.h: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.h: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/predicates.md: Likewise.
* config/ft32/constraints.md: Likewise.
* config/ft32/ft32.c: Likewise.
* config/ft32/ft32.md: Likewise.
* config/ft32/predicates.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/gcn/gcn.md: Likewise.
* config/h8300/h8300.h: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/iq2000/iq2000.h: Likewise.
* config/iq2000/predicates.md: Likewise.
* config/lm32/lm32.c: Likewise.
* config/lm32/lm32.h: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32r/constraints.md: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m32r/m32r.h: Likewise.
* config/m32r/predicates.md: Likewise.
* config/m68k/constraints.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.h: Likewise.
* config/m68k/predicates.md: Likewise.
* config/mcore/constraints.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.h: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/microblaze/predicates.md: Likewise.
* config/mips/mips.c: Likewise.
* config/mmix/mmix.c: Likewise.
* config/mmix/predicates.md: Likewise.
* config/mn10300/mn10300.c: Likewise.
* config/mn10300/mn10300.h: Likewise.
* config/moxie/constraints.md: Likewise.
* config/moxie/moxie.c: Likewise.
* config/moxie/predicates.md: Likewise.
* config/nds32/nds32-cost.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32.h: Likewise.
* config/nios2/nios2.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/nvptx/nvptx.md: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.h: Likewise.
* config/pa/pa.md: Likewise.
* config/pa/predicates.md: Likewise.
* config/riscv/riscv.c: Likewise.
* config/rs6000/freebsd64.h: Likewise.
* config/rs6000/linux64.h: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rs6000/rs6000.h: Likewise.
* config/rs6000/rtems.h: Likewise.
* config/rs6000/sysv4.h: Likewise.
* config/rs6000/xcoff.h: Likewise.
* config/rx/rx.c: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.h: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/constraints.md: Likewise.
* config/spu/spu.c: Likewise.
* config/tilegx/predicates.md: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilepro/predicates.md: Likewise.
* config/tilepro/tilepro.c: Likewise.
* config/v850/v850.c: Likewise.
* config/vax/predicates.md: Likewise.
* config/vax/vax.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.h: Likewise.
* cprop.c: Likewise.
* cse.c: Likewise.
* dbxout.c: Likewise.
* explow.c: Likewise.
* expr.c: Likewise.
* final.c: Likewise.
* genattrtab.c: Likewise.
* gensupport.c: Likewise.
* ifcvt.c: Likewise.
* ira.c: Likewise.
* jump.c: Likewise.
* loop-doloop.c: Likewise.
* lower-subreg.c: Likewise.
* print-rtl.c: Likewise.
* read-rtl-function.c: Likewise.
* recog.c: Likewise.
* reginfo.c: Likewise.
* reload.c: Likewise.
* reload1.c: Likewise.
* reorg.c: Likewise.
* rtlanal.c: Likewise.
* simplify-rtx.c: Likewise.
* tree-ssa-address.c: Likewise.
* varasm.c: Likewise.
133 files changed, 351 insertions(+), 351 deletions(-)
diff --git a/gcc/alias.c b/gcc/alias.c
index 2755df72907..24eaeae86f3 100644
--- a/gcc/alias.c
+++ b/gcc/alias.c
@@ -2954,7 +2954,7 @@ true_dependence_1 (const_rtx mem, machine_mode mem_mode, rtx mem_addr,
return 1;
base = find_base_term (x_addr);
- if (base && (GET_CODE (base) == LABEL_REF
+ if (base && (LABEL_REF_P (base)
|| (GET_CODE (base) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
@@ -3063,7 +3063,7 @@ write_dependence_p (const_rtx mem,
base = find_base_term (true_mem_addr);
if (! writep
&& base
- && (GET_CODE (base) == LABEL_REF
+ && (LABEL_REF_P (base)
|| (GET_CODE (base) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
diff --git a/gcc/bb-reorder.c b/gcc/bb-reorder.c
index 0ac39140c6c..43623e00d76 100644
--- a/gcc/bb-reorder.c
+++ b/gcc/bb-reorder.c
@@ -2167,7 +2167,7 @@ fix_crossing_conditional_branches (void)
new_label = gen_label_rtx ();
emit_label (new_label);
- gcc_assert (GET_CODE (old_label) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (old_label));
old_jump_target = old_jump_insn->jump_target ();
new_jump = as_a <rtx_jump_insn *>
(emit_jump_insn (targetm.gen_jump (old_jump_target)));
diff --git a/gcc/cfgbuild.c b/gcc/cfgbuild.c
index 934325c6538..8ac13b753dd 100644
--- a/gcc/cfgbuild.c
+++ b/gcc/cfgbuild.c
@@ -273,7 +273,7 @@ make_edges (basic_block min, basic_block max, int update_p)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2)))
make_label_edge (edge_cache, bb,
label_ref_label (XEXP (SET_SRC (tmp), 2)), 0);
}
@@ -414,7 +414,7 @@ purge_dead_tablejump_edges (basic_block bb, rtx_jump_table_data *table)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2)))
mark_tablejump_edge (label_ref_label (XEXP (SET_SRC (tmp), 2)));
for (ei = ei_start (bb->succs); (e = ei_safe_edge (ei)); )
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index aff97bb41be..f4832c6d2bb 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -5482,7 +5482,7 @@ expand_debug_locations (void)
|| (GET_MODE (val) == VOIDmode
&& (CONST_SCALAR_INT_P (val)
|| CONST_FIXED_P (val)
- || GET_CODE (val) == LABEL_REF)));
+ || LABEL_REF_P (val))));
}
INSN_VAR_LOCATION_LOC (insn) = val;
diff --git a/gcc/cfgrtl.c b/gcc/cfgrtl.c
index 1f222aea5d1..6e5ccd46c22 100644
--- a/gcc/cfgrtl.c
+++ b/gcc/cfgrtl.c
@@ -1217,7 +1217,7 @@ patch_jump_insn (rtx_insn *insn, rtx_insn *old_label, basic_block new_bb)
if ((tmp = single_set (insn)) != NULL
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (tmp), 2)) == LABEL_REF
+ && LABEL_REF_P (XEXP (SET_SRC (tmp), 2))
&& label_ref_label (XEXP (SET_SRC (tmp), 2)) == old_label)
{
XEXP (SET_SRC (tmp), 2) = gen_rtx_LABEL_REF (Pmode,
@@ -1238,7 +1238,7 @@ patch_jump_insn (rtx_insn *insn, rtx_insn *old_label, basic_block new_bb)
for (i = 0; i < n; ++i)
{
rtx old_ref = ASM_OPERANDS_LABEL (tmp, i);
- gcc_assert (GET_CODE (old_ref) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (old_ref));
if (XEXP (old_ref, 0) == old_label)
{
ASM_OPERANDS_LABEL (tmp, i)
diff --git a/gcc/combine.c b/gcc/combine.c
index a7af1ace40b..f1e786d5678 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -14483,14 +14483,14 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
/* ??? Ignore the without-reg_equal-note problem for now. */
if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
|| ((tem_note = find_reg_note (i3, REG_EQUAL, NULL_RTX))
- && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (tem_note, 0))
&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0)))
place = i3;
if (i2
&& (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
|| ((tem_note = find_reg_note (i2, REG_EQUAL, NULL_RTX))
- && GET_CODE (XEXP (tem_note, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (tem_note, 0))
&& label_ref_label (XEXP (tem_note, 0)) == XEXP (note, 0))))
{
if (place)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index f54a0d462a8..4927ee9320f 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3291,7 +3291,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm,
/* Check on what type of symbol it is. */
scalar_int_mode int_mode;
if ((GET_CODE (imm) == SYMBOL_REF
- || GET_CODE (imm) == LABEL_REF
+ || LABEL_REF_P (imm)
|| GET_CODE (imm) == CONST
|| GET_CODE (imm) == CONST_POLY_INT)
&& is_a <scalar_int_mode> (mode, &int_mode))
@@ -6329,7 +6329,7 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return true;
split_const (x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF || GET_CODE (base) == LABEL_REF)
+ if (GET_CODE (base) == SYMBOL_REF || LABEL_REF_P (base))
{
if (aarch64_classify_symbol (base, INTVAL (offset))
!= SYMBOL_FORCE_TO_MEM)
@@ -6854,7 +6854,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
rtx sym, addend;
split_const (x, &sym, &addend);
- return ((GET_CODE (sym) == LABEL_REF
+ return ((LABEL_REF_P (sym)
|| (GET_CODE (sym) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (sym)
&& aarch64_pcrelative_literal_loads)));
@@ -6932,7 +6932,7 @@ aarch64_symbolic_address_p (rtx x)
rtx offset;
split_const (x, &x, &offset);
- return GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF;
+ return GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x);
}
/* Classify the base of symbolic expression X. */
@@ -8236,7 +8236,7 @@ aarch64_label_mentioned_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return true;
/* UNSPEC_TLS entries for a symbol include a LABEL_REF for the
@@ -13091,7 +13091,7 @@ aarch64_classify_tls_symbol (rtx x)
enum aarch64_symbol_type
aarch64_classify_symbol (rtx x, HOST_WIDE_INT offset)
{
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
{
switch (aarch64_cmodel)
{
@@ -13249,7 +13249,7 @@ aarch64_legitimate_constant_p (machine_mode mode, rtx x)
return true;
/* Label references are always constant. */
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return true;
return false;
diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md
index 63110c77b53..f96c16b533c 100644
--- a/gcc/config/alpha/predicates.md
+++ b/gcc/config/alpha/predicates.md
@@ -296,7 +296,7 @@
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return 1;
if (GET_CODE (op) != SYMBOL_REF)
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index e79f36761b2..13cb4706ae5 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -5198,9 +5198,9 @@ arc_ccfsm_advance (rtx_insn *insn, struct arc_ccfsm *state)
if (!seeking_return)
label = XEXP (SET_SRC (body), 0);
}
- else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
+ else if (LABEL_REF_P (XEXP (SET_SRC (body), 1)))
label = XEXP (XEXP (SET_SRC (body), 1), 0);
- else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
+ else if (LABEL_REF_P (XEXP (SET_SRC (body), 2)))
{
label = XEXP (XEXP (SET_SRC (body), 2), 0);
then_not_else = FALSE;
@@ -5295,7 +5295,7 @@ arc_ccfsm_advance (rtx_insn *insn, struct arc_ccfsm *state)
if (GET_CODE (scanbody) == SET
&& GET_CODE (SET_DEST (scanbody)) == PC)
{
- if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
+ if (LABEL_REF_P (SET_SRC (scanbody))
&& XEXP (SET_SRC (scanbody), 0) == label && !reverse)
{
state->state = 2;
@@ -6032,7 +6032,7 @@ arc_legitimate_pic_addr_p (rtx addr)
return false;
if (GET_CODE (XVECEXP (addr, 0, 0)) != SYMBOL_REF
- && GET_CODE (XVECEXP (addr, 0, 0)) != LABEL_REF)
+ && !LABEL_REF_P (XVECEXP (addr, 0, 0)))
return false;
return true;
@@ -6048,7 +6048,7 @@ symbolic_reference_mentioned_p (rtx op)
register const char *fmt;
register int i;
- if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+ if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (op));
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 377e29d3547..94101cff349 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -841,7 +841,7 @@ extern int arc_initial_elimination_offset(int from, int to);
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
(flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) || GET_CODE (X) == CONST))
/* Is the argument a const_int rtx, containing an exact power of 2 */
@@ -1060,7 +1060,7 @@ arc_select_cc_mode (OP, X, Y)
#define ASM_OUTPUT_INT(FILE, VALUE) \
do { \
fprintf (FILE, "\t.word\t"); \
- if (GET_CODE (VALUE) == LABEL_REF) \
+ if (LABEL_REF_P (VALUE)) \
{ \
fprintf (FILE, "%%st(@"); \
output_addr_const (FILE, (VALUE)); \
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index fd18f92b6ec..2f8d68507ec 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7518,7 +7518,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
gcc_assert (compute_now == (pic_reg != NULL_RTX));
if (GET_CODE (orig) == SYMBOL_REF
- || GET_CODE (orig) == LABEL_REF)
+ || LABEL_REF_P (orig))
{
if (reg == 0)
{
@@ -7535,7 +7535,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
/* References to weak symbols cannot be resolved locally: they
may be overridden by a non-weak definition at link time. */
rtx_insn *insn;
- if ((GET_CODE (orig) == LABEL_REF
+ if ((LABEL_REF_P (orig)
|| (GET_CODE (orig) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (orig)
&& (SYMBOL_REF_DECL (orig)
@@ -7895,7 +7895,7 @@ arm_legitimate_address_outer_p (machine_mode mode, rtx x, RTX_CODE outer,
&& (code == LABEL_REF
|| (code == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1;
@@ -8008,7 +8008,7 @@ thumb2_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
&& (code == LABEL_REF
|| (code == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1;
@@ -8337,10 +8337,10 @@ thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
/* This is PC relative data after arm_reorg runs. */
else if ((GET_MODE_SIZE (mode) >= 4 || mode == HFmode)
&& reload_completed
- && (GET_CODE (x) == LABEL_REF
+ && (LABEL_REF_P (x)
|| (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return 1;
@@ -12571,10 +12571,10 @@ arm_coproc_mem_operand (rtx op, bool wb)
ind = XEXP (op, 0);
if (reload_completed
- && (GET_CODE (ind) == LABEL_REF
+ && (LABEL_REF_P (ind)
|| (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (ind, 0), 0))
&& CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE;
@@ -12643,10 +12643,10 @@ neon_vector_mem_operand (rtx op, int type, bool strict)
ind = XEXP (op, 0);
if (reload_completed
- && (GET_CODE (ind) == LABEL_REF
+ && (LABEL_REF_P (ind)
|| (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (ind, 0), 0))
&& CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE;
@@ -12709,10 +12709,10 @@ neon_struct_mem_operand (rtx op)
ind = XEXP (op, 0);
if (reload_completed
- && (GET_CODE (ind) == LABEL_REF
+ && (LABEL_REF_P (ind)
|| (GET_CODE (ind) == CONST
&& GET_CODE (XEXP (ind, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (ind, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (ind, 0), 0))
&& CONST_INT_P (XEXP (XEXP (ind, 0), 1)))))
return TRUE;
@@ -12859,7 +12859,7 @@ label_mentioned_p (rtx x)
const char * fmt;
int i;
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return 1;
/* UNSPEC_TLS entries for a symbol include a LABEL_REF for the referencing
@@ -19113,7 +19113,7 @@ arm_attr_length_move_neon (rtx_insn *insn)
if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS)
addr = XEXP (addr, 0);
- if (GET_CODE (addr) == LABEL_REF || GET_CODE (addr) == PLUS)
+ if (LABEL_REF_P (addr) || GET_CODE (addr) == PLUS)
{
int insns = REG_NREGS (reg) / 2;
return insns * 4;
@@ -23034,7 +23034,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
/* Mark symbols as position independent. We only do this in the
.text segment, not in the .data segment. */
if (NEED_GOT_RELOC && flag_pic && making_const_table &&
- (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF))
+ (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x)))
{
/* See legitimize_pic_address for an explanation of the
TARGET_VXWORKS_RTP check. */
@@ -23542,9 +23542,9 @@ arm_final_prescan_insn (rtx_insn *insn)
if (!seeking_return)
label = XEXP (SET_SRC (body), 0);
}
- else if (GET_CODE (XEXP (SET_SRC (body), 1)) == LABEL_REF)
+ else if (LABEL_REF_P (XEXP (SET_SRC (body), 1)))
label = XEXP (XEXP (SET_SRC (body), 1), 0);
- else if (GET_CODE (XEXP (SET_SRC (body), 2)) == LABEL_REF)
+ else if (LABEL_REF_P (XEXP (SET_SRC (body), 2)))
{
label = XEXP (XEXP (SET_SRC (body), 2), 0);
then_not_else = FALSE;
@@ -23643,7 +23643,7 @@ arm_final_prescan_insn (rtx_insn *insn)
if (GET_CODE (scanbody) == SET
&& GET_CODE (SET_DEST (scanbody)) == PC)
{
- if (GET_CODE (SET_SRC (scanbody)) == LABEL_REF
+ if (LABEL_REF_P (SET_SRC (scanbody))
&& XEXP (SET_SRC (scanbody), 0) == label && !reverse)
{
arm_ccfsm_state = 2;
@@ -29914,7 +29914,7 @@ arm_valid_symbolic_address_p (rtx addr)
if (target_word_relocations)
return false;
- if (GET_CODE (tmp) == SYMBOL_REF || GET_CODE (tmp) == LABEL_REF)
+ if (GET_CODE (tmp) == SYMBOL_REF || LABEL_REF_P (tmp))
return true;
/* (const (plus: symbol_ref const_int)) */
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index b142bfcb837..13ac28d0d85 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -464,7 +464,7 @@
if (GET_CODE (mem) == CONST)
mem = XEXP (mem, 0);
- if (GET_CODE (mem) == LABEL_REF)
+ if (LABEL_REF_P (mem))
return \"ldr\\t%0, %1\";
if (GET_CODE (mem) == PLUS)
@@ -472,7 +472,7 @@
rtx a = XEXP (mem, 0);
rtx b = XEXP (mem, 1);
- if (GET_CODE (a) == LABEL_REF
+ if (LABEL_REF_P (a)
&& CONST_INT_P (b))
return \"ldr\\t%0, %1\";
@@ -844,10 +844,10 @@
rtx addr;
gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0);
- if (GET_CODE (addr) == LABEL_REF
+ if (LABEL_REF_P (addr)
|| (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (addr, 0), 0))
&& CONST_INT_P (XEXP (XEXP (addr, 0), 1))))
{
/* Constant pool entry. */
diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c
index 015d36728a3..86c6cce55f0 100644
--- a/gcc/config/avr/avr.c
+++ b/gcc/config/avr/avr.c
@@ -3150,7 +3150,7 @@ avr_notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx_insn *insn)
int
avr_jump_mode (rtx x, rtx_insn *insn)
{
- int dest_addr = INSN_ADDRESSES (INSN_UID (GET_CODE (x) == LABEL_REF
+ int dest_addr = INSN_ADDRESSES (INSN_UID (LABEL_REF_P (x)
? XEXP (x, 0) : x));
int cur_addr = INSN_ADDRESSES (INSN_UID (insn));
int jump_distance = cur_addr - dest_addr;
@@ -12114,7 +12114,7 @@ avr_2word_insn_p (rtx_insn *insn)
int
jump_over_one_insn_p (rtx_insn *insn, rtx dest)
{
- int uid = INSN_UID (GET_CODE (dest) == LABEL_REF
+ int uid = INSN_UID (LABEL_REF_P (dest)
? XEXP (dest, 0)
: dest);
int jump_addr = INSN_ADDRESSES (INSN_UID (insn));
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 7ae604716e6..cf0986b2f13 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -138,7 +138,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
rtx addr = orig;
rtx new_rtx = orig;
- if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
+ if (GET_CODE (addr) == SYMBOL_REF || LABEL_REF_P (addr))
{
int unspec;
rtx tmp;
@@ -1791,7 +1791,7 @@ symbolic_reference_mentioned_p (rtx op)
register const char *fmt;
register int i;
- if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+ if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
return 1;
fmt = GET_RTX_FORMAT (GET_CODE (op));
diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index 4aba596f68e..2ee2abbd226 100644
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -783,7 +783,7 @@ typedef struct {
#define SYMBOLIC_CONST(X) \
(GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
#define NOTICE_UPDATE_CC(EXPR, INSN) 0
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index fa29cea79c3..261323a41b2 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -163,7 +163,7 @@
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (op, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
;; Returns 1 if OP is a plain constant or matched by symbolic_operand.
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index 938e42f24d6..7e52de17a4b 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1290,7 +1290,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
rtx addr = orig;
rtx new_rtx = orig;
- if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
+ if (GET_CODE (addr) == SYMBOL_REF || LABEL_REF_P (addr))
{
int unspec = UNSPEC_LOAD_GOT;
rtx tmp;
@@ -2430,7 +2430,7 @@ c6x_legitimate_address_p_1 (machine_mode mode, rtx x, bool strict,
&& XINT (XEXP (x, 1), 1) == UNSPEC_LOAD_GOT
&& XEXP (x, 0) == pic_offset_table_rtx
&& (GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == SYMBOL_REF
- || GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == LABEL_REF))
+ || LABEL_REF_P (XVECEXP (XEXP (x, 1), 0, 0))))
return !no_large_offset;
if (!CONST_INT_P (XEXP (x, 1)))
return false;
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index f108c671796..9ece4e9de8c 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -1521,7 +1521,7 @@
UNSPEC_REAL_JUMP)]
""
{
- if (GET_CODE (operands[0]) == LABEL_REF)
+ if (LABEL_REF_P (operands[0]))
return "%|%.\\tb\\t%$\\t%l0";
return "%|%.\\tb\\t%$\\t%0";
}
diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md
index b933de8b9dc..1670df870cc 100644
--- a/gcc/config/c6x/predicates.md
+++ b/gcc/config/c6x/predicates.md
@@ -85,7 +85,7 @@
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (op, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
(define_predicate "const_int_or_symbolic_operand"
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index fbc2b5cf67a..1fc95285ba5 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -1163,7 +1163,7 @@ legitimate_pic_operand_p (rtx x)
/* REVISIT: Use something like symbol_referenced_p. */
if (GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return 0;
break;
@@ -1191,7 +1191,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
rtx reg)
{
/* First handle a simple SYMBOL_REF or LABEL_REF. */
- if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
+ if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
{
if (reg == 0)
reg = gen_reg_rtx (Pmode);
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index dbc012a197d..9814b725aec 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -414,7 +414,7 @@ struct cumulative_args
/* ADDRESSING MODES. */
#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF \
+ (LABEL_REF_P (X) \
|| GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST \
|| CONST_INT_P (X))
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 2073f35f119..6a573dda1ab 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -3957,7 +3957,7 @@ cris_output_addr_const_extra (FILE *file, rtx xconst)
case UNSPEC:
x = XVECEXP (xconst, 0, 0);
CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == LABEL_REF
+ || LABEL_REF_P (x)
|| GET_CODE (x) == CONST);
output_addr_const (file, x);
switch (XINT (xconst, 1))
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 0c7ac21b2c7..94ebb9d8539 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1088,7 +1088,7 @@
{
if (!flag_pic
&& (GET_CODE (operands[1]) == SYMBOL_REF
- || GET_CODE (operands[1]) == LABEL_REF
+ || LABEL_REF_P (operands[1])
|| (GET_CODE (operands[1]) == CONST
&& (GET_CODE (XEXP (operands[1], 0)) != UNSPEC
|| (XINT (XEXP (operands[1], 0), 1)
diff --git a/gcc/config/csky/constraints.md b/gcc/config/csky/constraints.md
index d22e5a6237c..e8ada7af8a0 100644
--- a/gcc/config/csky/constraints.md
+++ b/gcc/config/csky/constraints.md
@@ -39,7 +39,7 @@
(define_constraint "R"
"Memory operands whose address is a label_ref"
(and (match_code "mem")
- (match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF")))
+ (match_test "LABEL_REF_P (XEXP (op, 0))")))
(define_constraint "S"
"Symbol reference with optional offset"
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 2cd0630ac88..a41b8ed431e 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -1413,7 +1413,7 @@ csky_minipool_load_p (rtx_insn *insn)
addr = XEXP (op1, 0);
if (GET_CODE (addr) == PLUS && CONST_INT_P (XEXP (addr, 1)))
addr = XEXP (addr, 0);
- return GET_CODE (addr) == LABEL_REF;
+ return LABEL_REF_P (addr);
}
@@ -3056,14 +3056,14 @@ csky_legitimate_address_p (machine_mode mode, rtx addr, bool strict_p)
&& ((code == LABEL_REF)
|| (code == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (addr, 0), 0))
&& CONST_INT_P (XEXP (XEXP (addr, 0), 1)))))
return 1;
if (is_csky_address_register_rtx_p (addr, strict_p))
return 1;
/* It is a pc-relative load, may be generated for constpool. */
- else if (GET_CODE (addr) == LABEL_REF)
+ else if (LABEL_REF_P (addr))
return 1;
if (code == PLUS)
@@ -3152,7 +3152,7 @@ decompose_csky_address (rtx addr, struct csky_address *out)
return true;
}
- if (GET_CODE (addr) == LABEL_REF)
+ if (LABEL_REF_P (addr))
{
out->label = addr;
return true;
@@ -3168,7 +3168,7 @@ decompose_csky_address (rtx addr, struct csky_address *out)
addends[0] = XEXP (addr, 0);
addends[1] = XEXP (addr, 1);
- if (GET_CODE (addends[0]) == LABEL_REF && CONST_INT_P (addends[1]))
+ if (LABEL_REF_P (addends[0]) && CONST_INT_P (addends[1]))
{
out->label = addends[0];
out->disp = addends[1];
@@ -3301,7 +3301,7 @@ csky_output_constpool_label (FILE *stream, rtx x)
{
char buf[15];
- gcc_assert (GET_CODE (x) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (x));
x = XEXP (x, 0);
if (GET_CODE (x) == UNSPEC_VOLATILE && XINT (x, 1) == VUNSPEC_POOL_LABEL)
@@ -4255,10 +4255,10 @@ csky_output_movedouble (rtx operands[],
decompose_csky_address (XEXP (src, 0), &op0);
- if (GET_CODE (memexp) == LABEL_REF
+ if (LABEL_REF_P (memexp)
|| (GET_CODE (memexp) == CONST
&& GET_CODE (XEXP (memexp, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (memexp, 0), 0)) == LABEL_REF))
+ && LABEL_REF_P (XEXP (XEXP (memexp, 0), 0))))
return "lrw\t%0, [%1]\n\tlrw\t%R0, [%R1]";
else if (REG_P (memexp))
basereg = REGNO (memexp);
@@ -4390,10 +4390,10 @@ csky_output_ck801_movedouble (rtx operands[],
decompose_csky_address (XEXP (src, 0), &op0);
- if (GET_CODE (memexp) == LABEL_REF
+ if (LABEL_REF_P (memexp)
|| (GET_CODE (memexp) == CONST
&& GET_CODE (XEXP (memexp, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (memexp, 0), 0)) == LABEL_REF))
+ && LABEL_REF_P (XEXP (XEXP (memexp, 0), 0))))
return "lrw\t%0, [%1]\n\tlrw\t%R0, [%R1]";
else if (REG_P (memexp))
basereg = REGNO (memexp);
@@ -4732,7 +4732,7 @@ csky_symbolic_address_p (rtx x)
case CONST:
x = XEXP (x, 0);
return ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (x, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (x, 0)))
&& CONST_INT_P (XEXP (x, 1)));
default:
return 0;
@@ -5621,7 +5621,7 @@ csky_label_mentioned_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (x));
@@ -5679,7 +5679,7 @@ csky_legitimize_pic_address (rtx orig, rtx reg, bool gotrel_p)
rtx pic_reg = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
bool optimize_p = false;
- if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
+ if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
{
rtx pic_ref, address, rtx_tmp;
rtx insn;
diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h
index ea95290eae2..1c86fd10b18 100644
--- a/gcc/config/csky/csky.h
+++ b/gcc/config/csky/csky.h
@@ -686,7 +686,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF)
+ (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF)
/* Maximum number of registers that can appear in a valid memory address.
Shifts in addresses can't be by a register. */
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index ef6e27ff34c..4ca16520080 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -822,7 +822,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
return orig;
/* First handle a simple SYMBOL_REF or LABEL_REF */
- if (GET_CODE (orig) == LABEL_REF
+ if (LABEL_REF_P (orig)
|| GET_CODE (orig) == SYMBOL_REF)
{
/* addr(foo) = &func+(foo-func) */
@@ -849,7 +849,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#if HAVE_lo_sum
if (MACHO_DYNAMIC_NO_PIC_P
&& (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (orig, 0)) == LABEL_REF))
+ || LABEL_REF_P (XEXP (orig, 0))))
{
#if defined (TARGET_TOC) /* ppc */
rtx temp_reg = (!can_create_pseudo_p ()
@@ -872,7 +872,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
}
else
if (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (orig, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (orig, 0)))
{
rtx offset = machopic_gen_offset (XEXP (orig, 0));
#if defined (TARGET_TOC) /* i.e., PowerPC */
@@ -942,7 +942,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#if HAVE_lo_sum
if (GET_CODE (orig) == SYMBOL_REF
- || GET_CODE (orig) == LABEL_REF)
+ || LABEL_REF_P (orig))
{
rtx offset = machopic_gen_offset (orig);
#if defined (TARGET_TOC) /* i.e., PowerPC */
@@ -1025,7 +1025,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
else if (GET_CODE (orig) == PLUS
&& (MEM_P (XEXP (orig, 0))
|| GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (orig, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (orig, 0)))
&& XEXP (orig, 0) != pic_offset_table_rtx
&& !REG_P (XEXP (orig, 1)))
@@ -1770,7 +1770,7 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
else if (MACHOPIC_INDIRECT
&& (GET_CODE (x) == SYMBOL_REF
|| GET_CODE (x) == CONST
- || GET_CODE (x) == LABEL_REF))
+ || LABEL_REF_P (x)))
return darwin_sections[const_data_section];
else
return darwin_sections[const_section];
diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h
index 38f6cac5a59..8d5a9c55616 100644
--- a/gcc/config/epiphany/epiphany.h
+++ b/gcc/config/epiphany/epiphany.h
@@ -602,7 +602,7 @@ typedef struct GTY (()) machine_function
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
-(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+(LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) || GET_CODE (X) == CONST)
#define RTX_OK_FOR_OFFSET_P(MODE, X) \
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index 07b44b5ec65..b59c23b9c10 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -27,7 +27,7 @@
if (GET_CODE (op) == SYMBOL_REF)
return (!epiphany_is_long_call_p (op)
&& (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return true;
if (GET_CODE (op) == CONST)
{
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index e16508dba44..13e8dafbc7d 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -4046,7 +4046,7 @@ frv_emit_movsi (rtx dest, rtx src)
sym = XEXP (sym, 0);
if (GET_CODE (sym) == SYMBOL_REF)
goto handle_sym;
- else if (GET_CODE (sym) == LABEL_REF)
+ else if (LABEL_REF_P (sym))
goto handle_label;
else
goto handle_whatever;
@@ -4280,7 +4280,7 @@ output_move_single (rtx operands[], rtx insn)
}
else if (GET_CODE (src) == SYMBOL_REF
- || GET_CODE (src) == LABEL_REF
+ || LABEL_REF_P (src)
|| GET_CODE (src) == CONST)
{
return "#";
@@ -6825,7 +6825,7 @@ frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
{
if (GET_CODE (value) == CONST
|| GET_CODE (value) == SYMBOL_REF
- || GET_CODE (value) == LABEL_REF)
+ || LABEL_REF_P (value))
{
if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (value))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index fb4f13b32e6..9fd855646c8 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -524,7 +524,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
op = XEXP (op, 0);
- return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
+ return GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op);
case SYMBOL_REF:
if (TARGET_FDPIC)
diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md
index 09a687e309a..b6f2bb1ba87 100644
--- a/gcc/config/ft32/constraints.md
+++ b/gcc/config/ft32/constraints.md
@@ -27,14 +27,14 @@
(and (match_code "mem")
(match_test "(!ft32_is_mem_pm(op))")
(ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF")
- (match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF")
+ (match_test "LABEL_REF_P (XEXP (op, 0))")
(match_test "CONST_INT_P (XEXP (op, 0))")
(and (match_test "(GET_CODE (XEXP (op, 0)) == PLUS)")
(ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF")
- (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF")
+ (match_test "LABEL_REF_P (XEXP (XEXP (op, 0), 0))")
(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 0))"))
(ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == SYMBOL_REF")
- (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF")
+ (match_test "LABEL_REF_P (XEXP (XEXP (op, 0), 1))")
(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))))
(define_memory_constraint "B"
@@ -55,7 +55,7 @@
(and (match_code "mem")
(match_test "ft32_is_mem_pm(op) && (
(GET_CODE (XEXP (op, 0)) == SYMBOL_REF) ||
- (GET_CODE (XEXP (op, 0)) == LABEL_REF) ||
+ (LABEL_REF_P (XEXP (op, 0))) ||
(CONST_INT_P (XEXP (op, 0))) ||
(GET_CODE (XEXP (op, 0)) == CONST))"
)))
@@ -98,7 +98,7 @@
(ior
(and (match_code "const_int")
(match_test "ival >= -524288 && ival <= 524287"))
- (match_test "GET_CODE (op) == LABEL_REF")
+ (match_test "LABEL_REF_P (op)")
(match_test "GET_CODE (op) == SYMBOL_REF")
(match_test "GET_CODE (op) == CONST")))
diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c
index d0f2ce262db..87defc3824f 100644
--- a/gcc/config/ft32/ft32.c
+++ b/gcc/config/ft32/ft32.c
@@ -890,7 +890,7 @@ ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
if (REG_P (x) && reg_ok_for_base_p (x, strict))
goto yes;
if (GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == LABEL_REF || CONST_INT_P (x))
+ || LABEL_REF_P (x) || CONST_INT_P (x))
goto yes;
}
else
diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md
index 174ef8d0bf7..cf30c11848d 100644
--- a/gcc/config/ft32/ft32.md
+++ b/gcc/config/ft32/ft32.md
@@ -301,7 +301,7 @@
if (!REG_P(o) &&
!CONST_INT_P(o) &&
GET_CODE(o) != SYMBOL_REF &&
- GET_CODE(o) != LABEL_REF) {
+ !LABEL_REF_P (o)) {
operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
}
}
@@ -440,7 +440,7 @@
if (!REG_P(o) &&
!CONST_INT_P(o) &&
GET_CODE(o) != SYMBOL_REF &&
- GET_CODE(o) != LABEL_REF) {
+ !LABEL_REF_P (o)) {
operands[0] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[0], 0)));
}
}
diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md
index a77301f0b37..51bdedd60ef 100644
--- a/gcc/config/ft32/predicates.md
+++ b/gcc/config/ft32/predicates.md
@@ -33,7 +33,7 @@
(match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
{
/* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
- if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ if (MEM_P (op) && LABEL_REF_P (XEXP (op, 0)))
return 1;
if (MEM_P (op)
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index bc57f0d7c33..402713135d4 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -2112,14 +2112,14 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src)
&& AS_FLAT_P (MEM_ADDR_SPACE (dest))
&& (gcn_flat_address_p (XEXP (dest, 0), mode)
|| GET_CODE (XEXP (dest, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (dest, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (dest, 0)))
&& gcn_vgpr_register_operand (src, mode))
return true;
else if (MEM_P (src)
&& AS_FLAT_P (MEM_ADDR_SPACE (src))
&& (gcn_flat_address_p (XEXP (src, 0), mode)
|| GET_CODE (XEXP (src, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (src, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (src, 0)))
&& gcn_vgpr_register_operand (dest, mode))
return true;
@@ -2127,14 +2127,14 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src)
&& AS_GLOBAL_P (MEM_ADDR_SPACE (dest))
&& (gcn_global_address_p (XEXP (dest, 0))
|| GET_CODE (XEXP (dest, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (dest, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (dest, 0)))
&& gcn_vgpr_register_operand (src, mode))
return true;
else if (MEM_P (src)
&& AS_GLOBAL_P (MEM_ADDR_SPACE (src))
&& (gcn_global_address_p (XEXP (src, 0))
|| GET_CODE (XEXP (src, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (src, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (src, 0)))
&& gcn_vgpr_register_operand (dest, mode))
return true;
@@ -2142,14 +2142,14 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src)
&& MEM_ADDR_SPACE (dest) == ADDR_SPACE_SCALAR_FLAT
&& (gcn_scalar_flat_address_p (XEXP (dest, 0))
|| GET_CODE (XEXP (dest, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (dest, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (dest, 0)))
&& gcn_ssrc_register_operand (src, mode))
return true;
else if (MEM_P (src)
&& MEM_ADDR_SPACE (src) == ADDR_SPACE_SCALAR_FLAT
&& (gcn_scalar_flat_address_p (XEXP (src, 0))
|| GET_CODE (XEXP (src, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (src, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (src, 0)))
&& gcn_sdst_register_operand (dest, mode))
return true;
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index f4c8e8d1251..202805b486a 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -407,7 +407,7 @@
if (<MODE>mode == DImode
&& (GET_CODE (operands[1]) == SYMBOL_REF
- || GET_CODE (operands[1]) == LABEL_REF))
+ || LABEL_REF_P (operands[1])))
{
if (lra_in_progress)
emit_insn (gen_movdi_symbol_save_scc (operands[0], operands[1]));
@@ -819,7 +819,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=Sg")
(match_operand:DI 1 "general_operand" "Y"))
(clobber (reg:BI SCC_REG))]
- "GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == LABEL_REF"
+ "GET_CODE (operands[1]) == SYMBOL_REF || LABEL_REF_P (operands[1])"
{
if (SYMBOL_REF_P (operands[1])
&& SYMBOL_REF_WEAK (operands[1]))
@@ -840,7 +840,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=Sg")
(match_operand:DI 1 "general_operand" "Y"))
(clobber (reg:BI CC_SAVE_REG))]
- "(GET_CODE (operands[1]) == SYMBOL_REF || GET_CODE (operands[1]) == LABEL_REF)
+ "(GET_CODE (operands[1]) == SYMBOL_REF || LABEL_REF_P (operands[1]))
&& (lra_in_progress || reload_completed)"
{
/* !!! These sequences clobber CC_SAVE_REG. */
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index 7a676f7ba8d..f0f95125404 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -477,7 +477,7 @@ struct cum_arg
/* 1 if X is an rtx for a constant that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| (CONST_INT_P (X) \
/* We handle signed and unsigned offsets here. */ \
&& INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000) \
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 180a0a1c88d..4b74e1fe0f2 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4941,7 +4941,7 @@ symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+ if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -9886,7 +9886,7 @@ ix86_legitimate_constant_p (machine_mode mode, rtx x)
}
/* We must have drilled down to a symbol. */
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return true;
if (GET_CODE (x) != SYMBOL_REF)
return false;
@@ -10056,7 +10056,7 @@ legitimate_pic_address_disp_p (rtx disp)
if (INTVAL (op1) >= 16*1024*1024
|| INTVAL (op1) < -16*1024*1024)
break;
- if (GET_CODE (op0) == LABEL_REF)
+ if (LABEL_REF_P (op0))
return true;
if (GET_CODE (op0) == CONST
&& GET_CODE (XEXP (op0, 0)) == UNSPEC
@@ -10130,7 +10130,7 @@ legitimate_pic_address_disp_p (rtx disp)
return false;
if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
- && GET_CODE (XVECEXP (disp, 0, 0)) != LABEL_REF)
+ && !LABEL_REF_P (XVECEXP (disp, 0, 0)))
return false;
return true;
}
@@ -10159,13 +10159,13 @@ legitimate_pic_address_disp_p (rtx disp)
text labels with @GOT rather than @GOTOFF. See gotoff_operand for
details. */
return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
- || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF);
+ || LABEL_REF_P (XVECEXP (disp, 0, 0)));
case UNSPEC_GOTOFF:
/* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
While ABI specify also 32bit relocation but we don't produce it in
small PIC model at all. */
if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
- || GET_CODE (XVECEXP (disp, 0, 0)) == LABEL_REF)
+ || LABEL_REF_P (XVECEXP (disp, 0, 0)))
&& !TARGET_64BIT)
return !TARGET_PECOFF && gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
return false;
@@ -10408,7 +10408,7 @@ ix86_legitimate_address_p (machine_mode, rtx addr, bool strict)
that never results in lea, this seems to be easier and
correct fix for crash to disable this test. */
}
- else if (GET_CODE (disp) != LABEL_REF
+ else if (!LABEL_REF_P (disp)
&& !CONST_INT_P (disp)
&& (GET_CODE (disp) != CONST
|| !ix86_legitimate_constant_p (Pmode, disp))
@@ -10530,7 +10530,7 @@ legitimize_pic_address (rtx orig, rtx reg)
else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
/* We can't use @GOTOFF for text labels
on VxWorks, see gotoff_operand. */
- || (TARGET_VXWORKS_RTP && GET_CODE (addr) == LABEL_REF))
+ || (TARGET_VXWORKS_RTP && LABEL_REF_P (addr)))
{
rtx tmp = legitimize_pe_coff_symbol (addr, true);
if (tmp)
@@ -10654,7 +10654,7 @@ legitimize_pic_address (rtx orig, rtx reg)
just disp32, not base nor index. */
if (TARGET_64BIT
&& (GET_CODE (base) == SYMBOL_REF
- || GET_CODE (base) == LABEL_REF))
+ || LABEL_REF_P (base)))
base = force_reg (mode, base);
if (GET_CODE (new_rtx) == PLUS
&& CONSTANT_P (XEXP (new_rtx, 1)))
@@ -12957,7 +12957,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
putc ('$', file);
}
else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == LABEL_REF)
+ || LABEL_REF_P (x))
{
if (ASSEMBLER_DIALECT == ASM_ATT)
putc ('$', file);
@@ -13052,7 +13052,7 @@ ix86_print_operand_address_as (FILE *file, rtx addr,
&& CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
symbol = XEXP (XEXP (disp, 0), 0);
- if (GET_CODE (symbol) == LABEL_REF
+ if (LABEL_REF_P (symbol)
|| (GET_CODE (symbol) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (symbol) == 0))
base = pc_rtx;
@@ -13141,7 +13141,7 @@ ix86_print_operand_address_as (FILE *file, rtx addr,
{
if (flag_pic)
output_pic_addr_const (file, disp, 0);
- else if (GET_CODE (disp) == LABEL_REF)
+ else if (LABEL_REF_P (disp))
output_asm_label (disp);
else
output_addr_const (file, disp);
@@ -13177,7 +13177,7 @@ ix86_print_operand_address_as (FILE *file, rtx addr,
if (flag_pic)
output_pic_addr_const (file, disp, 0);
- else if (GET_CODE (disp) == LABEL_REF)
+ else if (LABEL_REF_P (disp))
output_asm_label (disp);
else if (CONST_INT_P (disp))
offset = disp;
@@ -15663,7 +15663,7 @@ ix86_rip_relative_addr_p (struct ix86_address *parts)
&& CONST_INT_P (XEXP (symbol, 1)))
symbol = XEXP (symbol, 0);
- if (GET_CODE (symbol) == LABEL_REF
+ if (LABEL_REF_P (symbol)
|| (GET_CODE (symbol) == SYMBOL_REF
&& SYMBOL_REF_TLS_MODEL (symbol) == 0)
|| (GET_CODE (symbol) == UNSPEC
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index fba015c4260..3f037a72b18 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1844,7 +1844,7 @@ typedef struct ix86_args {
#define SYMBOLIC_CONST(X) \
(GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
\f
/* Max number of args passed in registers. If this is more than 3, we will
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index e19a591fa9d..785a0d11b1b 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -8477,7 +8477,7 @@
(clobber (reg:CC FLAGS_REG))])]
{
if (GET_CODE (operands[2]) == SYMBOL_REF
- || GET_CODE (operands[2]) == LABEL_REF)
+ || LABEL_REF_P (operands[2]))
{
operands[2] = shallow_copy_rtx (operands[2]);
PUT_MODE (operands[2], SImode);
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 8a241915ee8..9cf0473bd97 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -511,7 +511,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) == SYMBOL_REF
- || GET_CODE (op) == LABEL_REF
+ || LABEL_REF_P (op)
|| (GET_CODE (op) == UNSPEC
&& (XINT (op, 1) == UNSPEC_GOT
|| XINT (op, 1) == UNSPEC_GOTOFF
@@ -524,7 +524,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) == SYMBOL_REF
- || GET_CODE (op) == LABEL_REF)
+ || LABEL_REF_P (op))
return true;
/* Only @GOTOFF gets offsets. */
if (GET_CODE (op) != UNSPEC
@@ -533,7 +533,7 @@
op = XVECEXP (op, 0, 0);
if (GET_CODE (op) == SYMBOL_REF
- || GET_CODE (op) == LABEL_REF)
+ || LABEL_REF_P (op))
return true;
return false;
@@ -551,7 +551,7 @@
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return true;
if (GET_CODE (op) != SYMBOL_REF)
@@ -1132,7 +1132,7 @@
if (TARGET_64BIT
&& flag_pic
&& (GET_CODE (disp) == SYMBOL_REF
- || GET_CODE (disp) == LABEL_REF))
+ || LABEL_REF_P (disp)))
return false;
}
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index 74e52a16c7b..44a6fbfe122 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -292,7 +292,7 @@ iq2000_check_split (rtx address, machine_mode mode)
if ((GET_CODE (address) == SYMBOL_REF)
|| (GET_CODE (address) == CONST
&& GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF)
- || GET_CODE (address) == LABEL_REF)
+ || LABEL_REF_P (address))
return 1;
return 0;
@@ -822,7 +822,7 @@ iq2000_address_cost (rtx addr, machine_mode mode, addr_space_t as,
rtx offset = const0_rtx;
addr = eliminate_constant_term (XEXP (addr, 0), & offset);
- if (GET_CODE (addr) == LABEL_REF)
+ if (LABEL_REF_P (addr))
return 2;
if (GET_CODE (addr) != SYMBOL_REF)
@@ -3441,7 +3441,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
rtx offset = const0_rtx;
rtx symref = eliminate_constant_term (XEXP (x, 0), & offset);
- if (GET_CODE (symref) == LABEL_REF)
+ if (LABEL_REF_P (symref))
* total = COSTS_N_INSNS (2);
else if (GET_CODE (symref) != SYMBOL_REF)
* total = COSTS_N_INSNS (4);
diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index 04a36ab35b1..5224b0a49be 100644
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -345,7 +345,7 @@ typedef struct iq2000_args
/* Addressing Modes. */
#define CONSTANT_ADDRESS_P(X) \
- ( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ ( (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index e75fb05cac7..c2a0f54b769 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -193,7 +193,7 @@
if (op == pc_rtx)
return 1;
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return 1;
return 0;
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 13ad0bf65d7..9f7c4cc54aa 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -899,7 +899,7 @@ nonpic_symbol_mentioned_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
+ if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x)
|| GET_CODE (x) == PC)
return 1;
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index 8e98e37d16a..636e13e25e7 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -305,7 +305,7 @@ enum reg_class
/*---------------------*/
#define CONSTANT_ADDRESS_P(X) \
- ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ ((LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 76fe95bbf18..31337484f13 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -148,7 +148,7 @@
if (flag_pic && symbolic_operand (operands[1], SImode))
{
- if (GET_CODE (operands[1]) == LABEL_REF
+ if (LABEL_REF_P (operands[1])
|| (GET_CODE (operands[1]) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (operands[1])
&& !SYMBOL_REF_WEAK (operands[1])))
@@ -173,7 +173,7 @@
{
rtx arg0 = XEXP (op, 0);
rtx arg1 = XEXP (op, 1);
- if (GET_CODE (arg0) == LABEL_REF
+ if (LABEL_REF_P (arg0)
|| (GET_CODE (arg0) == SYMBOL_REF
&& SYMBOL_REF_LOCAL_P (arg0)
&& !SYMBOL_REF_WEAK (arg0)))
diff --git a/gcc/config/m32r/constraints.md b/gcc/config/m32r/constraints.md
index ad338e75d3f..0734a88a841 100644
--- a/gcc/config/m32r/constraints.md
+++ b/gcc/config/m32r/constraints.md
@@ -106,13 +106,13 @@
(define_constraint "Q"
"A symbolic address loadable when ld24."
(ior (and (match_test "TARGET_ADDR24")
- (match_test "GET_CODE (op) == LABEL_REF"))
+ (match_test "LABEL_REF_P (op)"))
(match_test "addr24_operand (op, VOIDmode)")))
(define_constraint "R"
"A symbolic address loadable with ld24 can't be used."
(ior (and (match_test "TARGET_ADDR32")
- (match_test "GET_CODE (op) == LABEL_REF"))
+ (match_test "LABEL_REF_P (op)"))
(match_test "addr32_operand (op, VOIDmode)")))
(define_constraint "S"
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 044718fdc69..19533fa4323 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -571,7 +571,7 @@ addr24_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
if (flag_pic)
return 0;
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return TARGET_ADDR24;
if (GET_CODE (op) == SYMBOL_REF)
@@ -602,7 +602,7 @@ addr32_operand (rtx op, machine_mode mode)
{
rtx sym;
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return TARGET_ADDR32;
if (GET_CODE (op) == SYMBOL_REF)
@@ -1931,13 +1931,13 @@ direct_return (void)
int
m32r_legitimate_pic_operand_p (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
return 0;
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return 0;
@@ -1951,7 +1951,7 @@ m32r_legitimize_pic_address (rtx orig, rtx reg)
printf("m32r_legitimize_pic_address()\n");
#endif
- if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
+ if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
{
rtx pic_ref, address;
int subregs = 0;
@@ -1971,7 +1971,7 @@ m32r_legitimize_pic_address (rtx orig, rtx reg)
crtl->uses_pic_offset_table = 1;
- if (GET_CODE (orig) == LABEL_REF
+ if (LABEL_REF_P (orig)
|| (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
{
emit_insn (gen_gotoff_load_addr (reg, orig));
@@ -2964,7 +2964,7 @@ m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return !(GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& UINTVAL (XEXP (XEXP (x, 0), 1)) > 32767);
}
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 2e7aacf0ccc..99b976523a8 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -685,7 +685,7 @@ L2: .word STATIC
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
- ( GET_CODE (X) == LABEL_REF \
+ ( LABEL_REF_P (X) \
|| GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) \
|| (GET_CODE (X) == CONST \
diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md
index 1d7e195f5bd..e180aee143e 100644
--- a/gcc/config/m32r/predicates.md
+++ b/gcc/config/m32r/predicates.md
@@ -427,7 +427,7 @@
return 0;
if (GET_CODE (op) == SYMBOL_REF
- || GET_CODE (op) == LABEL_REF)
+ || LABEL_REF_P (op))
return 1;
if (GET_CODE (op) == CONST
diff --git a/gcc/config/m68k/constraints.md b/gcc/config/m68k/constraints.md
index 2ccb5dd7570..c0318055286 100644
--- a/gcc/config/m68k/constraints.md
+++ b/gcc/config/m68k/constraints.md
@@ -88,7 +88,7 @@
(and (match_code "mem")
(match_test "TARGET_PCREL
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF
+ || LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST)")))
(define_constraint "T"
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 0f4c1f4fda9..64cedf626e9 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1985,7 +1985,7 @@ m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
static bool
m68k_jump_table_ref_p (rtx x)
{
- if (GET_CODE (x) != LABEL_REF)
+ if (!LABEL_REF_P (x))
return false;
rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0));
@@ -2471,7 +2471,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
rtx pic_ref = orig;
/* First handle a simple SYMBOL_REF or LABEL_REF */
- if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF)
+ if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
{
gcc_assert (reg);
@@ -4662,7 +4662,7 @@ m68k_delegitimize_address (rtx orig_x)
&& XINT (unspec, 1) != UNSPEC_RELOC32))
return orig_x;
x = XVECEXP (unspec, 0, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF);
+ gcc_assert (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x));
if (unspec != XEXP (addr.offset, 0))
x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1));
if (addr.index)
@@ -4757,7 +4757,7 @@ print_operand_address (FILE *file, rtx addr)
label being accessed, otherwise it is -1. */
labelno = (address.offset
&& !address.base
- && GET_CODE (address.offset) == LABEL_REF
+ && LABEL_REF_P (address.offset)
? CODE_LABEL_NUMBER (XEXP (address.offset, 0))
: -1);
if (MOTOROLA)
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index 4f7adbff060..cd74628fe55 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -630,7 +630,7 @@ __transfer_from_trampoline () \
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) \
- ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ ((LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) || GET_CODE (X) == CONST \
|| GET_CODE (X) == HIGH) \
&& m68k_legitimate_constant_p (Pmode, X))
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index 3238211a0de..6fa1df65938 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -27,7 +27,7 @@
if (TARGET_PCREL
&& MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF
+ || LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
return general_operand (op, mode);
@@ -42,7 +42,7 @@
{
if (TARGET_PCREL && MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF
+ || LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
return nonimmediate_operand (op, mode);
@@ -56,7 +56,7 @@
{
if (TARGET_PCREL && MEM_P (op)
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF
+ || LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
return memory_operand (op, mode);
@@ -151,7 +151,7 @@
case CONST:
op = XEXP (op, 0);
return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
#if 0 /* Deleted, with corresponding change in m68k.h,
diff --git a/gcc/config/mcore/constraints.md b/gcc/config/mcore/constraints.md
index 7e00a2c587e..95750775517 100644
--- a/gcc/config/mcore/constraints.md
+++ b/gcc/config/mcore/constraints.md
@@ -93,7 +93,7 @@
(define_constraint "R"
"@internal"
(and (match_code "mem")
- (match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF")))
+ (match_test "LABEL_REF_P (XEXP (op, 0))")))
(define_constraint "S"
"An integer constant with 0, 1, or 2 bits clear."
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 30d8c8b7c58..d7c70861426 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -699,7 +699,7 @@ mcore_symbolic_address_p (rtx x)
case CONST:
x = XEXP (x, 0);
return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (x, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (x, 0)))
&& CONST_INT_P (XEXP (x, 1)));
default:
return 0;
@@ -1293,7 +1293,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
}
else if (MEM_P (src))
{
- if (GET_CODE (XEXP (src, 0)) == LABEL_REF)
+ if (LABEL_REF_P (XEXP (src, 0)))
return "lrw\t%0,[%1]"; /* a-R */
else
switch (GET_MODE (src)) /* r-m */
@@ -1371,7 +1371,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
int dstreg = REGNO (dst);
int basereg = -1;
- if (GET_CODE (memexp) == LABEL_REF)
+ if (LABEL_REF_P (memexp))
return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
else if (REG_P (memexp))
basereg = REGNO (memexp);
@@ -2334,7 +2334,7 @@ is_cond_candidate (rtx insn)
}
else if (JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) == SET
- && GET_CODE (XEXP (PATTERN (insn), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (PATTERN (insn), 1)))
return COND_BRANCH_INSN;
return COND_NO;
@@ -2489,7 +2489,7 @@ conditionalize_block (rtx_insn *first)
cond = (GET_CODE (XEXP (XEXP (br_pat, 1), 0)) == EQ);
/* Determine what kind of branch we have. */
- if (GET_CODE (XEXP (XEXP (br_pat, 1), 1)) == LABEL_REF)
+ if (LABEL_REF_P (XEXP (XEXP (br_pat, 1), 1)))
{
/* A normal branch, so extract label out of first arm. */
br_lab_num = CODE_LABEL_NUMBER (XEXP (XEXP (XEXP (br_pat, 1), 1), 0));
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h
index 5830c8514c2..2c299453016 100644
--- a/gcc/config/mcore/mcore.h
+++ b/gcc/config/mcore/mcore.h
@@ -494,7 +494,7 @@ extern const enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
#define MAX_REGS_PER_ADDRESS 1
/* Recognize any constant value that is a valid address. */
-#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
+#define CONSTANT_ADDRESS_P(X) (LABEL_REF_P (X))
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index d34f9f7125b..820761e67af 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -40,7 +40,7 @@
(match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
{
/* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
- if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ if (MEM_P (op) && LABEL_REF_P (XEXP (op, 0)))
return 1;
return general_operand (op, mode);
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index e89c527cc41..d85030c47da 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -506,7 +506,7 @@ label_mentioned_p (rtx x)
const char * fmt;
int i;
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return 1;
/* UNSPEC entries for a symbol include a LABEL_REF for the referencing
@@ -779,7 +779,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
return microblaze_classify_unspec (info, xplus1);
}
else if ((GET_CODE (xplus1) == SYMBOL_REF ||
- GET_CODE (xplus1) == LABEL_REF))
+ LABEL_REF_P (xplus1)))
{
if (flag_pic == 2 || microblaze_tls_symbol_p(xplus1))
return false;
@@ -817,7 +817,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
}
if (GET_CODE (xconst0) == SYMBOL_REF
- || GET_CODE (xconst0) == LABEL_REF)
+ || LABEL_REF_P (xconst0))
{
if (flag_pic == 2 || microblaze_tls_symbol_p(xconst0))
return false;
@@ -883,7 +883,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
/* Avoid error in print_operand_address in case UNSPEC
is removed from SYMBOL or LABEL REFS during optimization. */
- if ((GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ if ((GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
&& flag_pic && TARGET_PIC_DATA_TEXT_REL && strict == 2)
{
info->type = ADDRESS_SYMBOLIC_TXT_REL;
@@ -928,7 +928,7 @@ microblaze_legitimate_address_p (machine_mode mode, rtx x, bool strict)
bool
microblaze_constant_address_p (rtx x)
{
- return ((GET_CODE (x) == LABEL_REF) || (GET_CODE (x) == SYMBOL_REF)
+ return ((LABEL_REF_P (x)) || (GET_CODE (x) == SYMBOL_REF)
|| CONST_INT_P (x)
|| (GET_CODE (x) == CONST
&& ! (flag_pic && pic_address_needs_scratch (x))));
@@ -1505,7 +1505,7 @@ pic_address_needs_scratch (rtx x)
p0 = XEXP (XEXP (x, 0), 0);
p1 = XEXP (XEXP (x, 0), 1);
- if ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
+ if ((GET_CODE (p0) == SYMBOL_REF || LABEL_REF_P (p0))
&& (CONST_INT_P (p1))
&& (flag_pic == 2 || microblaze_tls_symbol_p (p0) || !SMALL_INT (p1)))
return 1;
@@ -3396,7 +3396,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
}
/* If operands[1] is a constant address invalid for pic, then we need to
handle it just like LEGITIMIZE_ADDRESS does. */
- if (GET_CODE (op1) == SYMBOL_REF || GET_CODE (op1) == LABEL_REF)
+ if (GET_CODE (op1) == SYMBOL_REF || LABEL_REF_P (op1))
{
rtx result;
if (microblaze_tls_symbol_p(op1))
@@ -3451,7 +3451,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
if ((CONST_INT_P (p1))
&& ((GET_CODE (p0) == UNSPEC)
- || ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
+ || ((GET_CODE (p0) == SYMBOL_REF || LABEL_REF_P (p0))
&& (flag_pic == 2 || microblaze_tls_symbol_p (p0)
|| !SMALL_INT (p1)))))
{
@@ -3787,7 +3787,7 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
if ((GET_CODE (p0) == UNSPEC))
return false;
- if ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
+ if ((GET_CODE (p0) == SYMBOL_REF || LABEL_REF_P (p0))
&& (microblaze_tls_symbol_p (p0) || !SMALL_INT (p1)))
return false;
}
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index 10ec60ca70c..fae269894c4 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -64,7 +64,7 @@
p1 = XEXP (const0, 1);
if ((GET_CODE(p0) == SYMBOL_REF
- || GET_CODE (p0) == LABEL_REF)
+ || LABEL_REF_P (p0))
&& CONST_INT_P (p1))
{
return arith_plus_operand (p0, GET_MODE(p0));
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 4730c75ec5f..34287cb40e1 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -2071,7 +2071,7 @@ mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
if (TARGET_RTP_PIC)
return SYMBOL_GOT_DISP;
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
{
/* Only return SYMBOL_PC_RELATIVE if we are generating MIPS16
code and if we know that the label is in the current function's
@@ -2185,7 +2185,7 @@ mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
*symbol_type = UNSPEC_ADDRESS_TYPE (x);
x = UNSPEC_ADDRESS (x);
}
- else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ else if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
{
*symbol_type = mips_classify_symbol (x, context);
if (*symbol_type == SYMBOL_TLS)
@@ -2219,7 +2219,7 @@ mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
/* Allow constant pool references to be converted to LABEL+CONSTANT.
In this case, we no longer have access to the underlying constant,
but the original symbol-based access was known to be valid. */
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return true;
/* Fall through. */
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index 5da6713b5a2..6f68981f777 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -1062,7 +1062,7 @@ mmix_constant_address_p (rtx x)
rtx x1 = XEXP (XEXP (x, 0), 1);
if ((GET_CODE (x0) == SYMBOL_REF
- || GET_CODE (x0) == LABEL_REF)
+ || LABEL_REF_P (x0))
&& (CONST_INT_P (x1)
|| (CONST_DOUBLE_P (x1)
&& GET_MODE (x1) == VOIDmode)))
diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md
index f74c771f30f..41e4f342826 100644
--- a/gcc/config/mmix/predicates.md
+++ b/gcc/config/mmix/predicates.md
@@ -111,7 +111,7 @@
/* The reason why this body still is C. */
op = XEXP (op, 0);
if ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (op, 0)))
&& (CONST_INT_P (XEXP (op, 1))
|| (CONST_DOUBLE_P (XEXP (op, 1))
&& GET_MODE (XEXP (op, 1)) == VOIDmode)))
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 5d5bc734898..10cce63ca3f 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -1799,7 +1799,7 @@ mn10300_symbolic_operand (rtx op,
case CONST:
op = XEXP (op, 0);
return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
default:
return 0;
@@ -1866,7 +1866,7 @@ mn10300_legitimize_pic_address (rtx orig, rtx reg)
rtx x;
rtx_insn *insn;
- if (GET_CODE (orig) == LABEL_REF
+ if (LABEL_REF_P (orig)
|| (GET_CODE (orig) == SYMBOL_REF
&& (CONSTANT_POOL_ADDRESS_P (orig)
|| ! MN10300_GLOBAL_P (orig))))
@@ -1908,7 +1908,7 @@ mn10300_legitimate_pic_operand_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
return 0;
if (GET_CODE (x) == UNSPEC
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index 6a75b967a27..4239598aece 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -538,7 +538,7 @@ do { \
#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
#define SYMBOLIC_CONST_P(X) \
-((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
+((GET_CODE (X) == SYMBOL_REF || LABEL_REF_P (X)) \
&& ! LEGITIMATE_PIC_OPERAND_P (X))
/* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */
diff --git a/gcc/config/moxie/constraints.md b/gcc/config/moxie/constraints.md
index 2d3bdc84930..554b5cb5105 100644
--- a/gcc/config/moxie/constraints.md
+++ b/gcc/config/moxie/constraints.md
@@ -26,7 +26,7 @@
"An absolute address."
(and (match_code "mem")
(ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF")
- (match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF")
+ (match_test "LABEL_REF_P (XEXP (op, 0))")
(match_test "GET_CODE (XEXP (op, 0)) == CONST"))))
(define_constraint "B"
diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c
index 7f1bb5aac95..ed532244357 100644
--- a/gcc/config/moxie/moxie.c
+++ b/gcc/config/moxie/moxie.c
@@ -604,7 +604,7 @@ moxie_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED,
if (REG_P (x) && moxie_reg_ok_for_base_p (x, strict_p))
return true;
if (GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == LABEL_REF
+ || LABEL_REF_P (x)
|| GET_CODE (x) == CONST)
return true;
return false;
diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md
index c61ce12ac28..02c7f8cc8a7 100644
--- a/gcc/config/moxie/predicates.md
+++ b/gcc/config/moxie/predicates.md
@@ -28,7 +28,7 @@
(match_code "mem,const_int,reg,subreg,symbol_ref,label_ref,const")
{
/* Any (MEM LABEL_REF) is OK. That is a pc-relative load. */
- if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ if (MEM_P (op) && LABEL_REF_P (XEXP (op, 0)))
return 1;
if (MEM_P (op)
diff --git a/gcc/config/nds32/nds32-cost.c b/gcc/config/nds32/nds32-cost.c
index 010a5ce6402..d5a9f478001 100644
--- a/gcc/config/nds32/nds32-cost.c
+++ b/gcc/config/nds32/nds32-cost.c
@@ -339,7 +339,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
return true;
case IF_THEN_ELSE:
- if (GET_CODE (XEXP (x, 1)) == LABEL_REF)
+ if (LABEL_REF_P (XEXP (x, 1)))
/* branch */
*total = COSTS_N_INSNS (2);
else
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index 1bc365f11ba..90f9c89643c 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -3456,7 +3456,7 @@ symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+ if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -3502,7 +3502,7 @@ nds32_legitimize_pic_address (rtx x)
rtx pat;
int relax_group_id = nds32_alloc_relax_group_id ();
- if (GET_CODE (x) == LABEL_REF
+ if (LABEL_REF_P (x)
|| (GET_CODE (x) == SYMBOL_REF
&& (CONSTANT_POOL_ADDRESS_P (x)
|| SYMBOL_REF_LOCAL_P (x))))
@@ -3531,7 +3531,7 @@ nds32_legitimize_pic_address (rtx x)
rtx op0 = XEXP (addr, 0);
rtx op1 = XEXP (addr, 1);
- if ((GET_CODE (op0) == LABEL_REF
+ if ((LABEL_REF_P (op0)
|| (GET_CODE (op0) == SYMBOL_REF
&& (CONSTANT_POOL_ADDRESS_P (op0)
|| SYMBOL_REF_LOCAL_P (op0))))
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index 60a5f19cfd8..1a8a6675bba 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -1492,7 +1492,7 @@ enum reg_class
#define SYMBOLIC_CONST_P(X) \
(GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
\f
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 6378b7567a5..d2a85d0ad6f 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -2048,7 +2048,7 @@ nios2_symbolic_constant_p (rtx x)
if (flag_pic)
return false;
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return true;
else if (CONSTANT_P (x))
{
@@ -2554,7 +2554,7 @@ nios2_legitimate_pic_operand_p (rtx x)
return true;
return ! (GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == LABEL_REF || GET_CODE (x) == CONST);
+ || LABEL_REF_P (x) || GET_CODE (x) == CONST);
}
/* Return TRUE if X is a thread-local symbol. */
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index dd3b14c515a..07180eaad07 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -4863,13 +4863,13 @@ nvptx_condjump_label (const rtx_insn *insn, bool strict = true)
if (!x)
return NULL_RTX;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return x;
if (GET_CODE (x) != IF_THEN_ELSE)
return NULL_RTX;
- if (XEXP (x, 2) == pc_rtx && GET_CODE (XEXP (x, 1)) == LABEL_REF)
+ if (XEXP (x, 2) == pc_rtx && LABEL_REF_P (XEXP (x, 1)))
return XEXP (x, 1);
- if (XEXP (x, 1) == pc_rtx && GET_CODE (XEXP (x, 2)) == LABEL_REF)
+ if (XEXP (x, 1) == pc_rtx && LABEL_REF_P (XEXP (x, 2)))
return XEXP (x, 2);
return NULL_RTX;
}
diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md
index 58a18fe21cf..20f97be5861 100644
--- a/gcc/config/nvptx/nvptx.md
+++ b/gcc/config/nvptx/nvptx.md
@@ -288,7 +288,7 @@
DONE;
}
- if (GET_CODE (operands[1]) == LABEL_REF)
+ if (LABEL_REF_P (operands[1]))
sorry ("target cannot support label values");
})
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 1df00c00dbf..418dfc8c8f4 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -10355,7 +10355,7 @@ pa_legitimate_constant_p (machine_mode mode, rtx x)
if (GET_MODE_CLASS (mode) == MODE_FLOAT && x != CONST0_RTX (mode))
return false;
- if (!NEW_HP_ASSEMBLER && !TARGET_GAS && GET_CODE (x) == LABEL_REF)
+ if (!NEW_HP_ASSEMBLER && !TARGET_GAS && LABEL_REF_P (x))
return false;
/* TLS_MODEL_GLOBAL_DYNAMIC and TLS_MODEL_LOCAL_DYNAMIC are not
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 8de85da726d..b6b7ed17a5c 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -766,7 +766,7 @@ extern int may_call_alloca;
use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
#define CONSTANT_ADDRESS_P(X) \
- ((GET_CODE (X) == LABEL_REF \
+ ((LABEL_REF_P (X) \
|| (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
|| CONST_INT_P (X) \
|| (GET_CODE (X) == CONST && !tls_referenced_p (X)) \
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index f0e498e2782..5f7c45053cf 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -2538,7 +2538,7 @@
xoperands[0] = operands[0];
xoperands[1] = operands[1];
- if (GET_CODE (operands[1]) == LABEL_REF
+ if (LABEL_REF_P (operands[1])
&& !LABEL_REF_NONLOCAL_P (operands[1]))
{
xoperands[2] = gen_label_rtx ();
@@ -2588,7 +2588,7 @@
xoperands[0] = operands[0];
xoperands[1] = operands[1];
- if (GET_CODE (operands[1]) == LABEL_REF
+ if (LABEL_REF_P (operands[1])
&& !LABEL_REF_NONLOCAL_P (operands[1]))
{
xoperands[2] = gen_label_rtx ();
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 5fd0279c9fa..a633a276509 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -504,7 +504,7 @@
return true;
case CONST:
op = XEXP (op, 0);
- return (GET_CODE (XEXP (op, 0)) == LABEL_REF
+ return (LABEL_REF_P (XEXP (op, 0))
&& CONST_INT_P (XEXP (op, 1)));
default:
gcc_unreachable ();
@@ -630,7 +630,7 @@
return (GET_CODE (op) == PLUS
&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
- || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
default:
break;
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index c03f5b1e66c..c885bb5f0eb 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -581,7 +581,7 @@ riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type)
*symbol_type = UNSPEC_ADDRESS_TYPE (x);
x = UNSPEC_ADDRESS (x);
}
- else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ else if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
*symbol_type = riscv_classify_symbol (x);
else
return false;
diff --git a/gcc/config/rs6000/freebsd64.h b/gcc/config/rs6000/freebsd64.h
index 9367a6e40f3..b6b75635799 100644
--- a/gcc/config/rs6000/freebsd64.h
+++ b/gcc/config/rs6000/freebsd64.h
@@ -405,7 +405,7 @@ extern int dot_symbols;
&& (SYMBOL_REF_P (X) \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& SYMBOL_REF_P (XEXP (XEXP (X, 0), 0))) \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (CONST_INT_P (X) \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
|| (CONST_DOUBLE_P (X) \
diff --git a/gcc/config/rs6000/linux64.h b/gcc/config/rs6000/linux64.h
index 4d329b544ad..f34c16a29f7 100644
--- a/gcc/config/rs6000/linux64.h
+++ b/gcc/config/rs6000/linux64.h
@@ -574,7 +574,7 @@ extern int dot_symbols;
&& (SYMBOL_REF_P (X) \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& SYMBOL_REF_P (XEXP (XEXP (X, 0), 0))) \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (CONST_INT_P (X) \
&& TARGET_CMODEL != CMODEL_MEDIUM \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index d84e743c1af..facc468ec7c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -9738,7 +9738,7 @@ rs6000_emit_move (rtx dest, rtx source, machine_mode mode)
&& TARGET_NO_SUM_IN_TOC
&& GET_CODE (XEXP (operands[1], 0)) == PLUS
&& add_operand (XEXP (XEXP (operands[1], 0), 1), mode)
- && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (XEXP (operands[1], 0), 0))
|| SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0)))
&& ! side_effects_p (operands[0]))
{
@@ -11976,7 +11976,7 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode,
if (rclass != BASE_REGS
&& (SYMBOL_REF_P (in)
|| GET_CODE (in) == HIGH
- || GET_CODE (in) == LABEL_REF
+ || LABEL_REF_P (in)
|| GET_CODE (in) == CONST))
return BASE_REGS;
}
@@ -12629,7 +12629,7 @@ print_operand (FILE *file, rtx x, int code)
{
if (GET_CODE (XEXP (x, 0)) != PLUS
|| (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
- && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
+ && !LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
|| !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
output_operand_lossage ("invalid %%K value");
}
@@ -13097,7 +13097,7 @@ print_operand_address (FILE *file, rtx x)
fputs ("@pcrel", file);
}
else if (SYMBOL_REF_P (x) || GET_CODE (x) == CONST
- || GET_CODE (x) == LABEL_REF)
+ || LABEL_REF_P (x))
{
output_addr_const (file, x);
if (small_data_operand (x, GET_MODE (x)))
@@ -16064,7 +16064,7 @@ output_toc (FILE *file, rtx x, int labelno, machine_mode mode)
TOC entries (this happens on AIX if there is any kind of TOC,
and on SVR4 under -fPIC or -mrelocatable). Don't do this for
CODE_LABELs. */
- if (TARGET_TOC && GET_CODE (x) != LABEL_REF)
+ if (TARGET_TOC && !LABEL_REF_P (x))
{
struct toc_hash_struct *h;
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 9c11a3e4d46..b1952ca6ab1 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1745,7 +1745,7 @@ typedef struct rs6000_args
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == LABEL_REF || SYMBOL_REF_P (X) \
+ (LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == CONST \
|| GET_CODE (X) == HIGH)
diff --git a/gcc/config/rs6000/rtems.h b/gcc/config/rs6000/rtems.h
index 0c198020a42..7176bb5f2a4 100644
--- a/gcc/config/rs6000/rtems.h
+++ b/gcc/config/rs6000/rtems.h
@@ -225,7 +225,7 @@
&& (SYMBOL_REF_P (X) \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& SYMBOL_REF_P (XEXP (XEXP (X, 0), 0))) \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (CONST_INT_P (X) \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
|| (CONST_DOUBLE_P (X) \
diff --git a/gcc/config/rs6000/sysv4.h b/gcc/config/rs6000/sysv4.h
index 4645ef3b21e..ad80cb9bc91 100644
--- a/gcc/config/rs6000/sysv4.h
+++ b/gcc/config/rs6000/sysv4.h
@@ -380,7 +380,7 @@ do { \
&& (SYMBOL_REF_P (X) \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& SYMBOL_REF_P (XEXP (XEXP (X, 0), 0))) \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (CONST_INT_P (X) \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
|| (!TARGET_NO_FP_IN_TOC \
diff --git a/gcc/config/rs6000/xcoff.h b/gcc/config/rs6000/xcoff.h
index 80b2dcfba55..23e3f5efb68 100644
--- a/gcc/config/rs6000/xcoff.h
+++ b/gcc/config/rs6000/xcoff.h
@@ -78,7 +78,7 @@
&& (SYMBOL_REF_P (X) \
|| (GET_CODE (X) == CONST && GET_CODE (XEXP (X, 0)) == PLUS \
&& SYMBOL_REF_P (XEXP (XEXP (X, 0), 0))) \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (CONST_INT_P (X) \
&& GET_MODE_BITSIZE (MODE) <= GET_MODE_BITSIZE (Pmode)) \
|| (CONST_DOUBLE_P (X) \
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index e529f8b173e..b8d182e5944 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -136,7 +136,7 @@ rx_pid_data_operand (rtx op)
{
/* Sigh, some special cases. */
if (GET_CODE (op) == SYMBOL_REF
- || GET_CODE (op) == LABEL_REF)
+ || LABEL_REF_P (op))
return PID_UNENCODED;
}
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index e7ce44dbb43..40b11c23d03 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -158,7 +158,7 @@
(match_code "label_ref, symbol_ref, const")
{
/* Allow labels and local symbols. */
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return true;
if (SYMBOL_REF_P (op))
return (!SYMBOL_FLAG_NOTALIGN2_P (op)
@@ -183,7 +183,7 @@
}
/* Labels and local symbols allowed here as well. */
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return true;
if (SYMBOL_REF_P (op))
return (!SYMBOL_FLAG_NOTALIGN2_P (op)
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index acec764bc42..6f85090f2ce 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -3961,7 +3961,7 @@ symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF)
+ if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
return 1;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -4885,7 +4885,7 @@ legitimize_pic_address (rtx orig, rtx reg)
addr = XEXP (addr, 0);
}
- if ((GET_CODE (addr) == LABEL_REF
+ if ((LABEL_REF_P (addr)
|| (SYMBOL_REF_P (addr) && s390_rel_address_ok_p (addr))
|| (GET_CODE (addr) == UNSPEC &&
(XINT (addr, 1) == UNSPEC_GOTENT
@@ -13861,10 +13861,10 @@ s390_fix_long_loop_prediction (rtx_insn *insn)
&& XEXP (SET_SRC (set), 2) == pc_rtx)
return false;
- label_ref = (GET_CODE (XEXP (SET_SRC (set), 1)) == LABEL_REF ?
+ label_ref = (LABEL_REF_P (XEXP (SET_SRC (set), 1)) ?
XEXP (SET_SRC (set), 1) : XEXP (SET_SRC (set), 2));
- gcc_assert (GET_CODE (label_ref) == LABEL_REF);
+ gcc_assert (LABEL_REF_P (label_ref));
code_label = XEXP (label_ref, 0);
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index 969f58a2ba0..adf64951258 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -808,7 +808,7 @@ CUMULATIVE_ARGS;
/* Helper macro for s390.c and s390.md to check for symbolic constants. */
#define SYMBOLIC_CONST(X) \
(GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == LABEL_REF \
+ || LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
#define TLS_SYMBOLIC_CONST(X) \
diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md
index 4b19143d90e..5907bc8d73d 100644
--- a/gcc/config/sh/predicates.md
+++ b/gcc/config/sh/predicates.md
@@ -286,11 +286,11 @@
if (GET_CODE (inside) == CONST)
inside = XEXP (inside, 0);
- if (GET_CODE (inside) == LABEL_REF)
+ if (LABEL_REF_P (inside))
return 1;
if (GET_CODE (inside) == PLUS
- && GET_CODE (XEXP (inside, 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (inside, 0))
&& CONST_INT_P (XEXP (inside, 1)))
return 1;
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 1a2d110c2ae..2d1bd801851 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -4838,7 +4838,7 @@ mova_p (rtx_insn *insn)
&& GET_CODE (SET_SRC (PATTERN (insn))) == UNSPEC
&& XINT (SET_SRC (PATTERN (insn)), 1) == UNSPEC_MOVA
/* Don't match mova_const. */
- && GET_CODE (MOVA_LABELREF (insn)) == LABEL_REF);
+ && LABEL_REF_P (MOVA_LABELREF (insn)));
}
/* Fix up a mova from a switch that went out of range. */
@@ -5711,7 +5711,7 @@ fixup_addr_diff_vecs (rtx_insn *first)
if (GET_CODE (x) != USE)
continue;
x = XEXP (x, 0);
- if (GET_CODE (x) == LABEL_REF && XEXP (x, 0) == vec_lab)
+ if (LABEL_REF_P (x) && XEXP (x, 0) == vec_lab)
break;
}
/* FIXME: This is a bug in the optimizer, but it seems harmless
@@ -5988,7 +5988,7 @@ sh_reorg (void)
optimize calls to a constant location, but the assembler
and linker do not support that at present. */
if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
- && GET_CODE (SET_SRC (set)) != LABEL_REF)
+ && !LABEL_REF_P (SET_SRC (set)))
continue;
/* Scan forward from LINK to the place where REG dies, and
@@ -9096,7 +9096,7 @@ sh_legitimate_address_p (machine_mode mode, rtx x, bool strict)
bool
nonpic_symbol_mentioned_p (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF
+ if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x)
|| GET_CODE (x) == PC)
return true;
@@ -9145,7 +9145,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
if (tls_symbolic_operand (orig, Pmode) != TLS_MODEL_NONE)
return orig;
- if (GET_CODE (orig) == LABEL_REF
+ if (LABEL_REF_P (orig)
|| (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
{
if (reg == NULL_RTX)
@@ -9162,7 +9162,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
emit_insn (gen_symGOTOFFFUNCDESC2reg (reg, orig));
}
else if (TARGET_FDPIC
- && (GET_CODE (orig) == LABEL_REF
+ && (LABEL_REF_P (orig)
|| (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig)
&& (TREE_READONLY (SYMBOL_REF_DECL (orig))
|| SYMBOL_REF_EXTERNAL_P (orig)
@@ -10710,7 +10710,7 @@ sh_mark_label (rtx address, int nuses)
address = XEXP (address, 0);
address = XVECEXP (address, 0, 0);
}
- if (GET_CODE (address) == LABEL_REF
+ if (LABEL_REF_P (address)
&& LABEL_P (XEXP (address, 0)))
LABEL_NUSES (XEXP (address, 0)) += nuses;
}
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index f753c611aaf..4305398f9ff 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1338,7 +1338,7 @@ extern bool current_function_interrupt;
#define MAX_REGS_PER_ADDRESS 2
/* Recognize any constant value that is a valid address. */
-#define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF)
+#define CONSTANT_ADDRESS_P(X) (LABEL_REF_P (X))
/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
and check its validity for a certain class.
@@ -1363,10 +1363,10 @@ extern bool current_function_interrupt;
/* Macros for extra constraints. */
#define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \
- ((GET_CODE ((OP)) == LABEL_REF) \
+ ((LABEL_REF_P ((OP))) \
|| (GET_CODE ((OP)) == CONST \
&& GET_CODE (XEXP ((OP), 0)) == PLUS \
- && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \
+ && LABEL_REF_P (XEXP (XEXP ((OP), 0), 0)) \
&& CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
#define IS_NON_EXPLICIT_CONSTANT_P(OP) \
@@ -1376,7 +1376,7 @@ extern bool current_function_interrupt;
&& (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \
&& !PIC_ADDR_P (OP) \
- && GET_CODE (OP) != LABEL_REF)))
+ && !LABEL_REF_P (OP))))
#define GOT_ENTRY_P(OP) \
(GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \
@@ -1406,13 +1406,13 @@ extern bool current_function_interrupt;
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
#define NON_PIC_REFERENCE_P(OP) \
- (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \
+ (LABEL_REF_P (OP) || GET_CODE (OP) == SYMBOL_REF \
|| (GET_CODE (OP) == CONST \
- && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \
+ && (LABEL_REF_P (XEXP ((OP), 0)) \
|| GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \
|| (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
&& (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
- || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \
+ || LABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
&& CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
#define PIC_REFERENCE_P(OP) \
@@ -1595,7 +1595,7 @@ extern bool current_function_interrupt;
|| ! nonpic_symbol_mentioned_p (get_pool_constant (X)))))
#define SYMBOLIC_CONST_P(X) \
-((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \
+((GET_CODE (X) == SYMBOL_REF || LABEL_REF_P (X)) \
&& nonpic_symbol_mentioned_p (X))
\f
/* Compute extra cost of moving data between one register class
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index b1c2059dd43..7d1f700d421 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -108,7 +108,7 @@
op = XEXP (op, 0);
return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
- || GET_CODE (XEXP (op, 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
default:
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index f3f61bdb947..b5540da8d4a 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2253,11 +2253,11 @@ sparc_expand_move (machine_mode mode, rtx *operands)
operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX);
/* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */
- if ((GET_CODE (operands[1]) == LABEL_REF
+ if ((LABEL_REF_P (operands[1])
&& can_use_mov_pic_label_ref (operands[1]))
|| (GET_CODE (operands[1]) == CONST
&& GET_CODE (XEXP (operands[1], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (operands[1], 0), 0))
&& CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
&& can_use_mov_pic_label_ref (XEXP (XEXP (operands[1], 0), 0))))
{
@@ -4848,7 +4848,7 @@ sparc_legitimize_pic_address (rtx orig, rtx reg)
{
if (GET_CODE (orig) == SYMBOL_REF
/* See the comment in sparc_expand_move. */
- || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig)))
+ || (LABEL_REF_P (orig) && !can_use_mov_pic_label_ref (orig)))
{
bool gotdata_op = false;
rtx pic_ref, address;
@@ -4945,7 +4945,7 @@ sparc_legitimize_pic_address (rtx orig, rtx reg)
}
return gen_rtx_PLUS (Pmode, base, offset);
}
- else if (GET_CODE (orig) == LABEL_REF)
+ else if (LABEL_REF_P (orig))
/* ??? We ought to be checking that the register is live instead, in case
it is eliminated. */
crtl->uses_pic_offset_table = 1;
@@ -4997,7 +4997,7 @@ sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
copy_to_mode_reg (Pmode, XEXP (x, 0)));
else if (GET_CODE (x) == SYMBOL_REF
|| GET_CODE (x) == CONST
- || GET_CODE (x) == LABEL_REF)
+ || LABEL_REF_P (x))
x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
return x;
@@ -5042,10 +5042,10 @@ sparc_delegitimize_address (rtx x)
if (GET_CODE (y) == UNSPEC && XINT (y, 1) == UNSPEC_MOVE_PIC_LABEL)
{
x = XVECEXP (y, 0, 0);
- gcc_assert (GET_CODE (x) == LABEL_REF
+ gcc_assert (LABEL_REF_P (x)
|| (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))));
}
}
@@ -9687,14 +9687,14 @@ sparc_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
else if (REG_P (index))
fprintf (file, "+%s", reg_names[REGNO (index)]);
else if (GET_CODE (index) == SYMBOL_REF
- || GET_CODE (index) == LABEL_REF
+ || LABEL_REF_P (index)
|| GET_CODE (index) == CONST)
fputc ('+', file), output_addr_const (file, index);
else gcc_unreachable ();
}
}
else if (GET_CODE (addr) == MINUS
- && GET_CODE (XEXP (addr, 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (addr, 1)))
{
output_addr_const (file, XEXP (addr, 0));
fputs ("-(", file);
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 0c003a2fdf2..b7987b17923 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -6867,7 +6867,7 @@ visl")
gcc_assert (CONST_INT_P (operands[3]));
- if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
+ if (LABEL_REF_P (XEXP (operands[0], 0)))
{
/* This is really a PIC sequence. We want to represent
it as a funny jump so its delay slots can be filled.
diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index 0206d15d9a8..ad028ef3686 100644
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -156,7 +156,7 @@
(and (match_code "mem")
(match_test "!TARGET_LARGE_MEM
&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == LABEL_REF))")))
+ || LABEL_REF_P (XEXP (op, 0))))")))
(define_memory_constraint "T"
"Call operand, const_int, for absolute calls."
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 4527842e8b6..4888e90536b 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -2119,7 +2119,7 @@ spu_emit_branch_hint (rtx_insn *before, rtx_insn *branch, rtx target,
INSN_LOCATION (hint) = INSN_LOCATION (branch);
HINTED_P (branch) = 1;
- if (GET_CODE (target) == LABEL_REF)
+ if (LABEL_REF_P (target))
HINTED_P (XEXP (target, 0)) = 1;
else if (tablejump_p (branch, 0, &table))
{
@@ -3071,7 +3071,7 @@ spu_float_const (const char *string, machine_mode mode)
int
spu_constant_address_p (rtx x)
{
- return (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
+ return (LABEL_REF_P (x) || GET_CODE (x) == SYMBOL_REF
|| CONST_INT_P (x) || GET_CODE (x) == CONST
|| GET_CODE (x) == HIGH);
}
@@ -3492,7 +3492,7 @@ spu_legitimate_constant_p (machine_mode mode, rtx x)
if (!flag_pic
&& mode == V4SImode
&& (GET_CODE (CONST_VECTOR_ELT (x, 0)) == SYMBOL_REF
- || GET_CODE (CONST_VECTOR_ELT (x, 0)) == LABEL_REF
+ || LABEL_REF_P (CONST_VECTOR_ELT (x, 0))
|| GET_CODE (CONST_VECTOR_ELT (x, 0)) == CONST))
return const_vec_duplicate_p (x);
@@ -5220,7 +5220,7 @@ spu_assemble_integer (rtx x, unsigned int size, int aligned_p)
in case users support it in their own run-time loader. And we provide
a warning for those users that don't. */
if ((GET_CODE (x) == SYMBOL_REF)
- || GET_CODE (x) == LABEL_REF || GET_CODE (x) == CONST)
+ || LABEL_REF_P (x) || GET_CODE (x) == CONST)
reloc_diagnostic (x);
return default_assemble_integer (x, size, aligned_p);
@@ -6387,7 +6387,7 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
lsbits = 0;
}
- if (GET_CODE (op) == LABEL_REF
+ if (LABEL_REF_P (op)
|| (GET_CODE (op) == SYMBOL_REF
&& SYMBOL_REF_FUNCTION_P (op))
|| (v & ((1 << lsbits) - 1)) != 0)
diff --git a/gcc/config/tilegx/predicates.md b/gcc/config/tilegx/predicates.md
index 354d8109bed..412a7ed24f4 100644
--- a/gcc/config/tilegx/predicates.md
+++ b/gcc/config/tilegx/predicates.md
@@ -260,7 +260,7 @@
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (op,0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (op,0), 0)))
&& CONST_INT_P (XEXP (XEXP (op,0), 1))"))))
;; Return 1 for an unsigned 16 bit or a const symbolc operand.
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index 26ab4889147..b96994c5997 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -827,7 +827,7 @@ tilegx_pic_address_needs_scratch (rtx x)
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return true;
@@ -1327,7 +1327,7 @@ tilegx_legitimize_pic_address (rtx orig,
else
gcc_unreachable ();
}
- else if (GET_CODE (orig) == LABEL_REF)
+ else if (LABEL_REF_P (orig))
{
rtx address;
rtx temp_reg;
diff --git a/gcc/config/tilepro/predicates.md b/gcc/config/tilepro/predicates.md
index b711773f0c3..4f8ec509bf3 100644
--- a/gcc/config/tilepro/predicates.md
+++ b/gcc/config/tilepro/predicates.md
@@ -219,7 +219,7 @@
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (op,0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (op,0), 0)))
&& CONST_INT_P (XEXP (XEXP (op,0), 1))"))))
;; Returns 1 if OP is a symbolic operand, or a const unspec wrapper
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 2cf16edd86d..31b6d5af513 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -727,7 +727,7 @@ tilepro_pic_address_needs_scratch (rtx x)
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
+ || LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))
return true;
@@ -1084,7 +1084,7 @@ tilepro_legitimize_pic_address (rtx orig,
else
gcc_unreachable ();
}
- else if (GET_CODE (orig) == LABEL_REF)
+ else if (LABEL_REF_P (orig))
{
rtx address, temp_reg;
rtx text_label_symbol;
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 001b1baa8ec..9ccc41d7f86 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -797,7 +797,7 @@ v850_output_addr_const_extra (FILE * file, rtx x)
nothing, since the table will not be used.
(cf gcc.c-torture/compile/990801-1.c). */
if (GET_CODE (x) == MINUS
- && GET_CODE (XEXP (x, 0)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (x, 0)))
{
rtx_code_label *label
= dyn_cast<rtx_code_label *> (XEXP (XEXP (x, 0), 0));
@@ -872,7 +872,7 @@ output_move_single (rtx * operands)
else if (special_symbolref_operand (src, VOIDmode))
return "movea %O1(%P1),%Q1,%0";
- else if (GET_CODE (src) == LABEL_REF
+ else if (LABEL_REF_P (src)
|| GET_CODE (src) == SYMBOL_REF
|| GET_CODE (src) == CONST)
{
diff --git a/gcc/config/vax/predicates.md b/gcc/config/vax/predicates.md
index c6d66f771ef..99c21d57d06 100644
--- a/gcc/config/vax/predicates.md
+++ b/gcc/config/vax/predicates.md
@@ -26,11 +26,11 @@
(define_predicate "local_symbolic_operand"
(match_code "const,symbol_ref,label_ref")
{
- if (GET_CODE (op) == LABEL_REF)
+ if (LABEL_REF_P (op))
return 1;
if (GET_CODE (op) == SYMBOL_REF)
return !flag_pic || SYMBOL_REF_LOCAL_P (op);
- if (GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
+ if (LABEL_REF_P (XEXP (XEXP (op, 0), 0)))
return 1;
return !flag_pic || SYMBOL_REF_LOCAL_P (XEXP (XEXP (op, 0), 0));
})
diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c
index 3cee73c2e23..2094e852527 100644
--- a/gcc/config/vax/vax.c
+++ b/gcc/config/vax/vax.c
@@ -1637,7 +1637,7 @@ vax_output_int_subtract (rtx_insn *insn, rtx *operands, machine_mode mode)
bool
legitimate_constant_address_p (rtx x)
{
- if (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
+ if (LABEL_REF_P (x) || GET_CODE (x) == SYMBOL_REF
|| CONST_INT_P (x) || GET_CODE (x) == HIGH)
return true;
if (GET_CODE (x) != CONST)
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 85b4777a91d..30b27cb629f 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -2470,7 +2470,7 @@ print_operand (FILE *file, rtx x, int letter)
suitable for 'const16' that sets the high or low 16 bits. */
if (GET_CODE (XEXP (x, 0)) != PLUS
|| (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
+ && !LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
|| !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
output_operand_lossage ("invalid %%t/%%b value");
print_operand (file, XEXP (XEXP (x, 0), 0), 0);
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index a9e6e7ded5d..ccb64520c49 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -624,7 +624,7 @@ typedef struct xtensa_args
valid address. This is defined to be the same as 'CONSTANT_P (X)',
but rejecting CONST_DOUBLE. */
#define CONSTANT_ADDRESS_P(X) \
- ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
+ ((LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
|| CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
@@ -634,7 +634,7 @@ typedef struct xtensa_args
#define LEGITIMATE_PIC_OPERAND_P(X) \
((GET_CODE (X) != SYMBOL_REF \
|| (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
- && GET_CODE (X) != LABEL_REF \
+ && !LABEL_REF_P (X) \
&& GET_CODE (X) != CONST)
/* Specify the machine mode that this machine uses
diff --git a/gcc/cprop.c b/gcc/cprop.c
index 65c0130cc07..ecb383487bc 100644
--- a/gcc/cprop.c
+++ b/gcc/cprop.c
@@ -1621,7 +1621,7 @@ bypass_block (basic_block bb, rtx_insn *setcc, rtx_insn *jump)
edest = FALLTHRU_EDGE (bb);
dest = edest->insns.r ? NULL : edest->dest;
}
- else if (GET_CODE (new_rtx) == LABEL_REF)
+ else if (LABEL_REF_P (new_rtx))
{
dest = BLOCK_FOR_INSN (XEXP (new_rtx, 0));
/* Don't bypass edges containing instructions. */
diff --git a/gcc/cse.c b/gcc/cse.c
index afc6f50edbe..5662dc0eeae 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -3537,13 +3537,13 @@ fold_rtx (rtx x, rtx_insn *insn)
with that LABEL_REF as its second operand. If so, the result is
the first operand of that MINUS. This handles switches with an
ADDR_DIFF_VEC table. */
- if (const_arg1 && GET_CODE (const_arg1) == LABEL_REF)
+ if (const_arg1 && LABEL_REF_P (const_arg1))
{
rtx y
= GET_CODE (folded_arg0) == MINUS ? folded_arg0
: lookup_as_function (folded_arg0, MINUS);
- if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF
+ if (y != 0 && LABEL_REF_P (XEXP (y, 1))
&& label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg1))
return XEXP (y, 0);
@@ -3551,19 +3551,19 @@ fold_rtx (rtx x, rtx_insn *insn)
if ((y = (GET_CODE (folded_arg0) == CONST ? folded_arg0
: lookup_as_function (folded_arg0, CONST))) != 0
&& GET_CODE (XEXP (y, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (y, 0), 1))
&& label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg1))
return XEXP (XEXP (y, 0), 0);
}
/* Likewise if the operands are in the other order. */
- if (const_arg0 && GET_CODE (const_arg0) == LABEL_REF)
+ if (const_arg0 && LABEL_REF_P (const_arg0))
{
rtx y
= GET_CODE (folded_arg1) == MINUS ? folded_arg1
: lookup_as_function (folded_arg1, MINUS);
- if (y != 0 && GET_CODE (XEXP (y, 1)) == LABEL_REF
+ if (y != 0 && LABEL_REF_P (XEXP (y, 1))
&& label_ref_label (XEXP (y, 1)) == label_ref_label (const_arg0))
return XEXP (y, 0);
@@ -3571,7 +3571,7 @@ fold_rtx (rtx x, rtx_insn *insn)
if ((y = (GET_CODE (folded_arg1) == CONST ? folded_arg1
: lookup_as_function (folded_arg1, CONST))) != 0
&& GET_CODE (XEXP (y, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (y, 0), 1)) == LABEL_REF
+ && LABEL_REF_P (XEXP (XEXP (y, 0), 1))
&& label_ref_label (XEXP (XEXP (y, 0), 1)) == label_ref_label (const_arg0))
return XEXP (XEXP (y, 0), 0);
}
@@ -4310,7 +4310,7 @@ find_sets_in_insn (rtx_insn *insn, struct set **psets)
and not be misled by unchanged instructions
that were unconditional jumps to begin with. */
if (SET_DEST (x) == pc_rtx
- && GET_CODE (SET_SRC (x)) == LABEL_REF)
+ && LABEL_REF_P (SET_SRC (x)))
;
/* Don't count call-insns, (set (reg 0) (call ...)), as a set.
The hard function value register is used only once, to copy to
@@ -4334,7 +4334,7 @@ find_sets_in_insn (rtx_insn *insn, struct set **psets)
/* As above, we ignore unconditional jumps and call-insns and
ignore the result of apply_change_group. */
if (SET_DEST (y) == pc_rtx
- && GET_CODE (SET_SRC (y)) == LABEL_REF)
+ && LABEL_REF_P (SET_SRC (y)))
;
else if (GET_CODE (SET_SRC (y)) == CALL)
;
@@ -4842,8 +4842,8 @@ cse_insn (rtx_insn *insn)
"constant" here so we will record it. This allows us
to fold switch statements when an ADDR_DIFF_VEC is used. */
|| (GET_CODE (src_folded) == MINUS
- && GET_CODE (XEXP (src_folded, 0)) == LABEL_REF
- && GET_CODE (XEXP (src_folded, 1)) == LABEL_REF)))
+ && LABEL_REF_P (XEXP (src_folded, 0))
+ && LABEL_REF_P (XEXP (src_folded, 1)))))
src_const = src_folded, src_const_elt = elt;
else if (src_const == 0 && src_eqv_here && CONSTANT_P (src_eqv_here))
src_const = src_eqv_here, src_const_elt = src_eqv_elt;
@@ -5155,7 +5155,7 @@ cse_insn (rtx_insn *insn)
/* If this was an indirect jump insn, a known label will really be
cheaper even though it looks more expensive. */
- if (dest == pc_rtx && src_const && GET_CODE (src_const) == LABEL_REF)
+ if (dest == pc_rtx && src_const && LABEL_REF_P (src_const))
src_folded = src_const, src_folded_cost = src_folded_regcost = -1;
/* Terminate loop when replacement made. This must terminate since
@@ -5341,11 +5341,11 @@ cse_insn (rtx_insn *insn)
barriers). */
if (n_sets == 1 && dest == pc_rtx
&& (trial == pc_rtx
- || (GET_CODE (trial) == LABEL_REF
+ || (LABEL_REF_P (trial)
&& ! condjump_p (insn))))
{
/* Don't substitute non-local labels, this confuses CFG. */
- if (GET_CODE (trial) == LABEL_REF
+ if (LABEL_REF_P (trial)
&& LABEL_REF_NONLOCAL_P (trial))
continue;
@@ -5380,8 +5380,8 @@ cse_insn (rtx_insn *insn)
/* Likewise on IA-64, except without the
truncate. */
|| (GET_CODE (XEXP (trial, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (trial, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (trial, 0), 1)) == LABEL_REF)))
+ && LABEL_REF_P (XEXP (XEXP (trial, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (trial, 0), 1)))))
/* Do nothing for this case. */
;
@@ -5505,8 +5505,8 @@ cse_insn (rtx_insn *insn)
&& REG_P (SUBREG_REG (src_const)))
&& !(GET_CODE (src_const) == CONST
&& GET_CODE (XEXP (src_const, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (src_const, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (src_const, 0), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (XEXP (src_const, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (src_const, 0), 1)))
&& !rtx_equal_p (src, src_const))
{
/* Make sure that the rtx is not shared. */
@@ -5599,7 +5599,7 @@ cse_insn (rtx_insn *insn)
/* If this SET is now setting PC to a label, we know it used to
be a conditional or computed branch. */
- else if (dest == pc_rtx && GET_CODE (src) == LABEL_REF
+ else if (dest == pc_rtx && LABEL_REF_P (src)
&& !LABEL_REF_NONLOCAL_P (src))
{
/* We reemit the jump in as many cases as possible just in
@@ -6582,7 +6582,7 @@ check_for_label_ref (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == LABEL_REF
+ if (LABEL_REF_P (x)
&& !LABEL_REF_NONLOCAL_P (x)
&& (!JUMP_P (insn)
|| !label_is_jump_target_p (label_ref_label (x), insn))
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 24672f62635..a3cdd4ace85 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -3072,7 +3072,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
else
marked = true;
}
- else if (GET_CODE (tmp) == LABEL_REF)
+ else if (LABEL_REF_P (tmp))
{
addr = tmp;
marked = true;
diff --git a/gcc/explow.c b/gcc/explow.c
index 3253898b66e..bc813d07f2e 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -197,7 +197,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
if (maybe_ne (c, 0))
x = gen_rtx_PLUS (mode, x, gen_int_mode (c, mode));
- if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
+ if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
return x;
else if (all_constant)
return gen_rtx_CONST (mode, x);
@@ -686,7 +686,7 @@ force_reg (machine_mode mode, rtx x)
if (SYMBOL_REF_DECL (x) && DECL_P (SYMBOL_REF_DECL (x)))
align = DECL_ALIGN (SYMBOL_REF_DECL (x));
}
- else if (GET_CODE (x) == LABEL_REF)
+ else if (LABEL_REF_P (x))
align = BITS_PER_UNIT;
else if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
diff --git a/gcc/expr.c b/gcc/expr.c
index cb933203a2c..bffd3ca50df 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -7449,7 +7449,7 @@ force_operand (rtx value, rtx target)
if ((code == PLUS || code == MINUS)
&& XEXP (value, 0) == pic_offset_table_rtx
&& (GET_CODE (XEXP (value, 1)) == SYMBOL_REF
- || GET_CODE (XEXP (value, 1)) == LABEL_REF
+ || LABEL_REF_P (XEXP (value, 1))
|| GET_CODE (XEXP (value, 1)) == CONST))
{
if (!subtarget)
diff --git a/gcc/final.c b/gcc/final.c
index 7e5a574a5bb..a93acb29539 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -4003,7 +4003,7 @@ output_asm_label (rtx x)
{
char buf[256];
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
x = label_ref_label (x);
if (LABEL_P (x)
|| (NOTE_P (x)
diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c
index 6b24323f112..68aa1723073 100644
--- a/gcc/genattrtab.c
+++ b/gcc/genattrtab.c
@@ -3715,7 +3715,7 @@ write_test_expr (FILE *outf, rtx exp, unsigned int attrs_cached, int flags,
/* The address of the branch target. */
case MATCH_DUP:
fprintf (outf,
- "INSN_ADDRESSES_SET_P () ? INSN_ADDRESSES (INSN_UID (GET_CODE (operands[%d]) == LABEL_REF ? XEXP (operands[%d], 0) : operands[%d])) : 0",
+ "INSN_ADDRESSES_SET_P () ? INSN_ADDRESSES (INSN_UID (LABEL_REF_P (operands[%d]) ? XEXP (operands[%d], 0) : operands[%d])) : 0",
XINT (exp, 0), XINT (exp, 0), XINT (exp, 0));
break;
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index c26057079fd..8bdd0ae7502 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -3156,7 +3156,7 @@ needs_barrier_p (rtx x)
{
return (GET_CODE (x) == SET
&& GET_CODE (SET_DEST (x)) == PC
- && GET_CODE (SET_SRC (x)) == LABEL_REF);
+ && LABEL_REF_P (SET_SRC (x)));
}
#define NS "NULL"
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index 8ccf523c859..7a371a43bd9 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -438,7 +438,7 @@ cond_exec_get_condition (rtx_insn *jump)
/* If this branches to JUMP_LABEL when the condition is false,
reverse the condition. */
- if (GET_CODE (XEXP (test_if, 2)) == LABEL_REF
+ if (LABEL_REF_P (XEXP (test_if, 2))
&& label_ref_label (XEXP (test_if, 2)) == JUMP_LABEL (jump))
{
enum rtx_code rev = reversed_comparison_code (cond, jump);
@@ -832,7 +832,7 @@ noce_emit_store_flag (struct noce_if_info *if_info, rtx x, int reversep,
{
rtx set = pc_set (if_info->jump);
cond = XEXP (SET_SRC (set), 0);
- if (GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ if (LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (if_info->jump))
reversep = !reversep;
if (if_info->then_else_reversed)
@@ -2316,7 +2316,7 @@ noce_get_alt_condition (struct noce_if_info *if_info, rtx target,
set = pc_set (if_info->jump);
cond = XEXP (SET_SRC (set), 0);
reverse
- = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ = LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (if_info->jump);
if (if_info->then_else_reversed)
reverse = !reverse;
@@ -2928,7 +2928,7 @@ noce_get_condition (rtx_insn *jump, rtx_insn **earliest, bool then_else_reversed
/* If this branches to JUMP_LABEL when the condition is false,
reverse the condition. */
- reverse = (GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ reverse = (LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump));
/* We may have to reverse because the caller's if block is not canonical,
diff --git a/gcc/ira.c b/gcc/ira.c
index 84bff57fc95..9f7a72e3fe5 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -3933,12 +3933,12 @@ indirect_jump_optimize (void)
rtx_insn *def_insn = DF_REF_INSN (def);
rtx lab = NULL_RTX;
rtx set = single_set (def_insn);
- if (set && GET_CODE (SET_SRC (set)) == LABEL_REF)
+ if (set && LABEL_REF_P (SET_SRC (set)))
lab = SET_SRC (set);
else
{
rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX);
- if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF)
+ if (eqnote && LABEL_REF_P (XEXP (eqnote, 0)))
lab = XEXP (eqnote, 0);
}
if (lab && validate_replace_rtx (SET_SRC (x), lab, insn))
diff --git a/gcc/jump.c b/gcc/jump.c
index d6f4741e9f0..2ec071a6235 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -263,7 +263,7 @@ maybe_propagate_label_ref (rtx_insn *jump_insn, rtx_insn *prev_nonjump_insn)
if (label_set != NULL
/* The source must be the direct LABEL_REF, not a
PLUS, UNSPEC, IF_THEN_ELSE etc. */
- && GET_CODE (SET_SRC (label_set)) == LABEL_REF
+ && LABEL_REF_P (SET_SRC (label_set))
&& (rtx_equal_p (label_dest, pc_src)
|| (GET_CODE (pc_src) == IF_THEN_ELSE
&& (rtx_equal_p (label_dest, XEXP (pc_src, 1))
@@ -773,7 +773,7 @@ simplejump_p (const rtx_insn *insn)
return (JUMP_P (insn)
&& GET_CODE (PATTERN (insn)) == SET
&& GET_CODE (SET_DEST (PATTERN (insn))) == PC
- && GET_CODE (SET_SRC (PATTERN (insn))) == LABEL_REF);
+ && LABEL_REF_P (SET_SRC (PATTERN (insn))));
}
/* Return nonzero if INSN is a (possibly) conditional jump
@@ -792,15 +792,15 @@ condjump_p (const rtx_insn *insn)
return 0;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return 1;
else
return (GET_CODE (x) == IF_THEN_ELSE
&& ((GET_CODE (XEXP (x, 2)) == PC
- && (GET_CODE (XEXP (x, 1)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (x, 1))
|| ANY_RETURN_P (XEXP (x, 1))))
|| (GET_CODE (XEXP (x, 1)) == PC
- && (GET_CODE (XEXP (x, 2)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (x, 2))
|| ANY_RETURN_P (XEXP (x, 2))))));
}
@@ -824,16 +824,16 @@ condjump_in_parallel_p (const rtx_insn *insn)
return 0;
if (GET_CODE (SET_DEST (x)) != PC)
return 0;
- if (GET_CODE (SET_SRC (x)) == LABEL_REF)
+ if (LABEL_REF_P (SET_SRC (x)))
return 1;
if (GET_CODE (SET_SRC (x)) != IF_THEN_ELSE)
return 0;
if (XEXP (SET_SRC (x), 2) == pc_rtx
- && (GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (SET_SRC (x), 1))
|| ANY_RETURN_P (XEXP (SET_SRC (x), 1))))
return 1;
if (XEXP (SET_SRC (x), 1) == pc_rtx
- && (GET_CODE (XEXP (SET_SRC (x), 2)) == LABEL_REF
+ && (LABEL_REF_P (XEXP (SET_SRC (x), 2))
|| ANY_RETURN_P (XEXP (SET_SRC (x), 2))))
return 1;
return 0;
@@ -868,7 +868,7 @@ any_uncondjump_p (const rtx_insn *insn)
const_rtx x = pc_set (insn);
if (!x)
return 0;
- if (GET_CODE (SET_SRC (x)) != LABEL_REF)
+ if (!LABEL_REF_P (SET_SRC (x)))
return 0;
if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX))
return 0;
@@ -911,13 +911,13 @@ condjump_label (const rtx_insn *insn)
if (!x)
return NULL_RTX;
x = SET_SRC (x);
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
return x;
if (GET_CODE (x) != IF_THEN_ELSE)
return NULL_RTX;
- if (XEXP (x, 2) == pc_rtx && GET_CODE (XEXP (x, 1)) == LABEL_REF)
+ if (XEXP (x, 2) == pc_rtx && LABEL_REF_P (XEXP (x, 1)))
return XEXP (x, 1);
- if (XEXP (x, 1) == pc_rtx && GET_CODE (XEXP (x, 2)) == LABEL_REF)
+ if (XEXP (x, 1) == pc_rtx && LABEL_REF_P (XEXP (x, 2)))
return XEXP (x, 2);
return NULL_RTX;
}
@@ -1438,7 +1438,7 @@ redirect_exp_1 (rtx *loc, rtx olabel, rtx nlabel, rtx_insn *insn)
|| x == olabel)
{
x = redirect_target (nlabel);
- if (GET_CODE (x) == LABEL_REF && loc == &PATTERN (insn))
+ if (LABEL_REF_P (x) && loc == &PATTERN (insn))
x = gen_rtx_SET (pc_rtx, x);
validate_change (insn, loc, x, 1);
return;
@@ -1446,7 +1446,7 @@ redirect_exp_1 (rtx *loc, rtx olabel, rtx nlabel, rtx_insn *insn)
if (code == SET && SET_DEST (x) == pc_rtx
&& ANY_RETURN_P (nlabel)
- && GET_CODE (SET_SRC (x)) == LABEL_REF
+ && LABEL_REF_P (SET_SRC (x))
&& label_ref_label (SET_SRC (x)) == olabel)
{
validate_change (insn, loc, nlabel, 1);
diff --git a/gcc/loop-doloop.c b/gcc/loop-doloop.c
index 0efe7b449ff..e30d17be3ef 100644
--- a/gcc/loop-doloop.c
+++ b/gcc/loop-doloop.c
@@ -190,7 +190,7 @@ doloop_condition_get (rtx_insn *doloop_pat)
if (GET_CODE (cmp) != SET
|| SET_DEST (cmp) != pc_rtx
|| GET_CODE (SET_SRC (cmp)) != IF_THEN_ELSE
- || GET_CODE (XEXP (SET_SRC (cmp), 1)) != LABEL_REF
+ || !LABEL_REF_P (XEXP (SET_SRC (cmp), 1))
|| XEXP (SET_SRC (cmp), 2) != pc_rtx)
return 0;
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index ea09cd39cc1..dcc6044e7a2 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -306,7 +306,7 @@ simple_move_operand (rtx x)
if (!OBJECT_P (x))
return false;
- if (GET_CODE (x) == LABEL_REF
+ if (LABEL_REF_P (x)
|| GET_CODE (x) == SYMBOL_REF
|| GET_CODE (x) == HIGH
|| GET_CODE (x) == CONST)
diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index 10948efddd9..849e22726d7 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -573,7 +573,7 @@ rtx_writer::print_rtx_operand_code_u (const_rtx in_rtx, int idx)
rtx sub = XEXP (in_rtx, idx);
enum rtx_code subc = GET_CODE (sub);
- if (GET_CODE (in_rtx) == LABEL_REF)
+ if (LABEL_REF_P (in_rtx))
{
if (subc == NOTE
&& NOTE_KIND (sub) == NOTE_INSN_DELETED_LABEL)
diff --git a/gcc/read-rtl-function.c b/gcc/read-rtl-function.c
index 25d9f674612..0a3f79c8c36 100644
--- a/gcc/read-rtl-function.c
+++ b/gcc/read-rtl-function.c
@@ -955,7 +955,7 @@ function_reader::read_rtx_operand_u (rtx x, int idx)
{
/* In compact mode, the PREV/NEXT insn uids are not dumped, so skip
the "uu" when reading. */
- if (is_compact () && GET_CODE (x) != LABEL_REF)
+ if (is_compact () && !LABEL_REF_P (x))
return;
struct md_name name;
diff --git a/gcc/recog.c b/gcc/recog.c
index 56bd5716a87..5b6e957b2b4 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -123,7 +123,7 @@ asm_labels_ok (rtx body)
return true;
for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++)
- if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF)
+ if (!LABEL_REF_P (ASM_OPERANDS_LABEL (asmop, i)))
return false;
return true;
diff --git a/gcc/reginfo.c b/gcc/reginfo.c
index 22129db915a..ce65873b0f6 100644
--- a/gcc/reginfo.c
+++ b/gcc/reginfo.c
@@ -1145,20 +1145,20 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
&& REG_POINTER (XEXP (SET_SRC (x), 0)))
|| GET_CODE (SET_SRC (x)) == CONST
|| GET_CODE (SET_SRC (x)) == SYMBOL_REF
- || GET_CODE (SET_SRC (x)) == LABEL_REF
+ || LABEL_REF_P (SET_SRC (x))
|| (GET_CODE (SET_SRC (x)) == HIGH
&& (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
|| GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
- || GET_CODE (XEXP (SET_SRC (x), 0)) == LABEL_REF))
+ || LABEL_REF_P (XEXP (SET_SRC (x), 0))))
|| ((GET_CODE (SET_SRC (x)) == PLUS
|| GET_CODE (SET_SRC (x)) == LO_SUM)
&& (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
|| GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
- || GET_CODE (XEXP (SET_SRC (x), 1)) == LABEL_REF))
+ || LABEL_REF_P (XEXP (SET_SRC (x), 1))))
|| ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
&& (GET_CODE (XEXP (note, 0)) == CONST
|| GET_CODE (XEXP (note, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (note, 0)) == LABEL_REF))))
+ || LABEL_REF_P (XEXP (note, 0))))))
REG_POINTER (SET_DEST (x)) = 1;
/* If this is setting a register from a register or from a simple
diff --git a/gcc/reload.c b/gcc/reload.c
index e1f8329297c..a9efe22d965 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -4200,7 +4200,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we're replacing an operand with a LABEL_REF, we need to
make sure that there's a REG_LABEL_OPERAND note attached to
this instruction. */
- if (GET_CODE (substitution) == LABEL_REF
+ if (LABEL_REF_P (substitution)
&& !find_reg_note (insn, REG_LABEL_OPERAND,
label_ref_label (substitution))
/* For a JUMP_P, if it was a branch target it must have
@@ -6266,7 +6266,7 @@ subst_reloads (rtx_insn *insn)
/* If we're replacing a LABEL_REF with a register, there must
already be an indication (to e.g. flow) which label this
register refers to. */
- gcc_assert (GET_CODE (*r->where) != LABEL_REF
+ gcc_assert (!LABEL_REF_P (*r->where)
|| !JUMP_P (insn)
|| find_reg_note (insn,
REG_LABEL_OPERAND,
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 5cc8bb5cada..1a68d0567fc 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2436,13 +2436,13 @@ set_label_offsets (rtx x, rtx_insn *insn, int initial_p)
case IF_THEN_ELSE:
tem = XEXP (SET_SRC (x), 1);
- if (GET_CODE (tem) == LABEL_REF)
+ if (LABEL_REF_P (tem))
set_label_offsets (label_ref_label (tem), insn, initial_p);
else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
break;
tem = XEXP (SET_SRC (x), 2);
- if (GET_CODE (tem) == LABEL_REF)
+ if (LABEL_REF_P (tem))
set_label_offsets (label_ref_label (tem), insn, initial_p);
else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
break;
diff --git a/gcc/reorg.c b/gcc/reorg.c
index bdfcf8851cd..79684952595 100644
--- a/gcc/reorg.c
+++ b/gcc/reorg.c
@@ -894,19 +894,19 @@ get_branch_condition (const rtx_insn *insn, rtx target)
return 0;
src = SET_SRC (pat);
- if (GET_CODE (src) == LABEL_REF && label_ref_label (src) == target)
+ if (LABEL_REF_P (src) && label_ref_label (src) == target)
return const_true_rtx;
else if (GET_CODE (src) == IF_THEN_ELSE
&& XEXP (src, 2) == pc_rtx
- && ((GET_CODE (XEXP (src, 1)) == LABEL_REF
+ && ((LABEL_REF_P (XEXP (src, 1))
&& label_ref_label (XEXP (src, 1)) == target)
|| (ANY_RETURN_P (XEXP (src, 1)) && XEXP (src, 1) == target)))
return XEXP (src, 0);
else if (GET_CODE (src) == IF_THEN_ELSE
&& XEXP (src, 1) == pc_rtx
- && ((GET_CODE (XEXP (src, 2)) == LABEL_REF
+ && ((LABEL_REF_P (XEXP (src, 2))
&& label_ref_label (XEXP (src, 2)) == target)
|| (ANY_RETURN_P (XEXP (src, 2)) && XEXP (src, 2) == target)))
{
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 69095f8e38a..cb6c8902353 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -1052,7 +1052,7 @@ reg_mentioned_p (const_rtx reg, const_rtx in)
if (reg == in)
return 1;
- if (GET_CODE (in) == LABEL_REF)
+ if (LABEL_REF_P (in))
return reg == label_ref_label (in);
code = GET_CODE (in);
@@ -3196,7 +3196,7 @@ replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
}
}
- if ((GET_CODE (x) == LABEL_REF
+ if ((LABEL_REF_P (x)
|| GET_CODE (x) == INSN_LIST)
&& XEXP (x, 0) == old_label)
{
@@ -3230,7 +3230,7 @@ rtx_referenced_p (const_rtx x, const_rtx body)
if (const_rtx y = *iter)
{
/* Check if a label_ref Y refers to label X. */
- if (GET_CODE (y) == LABEL_REF
+ if (LABEL_REF_P (y)
&& LABEL_P (x)
&& label_ref_label (y) == x)
return true;
@@ -5804,7 +5804,7 @@ get_condition (rtx_insn *jump, rtx_insn **earliest, int allow_cc_mode,
/* If this branches to JUMP_LABEL when the condition is false, reverse
the condition. */
reverse
- = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF
+ = LABEL_REF_P (XEXP (SET_SRC (set), 2))
&& label_ref_label (XEXP (SET_SRC (set), 2)) == JUMP_LABEL (jump);
return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX,
@@ -6567,7 +6567,7 @@ contains_symbolic_reference_p (const_rtx x)
{
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
- if (SYMBOL_REF_P (*iter) || GET_CODE (*iter) == LABEL_REF)
+ if (SYMBOL_REF_P (*iter) || LABEL_REF_P (*iter))
return true;
return false;
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index d1cb817df44..98f2fe112f1 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1423,8 +1423,8 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
if (GET_CODE (op) == TRUNCATE
&& GET_MODE (XEXP (op, 0)) == mode
&& GET_CODE (XEXP (op, 0)) == MINUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF)
+ && LABEL_REF_P (XEXP (XEXP (op, 0), 0))
+ && LABEL_REF_P (XEXP (XEXP (op, 0), 1)))
return XEXP (op, 0);
/* Extending a widening multiplication should be canonicalized to
@@ -2263,12 +2263,12 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
if ((GET_CODE (op0) == CONST
|| GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF)
+ || LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, offset);
else if ((GET_CODE (op1) == CONST
|| GET_CODE (op1) == SYMBOL_REF
- || GET_CODE (op1) == LABEL_REF)
+ || LABEL_REF_P (op1))
&& poly_int_rtx_p (op0, &offset))
return plus_constant (mode, op1, offset);
@@ -2542,7 +2542,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
if ((GET_CODE (op0) == CONST
|| GET_CODE (op0) == SYMBOL_REF
- || GET_CODE (op0) == LABEL_REF)
+ || LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, trunc_int_for_mode (-offset, mode));
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 1d85e03ee2e..49bd7661fe3 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -151,7 +151,7 @@ gen_addr_rtx (machine_mode address_mode,
*offset_p = &XEXP (act_elem, 1);
if (GET_CODE (symbol) == SYMBOL_REF
- || GET_CODE (symbol) == LABEL_REF
+ || LABEL_REF_P (symbol)
|| GET_CODE (symbol) == CONST)
act_elem = gen_rtx_CONST (address_mode, act_elem);
}
diff --git a/gcc/varasm.c b/gcc/varasm.c
index e6263f09226..5d69da0df96 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -3900,7 +3900,7 @@ force_const_mem (machine_mode in_mode, rtx x)
/* If we're dropping a label to the constant pool, make sure we
don't delete it. */
- if (GET_CODE (x) == LABEL_REF)
+ if (LABEL_REF_P (x))
LABEL_PRESERVE_P (XEXP (x, 0)) = 1;
return copy_rtx (def);
@@ -4049,7 +4049,7 @@ output_constant_pool_1 (class constant_descriptor_rtx *desc,
{
case CONST:
if (GET_CODE (XEXP (tmp, 0)) != PLUS
- || GET_CODE (XEXP (XEXP (tmp, 0), 0)) != LABEL_REF)
+ || !LABEL_REF_P (XEXP (XEXP (tmp, 0), 0)))
break;
tmp = XEXP (XEXP (tmp, 0), 0);
/* FALLTHRU */
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 07/18] Add CONST_VECTOR_P rtx_code predicate.
2019-08-06 3:11 ` Arvind Sankar
` (7 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 08/18] Use CONST_VECTOR_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_VECTOR Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 10/18] Use CONST_STRING_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_STRING Arvind Sankar
` (8 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* rtl.h: Add a predicate macro for checking CONST_VECTOR.
1 file changed, 3 insertions(+)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 28b5a82d651..45e2b85867d 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -818,6 +818,9 @@ struct GTY(()) rtvec_def {
#define CONST_DOUBLE_AS_FLOAT_P(X) \
(GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
+/* Predicate yielding nonzero iff X is an rtx for a vector const. */
+#define CONST_VECTOR_P(X) (GET_CODE (X) == CONST_VECTOR)
+
/* Predicate yielding true iff X is an rtx for a integer const. */
#if TARGET_SUPPORTS_WIDE_INT
#define CONST_SCALAR_INT_P(X) \
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 12/18] Use SUBREG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SUBREG
2019-08-06 3:11 ` Arvind Sankar
` (4 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 06/18] Use CONST_DOUBLE_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_DOUBLE Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 13/18] Use MEM_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh MEM Arvind Sankar
` (11 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* bt-load.c: Convert GET_CODE (..) == SUBREG to SUBREG_P (..).
* caller-save.c: Likewise.
* calls.c: Likewise.
* cfgexpand.c: Likewise.
* combine.c: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/arc/arc.c: Likewise.
* config/arm/aarch-common.c: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/predicates.md: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/predicates.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cris/cris.c: Likewise.
* config/cris/cris.h: Likewise.
* config/csky/csky.c: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.md: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/fr30/fr30.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/predicates.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/gcn/predicates.md: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m32r/m32r.md: Likewise.
* config/m32r/predicates.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/mips/mips.c: Likewise.
* config/mn10300/mn10300.c: Likewise.
* config/mn10300/mn10300.h: Likewise.
* config/msp430/msp430.c: Likewise.
* config/msp430/msp430.md: Likewise.
* config/nds32/nds32-pipelines-auxiliary.c: Likewise.
* config/nds32/nds32-utils.c: Likewise.
* config/nds32/nds32.md: Likewise.
* config/nds32/predicates.md: Likewise.
* config/nios2/nios2.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/predicates.md: Likewise.
* config/pru/predicates.md: Likewise.
* config/pru/pru.c: Likewise.
* config/riscv/riscv.c: Likewise.
* config/rl78/rl78-expand.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rl78/rl78.h: Likewise.
* config/rx/rx.h: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/sh/predicates.md: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/spu.c: Likewise.
* config/stormy16/predicates.md: Likewise.
* config/stormy16/stormy16.c: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilepro/tilepro.c: Likewise.
* config/v850/v850.c: Likewise.
* config/visium/predicates.md: Likewise.
* config/visium/visium.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.md: Likewise.
* cse.c: Likewise.
* cselib.c: Likewise.
* dbxout.c: Likewise.
* df-core.c: Likewise.
* df-problems.c: Likewise.
* df-scan.c: Likewise.
* df.h: Likewise.
* dojump.c: Likewise.
* dse.c: Likewise.
* dwarf2out.c: Likewise.
* emit-rtl.c: Likewise.
* expmed.c: Likewise.
* expr.c: Likewise.
* final.c: Likewise.
* function.c: Likewise.
* fwprop.c: Likewise.
* gcse-common.c: Likewise.
* gcse.c: Likewise.
* genpreds.c: Likewise.
* ifcvt.c: Likewise.
* internal-fn.c: Likewise.
* ira-build.c: Likewise.
* ira-conflicts.c: Likewise.
* ira-costs.c: Likewise.
* ira-emit.c: Likewise.
* ira-lives.c: Likewise.
* ira.c: Likewise.
* jump.c: Likewise.
* loop-invariant.c: Likewise.
* loop-iv.c: Likewise.
* loop-unroll.c: Likewise.
* lower-subreg.c: Likewise.
* lra-constraints.c: Likewise.
* lra-eliminations.c: Likewise.
* lra.c: Likewise.
* mode-switching.c: Likewise.
* modulo-sched.c: Likewise.
* optabs.c: Likewise.
* postreload-gcse.c: Likewise.
* postreload.c: Likewise.
* read-rtl.c: Likewise.
* recog.c: Likewise.
* ree.c: Likewise.
* reg-stack.c: Likewise.
* regcprop.c: Likewise.
* reginfo.c: Likewise.
* regrename.c: Likewise.
* reload.c: Likewise.
* reload1.c: Likewise.
* resource.c: Likewise.
* rtlanal.c: Likewise.
* rtlhooks.c: Likewise.
* sched-deps.c: Likewise.
* sched-rgn.c: Likewise.
* sel-sched.c: Likewise.
* simplify-rtx.c: Likewise.
* valtrack.c: Likewise.
* var-tracking.c: Likewise.
142 files changed, 735 insertions(+), 735 deletions(-)
diff --git a/gcc/bt-load.c b/gcc/bt-load.c
index f68879ca49a..11eee41e9d5 100644
--- a/gcc/bt-load.c
+++ b/gcc/bt-load.c
@@ -226,7 +226,7 @@ insn_sets_btr_p (const rtx_insn *insn, int check_const, int *regno)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = XEXP (dest, 0);
if (REG_P (dest)
diff --git a/gcc/caller-save.c b/gcc/caller-save.c
index 7c1de894976..e816d080b82 100644
--- a/gcc/caller-save.c
+++ b/gcc/caller-save.c
@@ -955,7 +955,7 @@ mark_set_regs (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *data)
int regno, endregno, i;
HARD_REG_SET *this_insn_sets = (HARD_REG_SET *) data;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
rtx inner = SUBREG_REG (reg);
if (!REG_P (inner) || REGNO (inner) >= FIRST_PSEUDO_REGISTER)
@@ -990,7 +990,7 @@ add_stored_regs (rtx reg, const_rtx setter, void *data)
if (GET_CODE (setter) == CLOBBER)
return;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& REG_P (SUBREG_REG (reg))
&& REGNO (SUBREG_REG (reg)) < FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/calls.c b/gcc/calls.c
index 7507b698e27..453308f1ca1 100644
--- a/gcc/calls.c
+++ b/gcc/calls.c
@@ -1004,7 +1004,7 @@ precompute_register_parameters (int num_actuals, struct arg_data *args,
loading the parameters registers. */
else if ((! (REG_P (args[i].value)
- || (GET_CODE (args[i].value) == SUBREG
+ || (SUBREG_P (args[i].value)
&& REG_P (SUBREG_REG (args[i].value)))))
&& args[i].mode != BLKmode
&& (set_src_cost (args[i].value, args[i].mode,
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index b141a57d3af..aff97bb41be 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -3786,7 +3786,7 @@ expand_gimple_stmt_1 (gimple *stmt)
bool promoted = false;
target = expand_expr (lhs, NULL_RTX, VOIDmode, EXPAND_WRITE);
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
promoted = true;
ops.code = gimple_assign_rhs_code (assign_stmt);
diff --git a/gcc/combine.c b/gcc/combine.c
index 1c59ab54a40..b175ed9c4a0 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -582,7 +582,7 @@ find_single_use_1 (rtx dest, rtx *loc)
if (GET_CODE (SET_DEST (x)) != CC0
&& GET_CODE (SET_DEST (x)) != PC
&& !REG_P (SET_DEST (x))
- && ! (GET_CODE (SET_DEST (x)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& !read_modify_subreg_p (SET_DEST (x))))
break;
@@ -738,7 +738,7 @@ do_SUBST (rtx *into, rtx newval)
when do_SUBST is called to replace the operand thereof, so we
perform this test on oldval instead, checking whether an
invalid replacement took place before we got here. */
- gcc_assert (!(GET_CODE (oldval) == SUBREG
+ gcc_assert (!(SUBREG_P (oldval)
&& CONST_INT_P (SUBREG_REG (oldval))));
gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
&& CONST_INT_P (XEXP (oldval, 0))));
@@ -2222,7 +2222,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
rtx subdest;
while (GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT)
inner_dest = XEXP (inner_dest, 0);
@@ -2265,7 +2265,7 @@ combinable_i3pat (rtx_insn *i3, rtx *loc, rtx i2dest, rtx i1dest, rtx i0dest,
STACK_POINTER_REGNUM, since these are always considered to be
live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
subdest = dest;
- if (GET_CODE (subdest) == SUBREG && !partial_subreg_p (subdest))
+ if (SUBREG_P (subdest) && !partial_subreg_p (subdest))
subdest = SUBREG_REG (subdest);
if (pi3dest_killed
&& REG_P (subdest)
@@ -2352,9 +2352,9 @@ cant_combine_insn_p (rtx_insn *insn)
return 0;
src = SET_SRC (set);
dest = SET_DEST (set);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
src = SUBREG_REG (src);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (src) && REG_P (dest)
&& ((HARD_REGISTER_P (src)
@@ -2476,7 +2476,7 @@ adjust_for_new_dest (rtx_insn *insn)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
gcc_assert (REG_P (reg));
@@ -2530,7 +2530,7 @@ reg_subword_p (rtx x, rtx reg)
|| GET_CODE (x) == ZERO_EXTRACT)
x = XEXP (x, 0);
- return GET_CODE (x) == SUBREG
+ return SUBREG_P (x)
&& SUBREG_REG (x) == reg
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_INT;
}
@@ -3625,7 +3625,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (((REG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
- || (GET_CODE (SET_DEST (set1)) == SUBREG
+ || (SUBREG_P (SET_DEST (set1))
&& find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set1)))
@@ -3636,14 +3636,14 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (((REG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
- || (GET_CODE (SET_DEST (set0)) == SUBREG
+ || (SUBREG_P (SET_DEST (set0))
&& find_reg_note (i3, REG_UNUSED,
SUBREG_REG (SET_DEST (set0)))))
&& insn_nothrow_p (i3)
&& !side_effects_p (SET_SRC (set0)))
{
rtx dest = SET_DEST (set1);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!reg_used_between_p (dest, i2, i3))
{
@@ -3800,12 +3800,12 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
|| GET_CODE (new_i3_dest) == STRICT_LOW_PART
- || GET_CODE (new_i3_dest) == SUBREG)
+ || SUBREG_P (new_i3_dest))
new_i3_dest = XEXP (new_i3_dest, 0);
while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
|| GET_CODE (new_i2_dest) == STRICT_LOW_PART
- || GET_CODE (new_i2_dest) == SUBREG)
+ || SUBREG_P (new_i2_dest))
new_i2_dest = XEXP (new_i2_dest, 0);
if (REG_P (new_i3_dest)
@@ -4037,7 +4037,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
HOST_BITS_PER_INT)
&& (reg_stat[REGNO (temp_expr)].nonzero_bits
!= GET_MODE_MASK (word_mode))))
- && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
+ && ! (SUBREG_P (SET_DEST (XVECEXP (newpat, 0, 1)))
&& (temp_expr = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
(REG_P (temp_expr)
&& reg_stat[REGNO (temp_expr)].nonzero_bits != 0
@@ -4112,7 +4112,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
if (!modified_between_p (SET_SRC (set1), i2, i3)
&& !(REG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set1)))
- && !(GET_CODE (SET_DEST (set1)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set1))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set1))))
&& !modified_between_p (SET_DEST (set1), i2, i3)
@@ -4128,7 +4128,7 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0,
else if (!modified_between_p (SET_SRC (set0), i2, i3)
&& !(REG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD, SET_DEST (set0)))
- && !(GET_CODE (SET_DEST (set0)) == SUBREG
+ && !(SUBREG_P (SET_DEST (set0))
&& find_reg_note (i2, REG_DEAD,
SUBREG_REG (SET_DEST (set0))))
&& !modified_between_p (SET_DEST (set0), i2, i3)
@@ -5045,7 +5045,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 0)))))
{
@@ -5062,7 +5062,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS
&& OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 0))
&& !OBJECT_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
- && ! (GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (XEXP (x, 0), 0), 1))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (XEXP (x, 0),
0), 1)))))
{
@@ -5082,7 +5082,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
This will occur on machines that just support REG + CONST
and have a constant moved through some previous computation. */
if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
}
@@ -5093,7 +5093,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& ! memory_address_addr_space_p (GET_MODE (x), XEXP (x, 0),
MEM_ADDR_SPACE (x))
&& ! OBJECT_P (XEXP (XEXP (x, 0), 0))
- && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (XEXP (x, 0), 0))
&& OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
return &XEXP (XEXP (x, 0), 0);
break;
@@ -5108,7 +5108,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
&& GET_CODE (SET_SRC (x)) != COMPARE
&& GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
&& !OBJECT_P (SET_SRC (x))
- && ! (GET_CODE (SET_SRC (x)) == SUBREG
+ && ! (SUBREG_P (SET_SRC (x))
&& OBJECT_P (SUBREG_REG (SET_SRC (x)))))
return &SET_SRC (x);
@@ -5313,7 +5313,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (BINARY_P (SET_SRC (x))
&& CONSTANT_P (XEXP (SET_SRC (x), 1))
&& (OBJECT_P (XEXP (SET_SRC (x), 0))
- || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
+ || (SUBREG_P (XEXP (SET_SRC (x), 0))
&& OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
return &XEXP (SET_SRC (x), 1);
@@ -5626,7 +5626,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
tieable and it is valid if X is a SET that copies
FROM to CC0. */
- if (GET_CODE (to) == SUBREG
+ if (SUBREG_P (to)
&& !targetm.modes_tieable_p (GET_MODE (to),
GET_MODE (SUBREG_REG (to)))
&& ! (code == SUBREG
@@ -5676,7 +5676,7 @@ subst (rtx x, rtx from, rtx to, int in_dest, int in_cond, int unique_copy)
if (GET_CODE (new_rtx) == CLOBBER && XEXP (new_rtx, 0) == const0_rtx)
return new_rtx;
- if (GET_CODE (x) == SUBREG && CONST_SCALAR_INT_P (new_rtx))
+ if (SUBREG_P (x) && CONST_SCALAR_INT_P (new_rtx))
{
machine_mode mode = GET_MODE (x);
@@ -5830,14 +5830,14 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
if ((BINARY_P (x)
&& ((!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
|| (!OBJECT_P (XEXP (x, 1))
- && ! (GET_CODE (XEXP (x, 1)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 1))
&& OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
|| (UNARY_P (x)
&& (!OBJECT_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
{
rtx cond, true_rtx, false_rtx;
@@ -6049,7 +6049,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
complex if it was just a register. */
if (!REG_P (temp)
- && ! (GET_CODE (temp) == SUBREG
+ && ! (SUBREG_P (temp)
&& REG_P (SUBREG_REG (temp)))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (i = exact_log2 (nonzero_bits (temp, int_mode))) >= 0)
@@ -6151,7 +6151,7 @@ combine_simplify_rtx (rtx x, machine_mode op0_mode, int in_dest,
"a = (b & 8) == 0;" */
if (XEXP (x, 1) == constm1_rtx
&& !REG_P (XEXP (x, 0))
- && ! (GET_CODE (XEXP (x, 0)) == SUBREG
+ && ! (SUBREG_P (XEXP (x, 0))
&& REG_P (SUBREG_REG (XEXP (x, 0))))
&& is_a <scalar_int_mode> (mode, &int_mode)
&& nonzero_bits (XEXP (x, 0), int_mode) == 1)
@@ -6587,7 +6587,7 @@ simplify_if_then_else (rtx x)
&& !CONST_INT_P (false_rtx) && false_rtx != pc_rtx)
|| true_rtx == const0_rtx
|| (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
- || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
+ || (SUBREG_P (true_rtx) && OBJECT_P (SUBREG_REG (true_rtx))
&& !OBJECT_P (false_rtx))
|| reg_mentioned_p (true_rtx, false_rtx)
|| rtx_equal_p (false_rtx, XEXP (cond, 0))))
@@ -6712,7 +6712,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6729,7 +6729,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
&& (num_sign_bit_copies (f, GET_MODE (f))
@@ -6750,7 +6750,7 @@ simplify_if_then_else (rtx x)
|| GET_CODE (XEXP (t, 0)) == ASHIFT
|| GET_CODE (XEXP (t, 0)) == LSHIFTRT
|| GET_CODE (XEXP (t, 0)) == ASHIFTRT)
- && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 0))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
@@ -6767,7 +6767,7 @@ simplify_if_then_else (rtx x)
&& (GET_CODE (XEXP (t, 0)) == PLUS
|| GET_CODE (XEXP (t, 0)) == IOR
|| GET_CODE (XEXP (t, 0)) == XOR)
- && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (t, 0), 1))
&& HWI_COMPUTABLE_MODE_P (int_mode)
&& subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
&& rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
@@ -7051,7 +7051,7 @@ simplify_set (rtx x)
be undefined. On machine where it is defined, this transformation is safe
as long as M1 and M2 have the same number of words. */
- if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
+ if (SUBREG_P (src) && subreg_lowpart_p (src)
&& !OBJECT_P (SUBREG_REG (src))
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (src)),
@@ -7063,7 +7063,7 @@ simplify_set (rtx x)
GET_MODE (SUBREG_REG (src)),
GET_MODE (src)))
&& (REG_P (dest)
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest)))))
{
SUBST (SET_DEST (x),
@@ -7387,7 +7387,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& HWI_COMPUTABLE_MODE_P (mode)
@@ -7407,7 +7407,7 @@ expand_compound_operation (rtx x)
return XEXP (XEXP (x, 0), 0);
/* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
- if (GET_CODE (XEXP (x, 0)) == SUBREG
+ if (SUBREG_P (XEXP (x, 0))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == mode
&& subreg_lowpart_p (XEXP (x, 0))
&& COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
@@ -7482,7 +7482,7 @@ expand_field_assignment (const_rtx x)
while (1)
{
if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
- && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
+ && SUBREG_P (XEXP (SET_DEST (x), 0)))
{
rtx x0 = XEXP (SET_DEST (x), 0);
if (!GET_MODE_PRECISION (GET_MODE (x0)).is_constant (&len))
@@ -7524,7 +7524,7 @@ expand_field_assignment (const_rtx x)
/* If the destination is a subreg that overwrites the whole of the inner
register, we can move the subreg to the source. */
- else if (GET_CODE (SET_DEST (x)) == SUBREG
+ else if (SUBREG_P (SET_DEST (x))
/* We need SUBREGs to compute nonzero_bits properly. */
&& nonzero_sign_valid
&& !read_modify_subreg_p (SET_DEST (x)))
@@ -7538,7 +7538,7 @@ expand_field_assignment (const_rtx x)
else
break;
- while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
+ while (SUBREG_P (inner) && subreg_lowpart_p (inner))
inner = SUBREG_REG (inner);
/* Don't attempt bitwise arithmetic on non scalar integer modes. */
@@ -7631,7 +7631,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (pos_rtx && CONST_INT_P (pos_rtx))
pos = INTVAL (pos_rtx), pos_rtx = 0;
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& subreg_lowpart_p (inner)
&& (paradoxical_subreg_p (inner)
/* If trying or potentionally trying to extract
@@ -7764,7 +7764,7 @@ make_extraction (machine_mode mode, rtx inner, HOST_WIDE_INT pos,
if (in_dest)
return (MEM_P (new_rtx) ? new_rtx
- : (GET_CODE (new_rtx) != SUBREG
+ : (!SUBREG_P (new_rtx)
? gen_rtx_CLOBBER (tmode, const0_rtx)
: gen_rtx_STRICT_LOW_PART (VOIDmode, new_rtx)));
@@ -8189,7 +8189,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
}
/* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG
+ else if (SUBREG_P (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0))
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (XEXP (x, 0))),
&inner_mode)
@@ -8294,7 +8294,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
the constant (limited to the smaller mode) has only zero bits where
the sub expression has known zero bits, this can be expressed as
a zero_extend. */
- else if (GET_CODE (XEXP (x, 0)) == SUBREG)
+ else if (SUBREG_P (XEXP (x, 0)))
{
rtx sub;
@@ -8365,7 +8365,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
seem worth the effort; the case checked for occurs on Alpha. */
if (!OBJECT_P (lhs)
- && ! (GET_CODE (lhs) == SUBREG
+ && ! (SUBREG_P (lhs)
&& (OBJECT_P (SUBREG_REG (lhs))))
&& CONST_INT_P (rhs)
&& INTVAL (rhs) >= 0
@@ -8410,7 +8410,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
to the recursive make_compound_operation call. */
if (subreg_code == COMPARE
&& (!subreg_lowpart_p (x)
- || GET_CODE (inner) == SUBREG
+ || SUBREG_P (inner)
/* (subreg:SI (and:DI (reg:DI) (const_int 0x800000000)) 0)
is (const_int 0), rather than
(subreg:SI (lshiftrt:DI (reg:DI) (const_int 35)) 0).
@@ -8440,7 +8440,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* If we have something other than a SUBREG, we might have
done an expansion, so rerun ourselves. */
- if (GET_CODE (newer) != SUBREG)
+ if (!SUBREG_P (newer))
newer = make_compound_operation (newer, in_code);
/* force_to_mode can expand compounds. If it just re-expanded
@@ -8450,7 +8450,7 @@ make_compound_operation_int (scalar_int_mode mode, rtx *x_ptr,
/* Likewise if it re-expanded the compound only partially.
This happens for SUBREG of ZERO_EXTRACT if they extract
the same number of bits. */
- || (GET_CODE (newer) == SUBREG
+ || (SUBREG_P (newer)
&& (GET_CODE (SUBREG_REG (newer)) == LSHIFTRT
|| GET_CODE (SUBREG_REG (newer)) == ASHIFTRT)
&& GET_CODE (inner) == AND
@@ -8777,7 +8777,7 @@ force_to_mode (rtx x, machine_mode mode, unsigned HOST_WIDE_INT mask,
/* We can ignore the effect of a SUBREG if it narrows the mode or
if the constant masks to zero all the bits the mode doesn't have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& (partial_subreg_p (x)
|| (mask
@@ -9711,13 +9711,13 @@ rtx_equal_for_field_assignment_p (rtx x, rtx y, bool widen_x)
/* Check for a paradoxical SUBREG of a MEM compared with the MEM.
Note that all SUBREGs of MEM are paradoxical; otherwise they
would have been rewritten. */
- if (MEM_P (x) && GET_CODE (y) == SUBREG
+ if (MEM_P (x) && SUBREG_P (y)
&& MEM_P (SUBREG_REG (y))
&& rtx_equal_p (SUBREG_REG (y),
gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
return 1;
- if (MEM_P (y) && GET_CODE (x) == SUBREG
+ if (MEM_P (y) && SUBREG_P (x)
&& MEM_P (SUBREG_REG (x))
&& rtx_equal_p (SUBREG_REG (x),
gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
@@ -9770,7 +9770,7 @@ make_field_assignment (rtx x)
return x;
}
- if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
+ if (GET_CODE (src) == AND && SUBREG_P (XEXP (src, 0))
&& subreg_lowpart_p (XEXP (src, 0))
&& partial_subreg_p (XEXP (src, 0))
&& GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
@@ -9842,7 +9842,7 @@ make_field_assignment (rtx x)
narrowing SUBREG, which we can just strip for the purposes of
identifying the constant-field assignment. */
scalar_int_mode src_mode = mode;
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& subreg_lowpart_p (src)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (src)), &src_mode))
src = SUBREG_REG (src);
@@ -11622,7 +11622,7 @@ change_zero_ext (rtx pat)
}
}
else if (GET_CODE (x) == ZERO_EXTEND
- && GET_CODE (XEXP (x, 0)) == SUBREG
+ && SUBREG_P (XEXP (x, 0))
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (XEXP (x, 0))))
&& !paradoxical_subreg_p (XEXP (x, 0))
&& subreg_lowpart_p (XEXP (x, 0)))
@@ -11781,7 +11781,7 @@ gen_lowpart_for_combine (machine_mode omode, rtx x)
/* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
won't know what to do. So we will strip off the SUBREG here and
process normally. */
- if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
{
x = SUBREG_REG (x);
@@ -12076,8 +12076,8 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
&& GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
&& GET_CODE (XEXP (op0, 0)) == ASHIFT
&& GET_CODE (XEXP (op1, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
- && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
+ && SUBREG_P (XEXP (XEXP (op0, 0), 0))
+ && SUBREG_P (XEXP (XEXP (op1, 0), 0))
&& is_a <scalar_int_mode> (GET_MODE (op0), &mode)
&& (is_a <scalar_int_mode>
(GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))), &inner_mode))
@@ -12151,7 +12151,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
int changed = 0;
if (paradoxical_subreg_p (inner_op0)
- && GET_CODE (inner_op1) == SUBREG
+ && SUBREG_P (inner_op1)
&& HWI_COMPUTABLE_MODE_P (GET_MODE (SUBREG_REG (inner_op0)))
&& (GET_MODE (SUBREG_REG (inner_op0))
== GET_MODE (SUBREG_REG (inner_op1)))
@@ -12729,7 +12729,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
fits in both M1 and M2 and the SUBREG is either paradoxical
or represents the low part, permute the SUBREG and the AND
and try again. */
- if (GET_CODE (XEXP (op0, 0)) == SUBREG
+ if (SUBREG_P (XEXP (op0, 0))
&& CONST_INT_P (XEXP (op0, 1)))
{
unsigned HOST_WIDE_INT c1 = INTVAL (XEXP (op0, 1));
@@ -13008,7 +13008,7 @@ simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
op0 = make_compound_operation (op0, op0_mco_code);
op1 = make_compound_operation (op1, SET);
- if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
+ if (SUBREG_P (op0) && subreg_lowpart_p (op0)
&& is_int_mode (GET_MODE (op0), &mode)
&& is_int_mode (GET_MODE (SUBREG_REG (op0)), &inner_mode)
&& (code == NE || code == EQ))
@@ -13376,7 +13376,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
{
rtx_insn *record_dead_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (!record_dead_insn)
@@ -13397,7 +13397,7 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data)
if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
else if (GET_CODE (setter) == SET
- && GET_CODE (SET_DEST (setter)) == SUBREG
+ && SUBREG_P (SET_DEST (setter))
&& SUBREG_REG (SET_DEST (setter)) == dest
&& known_le (GET_MODE_PRECISION (GET_MODE (dest)),
BITS_PER_WORD)
@@ -13577,7 +13577,7 @@ record_truncated_value (rtx x)
machine_mode truncated_mode;
reg_stat_type *rsp;
- if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x)))
+ if (SUBREG_P (x) && REG_P (SUBREG_REG (x)))
{
machine_mode original_mode = GET_MODE (SUBREG_REG (x));
truncated_mode = GET_MODE (x);
@@ -13629,7 +13629,7 @@ record_truncated_values (rtx *loc, void *data ATTRIBUTE_UNUSED)
static void
check_promoted_subreg (rtx_insn *insn, rtx x)
{
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& REG_P (SUBREG_REG (x)))
record_promoted_value (insn, x);
@@ -13775,7 +13775,7 @@ get_last_value (const_rtx x)
/* If this is a non-paradoxical SUBREG, get the value of its operand and
then convert it to the desired mode. If this is a paradoxical SUBREG,
we cannot predict what values the "extra" bits might have. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& subreg_lowpart_p (x)
&& !paradoxical_subreg_p (x)
&& (value = get_last_value (SUBREG_REG (x))) != 0)
@@ -13982,7 +13982,7 @@ mark_used_regs_combine (rtx x)
the address. */
rtx testreg = SET_DEST (x);
- while (GET_CODE (testreg) == SUBREG
+ while (SUBREG_P (testreg)
|| GET_CODE (testreg) == ZERO_EXTRACT
|| GET_CODE (testreg) == STRICT_LOW_PART)
testreg = XEXP (testreg, 0);
@@ -14162,7 +14162,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
if (GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART
- || (GET_CODE (dest) == SUBREG
+ || (SUBREG_P (dest)
&& !read_modify_subreg_p (dest)))
{
move_deaths (dest, maybe_kill_insn, from_luid, to_insn, pnotes);
@@ -14171,7 +14171,7 @@ move_deaths (rtx x, rtx maybe_kill_insn, int from_luid, rtx_insn *to_insn,
/* If this is some other SUBREG, we know it replaces the entire
value, so use that as the destination. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
/* If this is a MEM, adjust deaths of anything used in the address.
@@ -14225,7 +14225,7 @@ reg_bitfield_target_p (rtx x, rtx body)
else
return 0;
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
target = SUBREG_REG (target);
if (!REG_P (target))
@@ -14624,7 +14624,7 @@ distribute_notes (rtx notes, rtx_insn *from_insn, rtx_insn *i3, rtx_insn *i2,
if (set != 0)
for (inner_dest = SET_DEST (set);
(GET_CODE (inner_dest) == STRICT_LOW_PART
- || GET_CODE (inner_dest) == SUBREG
+ || SUBREG_P (inner_dest)
|| GET_CODE (inner_dest) == ZERO_EXTRACT);
inner_dest = XEXP (inner_dest, 0))
;
@@ -14892,7 +14892,7 @@ distribute_links (struct insn_link *links)
reg = SET_DEST (set);
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (!REG_P (reg))
@@ -14911,7 +14911,7 @@ distribute_links (struct insn_link *links)
while (GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART
- || GET_CODE (reg) == SUBREG)
+ || SUBREG_P (reg))
reg = XEXP (reg, 0);
if (reg == pc_rtx)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 9bdbc198dae..70cac11c257 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3522,9 +3522,9 @@ bool
aarch64_maybe_expand_sve_subreg_move (rtx dest, rtx src)
{
gcc_assert (BYTES_BIG_ENDIAN);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
src = SUBREG_REG (src);
/* The optimization handles two single SVE REGs with different element
@@ -6414,7 +6414,7 @@ static bool
aarch64_base_register_rtx_p (rtx x, bool strict_p)
{
if (!strict_p
- && GET_CODE (x) == SUBREG
+ && SUBREG_P (x)
&& contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (x))])
x = SUBREG_REG (x);
@@ -6433,7 +6433,7 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
int shift;
/* (reg:P) */
- if ((REG_P (x) || GET_CODE (x) == SUBREG)
+ if ((REG_P (x) || SUBREG_P (x))
&& GET_MODE (x) == Pmode)
{
type = ADDRESS_REG_REG;
@@ -6563,7 +6563,7 @@ aarch64_classify_index (struct aarch64_address_info *info, rtx x,
return false;
if (!strict_p
- && GET_CODE (index) == SUBREG
+ && SUBREG_P (index)
&& contains_reg_of_mode[GENERAL_REGS][GET_MODE (SUBREG_REG (index))])
index = SUBREG_REG (index);
@@ -7294,7 +7294,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
the comparison will have to be swapped when we emit the assembly
code. */
if ((mode_x == SImode || mode_x == DImode)
- && (REG_P (y) || GET_CODE (y) == SUBREG || y == const0_rtx)
+ && (REG_P (y) || SUBREG_P (y) || y == const0_rtx)
&& (code_x == ASHIFT || code_x == ASHIFTRT
|| code_x == LSHIFTRT
|| code_x == ZERO_EXTEND || code_x == SIGN_EXTEND))
@@ -7303,7 +7303,7 @@ aarch64_select_cc_mode (RTX_CODE code, rtx x, rtx y)
/* Similarly for a negated operand, but we can only do this for
equalities. */
if ((mode_x == SImode || mode_x == DImode)
- && (REG_P (y) || GET_CODE (y) == SUBREG)
+ && (REG_P (y) || SUBREG_P (y))
&& (code == EQ || code == NE)
&& code_x == NEG)
return CC_Zmode;
@@ -8615,7 +8615,7 @@ aarch64_preferred_reload_class (rtx x, reg_class_t regclass)
rtx lhs = XEXP (x, 0);
/* Look through a possible SUBREG introduced by ILP32. */
- if (GET_CODE (lhs) == SUBREG)
+ if (SUBREG_P (lhs))
lhs = SUBREG_REG (lhs);
gcc_assert (REG_P (lhs));
@@ -9523,7 +9523,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
case SIGN_EXTRACT:
/* Bit-field insertion. Strip any redundant widening of
the RHS to meet the width of the target. */
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = SUBREG_REG (op1);
if ((GET_CODE (op1) == ZERO_EXTEND
|| GET_CODE (op1) == SIGN_EXTEND)
@@ -9789,7 +9789,7 @@ aarch64_rtx_costs (rtx x, machine_mode mode, int outer ATTRIBUTE_UNUSED,
But the integer MINUS logic expects the shift/extend
operation in op1. */
if (! (REG_P (op0)
- || (GET_CODE (op0) == SUBREG && REG_P (SUBREG_REG (op0)))))
+ || (SUBREG_P (op0) && REG_P (SUBREG_REG (op0)))))
{
op0 = XEXP (x, 1);
op1 = XEXP (x, 0);
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index e417756a9f4..5a06d94d5f7 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -11352,7 +11352,7 @@ mem_ok_for_ldd_std (rtx mem, rtx *base, rtx *offset)
return false;
/* Can't deal with subregs. */
- if (GET_CODE (mem) == SUBREG)
+ if (SUBREG_P (mem))
return false;
gcc_assert (MEM_P (mem));
@@ -11412,7 +11412,7 @@ gen_operands_ldd_std (rtx *operands, bool load, bool commute)
return false;
offsets[i] = INTVAL (cur_offset);
- if (GET_CODE (operands[i]) == SUBREG)
+ if (SUBREG_P (operands[i]))
{
tmp = SUBREG_REG (operands[i]);
gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp));
diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c
index 965a07a43e3..7348c42be85 100644
--- a/gcc/config/arm/aarch-common.c
+++ b/gcc/config/arm/aarch-common.c
@@ -479,7 +479,7 @@ aarch_accumulator_forwarding (rtx_insn *producer, rtx_insn *consumer)
return 0;
}
- if (GET_CODE (accumulator) == SUBREG)
+ if (SUBREG_P (accumulator))
accumulator = SUBREG_REG (accumulator);
if (!REG_P (accumulator))
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index c67b7c97dcc..2a5359c26ec 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -5347,7 +5347,7 @@ arm_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
to facilitate possible combining with a cmp into 'ands'. */
if (mode == SImode
&& GET_CODE (*op0) == ZERO_EXTEND
- && GET_CODE (XEXP (*op0, 0)) == SUBREG
+ && SUBREG_P (XEXP (*op0, 0))
&& GET_MODE (XEXP (*op0, 0)) == QImode
&& GET_MODE (SUBREG_REG (XEXP (*op0, 0))) == SImode
&& subreg_lowpart_p (XEXP (*op0, 0))
@@ -8973,7 +8973,7 @@ arm_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
\f
#define REG_OR_SUBREG_REG(X) \
(REG_P (X) \
- || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X))))
+ || (SUBREG_P (X) && REG_P (SUBREG_REG (X))))
#define REG_OR_SUBREG_RTX(X) \
(REG_P (X) ? (X) : SUBREG_REG (X))
@@ -10514,7 +10514,7 @@ arm_rtx_costs_internal (rtx x, enum rtx_code code, enum rtx_code outer_code,
if (XEXP (x, 1) == const0_rtx
&& !(REG_P (XEXP (x, 0))
- || (GET_CODE (XEXP (x, 0)) == SUBREG
+ || (SUBREG_P (XEXP (x, 0))
&& REG_P (SUBREG_REG (XEXP (x, 0))))))
{
*cost = rtx_cost (XEXP (x, 0), op0mode, COMPARE, 0, speed_p);
@@ -13395,7 +13395,7 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
rtx offset;
/* Convert a subreg of a mem into the mem itself. */
- if (GET_CODE (operands[nops + i]) == SUBREG)
+ if (SUBREG_P (operands[nops + i]))
operands[nops + i] = alter_subreg (operands + (nops + i), true);
gcc_assert (MEM_P (operands[nops + i]));
@@ -13408,11 +13408,11 @@ load_multiple_sequence (rtx *operands, int nops, int *regs, int *saved_order,
offset = const0_rtx;
if ((REG_P (reg = XEXP (operands[nops + i], 0))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
&& ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
&& (CONST_INT_P (offset
= XEXP (XEXP (operands[nops + i], 0), 1)))))
@@ -13549,7 +13549,7 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
rtx offset;
/* Convert a subreg of a mem into the mem itself. */
- if (GET_CODE (operands[nops + i]) == SUBREG)
+ if (SUBREG_P (operands[nops + i]))
operands[nops + i] = alter_subreg (operands + (nops + i), true);
gcc_assert (MEM_P (operands[nops + i]));
@@ -13562,11 +13562,11 @@ store_multiple_sequence (rtx *operands, int nops, int nops_total,
offset = const0_rtx;
if ((REG_P (reg = XEXP (operands[nops + i], 0))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
|| (GET_CODE (XEXP (operands[nops + i], 0)) == PLUS
&& ((REG_P (reg = XEXP (XEXP (operands[nops + i], 0), 0)))
- || (GET_CODE (reg) == SUBREG
+ || (SUBREG_P (reg)
&& REG_P (reg = SUBREG_REG (reg))))
&& (CONST_INT_P (offset
= XEXP (XEXP (operands[nops + i], 0), 1)))))
@@ -14877,7 +14877,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* A compare with a shifted operand. Because of canonicalization, the
comparison will have to be swapped when we emit the assembler. */
if (GET_MODE (y) == SImode
- && (REG_P (y) || (GET_CODE (y) == SUBREG))
+ && (REG_P (y) || (SUBREG_P (y)))
&& (GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT
|| GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ROTATE
|| GET_CODE (x) == ROTATERT))
@@ -14886,7 +14886,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
/* This operation is performed swapped, but since we only rely on the Z
flag we don't need an additional mode. */
if (GET_MODE (y) == SImode
- && (REG_P (y) || (GET_CODE (y) == SUBREG))
+ && (REG_P (y) || (SUBREG_P (y)))
&& GET_CODE (x) == NEG
&& (op == EQ || op == NE))
return CC_Zmode;
@@ -14898,7 +14898,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y)
if (GET_MODE (x) == SImode
&& GET_CODE (x) == ASHIFT
&& CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) == 24
- && GET_CODE (XEXP (x, 0)) == SUBREG
+ && SUBREG_P (XEXP (x, 0))
&& MEM_P (SUBREG_REG (XEXP (x, 0)))
&& GET_MODE (SUBREG_REG (XEXP (x, 0))) == QImode
&& (op == EQ || op == NE
@@ -15087,7 +15087,7 @@ arm_reload_in_hi (rtx *operands)
rtx base, scratch;
HOST_WIDE_INT offset = 0;
- if (GET_CODE (ref) == SUBREG)
+ if (SUBREG_P (ref))
{
offset = SUBREG_BYTE (ref);
ref = SUBREG_REG (ref);
@@ -15215,7 +15215,7 @@ arm_reload_out_hi (rtx *operands)
rtx base, scratch;
HOST_WIDE_INT offset = 0;
- if (GET_CODE (ref) == SUBREG)
+ if (SUBREG_P (ref))
{
offset = SUBREG_BYTE (ref);
ref = SUBREG_REG (ref);
@@ -15546,7 +15546,7 @@ mem_ok_for_ldrd_strd (rtx mem, rtx *base, rtx *offset, HOST_WIDE_INT *align)
return false;
/* Can't deal with subregs. */
- if (GET_CODE (mem) == SUBREG)
+ if (SUBREG_P (mem))
return false;
gcc_assert (MEM_P (mem));
@@ -15615,7 +15615,7 @@ gen_operands_ldrd_strd (rtx *operands, bool load,
return false;
offsets[i] = INTVAL (cur_offset);
- if (GET_CODE (operands[i]) == SUBREG)
+ if (SUBREG_P (operands[i]))
{
tmp = SUBREG_REG (operands[i]);
gcc_assert (GET_MODE (operands[i]) == GET_MODE (tmp));
@@ -15841,7 +15841,7 @@ valid_operands_ldrd_strd (rtx *operands, bool load)
return false;
offsets[i] = INTVAL (cur_offset);
- if (GET_CODE (operands[i]) == SUBREG)
+ if (SUBREG_P (operands[i]))
return false;
}
@@ -29679,13 +29679,13 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in,
gcc_assert (code == ASHIFT || code == ASHIFTRT || code == LSHIFTRT);
gcc_assert (out
- && (REG_P (out) || GET_CODE (out) == SUBREG)
+ && (REG_P (out) || SUBREG_P (out))
&& GET_MODE (out) == DImode);
gcc_assert (in
- && (REG_P (in) || GET_CODE (in) == SUBREG)
+ && (REG_P (in) || SUBREG_P (in))
&& GET_MODE (in) == DImode);
gcc_assert (amount
- && (((REG_P (amount) || GET_CODE (amount) == SUBREG)
+ && (((REG_P (amount) || SUBREG_P (amount))
&& GET_MODE (amount) == SImode)
|| CONST_INT_P (amount)));
gcc_assert (scratch1 == NULL
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 4866e1e4b7d..b2a2bc8cf39 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1240,7 +1240,7 @@ enum reg_class
? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 \
&& (MEM_P (X) \
- || ((REG_P (X) || GET_CODE (X) == SUBREG) \
+ || ((REG_P (X) || SUBREG_P (X)) \
&& true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index ccc48a57dda..5eadcc58df6 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -2809,7 +2809,7 @@
target = copy_rtx (operands[0]);
/* Avoid using a subreg as a subtarget, and avoid writing a paradoxical
subreg as the final target. */
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
{
subtarget = gen_reg_rtx (SImode);
if (GET_MODE_SIZE (GET_MODE (SUBREG_REG (target)))
@@ -2919,7 +2919,7 @@
{
/* If TARGET is still a SUBREG, then it must be wider than a word,
so we must be careful only to set the subword we were asked to. */
- if (GET_CODE (target) == SUBREG)
+ if (SUBREG_P (target))
emit_move_insn (target, subtarget);
else
emit_move_insn (target, gen_lowpart (GET_MODE (target), subtarget));
@@ -4357,7 +4357,7 @@
rtx tmp = gen_reg_rtx (SImode);
/* We may get a paradoxical subreg here. Strip it off. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& GET_MODE (dest) == SImode
&& GET_MODE (SUBREG_REG (dest)) == HImode)
dest = SUBREG_REG (dest);
@@ -4441,7 +4441,7 @@
rtx tmp = gen_reg_rtx (SImode);
/* We may get a paradoxical subreg here. Strip it off. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& GET_MODE (dest) == SImode
&& GET_MODE (SUBREG_REG (dest)) == HImode)
dest = SUBREG_REG (dest);
diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md
index 25f86471ded..de040cec465 100644
--- a/gcc/config/arm/predicates.md
+++ b/gcc/config/arm/predicates.md
@@ -21,7 +21,7 @@
(define_predicate "s_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
@@ -91,7 +91,7 @@
(define_predicate "arm_general_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return (REG_P (op)
@@ -107,7 +107,7 @@
(define_predicate "vfp_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
/* We don't consider registers whose class is NO_REGS
@@ -466,7 +466,7 @@
if (s_register_operand (op, mode))
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
@@ -483,7 +483,7 @@
if (s_register_operand (op, mode))
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 7f8424b5f5d..716e7345d50 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -2875,7 +2875,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
*total = cost2;
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += set_src_cost (op0, mode, speed);
#if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
towards creating too many induction variables. */
@@ -2890,7 +2890,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
|| !satisfies_constraint_Ks7 (op1))
*total += rtx_cost (op1, mode, PLUS, 1, speed);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, PLUS, 0, speed);
}
return true;
@@ -2913,7 +2913,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
return true;
@@ -2938,7 +2938,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
if (mode == DImode)
@@ -2997,10 +2997,10 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
*total = COSTS_N_INSNS (3);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
if (!REG_P (op1)
- && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
+ && (!SUBREG_P (op1) || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
}
return true;
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index 04eb584df0f..fa29cea79c3 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -76,7 +76,7 @@
(define_predicate "valid_reg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REGNO (op) < FIRST_PSEUDO_REGISTER)
return targetm.hard_regno_mode_ok (REGNO (op), mode);
@@ -122,7 +122,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -180,7 +180,7 @@
(define_predicate "register_no_elim_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return !(op == arg_pointer_rtx
|| op == frame_pointer_rtx
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index fe78ed0dfce..dab63cb3011 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -6175,10 +6175,10 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
*total = COSTS_N_INSNS (speed ? 2 : 1);
if (!REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
if (op1 && !REG_P (op1)
- && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
+ && (!SUBREG_P (op1) || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
return true;
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 2b35d6717cb..1404363f8f8 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -632,7 +632,7 @@
(match_operand:SISFVM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,S0,S0,Si,Q, R, R, Q, a,?a, b,?b"))]
"(GET_CODE (operands[0]) != MEM || REG_P (operands[1])
- || (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))))"
+ || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))"
"@
%|%.\\tmv\\t%$\\t%1, %0
%|%.\\tmv\\t%$\\t%1, %0
@@ -666,7 +666,7 @@
(match_operand:DIDFVM 1 "general_operand"
"a,b,?b,?a,iF,Q, R, R, Q, a,?a, b,?b"))]
"(!MEM_P (operands[0]) || REG_P (operands[1])
- || (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))))"
+ || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1]))))"
{
if (MEM_P (operands[1]) && TARGET_LDDW)
return "%|%.\\tlddw\\t%$\\t%1, %0";
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 4cdb58b06bb..0dc9435078d 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -715,7 +715,7 @@ cr16_addr_reg_p (rtx addr_reg)
if (REG_P (addr_reg))
reg = addr_reg;
- else if ((GET_CODE (addr_reg) == SUBREG)
+ else if ((SUBREG_P (addr_reg))
&& REG_P (SUBREG_REG (addr_reg))
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (addr_reg)))
<= UNITS_PER_WORD))
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 67d7c316841..2073f35f119 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -2890,7 +2890,7 @@ cris_split_movdx (rtx *operands)
/* We used to have to handle (SUBREG (MEM)) here, but that should no
longer happen; after reload there are no SUBREGs any more, and we're
only called after reload. */
- CRIS_ASSERT (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
+ CRIS_ASSERT (!SUBREG_P (dest) && !SUBREG_P (src));
start_sequence ();
if (REG_P (dest))
diff --git a/gcc/config/cris/cris.h b/gcc/config/cris/cris.h
index 2c77ab865b4..8006c25390b 100644
--- a/gcc/config/cris/cris.h
+++ b/gcc/config/cris/cris.h
@@ -44,7 +44,7 @@ along with GCC; see the file COPYING3. If not see
/* Replacement for REG_P since it does not match SUBREGs. Happens for
testcase Axis-20000320 with gcc-2.9x. */
#define REG_S_P(x) \
- (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (XEXP (x, 0))))
+ (REG_P (x) || (SUBREG_P (x) && REG_P (XEXP (x, 0))))
/* Last register in main register bank r0..r15. */
#define CRIS_LAST_GENERAL_REGISTER 15
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 6d2192a5096..fd2291f176c 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -2313,7 +2313,7 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
regno = true_regnum (x);
else
{
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
{
off += subreg_regno_offset (REGNO (SUBREG_REG (x)),
GET_MODE (SUBREG_REG (x)),
@@ -2325,7 +2325,7 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
regno = REGNO (x) + off;
}
}
- else if (REG_P (x) || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || SUBREG_P (x))
regno = true_regnum (x);
/* We always require a general register when copying anything to
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 9089c4673dc..8dea5b9f33c 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -981,7 +981,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#endif /* HAVE_lo_sum */
{
if (REG_P (orig)
- || GET_CODE (orig) == SUBREG)
+ || SUBREG_P (orig))
{
return orig;
}
diff --git a/gcc/config/epiphany/epiphany.md b/gcc/config/epiphany/epiphany.md
index be9ea9ab5aa..354a21f5c41 100644
--- a/gcc/config/epiphany/epiphany.md
+++ b/gcc/config/epiphany/epiphany.md
@@ -335,10 +335,10 @@
&& !reload_in_progress
&& (GET_CODE (operands[0]) == MEM || GET_CODE (operands[1]) == MEM)
&& !misaligned_operand (operands[1], <MODE>mode)
- && (GET_CODE (operands[0]) != SUBREG
+ && (!SUBREG_P (operands[0])
|| (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
!= GET_MODE_SIZE (<MODE>mode)
- && GET_CODE (operands[1]) != SUBREG)))
+ && !SUBREG_P (operands[1]))))
{
operands[0]
= simplify_gen_subreg (DImode, operands[0], <MODE>mode, 0);
@@ -2579,8 +2579,8 @@
gcc_assert (!reg_overlap_mentioned_p (last_out, xop[i])
/* ??? reg_overlap_mentioned_p doesn't understand
about multi-word SUBREGs. */
- || (GET_CODE (last_out) == SUBREG
- && GET_CODE (xop[i]) == SUBREG
+ || (SUBREG_P (last_out)
+ && SUBREG_P (xop[i])
&& SUBREG_REG (last_out) == SUBREG_REG (xop[i])
&& ((SUBREG_BYTE (last_out) & -UNITS_PER_WORD)
!= (SUBREG_BYTE (xop[i]) & -UNITS_PER_WORD))));
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index 6804a75a290..1d881a22d50 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -62,7 +62,7 @@
if (!register_operand (op, mode))
return 0;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = XEXP (op, 0);
regno = REGNO (op);
return regno >= FIRST_PSEUDO_REGISTER || regno <= 63;
@@ -84,7 +84,7 @@
if (!register_operand (op, mode))
return 0;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = XEXP (op, 0);
regno = REGNO (op);
return (regno >= FIRST_PSEUDO_REGISTER || regno <= 63
@@ -96,7 +96,7 @@
(define_predicate "add_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return add_reg_operand (op, mode);
return satisfies_constraint_L (op) || satisfies_constraint_CnL (op);
})
@@ -105,7 +105,7 @@
(define_predicate "arith_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
return satisfies_constraint_L (op);
})
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index b8670bbdb14..f19dbdabd81 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -291,7 +291,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))]
"INTVAL (operands[1]) <= -1 && INTVAL (operands[1]) >= -128
- && (GET_CODE (operands[0]) != SUBREG
+ && (!SUBREG_P (operands[0])
|| SCALAR_INT_MODE_P (GET_MODE (XEXP (operands[0], 0))))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 0) (sign_extend:SI (match_dup 2)))]
@@ -654,7 +654,7 @@
""
"{
if ( REG_P (operands[2])
- || GET_CODE (operands[2]) == SUBREG)
+ || SUBREG_P (operands[2]))
emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
else if (!CONST_INT_P (operands[2]))
emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index f8b9b781e28..330a74523a5 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -72,7 +72,7 @@
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
switch (GET_CODE (op))
@@ -100,7 +100,7 @@
if (mode != VOIDmode && GET_MODE (op) != VOIDmode && GET_MODE (op) != DImode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == MEM)
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 72f867d3306..a1df8153a22 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -2564,7 +2564,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
fputs ("@(", stream);
if (!x0)
fputs (reg_names[GPR_R0], stream);
- else if (REG_P (x0) || GET_CODE (x0) == SUBREG)
+ else if (REG_P (x0) || SUBREG_P (x0))
frv_print_operand_memory_reference_reg (stream, x0);
else
fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
@@ -3368,7 +3368,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
x0 = XEXP (x, 0);
x1 = XEXP (x, 1);
- if (GET_CODE (x0) == SUBREG)
+ if (SUBREG_P (x0))
x0 = SUBREG_REG (x0);
if (!REG_P (x0))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index c3724de35e6..bbe55939a62 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -25,7 +25,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -51,7 +51,7 @@
if (reload_in_progress)
{
rtx tmp = op;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
@@ -86,7 +86,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -118,7 +118,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -146,7 +146,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -175,7 +175,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -200,7 +200,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -747,7 +747,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -771,7 +771,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -805,7 +805,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -840,7 +840,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -871,7 +871,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -903,7 +903,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -934,7 +934,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -965,7 +965,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
@@ -1447,7 +1447,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 0006583b11e..bc57f0d7c33 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -611,7 +611,7 @@ gcn_can_split_p (machine_mode, rtx op)
{
if (vgpr_vector_mode_p (GET_MODE (op)))
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
return true;
@@ -1015,7 +1015,7 @@ gcn_gen_undef (machine_mode mode)
static bool
gcn_address_register_p (rtx reg, machine_mode mode, bool strict)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -1047,7 +1047,7 @@ gcn_address_register_p (rtx reg, machine_mode mode, bool strict)
static bool
gcn_vec_address_register_p (rtx reg, machine_mode mode, bool strict)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -1917,7 +1917,7 @@ gcn_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
{
reg_class_t result = NO_REGS;
bool spilled_pseudo =
- (REG_P (x) || GET_CODE (x) == SUBREG) && true_regnum (x) == -1;
+ (REG_P (x) || SUBREG_P (x)) && true_regnum (x) == -1;
if (dump_file && (dump_flags & TDF_DETAILS))
{
@@ -1925,7 +1925,7 @@ gcn_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
dump_value_slim (dump_file, x, 1);
fprintf (dump_file, " %s %s:%s", (in_p ? "->" : "<-"),
reg_class_names[rclass], GET_MODE_NAME (reload_mode));
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
fprintf (dump_file, " (true regnum: %d \"%s\")", true_regnum (x),
(true_regnum (x) >= 0
&& true_regnum (x) < FIRST_PSEUDO_REGISTER
diff --git a/gcc/config/gcn/predicates.md b/gcc/config/gcn/predicates.md
index 5b54f49f3cd..5e08a8bf32b 100644
--- a/gcc/config/gcn/predicates.md
+++ b/gcc/config/gcn/predicates.md
@@ -21,7 +21,7 @@
(define_predicate "gcn_conditional_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op) || GET_MODE (op) != BImode)
@@ -37,7 +37,7 @@
(define_predicate "gcn_ssrc_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
@@ -49,7 +49,7 @@
(define_predicate "gcn_sdst_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
@@ -61,7 +61,7 @@
(define_predicate "gcn_vgpr_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!REG_P (op))
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index 44a4352f36a..5e1fe1b682b 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -5840,7 +5840,7 @@ static int
h8300_rtx_ok_for_base_p (rtx x, int strict)
{
/* Strip off SUBREG if any. */
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 1b495be4582..082ef9a7f74 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -3027,7 +3027,7 @@
/* Optimize the case where we're extracting into a paradoxical
subreg. It's only necessary to extend to the inner reg. */
- if (GET_CODE (operands[0]) == SUBREG
+ if (SUBREG_P (operands[0])
&& subreg_lowpart_p (operands[0])
&& (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0])))
< GET_MODE_SIZE (GET_MODE (operands[0])))
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 5f30de3c80a..4eeb34bb75d 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -347,7 +347,7 @@
if (REG_P (op))
return 1;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
return 1;
return (GET_CODE (op) == MEM
&& satisfies_constraint_U (op));
@@ -386,7 +386,7 @@
(define_predicate "register_no_sp_elim_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return !(op == stack_pointer_rtx
|| op == arg_pointer_rtx
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index a266f2a6fa8..a5813a80bfa 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -1004,7 +1004,7 @@ static bool
ia64_legitimate_address_reg (const_rtx reg, bool strict)
{
if ((REG_P (reg) && ia64_reg_ok_for_base_p (reg, strict))
- || (GET_CODE (reg) == SUBREG && REG_P (XEXP (reg, 0))
+ || (SUBREG_P (reg) && REG_P (XEXP (reg, 0))
&& ia64_reg_ok_for_base_p (XEXP (reg, 0), strict)))
return true;
@@ -1647,7 +1647,7 @@ ia64_split_tmode_move (rtx operands[])
static rtx
spill_xfmode_rfmode_operand (rtx in, int force, machine_mode mode)
{
- if (GET_CODE (in) == SUBREG
+ if (SUBREG_P (in)
&& GET_MODE (SUBREG_REG (in)) == TImode
&& REG_P (SUBREG_REG (in)))
{
@@ -1674,7 +1674,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
{
rtx op0 = operands[0];
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = SUBREG_REG (op0);
/* We must support XFmode loads into general registers for stdarg/vararg,
@@ -1693,14 +1693,14 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
gcc_assert (can_create_pseudo_p ());
/* Struct to register can just use TImode instead. */
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& GET_MODE (SUBREG_REG (operands[1])) == TImode)
|| (REG_P (operands[1])
&& GR_REGNO_P (REGNO (operands[1]))))
{
rtx op1 = operands[1];
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = SUBREG_REG (op1);
else
op1 = gen_rtx_REG (TImode, REGNO (op1));
@@ -5898,7 +5898,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
{
int regno = -1;
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
regno = true_regnum (x);
switch (rclass)
@@ -9626,7 +9626,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (dest);
reg = SET_DEST (dest);
gcc_assert (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -9650,7 +9650,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (dest);
reg = SET_DEST (dest);
gcc_assert (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -9668,7 +9668,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
mem = XEXP (mem, 1);
}
- while (GET_CODE (mem) == SUBREG || GET_CODE (mem) == ZERO_EXTEND)
+ while (SUBREG_P (mem) || GET_CODE (mem) == ZERO_EXTEND)
mem = XEXP (mem, 0);
if (GET_CODE (mem) == UNSPEC)
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index 4a539cdf423..c1f3e09322c 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -380,7 +380,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -392,7 +392,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -404,7 +404,7 @@
(match_operand 0 "register_operand")
{
unsigned int regno;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -421,7 +421,7 @@
if (GET_CODE (op) == MEM)
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -436,7 +436,7 @@
if (GET_CODE (op) == MEM)
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
@@ -451,7 +451,7 @@
if (GET_CODE (op) == MEM)
return true;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
regno = REGNO (op);
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index b5e2754dc3e..2092093b877 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -331,7 +331,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
&& ! (CONST_INT_P (xinsn) && ! SMALL_INT (xinsn)))
return 1;
- while (GET_CODE (xinsn) == SUBREG)
+ while (SUBREG_P (xinsn))
xinsn = SUBREG_REG (xinsn);
if (REG_P (xinsn)
@@ -343,7 +343,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
rtx xlow0 = XEXP (xinsn, 0);
rtx xlow1 = XEXP (xinsn, 1);
- while (GET_CODE (xlow0) == SUBREG)
+ while (SUBREG_P (xlow0))
xlow0 = SUBREG_REG (xlow0);
if (REG_P (xlow0)
&& iq2000_reg_mode_ok_for_base_p (xlow0, mode, strict)
@@ -358,11 +358,11 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
enum rtx_code code0;
enum rtx_code code1;
- while (GET_CODE (xplus0) == SUBREG)
+ while (SUBREG_P (xplus0))
xplus0 = SUBREG_REG (xplus0);
code0 = GET_CODE (xplus0);
- while (GET_CODE (xplus1) == SUBREG)
+ while (SUBREG_P (xplus1))
xplus1 = SUBREG_REG (xplus1);
code1 = GET_CODE (xplus1);
@@ -434,7 +434,7 @@ iq2000_fill_delay_slot (const char *ret, enum delay_type type, rtx operands[],
if (set_reg == 0)
return ret;
- while (GET_CODE (set_reg) == SUBREG)
+ while (SUBREG_P (set_reg))
set_reg = SUBREG_REG (set_reg);
mode = GET_MODE (set_reg);
@@ -956,7 +956,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
branch_p = (result == 0);
if (branch_p)
{
- if (REG_P (cmp0) || GET_CODE (cmp0) == SUBREG)
+ if (REG_P (cmp0) || SUBREG_P (cmp0))
{
/* Comparisons against zero are simple branches. */
if (CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 095a9a6818f..e52354eb8d8 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -138,7 +138,7 @@
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) == MEM
- || (GET_CODE (operands[0]) == SUBREG
+ || (SUBREG_P (operands[0])
&& GET_CODE (SUBREG_REG (operands[0])) == MEM))
{
/* Source operand for store must be in a register. */
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 1ff54b41363..922ea03ce80 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1770,7 +1770,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
/* case SB_REGNO: */
return 1;
default:
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
return 0;
if (IS_PSEUDO (reg, strict))
return 1;
@@ -3138,7 +3138,7 @@ m32c_illegal_subreg_p (rtx op)
return true;
}
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
return false;
dest_mode = GET_MODE (op);
@@ -3199,9 +3199,9 @@ m32c_mov_ok (rtx * operands, machine_mode mode ATTRIBUTE_UNUSED)
debug_rtx (op1);
#endif
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = XEXP (op0, 0);
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
if (GET_CODE (op0) == MEM
@@ -3244,7 +3244,7 @@ m32c_subreg (machine_mode outer,
/* Converting MEMs to different types that are the same size, we
just rewrite them. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_BYTE (x) == 0
&& GET_CODE (SUBREG_REG (x)) == MEM
&& (GET_MODE_SIZE (GET_MODE (x))
@@ -3260,7 +3260,7 @@ m32c_subreg (machine_mode outer,
&& (GET_CODE (XEXP (x, 0)) == PRE_DEC
|| GET_CODE (XEXP (x, 0)) == POST_INC))
return gen_rtx_MEM (outer, XEXP (x, 0));
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& GET_CODE (XEXP (x, 0)) == MEM
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == PRE_DEC
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
@@ -3269,7 +3269,7 @@ m32c_subreg (machine_mode outer,
if (!REG_P (x))
{
rtx r = simplify_gen_subreg (outer, x, inner, byte);
- if (GET_CODE (r) == SUBREG
+ if (SUBREG_P (r)
&& GET_CODE (x) == MEM
&& MEM_VOLATILE_P (x))
{
@@ -3906,7 +3906,7 @@ m32c_expand_insv (rtx *operands)
mask = 1 << INTVAL (operands[2]);
op0 = operands[0];
- if (GET_CODE (op0) == SUBREG
+ if (SUBREG_P (op0)
&& SUBREG_BYTE (op0) == 0)
{
rtx sub = SUBREG_REG (op0);
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 13e5675040e..044718fdc69 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -1064,9 +1064,9 @@ gen_split_move_double (rtx operands[])
/* We might have (SUBREG (MEM)) here, so just get rid of the
subregs to make this code simpler. It is safe to call
alter_subreg any time after reload. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
alter_subreg (&dest, true);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
alter_subreg (&src, true);
start_sequence ();
@@ -2462,13 +2462,13 @@ m32r_not_same_reg (rtx a, rtx b)
int reg_a = -1;
int reg_b = -2;
- while (GET_CODE (a) == SUBREG)
+ while (SUBREG_P (a))
a = SUBREG_REG (a);
if (REG_P (a))
reg_a = REGNO (a);
- while (GET_CODE (b) == SUBREG)
+ while (SUBREG_P (b))
b = SUBREG_REG (b);
if (REG_P (b))
diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md
index e944363fd9b..3e191012659 100644
--- a/gcc/config/m32r/m32r.md
+++ b/gcc/config/m32r/m32r.md
@@ -366,7 +366,7 @@
"register_operand (operands[0], SImode) || register_operand (operands[1], SImode)"
"*
{
- if (REG_P (operands[0]) || GET_CODE (operands[1]) == SUBREG)
+ if (REG_P (operands[0]) || SUBREG_P (operands[1]))
{
switch (GET_CODE (operands[1]))
{
@@ -407,7 +407,7 @@
}
else if (MEM_P (operands[0])
- && (REG_P (operands[1]) || GET_CODE (operands[1]) == SUBREG))
+ && (REG_P (operands[1]) || SUBREG_P (operands[1])))
{
if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md
index a469c976bc3..1d7e195f5bd 100644
--- a/gcc/config/m32r/predicates.md
+++ b/gcc/config/m32r/predicates.md
@@ -22,7 +22,7 @@
(define_predicate "reg_or_zero_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
@@ -277,7 +277,7 @@
(define_predicate "reg_or_int16_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
return 0;
@@ -289,7 +289,7 @@
(define_predicate "reg_or_uint16_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
return 0;
@@ -302,7 +302,7 @@
(define_predicate "reg_or_cmp_int16_operand"
(match_code "reg,subreg,const_int")
{
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
return 0;
@@ -319,7 +319,7 @@
{
HOST_WIDE_INT value;
- if (REG_P (op) || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || SUBREG_P (op))
return register_operand (op, mode);
if (!CONST_INT_P (op))
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 5c02c6eb3df..0fb4b059daa 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1863,7 +1863,7 @@ bool
m68k_legitimate_base_reg_p (rtx x, bool strict_p)
{
/* Allow SUBREG everywhere we allow REG. This results in better code. */
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -1878,7 +1878,7 @@ m68k_legitimate_base_reg_p (rtx x, bool strict_p)
bool
m68k_legitimate_index_reg_p (rtx x, bool strict_p)
{
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -3685,7 +3685,7 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == SUBREG
+ && reload_in_progress && SUBREG_P (operand0)
&& REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
@@ -3702,7 +3702,7 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == SUBREG
+ && reload_in_progress && SUBREG_P (operand1)
&& REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
@@ -3728,12 +3728,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
if (fp_reg_operand (operand0, mode)
&& ((GET_CODE (operand1) == MEM
&& ! memory_address_p (DFmode, XEXP (operand1, 0)))
- || ((GET_CODE (operand1) == SUBREG
+ || ((SUBREG_P (operand1)
&& GET_CODE (XEXP (operand1, 0)) == MEM
&& !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0)))))
&& scratch_reg)
{
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
operand1 = XEXP (operand1, 0);
/* SCRATCH_REG will hold an address. We want
@@ -3759,12 +3759,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
else if (fp_reg_operand (operand1, mode)
&& ((GET_CODE (operand0) == MEM
&& ! memory_address_p (DFmode, XEXP (operand0, 0)))
- || ((GET_CODE (operand0) == SUBREG)
+ || ((SUBREG_P (operand0))
&& GET_CODE (XEXP (operand0, 0)) == MEM
&& !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0))))
&& scratch_reg)
{
- if (GET_CODE (operand0) == SUBREG)
+ if (SUBREG_P (operand0))
operand0 = XEXP (operand0, 0);
/* SCRATCH_REG will hold an address and maybe the actual data. We want
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index d4f417a16e9..4df4551fd95 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -929,7 +929,7 @@ mcore_is_dead (rtx_insn *first, rtx reg)
rtx_insn *insn;
/* For mcore, subregs can't live independently of their parent regs. */
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
/* Dies immediately. */
@@ -2292,14 +2292,14 @@ is_cond_candidate (rtx insn)
dst = XEXP (pat, 0);
if ((!REG_P (dst) &&
- GET_CODE (dst) != SUBREG) ||
+ !SUBREG_P (dst)) ||
GET_MODE (dst) != SImode)
return COND_NO;
src = XEXP (pat, 1);
if ((REG_P (src) ||
- (GET_CODE (src) == SUBREG &&
+ (SUBREG_P (src) &&
REG_P (SUBREG_REG (src)))) &&
GET_MODE (src) == SImode)
return COND_MOV_INSN;
@@ -2308,7 +2308,7 @@ is_cond_candidate (rtx insn)
return COND_CLR_INSN;
else if (GET_CODE (src) == PLUS &&
(REG_P (XEXP (src, 0)) ||
- (GET_CODE (XEXP (src, 0)) == SUBREG &&
+ (SUBREG_P (XEXP (src, 0)) &&
REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode &&
CONST_INT_P (XEXP (src, 1)) &&
@@ -2321,7 +2321,7 @@ is_cond_candidate (rtx insn)
CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == -1)) &&
(REG_P (XEXP (src, 0)) ||
- (GET_CODE (XEXP (src, 0)) == SUBREG &&
+ (SUBREG_P (XEXP (src, 0)) &&
REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode)
return COND_DEC_INSN;
@@ -2684,10 +2684,10 @@ int
mcore_is_same_reg (rtx x, rtx y)
{
/* Strip any and all of the subreg wrappers. */
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
x = SUBREG_REG (x);
- while (GET_CODE (y) == SUBREG)
+ while (SUBREG_P (y))
y = SUBREG_REG (y);
if (REG_P (x) && REG_P (y) && REGNO(x) == REGNO(y))
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index 755a322139c..c71cb67fdb6 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -96,7 +96,7 @@
(ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
(const_int 7))
(const_int 0)))]
- "GET_CODE(operands[0]) == SUBREG &&
+ "SUBREG_P (operands[0]) &&
GET_MODE(SUBREG_REG(operands[0])) == QImode"
"btsti %0,7"
[(set_attr "type" "shift")])
@@ -106,7 +106,7 @@
(ne:CC (lshiftrt:SI (match_operand:SI 0 "mcore_arith_reg_operand" "r")
(const_int 15))
(const_int 0)))]
- "GET_CODE(operands[0]) == SUBREG &&
+ "SUBREG_P (operands[0]) &&
GET_MODE(SUBREG_REG(operands[0])) == HImode"
"btsti %0,15"
[(set_attr "type" "shift")])
@@ -1937,7 +1937,7 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
(match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
- "GET_CODE (operands[1]) == SUBREG &&
+ "SUBREG_P (operands[1]) &&
GET_MODE (SUBREG_REG (operands[1])) == QImode"
"@
btsti %1,7\;movf %0,%2
@@ -2024,7 +2024,7 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_imm_operand" "r,0,U,0")
(match_operand:SI 3 "mcore_arith_imm_operand" "0,r,0,U")))]
- "GET_CODE (operands[1]) == SUBREG &&
+ "SUBREG_P (operands[1]) &&
GET_MODE (SUBREG_REG (operands[1])) == QImode"
"@
btsti %1,7\;movt %0,%2
@@ -2704,7 +2704,7 @@
(set (match_operand:SI 2 "mcore_arith_reg_operand" "")
(and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
(match_dup 0)))]
- "GET_CODE (operands[3]) == SUBREG &&
+ "SUBREG_P (operands[3]) &&
GET_MODE (SUBREG_REG (operands[3])) == QImode &&
mcore_num_zeros (INTVAL (operands[1]) | 0xffffff00) == 1 &&
mcore_is_dead (insn, operands[0])"
@@ -2721,7 +2721,7 @@
(set (match_operand:SI 2 "mcore_arith_reg_operand" "")
(and:SI (match_operand:SI 3 "mcore_arith_reg_operand" "")
(match_dup 0)))]
- "GET_CODE (operands[3]) == SUBREG &&
+ "SUBREG_P (operands[3]) &&
GET_MODE (SUBREG_REG (operands[3])) == HImode &&
mcore_num_zeros (INTVAL (operands[1]) | 0xffff0000) == 1 &&
operands[2] == operands[3] &&
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index c29792cc520..5bc901e55ea 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -25,7 +25,7 @@
if (! register_operand (op, mode))
return 0;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op))
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index f9c2adf9ab7..800baefc070 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -406,7 +406,7 @@ microblaze_valid_base_register_p (rtx x,
machine_mode mode ATTRIBUTE_UNUSED,
int strict)
{
- if (!strict && GET_CODE (x) == SUBREG)
+ if (!strict && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -671,7 +671,7 @@ microblaze_valid_index_register_p (rtx x,
machine_mode mode ATTRIBUTE_UNUSED,
int strict)
{
- if (!strict && GET_CODE (x) == SUBREG)
+ if (!strict && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -3473,7 +3473,7 @@ microblaze_expand_shift (rtx operands[])
{
gcc_assert ((CONST_INT_P (operands[2]))
|| (REG_P (operands[2]))
- || (GET_CODE (operands[2]) == SUBREG));
+ || (SUBREG_P (operands[2])));
/* Shift by one -- generate pattern. */
if ((CONST_INT_P (operands[2])) && (INTVAL (operands[2]) == 1))
@@ -3484,9 +3484,9 @@ microblaze_expand_shift (rtx operands[])
return 0;
gcc_assert ((REG_P (operands[0]))
- || (GET_CODE (operands[0]) == SUBREG)
+ || (SUBREG_P (operands[0]))
|| (REG_P (operands[1]))
- || (GET_CODE (operands[1]) == SUBREG));
+ || (SUBREG_P (operands[1])));
/* Shift by zero -- copy regs if necessary. */
if (operands[2] == const0_rtx
@@ -3594,7 +3594,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
rtx comp_reg = gen_reg_rtx (SImode);
rtx condition;
- gcc_assert ((REG_P (cmp_op0)) || (GET_CODE (cmp_op0) == SUBREG));
+ gcc_assert ((REG_P (cmp_op0)) || (SUBREG_P (cmp_op0)));
/* If comparing against zero, just test source reg. */
if (cmp_op1 == const0_rtx)
@@ -3631,7 +3631,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
rtx condition;
gcc_assert ((REG_P (cmp_op0))
- || (GET_CODE (cmp_op0) == SUBREG));
+ || (SUBREG_P (cmp_op0)));
/* If comparing against zero, just test source reg. */
if (cmp_op1 == const0_rtx)
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index e72e0d57a97..4730c75ec5f 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -2480,7 +2480,7 @@ mips_regno_mode_ok_for_base_p (int regno, machine_mode mode,
static bool
mips_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
{
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -4480,7 +4480,7 @@ mips_rtx_costs (rtx x, machine_mode mode, int outer_code,
if (outer_code == SET
&& ISA_HAS_BADDU
&& (GET_CODE (XEXP (x, 0)) == TRUNCATE
- || GET_CODE (XEXP (x, 0)) == SUBREG)
+ || SUBREG_P (XEXP (x, 0)))
&& GET_MODE (XEXP (x, 0)) == QImode
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == PLUS)
{
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 8fdd1c5adf6..5d5bc734898 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -1335,7 +1335,7 @@ mn10300_preferred_reload_class (rtx x, reg_class_t rclass)
else if (MEM_P (x)
|| (REG_P (x)
&& !HARD_REGISTER_P (x))
- || (GET_CODE (x) == SUBREG
+ || (SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& !HARD_REGISTER_P (SUBREG_REG (x))))
return LIMIT_RELOAD_CLASS (GET_MODE (x), rclass);
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index b36c8f5e38d..6a75b967a27 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -510,7 +510,7 @@ struct cum_arg
#define RTX_OK_FOR_BASE_P(X, strict) \
((REG_P (X) && REGNO_STRICT_OK_FOR_BASE_P (REGNO (X), \
(strict))) \
- || (GET_CODE (X) == SUBREG && REG_P (SUBREG_REG (X)) \
+ || (SUBREG_P (X) && REG_P (SUBREG_REG (X)) \
&& REGNO_STRICT_OK_FOR_BASE_P (REGNO (SUBREG_REG (X)), \
(strict))))
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index d28023b339f..40796b45883 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3180,7 +3180,7 @@ msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
{
rtx rv;
- if (GET_CODE (r) == SUBREG
+ if (SUBREG_P (r)
&& SUBREG_BYTE (r) == 0)
{
rtx ireg = SUBREG_REG (r);
diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index b516ec15462..e2aef5bd636 100644
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -756,7 +756,7 @@
(match_operand:HI 2 "general_operand")))]
""
{
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& REG_P (XEXP (operands[1], 0)))
|| MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
@@ -844,7 +844,7 @@
(match_operand:HI 2 "general_operand")))]
""
{
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& REG_P (XEXP (operands[1], 0)))
|| MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
@@ -945,7 +945,7 @@
(match_operand:HI 2 "general_operand")))]
""
{
- if ((GET_CODE (operands[1]) == SUBREG
+ if ((SUBREG_P (operands[1])
&& REG_P (XEXP (operands[1], 0)))
|| MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c
index 09ad3d59af3..f205bcdff43 100644
--- a/gcc/config/nds32/nds32-pipelines-auxiliary.c
+++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c
@@ -248,7 +248,7 @@ extract_nth_ls2_access_reg (rtx_insn *insn, int n)
gcc_unreachable ();
}
- gcc_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
+ gcc_assert (REG_P (reg) || SUBREG_P (reg));
switch (GET_MODE (reg))
{
@@ -332,7 +332,7 @@ movd44_even_dep_p (rtx_insn *insn, rtx def_reg)
{
return rtx_equal_p (def_reg, use_rtx);
}
- else if (GET_CODE (def_reg) == SUBREG
+ else if (SUBREG_P (def_reg)
&& GET_MODE (def_reg) == SImode
&& rtx_equal_p (SUBREG_REG (def_reg), use_rtx))
{
@@ -362,8 +362,8 @@ wext_odd_dep_p (rtx insn, rtx def_reg)
if (GET_MODE (def_reg) == DImode)
return reg_overlap_p (def_reg, use_reg);
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
- gcc_assert (REG_P (use_reg) || GET_CODE (use_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
+ gcc_assert (REG_P (use_reg) || SUBREG_P (use_reg));
if (REG_P (def_reg))
{
@@ -378,12 +378,12 @@ wext_odd_dep_p (rtx insn, rtx def_reg)
return true;
}
- if (GET_CODE (def_reg) == SUBREG)
+ if (SUBREG_P (def_reg))
{
if (!reg_overlap_p (def_reg, use_reg))
return false;
- if (GET_CODE (use_reg) == SUBREG)
+ if (SUBREG_P (use_reg))
return true;
if (!TARGET_BIG_ENDIAN)
@@ -1200,7 +1200,7 @@ nds32_n7_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return n7_consumed_by_ii_dep_p (consumer, last_def_reg);
}
@@ -1298,7 +1298,7 @@ nds32_n8_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return n8_consumed_by_addr_in_p (consumer, last_def_reg);
}
@@ -1320,7 +1320,7 @@ nds32_n8_last_load_two_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
return false;
gcc_assert (REG_P (last_two_def_reg)
- || GET_CODE (last_two_def_reg) == SUBREG);
+ || SUBREG_P (last_two_def_reg));
return n8_consumed_by_addr_in_p (consumer, last_two_def_reg);
}
@@ -1340,7 +1340,7 @@ nds32_n8_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return n8_consumed_by_ex_p (consumer, last_def_reg);
}
@@ -1377,7 +1377,7 @@ nds32_e8_ex_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
rtx dest = SET_DEST (PATTERN (producer));
rtx src = SET_SRC (PATTERN (producer));
- if ((REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if ((REG_P (dest) || SUBREG_P (dest))
&& (CONST_INT_P (src) || GET_CODE (src) == HIGH))
return false;
}
@@ -1428,7 +1428,7 @@ nds32_e8_last_load_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return e8_consumed_by_addr_in_p (consumer, last_def_reg);
}
@@ -1441,7 +1441,7 @@ nds32_e8_last_load_to_ex_p (rtx_insn *producer, rtx_insn *consumer)
if (last_def_reg == NULL_RTX)
return false;
- gcc_assert (REG_P (last_def_reg) || GET_CODE (last_def_reg) == SUBREG);
+ gcc_assert (REG_P (last_def_reg) || SUBREG_P (last_def_reg));
return e8_consumed_by_ex_p (consumer, last_def_reg);
}
@@ -1747,7 +1747,7 @@ nds32_n13_load_to_e1_p (rtx_insn *producer, rtx_insn *consumer)
rtx def_reg = SET_DEST (PATTERN (producer));
gcc_assert (get_attr_type (producer) == TYPE_LOAD);
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
return n13_consumed_by_e1_dep_p (consumer, def_reg);
}
@@ -1759,7 +1759,7 @@ nds32_n13_load_to_e2_p (rtx_insn *producer, rtx_insn *consumer)
rtx def_reg = SET_DEST (PATTERN (producer));
gcc_assert (get_attr_type (producer) == TYPE_LOAD);
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
return n13_consumed_by_e2_dep_p (consumer, def_reg);
}
diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c
index 96ee791de54..327636bbd55 100644
--- a/gcc/config/nds32/nds32-utils.c
+++ b/gcc/config/nds32/nds32-utils.c
@@ -476,8 +476,8 @@ movd44_insn_p (rtx_insn *insn)
rtx src = SET_SRC (body);
rtx dest = SET_DEST (body);
- if ((REG_P (src) || GET_CODE (src) == SUBREG)
- && (REG_P (dest) || GET_CODE (dest) == SUBREG))
+ if ((REG_P (src) || SUBREG_P (src))
+ && (REG_P (dest) || SUBREG_P (dest)))
return true;
return false;
@@ -495,7 +495,7 @@ extract_movd44_odd_reg (rtx_insn *insn)
rtx def_reg = SET_DEST (PATTERN (insn));
machine_mode mode;
- gcc_assert (REG_P (def_reg) || GET_CODE (def_reg) == SUBREG);
+ gcc_assert (REG_P (def_reg) || SUBREG_P (def_reg));
switch (GET_MODE (def_reg))
{
case E_DImode:
diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md
index 1e5f8decada..68ad1029387 100644
--- a/gcc/config/nds32/nds32.md
+++ b/gcc/config/nds32/nds32.md
@@ -216,7 +216,7 @@
DONE;
}
- if ((REG_P (operands[0]) || GET_CODE (operands[0]) == SUBREG)
+ if ((REG_P (operands[0]) || SUBREG_P (operands[0]))
&& SYMBOLIC_CONST_P (operands[1]))
{
if (TARGET_ICT_MODEL_LARGE
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md
index 9983eb4c409..6049c5c1b15 100644
--- a/gcc/config/nds32/predicates.md
+++ b/gcc/config/nds32/predicates.md
@@ -141,7 +141,7 @@
(match_operand 0 "nds32_reg_constant_operand")
{
return REG_P (op)
- || GET_CODE (op) == SUBREG
+ || SUBREG_P (op)
|| satisfies_constraint_Izeb (op)
|| satisfies_constraint_Izeh (op)
|| satisfies_constraint_Ixls (op)
@@ -157,7 +157,7 @@
(match_operand 0 "nds32_reg_constant_operand")
{
return REG_P (op)
- || GET_CODE (op) == SUBREG
+ || SUBREG_P (op)
|| satisfies_constraint_Iu15 (op)
|| satisfies_constraint_Ie15 (op);
})
@@ -166,7 +166,7 @@
(match_operand 0 "nds32_reg_constant_operand")
{
return REG_P (op)
- || GET_CODE (op) == SUBREG
+ || SUBREG_P (op)
|| satisfies_constraint_Iu15 (op)
|| satisfies_constraint_It15 (op);
})
@@ -174,7 +174,7 @@
(define_predicate "nds32_general_register_operand"
(match_code "reg,subreg")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return (REG_P (op)
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 6893ebb1528..74c80bbd1e3 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -2133,7 +2133,7 @@ nios2_valid_addr_offset_p (rtx offset)
static bool
nios2_valid_addr_expr_p (rtx base, rtx offset, bool strict_p)
{
- if (!strict_p && GET_CODE (base) == SUBREG)
+ if (!strict_p && SUBREG_P (base))
base = SUBREG_REG (base);
return (REG_P (base)
&& nios2_regno_ok_for_base_p (REGNO (base), strict_p)
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 3107ea58818..39050c5e492 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -2308,9 +2308,9 @@ const char *
nvptx_output_mov_insn (rtx dst, rtx src)
{
machine_mode dst_mode = GET_MODE (dst);
- machine_mode dst_inner = (GET_CODE (dst) == SUBREG
+ machine_mode dst_inner = (SUBREG_P (dst)
? GET_MODE (XEXP (dst, 0)) : dst_mode);
- machine_mode src_inner = (GET_CODE (src) == SUBREG
+ machine_mode src_inner = (SUBREG_P (src)
? GET_MODE (XEXP (src, 0)) : dst_mode);
rtx sym = src;
@@ -2825,7 +2825,7 @@ nvptx_reorg_subreg (void)
for (int i = 0; i < recog_data.n_operands; i++)
{
rtx op = recog_data.operand[i];
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
continue;
rtx inner = SUBREG_REG (op);
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 6795fc393fd..cdd2e031bf7 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1169,7 +1169,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (x) == PLUS
&& mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
&& (OBJECT_P (XEXP (x, 1))
- || GET_CODE (XEXP (x, 1)) == SUBREG)
+ || SUBREG_P (XEXP (x, 1)))
&& GET_CODE (XEXP (x, 1)) != CONST)
{
/* If we were given a MULT, we must fix the constant
@@ -1670,7 +1670,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == SUBREG
+ && reload_in_progress && SUBREG_P (operand0)
&& REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
@@ -1687,7 +1687,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == SUBREG
+ && reload_in_progress && SUBREG_P (operand1)
&& REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
@@ -1716,12 +1716,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
if (scratch_reg
&& FP_REG_P (operand0)
&& (MEM_P (operand1)
- || (GET_CODE (operand1) == SUBREG
+ || (SUBREG_P (operand1)
&& MEM_P (XEXP (operand1, 0)))))
{
rtx op1 = operand1;
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
if (reg_plus_base_memory_operand (op1, GET_MODE (op1)))
@@ -1767,12 +1767,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
else if (scratch_reg
&& FP_REG_P (operand1)
&& (MEM_P (operand0)
- || (GET_CODE (operand0) == SUBREG
+ || (SUBREG_P (operand0)
&& MEM_P (XEXP (operand0, 0)))))
{
rtx op0 = operand0;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = XEXP (op0, 0);
if (reg_plus_base_memory_operand (op0, GET_MODE (op0)))
@@ -6110,7 +6110,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
/* Profiling showed the PA port spends about 1.3% of its compilation
time in true_regnum from calls inside pa_secondary_reload_class. */
- if (regno >= FIRST_PSEUDO_REGISTER || GET_CODE (x) == SUBREG)
+ if (regno >= FIRST_PSEUDO_REGISTER || SUBREG_P (x))
regno = true_regnum (x);
/* Handle reloads for floating point loads and stores. */
@@ -10546,7 +10546,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
{
rtx y = XEXP (x, 0);
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
y = SUBREG_REG (y);
if (REG_P (y)
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 903fa82b858..5fd0279c9fa 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -224,7 +224,7 @@
return false;
/* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
- if (reload_completed && GET_CODE (op) == SUBREG)
+ if (reload_completed && SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -243,7 +243,7 @@
return false;
/* Before reload, a (SUBREG (MEM...)) forces reloading into a register. */
- if (reload_completed && GET_CODE (op) == SUBREG)
+ if (reload_completed && SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -308,7 +308,7 @@
return true;
/* Extract CONST_INT operand. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
op = XEXP (op, 0);
op = REG_P (XEXP (op, 0)) ? XEXP (op, 1) : XEXP (op, 0);
@@ -345,7 +345,7 @@
return true;
/* Extract CONST_INT operand. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
op = XEXP (op, 0);
op = REG_P (XEXP (op, 0)) ? XEXP (op, 1) : XEXP (op, 0);
@@ -409,7 +409,7 @@
if (GET_MODE (op) != mode)
return false;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -440,7 +440,7 @@
if (GET_MODE (op) != mode)
return false;
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -464,7 +464,7 @@
(define_predicate "nonsymb_mem_operand"
(match_code "subreg,mem")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (! MEM_P (op))
@@ -603,7 +603,7 @@
(define_predicate "symbolic_memory_operand"
(match_code "subreg,mem")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (!MEM_P (op))
return false;
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index a14c77373fc..eae67483f63 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -70,7 +70,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 0;
@@ -90,7 +90,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 0;
@@ -110,7 +110,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 0;
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index 971428e65bc..ead4c3b320f 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -1410,9 +1410,9 @@ pru_get_ctable_base_offset (unsigned HOST_WIDE_INT caddr)
static bool
pru_valid_addr_expr_p (machine_mode mode, rtx base, rtx offset, bool strict_p)
{
- if (!strict_p && GET_CODE (base) == SUBREG)
+ if (!strict_p && SUBREG_P (base))
base = SUBREG_REG (base);
- if (!strict_p && GET_CODE (offset) == SUBREG)
+ if (!strict_p && SUBREG_P (offset))
offset = SUBREG_REG (offset);
if (REG_P (base)
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index ca868a2ddca..c03f5b1e66c 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -689,7 +689,7 @@ riscv_regno_mode_ok_for_base_p (int regno,
static bool
riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p)
{
- if (!strict_p && GET_CODE (x) == SUBREG)
+ if (!strict_p && SUBREG_P (x))
x = SUBREG_REG (x);
return (REG_P (x)
@@ -2121,11 +2121,11 @@ riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1)
is a constant or has already been sign-extended also. */
if (unsigned_condition (code) == code
&& (GET_MODE (*op0) == QImode
- && ! (GET_CODE (*op0) == SUBREG
+ && ! (SUBREG_P (*op0)
&& SUBREG_PROMOTED_VAR_P (*op0)
&& SUBREG_PROMOTED_SIGNED_P (*op0)
&& (CONST_INT_P (*op1)
- || (GET_CODE (*op1) == SUBREG
+ || (SUBREG_P (*op1)
&& SUBREG_PROMOTED_VAR_P (*op1)
&& SUBREG_PROMOTED_SIGNED_P (*op1))))))
{
diff --git a/gcc/config/rl78/rl78-expand.md b/gcc/config/rl78/rl78-expand.md
index 4b76101c1cb..3706a8c01f6 100644
--- a/gcc/config/rl78/rl78-expand.md
+++ b/gcc/config/rl78/rl78-expand.md
@@ -34,14 +34,14 @@
into a bitfield, or a packed ordinary field. We can handle this
provided that the destination is a register. If not, then load the
source into a register first. */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
&& ! REG_P (operands[0]))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
/* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))).
cf. g++.dg/abi/packed.C. */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == CONST
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
&& GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF
@@ -65,11 +65,11 @@
/* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)),
but it does. Since this makes no sense, reject it here. */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
FAIL;
/* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). */
- if (GET_CODE (operands[1]) == SUBREG
+ if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == CONST
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
&& GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF)
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index f3f7ecb4b22..779c94e038f 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -951,7 +951,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
*base = XEXP (x, 0);
x = XEXP (x, 1);
- if (GET_CODE (*base) == SUBREG)
+ if (SUBREG_P (*base))
{
if (GET_MODE (*base) == HImode
&& GET_MODE (XEXP (*base, 0)) == SImode
diff --git a/gcc/config/rl78/rl78.h b/gcc/config/rl78/rl78.h
index a04f7b3fe0e..341e5404ad2 100644
--- a/gcc/config/rl78/rl78.h
+++ b/gcc/config/rl78/rl78.h
@@ -454,7 +454,7 @@ typedef unsigned int CUMULATIVE_ARGS;
#define JUMP_TABLES_IN_TEXT_SECTION (flag_pic)
\f
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
-#define RL78_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
+#define RL78_REG_P(rtl) (REG_P (rtl) || SUBREG_P (rtl))
/* Like REG_P except that this macro is true for SET expressions. */
#define SET_P(rtl) (GET_CODE (rtl) == SET)
diff --git a/gcc/config/rx/rx.h b/gcc/config/rx/rx.h
index 672e087cd13..9846ad017c5 100644
--- a/gcc/config/rx/rx.h
+++ b/gcc/config/rx/rx.h
@@ -294,12 +294,12 @@ enum reg_class
((STRICT) ? \
( (REG_P (X) \
&& REGNO_IN_RANGE (REGNO (X), 0, 15)) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X)) \
&& REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \
: \
( (REG_P (X) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X))))))
\f
@@ -615,7 +615,7 @@ typedef unsigned int CUMULATIVE_ARGS;
#define JUMP_TABLES_IN_TEXT_SECTION (TARGET_PID || flag_pic)
\f
/* This is a version of REG_P that also returns TRUE for SUBREGs. */
-#define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG)
+#define RX_REG_P(rtl) (REG_P (rtl) || SUBREG_P (rtl))
/* Like REG_P except that this macro is true for SET expressions. */
#define SET_P(rtl) (GET_CODE (rtl) == SET)
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index aec2de30219..b05e8ed6ed0 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -65,7 +65,7 @@
/* Just like memory_operand, allow (subreg (mem ...))
after reload. */
if (reload_completed
- && GET_CODE (op) == SUBREG
+ && SUBREG_P (op)
&& GET_CODE (SUBREG_REG (op)) == MEM)
op = SUBREG_REG (op);
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index a61c7d5ed79..d38cf3aad12 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1647,7 +1647,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
rtx mask = XEXP (*op0, 1);
/* Ignore paradoxical SUBREGs if all extra bits are masked out. */
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (inner)))
&& (GET_MODE_SIZE (GET_MODE (inner))
>= GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
@@ -2666,7 +2666,7 @@ s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
/* Widen operands if required. */
if (mode != wmode)
{
- if (GET_CODE (dst) == SUBREG
+ if (SUBREG_P (dst)
&& (tem = simplify_subreg (wmode, dst, mode, 0)) != 0)
dst = tem;
else if (REG_P (dst))
@@ -2674,13 +2674,13 @@ s390_expand_logical_operator (enum rtx_code code, machine_mode mode,
else
dst = gen_reg_rtx (wmode);
- if (GET_CODE (src1) == SUBREG
+ if (SUBREG_P (src1)
&& (tem = simplify_subreg (wmode, src1, mode, 0)) != 0)
src1 = tem;
else if (GET_MODE (src1) != VOIDmode)
src1 = gen_rtx_SUBREG (wmode, force_reg (mode, src1), 0);
- if (GET_CODE (src2) == SUBREG
+ if (SUBREG_P (src2)
&& (tem = simplify_subreg (wmode, src2, mode, 0)) != 0)
src2 = tem;
else if (GET_MODE (src2) != VOIDmode)
@@ -3116,7 +3116,7 @@ s390_decompose_addrstyle_without_index (rtx op, rtx *base,
off = XEXP (op, 1);
op = XEXP (op, 0);
}
- while (op && GET_CODE (op) == SUBREG)
+ while (op && SUBREG_P (op))
op = SUBREG_REG (op);
if (op && !REG_P (op))
@@ -3155,7 +3155,7 @@ bool
s390_valid_shift_count (rtx op, HOST_WIDE_INT implicit_mask)
{
/* Strip subreg. */
- while (GET_CODE (op) == SUBREG && subreg_lowpart_p (op))
+ while (SUBREG_P (op) && subreg_lowpart_p (op))
op = XEXP (op, 0);
/* Check for an and with proper constant. */
@@ -3164,7 +3164,7 @@ s390_valid_shift_count (rtx op, HOST_WIDE_INT implicit_mask)
rtx op1 = XEXP (op, 0);
rtx imm = XEXP (op, 1);
- if (GET_CODE (op1) == SUBREG && subreg_lowpart_p (op1))
+ if (SUBREG_P (op1) && subreg_lowpart_p (op1))
op1 = XEXP (op1, 0);
if (!(register_operand (op1, GET_MODE (op1)) || GET_CODE (op1) == PLUS))
@@ -7513,7 +7513,7 @@ print_shift_count_operand (FILE *file, rtx op)
if (!s390_valid_shift_count (op, 0))
gcc_unreachable ();
- while (op && GET_CODE (op) == SUBREG)
+ while (op && SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == AND)
@@ -8208,7 +8208,7 @@ addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
target = SET_DEST (dep_rtx);
if (GET_CODE (target) == STRICT_LOW_PART)
target = XEXP (target, 0);
- while (GET_CODE (target) == SUBREG)
+ while (SUBREG_P (target))
target = SUBREG_REG (target);
if (REG_P (target))
@@ -9379,7 +9379,7 @@ s390_reg_clobbered_rtx (rtx setreg, const_rtx set_insn ATTRIBUTE_UNUSED, void *d
unsigned int i, regno;
machine_mode mode = GET_MODE (setreg);
- if (GET_CODE (setreg) == SUBREG)
+ if (SUBREG_P (setreg))
{
rtx inner = SUBREG_REG (setreg);
if (!GENERAL_REG_P (inner) && !FP_REG_P (inner))
diff --git a/gcc/config/sh/predicates.md b/gcc/config/sh/predicates.md
index c22f3e2e31e..4b19143d90e 100644
--- a/gcc/config/sh/predicates.md
+++ b/gcc/config/sh/predicates.md
@@ -28,7 +28,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 1;
@@ -49,11 +49,11 @@
return register_operand (XEXP (op, 0), VOIDmode);
#endif
if (GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_INT
- && GET_CODE (op) == SUBREG
+ && SUBREG_P (op)
&& GET_MODE (SUBREG_REG (op)) == DImode
&& GET_CODE (SUBREG_REG (op)) == SIGN_EXTEND
&& GET_MODE (XEXP (SUBREG_REG (op), 0)) == SImode
- && GET_CODE (XEXP (SUBREG_REG (op), 0)) != SUBREG)
+ && !SUBREG_P (XEXP (SUBREG_REG (op), 0)))
return register_operand (XEXP (SUBREG_REG (op), 0), VOIDmode);
return 0;
})
@@ -121,7 +121,7 @@
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
regno = REGNO (SUBREG_REG (op));
else
return 1;
@@ -199,7 +199,7 @@
if (reload_completed && GET_CODE (op) == TRUNCATE)
return arith_operand (op, mode);
- if (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))))
+ if (MEM_P (op) || (SUBREG_P (op) && MEM_P (SUBREG_REG (op))))
return general_movsrc_operand (op, mode);
return nonimmediate_operand (op, mode);
@@ -300,7 +300,7 @@
}
if (mode == GET_MODE (op)
- && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
+ && (MEM_P (op) || (SUBREG_P (op) && MEM_P (SUBREG_REG (op)))))
{
rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
rtx x = XEXP (mem_rtx, 0);
@@ -310,11 +310,11 @@
rtx y = XEXP (x, 0);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y))))
return false;
y = XEXP (x, 1);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y)))
&& ! CONST_INT_P (y))
return false;
}
@@ -385,7 +385,7 @@
return 0;
if (mode == GET_MODE (op)
- && (MEM_P (op) || (GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))))
+ && (MEM_P (op) || (SUBREG_P (op) && MEM_P (SUBREG_REG (op)))))
{
rtx mem_rtx = MEM_P (op) ? op : SUBREG_REG (op);
rtx x = XEXP (mem_rtx, 0);
@@ -395,11 +395,11 @@
rtx y = XEXP (x, 0);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y))))
return false;
y = XEXP (x, 1);
if (! REG_P (y)
- && ! (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))
+ && ! (SUBREG_P (y) && REG_P (SUBREG_REG (y)))
&& ! CONST_INT_P (y))
return false;
}
@@ -658,7 +658,7 @@
case SIGN_EXTEND:
if (REG_P (XEXP (op, 0)) && REGNO (XEXP (op, 0)) == T_REG)
return true;
- return GET_CODE (XEXP (op, 0)) == SUBREG
+ return SUBREG_P (XEXP (op, 0))
&& REG_P (SUBREG_REG (XEXP (op, 0)))
&& REGNO (SUBREG_REG (XEXP (op, 0))) == T_REG;
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 3e2ffcff0f1..1a2d110c2ae 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -1194,7 +1194,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
held in general purpose registers, that won't work with memory -
neither for fp registers, since the frxx names are used. */
case 'R':
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
{
regno = true_regnum (x);
regno += FP_REGISTER_P (regno) ? 1 : SH_REG_LSW_OFFSET;
@@ -1221,7 +1221,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
}
break;
case 'S':
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
{
regno = true_regnum (x);
regno += FP_REGISTER_P (regno) ? 0 : SH_REG_MSW_OFFSET;
@@ -1389,7 +1389,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
machine_mode inner_mode;
/* We might see SUBREGs with vector mode registers inside. */
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& (GET_MODE_SIZE (GET_MODE (inner))
== GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
&& subreg_lowpart_p (inner))
@@ -1400,7 +1400,7 @@ sh_print_operand (FILE *stream, rtx x, int code)
goto default_output;
}
inner_mode = GET_MODE (inner);
- if (GET_CODE (inner) == SUBREG
+ if (SUBREG_P (inner)
&& (GET_MODE_SIZE (GET_MODE (inner))
< GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner))))
&& REG_P (SUBREG_REG (inner)))
@@ -3180,7 +3180,7 @@ addsubcosts (rtx x)
/* Adding a register is a single cycle insn. */
if (REG_P (XEXP (x, 1))
- || GET_CODE (XEXP (x, 1)) == SUBREG)
+ || SUBREG_P (XEXP (x, 1)))
return 1 * cost_scale;
/* Likewise for small constants. */
@@ -3711,7 +3711,7 @@ gen_ashift_hi (int type, int n, rtx reg)
sign extension works out correctly. */
{
int offset = 0;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
offset = SUBREG_BYTE (reg);
reg = SUBREG_REG (reg);
@@ -6208,7 +6208,7 @@ sh_reorg (void)
int offset = 0;
mode = HImode;
- while (GET_CODE (dst) == SUBREG)
+ while (SUBREG_P (dst))
{
offset += subreg_regno_offset (REGNO (SUBREG_REG (dst)),
GET_MODE (SUBREG_REG (dst)),
@@ -11391,7 +11391,7 @@ sh_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
and that has to be added to the final address. At this point we don't
know the cumulative displacement so we assume the worst case. */
if ((mode == QImode || mode == HImode) && rclass != R0_REGS
- && GET_CODE (x) == SUBREG && true_regnum (x) == -1)
+ && SUBREG_P (x) && true_regnum (x) == -1)
return R0_REGS;
return NO_REGS;
@@ -11940,7 +11940,7 @@ sh_try_omit_signzero_extend (rtx extended_op, rtx_insn* insn)
{
if (REG_P (extended_op))
extended_op = extended_op;
- else if (GET_CODE (extended_op) == SUBREG && REG_P (SUBREG_REG (extended_op)))
+ else if (SUBREG_P (extended_op) && REG_P (SUBREG_REG (extended_op)))
extended_op = SUBREG_REG (extended_op);
else
return NULL_RTX;
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 37bfc02de98..f753c611aaf 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1421,7 +1421,7 @@ extern bool current_function_interrupt;
#define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \
((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X)) \
&& REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT)))
@@ -1430,7 +1430,7 @@ extern bool current_function_interrupt;
outside the class. */
#define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \
((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \
- || (GET_CODE (X) == SUBREG \
+ || (SUBREG_P (X) \
&& REG_P (SUBREG_REG (X)) \
&& SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT)))
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index ed70e344dfa..86a27e24788 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -5682,7 +5682,7 @@
mem = operands[1];
store_p = 0;
}
- if (GET_CODE (mem) == SUBREG && SUBREG_BYTE (mem) == 0)
+ if (SUBREG_P (mem) && SUBREG_BYTE (mem) == 0)
mem = SUBREG_REG (mem);
if (MEM_P (mem))
{
@@ -5695,7 +5695,7 @@
rtx reg0 = gen_rtx_REG (Pmode, 0);
rtx regop = operands[store_p], word0 ,word1;
- if (GET_CODE (regop) == SUBREG)
+ if (SUBREG_P (regop))
alter_subreg (®op, true);
if (REGNO (XEXP (addr, 0)) == REGNO (XEXP (addr, 1)))
offset = 2;
@@ -10781,7 +10781,7 @@
(match_operand:SF 2 "general_movsrc_operand" ""))]
"TARGET_SH1 && REGNO (operands[0]) == 0
&& ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& REGNO (SUBREG_REG (operands[2])) < 16))
&& reg_unused_after (operands[0], insn)"
"mov.l %2,@(%0,%1)")
@@ -10794,7 +10794,7 @@
(mem:SF (match_dup 0)))]
"TARGET_SH1 && REGNO (operands[0]) == 0
&& ((REG_P (operands[2]) && REGNO (operands[2]) < 16)
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& REGNO (SUBREG_REG (operands[2])) < 16))
&& reg_unused_after (operands[0], insn)"
"mov.l @(%0,%1),%2")
@@ -10807,7 +10807,7 @@
"TARGET_SH2E && REGNO (operands[0]) == 0
&& ((REG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
&& reg_unused_after (operands[0], insn)"
"fmov{.s|} %2,@(%0,%1)")
@@ -10821,7 +10821,7 @@
"TARGET_SH2E && REGNO (operands[0]) == 0
&& ((REG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (operands[2])))
- || (GET_CODE (operands[2]) == SUBREG
+ || (SUBREG_P (operands[2])
&& FP_OR_XD_REGISTER_P (REGNO (SUBREG_REG (operands[2])))))
&& reg_unused_after (operands[0], insn)"
"fmov{.s|} @(%0,%1),%2")
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 09c3312f955..d947736e933 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -222,7 +222,7 @@
(define_predicate "fp_register_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op); /* Possibly a MEM */
return REG_P (op) && SPARC_FP_REG_P (REGNO (op));
})
@@ -411,7 +411,7 @@
return true;
/* If this is a SUBREG, look inside so that we handle paradoxical ones. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
/* Check for valid MEM forms. */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index df371584f9e..523f2851d31 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2958,7 +2958,7 @@ sparc_emit_set_const64 (rtx op0, rtx op1)
/* Sanity check that we know what we are working with. */
gcc_assert (TARGET_ARCH64
- && (GET_CODE (op0) == SUBREG
+ && (SUBREG_P (op0)
|| (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0)))));
if (! can_create_pseudo_p ())
@@ -3490,8 +3490,8 @@ emit_scc_insn (rtx operands[])
back to the easy case. */
if (code == GTU || code == LEU)
{
- if ((REG_P (x) || GET_CODE (x) == SUBREG)
- && (REG_P (y) || GET_CODE (y) == SUBREG))
+ if ((REG_P (x) || SUBREG_P (x))
+ && (REG_P (y) || SUBREG_P (y)))
{
tem = x;
x = y;
@@ -4016,7 +4016,7 @@ eligible_for_restore_insn (rtx trial, bool return_p)
VIS3 is enabled, we have to catch this case. We can allow such
moves when doing a 'return' however. */
src_reg = src;
- if (GET_CODE (src_reg) == SUBREG)
+ if (SUBREG_P (src_reg))
src_reg = SUBREG_REG (src_reg);
if (REG_P (src_reg)
&& SPARC_FP_REG_P (REGNO (src_reg)))
@@ -4480,7 +4480,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
{
rtx rs1 = NULL, rs2 = NULL, imm1 = NULL;
- if (REG_P (addr) || GET_CODE (addr) == SUBREG)
+ if (REG_P (addr) || SUBREG_P (addr))
rs1 = addr;
else if (GET_CODE (addr) == PLUS)
{
@@ -4490,9 +4490,9 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
/* Canonicalize. REG comes first, if there are no regs,
LO_SUM comes first. */
if (!REG_P (rs1)
- && GET_CODE (rs1) != SUBREG
+ && !SUBREG_P (rs1)
&& (REG_P (rs2)
- || GET_CODE (rs2) == SUBREG
+ || SUBREG_P (rs2)
|| (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM)))
{
rs1 = XEXP (addr, 1);
@@ -4502,21 +4502,21 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
if ((flag_pic == 1
&& sparc_pic_register_p (rs1)
&& !REG_P (rs2)
- && GET_CODE (rs2) != SUBREG
+ && !SUBREG_P (rs2)
&& GET_CODE (rs2) != LO_SUM
&& GET_CODE (rs2) != MEM
&& !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
&& (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
&& (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
|| ((REG_P (rs1)
- || GET_CODE (rs1) == SUBREG)
+ || SUBREG_P (rs1))
&& RTX_OK_FOR_OFFSET_P (rs2, mode)))
{
imm1 = rs2;
rs2 = NULL;
}
- else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG)
- && (REG_P (rs2) || GET_CODE (rs2) == SUBREG))
+ else if ((REG_P (rs1) || SUBREG_P (rs1))
+ && (REG_P (rs2) || SUBREG_P (rs2)))
{
/* We prohibit REG + REG for TFmode when there are no quad move insns
and we consequently need to split. We do this because REG+REG
@@ -4580,14 +4580,14 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
else
return 0;
- if (GET_CODE (rs1) == SUBREG)
+ if (SUBREG_P (rs1))
rs1 = SUBREG_REG (rs1);
if (!REG_P (rs1))
return 0;
if (rs2)
{
- if (GET_CODE (rs2) == SUBREG)
+ if (SUBREG_P (rs2))
rs2 = SUBREG_REG (rs2);
if (!REG_P (rs2))
return 0;
@@ -9036,13 +9036,13 @@ sparc_split_reg_reg_legitimate (rtx reg1, rtx reg2)
/* Punt if we are here by mistake. */
gcc_assert (reload_completed);
- if (GET_CODE (reg1) == SUBREG)
+ if (SUBREG_P (reg1))
reg1 = SUBREG_REG (reg1);
if (!REG_P (reg1))
return 0;
const int regno1 = REGNO (reg1);
- if (GET_CODE (reg2) == SUBREG)
+ if (SUBREG_P (reg2))
reg2 = SUBREG_REG (reg2);
if (!REG_P (reg2))
return 0;
@@ -13403,7 +13403,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
if (FP_REG_CLASS_P (rclass)
&& (mode == HImode || mode == QImode)
&& (GET_CODE (x) == MEM
- || ((REG_P (x) || GET_CODE (x) == SUBREG)
+ || ((REG_P (x) || SUBREG_P (x))
&& true_regnum (x) == -1)))
return GENERAL_REGS;
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 26b7f808e82..0c003a2fdf2 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2133,7 +2133,7 @@ visl")
&& TARGET_ARCH32
&& ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
- || (GET_CODE (operands[0]) == SUBREG
+ || (SUBREG_P (operands[0])
&& REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
@@ -2579,7 +2579,7 @@ visl")
&& TARGET_ARCH32
&& ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
- || (GET_CODE (operands[0]) == SUBREG
+ || (SUBREG_P (operands[0])
&& REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
@@ -3031,7 +3031,7 @@ visl")
rtx shift_16 = GEN_INT (16);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
@@ -3114,7 +3114,7 @@ visl")
rtx shift_48 = GEN_INT (48);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (DImode);
@@ -3300,7 +3300,7 @@ visl")
rtx shift_16 = GEN_INT (16);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
@@ -3332,14 +3332,14 @@ visl")
int op1_subbyte = 0;
int op0_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
op1_subbyte *= GET_MODE_SIZE (SImode);
operand1 = XEXP (operand1, 0);
}
- if (GET_CODE (operand0) == SUBREG)
+ if (SUBREG_P (operand0))
{
op0_subbyte = SUBREG_BYTE (operand0);
op0_subbyte /= GET_MODE_SIZE (SImode);
@@ -3371,7 +3371,7 @@ visl")
rtx shift_24 = GEN_INT (24);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (SImode);
@@ -3402,7 +3402,7 @@ visl")
rtx shift_56 = GEN_INT (56);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (DImode);
@@ -3433,7 +3433,7 @@ visl")
rtx shift_48 = GEN_INT (48);
int op1_subbyte = 0;
- if (GET_CODE (operand1) == SUBREG)
+ if (SUBREG_P (operand1))
{
op1_subbyte = SUBREG_BYTE (operand1);
op1_subbyte /= GET_MODE_SIZE (DImode);
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index e850c9ba40e..668a1950c9a 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -362,7 +362,7 @@ adjust_operand (rtx op, HOST_WIDE_INT * start)
machine_mode mode;
int op_size;
/* Strip any paradoxical SUBREG. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& (GET_MODE_BITSIZE (GET_MODE (op))
> GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op)))))
{
@@ -440,7 +440,7 @@ spu_expand_extv (rtx ops[], int unsignedp)
}
}
- else if (GET_CODE (src) == SUBREG)
+ else if (SUBREG_P (src))
{
rtx r = SUBREG_REG (src);
gcc_assert (REG_P (r) && SCALAR_INT_MODE_P (GET_MODE (r)));
@@ -3551,9 +3551,9 @@ spu_legitimate_address_p (machine_mode mode,
{
rtx op0 = XEXP (x, 0);
rtx op1 = XEXP (x, 1);
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = XEXP (op0, 0);
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
op1 = XEXP (op1, 0);
if (REG_P (op0)
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
@@ -4442,7 +4442,7 @@ expand_ea_mem (rtx mem, bool is_store)
int
spu_expand_mov (rtx * ops, machine_mode mode)
{
- if (GET_CODE (ops[0]) == SUBREG && !valid_subreg (ops[0]))
+ if (SUBREG_P (ops[0]) && !valid_subreg (ops[0]))
{
/* Perform the move in the destination SUBREG's inner mode. */
ops[0] = SUBREG_REG (ops[0]);
@@ -4451,7 +4451,7 @@ spu_expand_mov (rtx * ops, machine_mode mode)
gcc_assert (ops[1]);
}
- if (GET_CODE (ops[1]) == SUBREG && !valid_subreg (ops[1]))
+ if (SUBREG_P (ops[1]) && !valid_subreg (ops[1]))
{
rtx from = SUBREG_REG (ops[1]);
scalar_int_mode imode = int_mode_for_mode (GET_MODE (from)).require ();
@@ -4843,7 +4843,7 @@ spu_split_store (rtx * ops)
{
if (REG_P (ops[1]))
emit_insn (gen_spu_convert (reg, ops[1]));
- else if (GET_CODE (ops[1]) == SUBREG)
+ else if (SUBREG_P (ops[1]))
emit_insn (gen_spu_convert (reg, SUBREG_REG (ops[1])));
else
abort ();
@@ -5481,7 +5481,7 @@ spu_init_libfuncs (void)
rtx
spu_gen_subreg (machine_mode mode, rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (GET_MODE (x) == mode)
return x;
@@ -5662,7 +5662,7 @@ spu_builtin_splats (rtx ops[])
rtx reg = gen_reg_rtx (TImode);
rtx shuf;
if (!REG_P (ops[1])
- && GET_CODE (ops[1]) != SUBREG)
+ && !SUBREG_P (ops[1]))
ops[1] = force_reg (GET_MODE_INNER (mode), ops[1]);
switch (mode)
{
diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md
index e5a653ac5a7..9f9edcb4b1b 100644
--- a/gcc/config/stormy16/predicates.md
+++ b/gcc/config/stormy16/predicates.md
@@ -67,7 +67,7 @@
return 0;
if (GET_CODE (op) == MEM)
op = XEXP (op, 0);
- else if (GET_CODE (op) == SUBREG
+ else if (SUBREG_P (op)
&& GET_CODE (XEXP (op, 0)) == MEM
&& !MEM_VOLATILE_P (XEXP (op, 0)))
op = XEXP (XEXP (op, 0), 0);
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index bd551100183..9a2b744426f 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -482,7 +482,7 @@ xstormy16_secondary_reload_class (enum reg_class rclass,
/* This chip has the interesting property that only the first eight
registers can be moved to/from memory. */
if ((MEM_P (x)
- || ((GET_CODE (x) == SUBREG || REG_P (x))
+ || ((SUBREG_P (x) || REG_P (x))
&& (true_regnum (x) == -1
|| true_regnum (x) >= FIRST_PSEUDO_REGISTER)))
&& ! reg_class_subset_p (rclass, EIGHT_REGS))
@@ -732,7 +732,7 @@ xstormy16_split_move (machine_mode mode, rtx dest, rtx src)
gcc_assert (! MEM_P (dest) || ! MEM_P (src));
/* This case is very very bad after reload, so trap it now. */
- gcc_assert (GET_CODE (dest) != SUBREG && GET_CODE (src) != SUBREG);
+ gcc_assert (!SUBREG_P (dest) && !SUBREG_P (src));
/* The general idea is to copy by words, offsetting the source and
destination. Normally the least-significant word will be copied
@@ -828,8 +828,8 @@ xstormy16_split_move (machine_mode mode, rtx dest, rtx src)
MEM_VOLATILE_P (w_dest) = 1;
/* The simplify_subreg calls must always be able to simplify. */
- gcc_assert (GET_CODE (w_src) != SUBREG
- && GET_CODE (w_dest) != SUBREG);
+ gcc_assert (!SUBREG_P (w_src)
+ && !SUBREG_P (w_dest));
insn = emit_insn (gen_rtx_SET (w_dest, w_src));
if (auto_inc_reg_rtx)
@@ -876,7 +876,7 @@ xstormy16_expand_move (machine_mode mode, rtx dest, rtx src)
|| ! xstormy16_legitimate_address_p (mode, XEXP (dest, 0), 0))
&& ! xstormy16_below100_operand (dest, mode)
&& ! REG_P (src)
- && GET_CODE (src) != SUBREG)
+ && !SUBREG_P (src))
src = copy_to_mode_reg (mode, src);
/* Don't emit something we would immediately split. */
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index b6cf8115c13..26ab4889147 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -875,7 +875,7 @@ static bool
tilegx_legitimate_address_p (machine_mode ARG_UNUSED (mode), rtx x,
bool strict)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
switch (GET_CODE (x))
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index f2e24858970..2cf16edd86d 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -775,7 +775,7 @@ static bool
tilepro_legitimate_address_p (machine_mode ARG_UNUSED (mode), rtx x,
bool strict)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
switch (GET_CODE (x))
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 201bed4bcdb..3412e69563b 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -688,7 +688,7 @@ v850_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
break;
case PLUS:
if (REG_P (XEXP (addr, 0))
- || GET_CODE (XEXP (addr, 0)) == SUBREG)
+ || SUBREG_P (XEXP (addr, 0)))
{
/* reg,foo */
v850_print_operand (file, XEXP (addr, 1), 0);
@@ -1300,11 +1300,11 @@ v850_reorg (void)
/* We might have (SUBREG (MEM)) here, so just get rid of the
subregs to make this code simpler. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& (GET_CODE (SUBREG_REG (dest)) == MEM
|| REG_P (SUBREG_REG (dest))))
alter_subreg (&dest, false);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& (GET_CODE (SUBREG_REG (src)) == MEM
|| REG_P (SUBREG_REG (src))))
alter_subreg (&src, false);
diff --git a/gcc/config/visium/predicates.md b/gcc/config/visium/predicates.md
index 1515abd968c..5547ec56444 100644
--- a/gcc/config/visium/predicates.md
+++ b/gcc/config/visium/predicates.md
@@ -47,7 +47,7 @@
(define_predicate "gpc_reg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
op = SUBREG_REG (op);
if (!REG_P (op))
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index b2bc847b971..1621f4a6403 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -1051,7 +1051,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
out_reg = REGNO (dest);
@@ -1066,7 +1066,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
if (GET_CODE (memexpr) == PLUS)
{
memexpr = XEXP (memexpr, 0);
- if (GET_CODE (memexpr) == SUBREG)
+ if (SUBREG_P (memexpr))
in_reg = REGNO (SUBREG_REG (memexpr));
else
in_reg = REGNO (memexpr);
@@ -1078,7 +1078,7 @@ gr5_hazard_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn)
{
if (GET_CODE (memexpr) == STRICT_LOW_PART)
memexpr = XEXP (memexpr, 0);
- if (GET_CODE (memexpr) == SUBREG)
+ if (SUBREG_P (memexpr))
memexpr = SUBREG_REG (memexpr);
in_reg = REGNO (memexpr);
@@ -1842,7 +1842,7 @@ visium_legitimate_address_p (machine_mode mode, rtx x, bool strict)
base = x;
/* Now check the base: it must be either a register or a subreg thereof. */
- if (GET_CODE (base) == SUBREG)
+ if (SUBREG_P (base))
base = SUBREG_REG (base);
if (!REG_P (base))
return false;
@@ -2124,7 +2124,7 @@ visium_split_double_move (rtx *operands, machine_mode mode)
{
rtx op = XEXP (operands[1], 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op) && REGNO (op) == REGNO (operands[0]))
@@ -4305,7 +4305,7 @@ reg_or_subreg_regno (rtx op)
if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
+ else if (SUBREG_P (op) && REG_P (SUBREG_REG (op)))
{
if (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
regno = subreg_regno (op);
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index d5aad718e41..505b86397b9 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -477,7 +477,7 @@ xt_true_regnum (rtx x)
return reg_renumber[REGNO (x)];
return REGNO (x);
}
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
int base = xt_true_regnum (SUBREG_REG (x));
if (base >= 0 && base < FIRST_PSEUDO_REGISTER)
@@ -580,7 +580,7 @@ constantpool_address_p (const_rtx addr)
int
constantpool_mem_p (rtx op)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == MEM)
return constantpool_address_p (XEXP (op, 0));
@@ -742,7 +742,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
cmp1 = force_reg (mode, cmp1);
}
}
- else if ((!REG_P (cmp1)) && (GET_CODE (cmp1) != SUBREG))
+ else if ((!REG_P (cmp1)) && (!SUBREG_P (cmp1)))
{
cmp1 = force_reg (mode, cmp1);
}
@@ -1118,7 +1118,7 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
static rtx
fixup_subreg_mem (rtx x)
{
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
{
@@ -1168,7 +1168,7 @@ xtensa_copy_incoming_a7 (rtx opnd)
/* The operand using a7 may come in a later instruction, so just return
the original operand if it doesn't use a7. */
reg = opnd;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
gcc_assert (SUBREG_BYTE (reg) == 0);
reg = SUBREG_REG (reg);
@@ -1831,7 +1831,7 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& ! xtensa_tls_referenced_p (addr))
return true;
- while (GET_CODE (addr) == SUBREG)
+ while (SUBREG_P (addr))
addr = SUBREG_REG (addr);
/* Allow base registers. */
@@ -1846,11 +1846,11 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
enum rtx_code code0;
enum rtx_code code1;
- while (GET_CODE (xplus0) == SUBREG)
+ while (SUBREG_P (xplus0))
xplus0 = SUBREG_REG (xplus0);
code0 = GET_CODE (xplus0);
- while (GET_CODE (xplus1) == SUBREG)
+ while (SUBREG_P (xplus1))
xplus1 = SUBREG_REG (xplus1);
code1 = GET_CODE (xplus1);
@@ -2369,7 +2369,7 @@ print_operand (FILE *file, rtx x, int letter)
switch (letter)
{
case 'D':
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
else
output_operand_lossage ("invalid %%D value");
@@ -2501,7 +2501,7 @@ print_operand (FILE *file, rtx x, int letter)
/* fall through */
default:
- if (REG_P (x) || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || SUBREG_P (x))
fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 40af6056024..757ece341e6 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -862,7 +862,7 @@
}
else
{
- gcc_assert (GET_CODE (operands[1]) == SUBREG);
+ gcc_assert (SUBREG_P (operands[1]));
lit = SUBREG_REG (operands[1]);
word_off = SUBREG_BYTE (operands[1]) & ~(UNITS_PER_WORD - 1);
byte_off = SUBREG_BYTE (operands[1]) - word_off;
diff --git a/gcc/cse.c b/gcc/cse.c
index 7747986d637..afc6f50edbe 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -722,7 +722,7 @@ static int
notreg_cost (rtx x, machine_mode mode, enum rtx_code outer, int opno)
{
scalar_int_mode int_mode, inner_mode;
- return ((GET_CODE (x) == SUBREG
+ return ((SUBREG_P (x)
&& REG_P (SUBREG_REG (x))
&& is_int_mode (mode, &int_mode)
&& is_int_mode (GET_MODE (SUBREG_REG (x)), &inner_mode)
@@ -1171,7 +1171,7 @@ insert_regs (rtx x, struct table_elt *classp, int modified)
not be accessible because its hash code will have changed. So assign
a quantity number now. */
- else if (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))
+ else if (SUBREG_P (x) && REG_P (SUBREG_REG (x))
&& ! REGNO_QTY_VALID_P (REGNO (SUBREG_REG (x))))
{
insert_regs (SUBREG_REG (x), NULL, 0);
@@ -1984,7 +1984,7 @@ static void
invalidate_dest (rtx dest)
{
if (REG_P (dest)
- || GET_CODE (dest) == SUBREG
+ || SUBREG_P (dest)
|| MEM_P (dest))
invalidate (dest, VOIDmode);
else if (GET_CODE (dest) == STRICT_LOW_PART
@@ -2028,7 +2028,7 @@ remove_invalid_subreg_refs (unsigned int regno, poly_uint64 offset,
next = p->next_same_hash;
if (!REG_P (exp)
- && (GET_CODE (exp) != SUBREG
+ && (!SUBREG_P (exp)
|| !REG_P (SUBREG_REG (exp))
|| REGNO (SUBREG_REG (exp)) != regno
|| ranges_maybe_overlap_p (SUBREG_BYTE (exp),
@@ -2051,7 +2051,7 @@ rehash_using_reg (rtx x)
struct table_elt *p, *next;
unsigned hash;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
/* If X is not a register or if the register is known not to be in any
@@ -3811,7 +3811,7 @@ equiv_constant (rtx x)
if (x == 0 || CONSTANT_P (x))
return x;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
machine_mode mode = GET_MODE (x);
machine_mode imode = GET_MODE (SUBREG_REG (x));
@@ -4517,7 +4517,7 @@ canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets)
canon_reg (XEXP (dest, 2), insn), 1);
}
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -5066,7 +5066,7 @@ cse_insn (rtx_insn *insn)
looking for. */
if (paradoxical_subreg_p (p->exp)
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (p->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (p->exp)))))
@@ -5177,7 +5177,7 @@ cse_insn (rtx_insn *insn)
/* It is okay, though, if the rtx we're trying to match
will ignore any of the bits we can't predict. */
&& ! (src != 0
- && GET_CODE (src) == SUBREG
+ && SUBREG_P (src)
&& GET_MODE (src) == GET_MODE (elt->exp)
&& partial_subreg_p (GET_MODE (SUBREG_REG (src)),
GET_MODE (SUBREG_REG (elt->exp)))))
@@ -5501,7 +5501,7 @@ cse_insn (rtx_insn *insn)
&& REG_P (dest)
&& src_const
&& !REG_P (src_const)
- && !(GET_CODE (src_const) == SUBREG
+ && !(SUBREG_P (src_const)
&& REG_P (SUBREG_REG (src_const)))
&& !(GET_CODE (src_const) == CONST
&& GET_CODE (XEXP (src_const, 0)) == MINUS
@@ -5522,7 +5522,7 @@ cse_insn (rtx_insn *insn)
do_not_record = 0;
/* Look within any ZERO_EXTRACT to the MEM or REG within it. */
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -5853,7 +5853,7 @@ cse_insn (rtx_insn *insn)
previous quantity's chain.
Needed for memory if this is a nonvarying address, unless
we have just done an invalidate_memory that covers even those. */
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
invalidate (dest, VOIDmode);
else if (MEM_P (dest))
invalidate (dest, VOIDmode);
@@ -5975,7 +5975,7 @@ cse_insn (rtx_insn *insn)
if (GET_CODE (dest) == STRICT_LOW_PART)
dest = SUBREG_REG (XEXP (dest, 0));
- if (REG_P (dest) || GET_CODE (dest) == SUBREG)
+ if (REG_P (dest) || SUBREG_P (dest))
/* Registers must also be inserted into chains for quantities. */
if (insert_regs (dest, sets[i].src_elt, 1))
{
@@ -6019,7 +6019,7 @@ cse_insn (rtx_insn *insn)
Note the loop below will find SUBREG_REG (DEST) since we have
already entered SRC and DEST of the SET in the table. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& (known_equal_after_align_down
(GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) - 1,
GET_MODE_SIZE (GET_MODE (dest)) - 1,
@@ -6147,7 +6147,7 @@ invalidate_from_clobbers (rtx_insn *insn)
rtx ref = XEXP (x, 0);
if (ref)
{
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6170,7 +6170,7 @@ invalidate_from_clobbers (rtx_insn *insn)
if (GET_CODE (y) == CLOBBER)
{
rtx ref = XEXP (y, 0);
- if (REG_P (ref) || GET_CODE (ref) == SUBREG
+ if (REG_P (ref) || SUBREG_P (ref)
|| MEM_P (ref))
invalidate (ref, VOIDmode);
else if (GET_CODE (ref) == STRICT_LOW_PART
@@ -6231,7 +6231,7 @@ invalidate_from_sets_and_clobbers (rtx_insn *insn)
rtx clobbered = XEXP (y, 0);
if (REG_P (clobbered)
- || GET_CODE (clobbered) == SUBREG)
+ || SUBREG_P (clobbered))
invalidate (clobbered, VOIDmode);
else if (GET_CODE (clobbered) == STRICT_LOW_PART
|| GET_CODE (clobbered) == ZERO_EXTRACT)
diff --git a/gcc/cselib.c b/gcc/cselib.c
index 7b0545e779c..3575141d601 100644
--- a/gcc/cselib.c
+++ b/gcc/cselib.c
@@ -1692,7 +1692,7 @@ cselib_expand_value_rtx_1 (rtx orig, struct expand_value_data *evd,
GET_MODE (SUBREG_REG (orig)),
SUBREG_BYTE (orig));
if (scopy == NULL
- || (GET_CODE (scopy) == SUBREG
+ || (SUBREG_P (scopy)
&& !REG_P (SUBREG_REG (scopy))
&& !MEM_P (SUBREG_REG (scopy))))
return NULL;
@@ -2376,7 +2376,7 @@ cselib_invalidate_mem (rtx mem_rtx)
void
cselib_invalidate_rtx (rtx dest, const_rtx setter)
{
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index 81577dfe5cd..1d487a5475e 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -3000,11 +3000,11 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
If the decl was from an inline function, then its rtl
is not identically the rtl that was used in this
particular compilation. */
- if (GET_CODE (home) == SUBREG)
+ if (SUBREG_P (home))
{
rtx value = home;
- while (GET_CODE (value) == SUBREG)
+ while (SUBREG_P (value))
value = SUBREG_REG (value);
if (REG_P (value))
{
diff --git a/gcc/df-core.c b/gcc/df-core.c
index be19aba0f1e..1eae8dba891 100644
--- a/gcc/df-core.c
+++ b/gcc/df-core.c
@@ -1955,7 +1955,7 @@ df_find_def (rtx_insn *insn, rtx reg)
{
df_ref def;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -1984,7 +1984,7 @@ df_find_use (rtx_insn *insn, rtx reg)
{
df_ref use;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
diff --git a/gcc/df-problems.c b/gcc/df-problems.c
index d32c688510c..bc3f38a94bd 100644
--- a/gcc/df-problems.c
+++ b/gcc/df-problems.c
@@ -2811,7 +2811,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
int which_subword = -1;
bool changed = false;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (orig_reg);
regno = REGNO (reg);
reg_mode = GET_MODE (reg);
@@ -2819,7 +2819,7 @@ df_word_lr_mark_ref (df_ref ref, bool is_set, regset live)
|| maybe_ne (GET_MODE_SIZE (reg_mode), 2 * UNITS_PER_WORD))
return true;
- if (GET_CODE (orig_reg) == SUBREG
+ if (SUBREG_P (orig_reg)
&& read_modify_subreg_p (orig_reg))
{
gcc_assert (DF_REF_FLAGS_IS_SET (ref, DF_REF_PARTIAL));
@@ -4002,7 +4002,7 @@ find_memory_stores (rtx x, const_rtx pat ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
int *pflags = (int *)data;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = XEXP (x, 0);
/* Treat stores to SP as stores to memory, this will prevent problems
when there are references to the stack frame. */
diff --git a/gcc/df-scan.c b/gcc/df-scan.c
index 03294a8a2c3..57d6efd709f 100644
--- a/gcc/df-scan.c
+++ b/gcc/df-scan.c
@@ -2474,7 +2474,7 @@ df_ref_create_structure (enum df_ref_class cl,
int ref_flags)
{
df_ref this_ref = NULL;
- unsigned int regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ unsigned int regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
struct df_scan_problem_data *problem_data
= (struct df_scan_problem_data *) df_scan->problem_data;
@@ -2561,9 +2561,9 @@ df_ref_record (enum df_ref_class cl,
{
unsigned int regno;
- gcc_checking_assert (REG_P (reg) || GET_CODE (reg) == SUBREG);
+ gcc_checking_assert (REG_P (reg) || SUBREG_P (reg));
- regno = REGNO (GET_CODE (reg) == SUBREG ? SUBREG_REG (reg) : reg);
+ regno = REGNO (SUBREG_P (reg) ? SUBREG_REG (reg) : reg);
if (regno < FIRST_PSEUDO_REGISTER)
{
struct df_mw_hardreg *hardreg = NULL;
@@ -2573,7 +2573,7 @@ df_ref_record (enum df_ref_class cl,
unsigned int endregno;
df_ref ref;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno += subreg_regno_offset (regno, GET_MODE (SUBREG_REG (reg)),
SUBREG_BYTE (reg), GET_MODE (reg));
@@ -2590,7 +2590,7 @@ df_ref_record (enum df_ref_class cl,
{
/* Sets to a subreg of a multiword register are partial.
Sets to a non-subreg of a multiword register are not. */
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
ref_flags |= DF_REF_PARTIAL;
ref_flags |= DF_REF_MW_HARDREG;
@@ -2673,7 +2673,7 @@ df_def_record_1 (class df_collection_rec *collection_rec,
df_ref_record (DF_REF_BASE, collection_rec,
dst, NULL, bb, insn_info, DF_REF_REG_USE, flags);
}
- else if (GET_CODE (dst) == SUBREG && REG_P (SUBREG_REG (dst)))
+ else if (SUBREG_P (dst) && REG_P (SUBREG_REG (dst)))
{
if (read_modify_subreg_p (dst))
flags |= DF_REF_READ_WRITE | DF_REF_PARTIAL;
@@ -2753,7 +2753,7 @@ df_find_hard_reg_defs_1 (rtx dst, HARD_REG_SET *defs)
/* At this point if we do not have a reg or a subreg, just return. */
if (REG_P (dst) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (dst));
- else if (GET_CODE (dst) == SUBREG
+ else if (SUBREG_P (dst)
&& REG_P (SUBREG_REG (dst)) && HARD_REGISTER_P (dst))
SET_HARD_REG_BIT (*defs, REGNO (SUBREG_REG (dst)));
}
@@ -2919,7 +2919,7 @@ df_uses_record (class df_collection_rec *collection_rec,
SUBREG. */
dst = XEXP (dst, 0);
df_uses_record (collection_rec,
- (GET_CODE (dst) == SUBREG) ? &SUBREG_REG (dst) : temp,
+ (SUBREG_P (dst)) ? &SUBREG_REG (dst) : temp,
DF_REF_REG_USE, bb, insn_info,
DF_REF_READ_WRITE | DF_REF_STRICT_LOW_PART);
}
diff --git a/gcc/df.h b/gcc/df.h
index 2e3b825065e..039fe9e9b22 100644
--- a/gcc/df.h
+++ b/gcc/df.h
@@ -647,10 +647,10 @@ public:
/* Macros to access the elements within the ref structure. */
-#define DF_REF_REAL_REG(REF) (GET_CODE ((REF)->base.reg) == SUBREG \
+#define DF_REF_REAL_REG(REF) (SUBREG_P ((REF)->base.reg) \
? SUBREG_REG ((REF)->base.reg) : ((REF)->base.reg))
#define DF_REF_REGNO(REF) ((REF)->base.regno)
-#define DF_REF_REAL_LOC(REF) (GET_CODE (*((REF)->regular_ref.loc)) == SUBREG \
+#define DF_REF_REAL_LOC(REF) (SUBREG_P (*((REF)->regular_ref.loc)) \
? &SUBREG_REG (*((REF)->regular_ref.loc)) : ((REF)->regular_ref.loc))
#define DF_REF_REG(REF) ((REF)->base.reg)
#define DF_REF_LOC(REF) (DF_REF_CLASS (REF) == DF_REF_REGULAR ? \
diff --git a/gcc/dojump.c b/gcc/dojump.c
index bac37a357a9..040d2c260fb 100644
--- a/gcc/dojump.c
+++ b/gcc/dojump.c
@@ -610,7 +610,7 @@ do_jump (tree exp, rtx_code_label *if_false_label,
temp = expand_normal (exp);
do_pending_stack_adjust ();
/* The RTL optimizers prefer comparisons against pseudos. */
- if (GET_CODE (temp) == SUBREG)
+ if (SUBREG_P (temp))
{
/* Compare promoted variables in their promoted mode. */
if (SUBREG_PROMOTED_VAR_P (temp)
diff --git a/gcc/dse.c b/gcc/dse.c
index 40ef3fb74e3..e76d67b5748 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1464,7 +1464,7 @@ record_store (rtx body, bb_info_t bb_info)
/* No place to keep the value after ra. */
&& !reload_completed
&& (REG_P (SET_SRC (body))
- || GET_CODE (SET_SRC (body)) == SUBREG
+ || SUBREG_P (SET_SRC (body))
|| CONSTANT_P (SET_SRC (body)))
&& !MEM_VOLATILE_P (mem)
/* Sometimes the store and reload is used for truncation and
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 7417551b120..d1fb7bf494d 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -4222,7 +4222,7 @@ static inline int
is_pseudo_reg (const_rtx rtl)
{
return ((REG_P (rtl) && REGNO (rtl) >= FIRST_PSEUDO_REGISTER)
- || (GET_CODE (rtl) == SUBREG
+ || (SUBREG_P (rtl)
&& REGNO (SUBREG_REG (rtl)) >= FIRST_PSEUDO_REGISTER));
}
@@ -17133,7 +17133,7 @@ dw_sra_loc_expr (tree decl, rtx loc)
|| GET_CODE (varloc) == SIGN_EXTEND
|| GET_CODE (varloc) == ZERO_EXTEND)
varloc = XEXP (varloc, 0);
- else if (GET_CODE (varloc) == SUBREG)
+ else if (SUBREG_P (varloc))
varloc = SUBREG_REG (varloc);
else
break;
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index 7a811548149..13cfd0b00ea 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -1294,7 +1294,7 @@ set_reg_attrs_from_value (rtx reg, rtx x)
while (GET_CODE (x) == SIGN_EXTEND
|| GET_CODE (x) == ZERO_EXTEND
|| GET_CODE (x) == TRUNCATE
- || (GET_CODE (x) == SUBREG && subreg_lowpart_p (x)))
+ || (SUBREG_P (x) && subreg_lowpart_p (x)))
{
#if defined(POINTERS_EXTEND_UNSIGNED)
if (((GET_CODE (x) == SIGN_EXTEND && POINTERS_EXTEND_UNSIGNED)
@@ -1377,7 +1377,7 @@ set_reg_attrs_for_decl_rtl (tree t, rtx x)
if (!t)
return;
tree tdecl = t;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
gcc_assert (subreg_lowpart_p (x));
x = SUBREG_REG (x);
@@ -1595,7 +1595,7 @@ gen_lowpart_common (machine_mode mode, rtx x)
else if (GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (int_innermode))
return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
}
- else if (GET_CODE (x) == SUBREG || REG_P (x)
+ else if (SUBREG_P (x) || REG_P (x)
|| GET_CODE (x) == CONCAT || CONST_VECTOR_P (x)
|| CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
|| CONST_POLY_INT_P (x))
@@ -1690,7 +1690,7 @@ subreg_size_highpart_offset (poly_uint64 outer_bytes, poly_uint64 inner_bytes)
int
subreg_lowpart_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return 1;
else if (GET_MODE (SUBREG_REG (x)) == VOIDmode)
return 0;
@@ -3348,7 +3348,7 @@ make_safe_from (rtx x, rtx other)
if ((MEM_P (other)
&& ! CONSTANT_P (x)
&& !REG_P (x)
- && GET_CODE (x) != SUBREG)
+ && !SUBREG_P (x))
|| (REG_P (other)
&& (REGNO (other) < FIRST_PSEUDO_REGISTER
|| reg_mentioned_p (other, x))))
@@ -5416,7 +5416,7 @@ set_for_reg_notes (rtx insn)
reg = XEXP (reg, 0);
/* Check that we have a register. */
- if (!(REG_P (reg) || GET_CODE (reg) == SUBREG))
+ if (!(REG_P (reg) || SUBREG_P (reg)))
return NULL_RTX;
return pat;
diff --git a/gcc/expmed.c b/gcc/expmed.c
index c582f3a1e62..25d19a05794 100644
--- a/gcc/expmed.c
+++ b/gcc/expmed.c
@@ -622,7 +622,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
/* If xop0 is a register, we need it in OP_MODE
to make it acceptable to the format of insv. */
- if (GET_CODE (xop0) == SUBREG)
+ if (SUBREG_P (xop0))
/* We can't just change the mode, because this might clobber op0,
and we will need the original value of op0 if insv fails. */
xop0 = gen_rtx_SUBREG (op_mode, SUBREG_REG (xop0), SUBREG_BYTE (xop0));
@@ -635,7 +635,7 @@ store_bit_field_using_insv (const extraction_insn *insv, rtx op0,
truncate the result to the original destination. Note that we can't
just truncate the paradoxical subreg as (truncate:N (subreg:W (reg:N
X) 0)) is (reg:N X). */
- if (GET_CODE (xop0) == SUBREG
+ if (SUBREG_P (xop0)
&& REG_P (SUBREG_REG (xop0))
&& !TRULY_NOOP_TRUNCATION_MODES_P (GET_MODE (SUBREG_REG (xop0)),
op_mode))
@@ -735,7 +735,7 @@ store_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
{
rtx op0 = str_rtx;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += subreg_memory_offset (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -875,7 +875,7 @@ store_integral_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
rtx arg0 = op0;
unsigned HOST_WIDE_INT subreg_off;
- if (GET_CODE (arg0) == SUBREG)
+ if (SUBREG_P (arg0))
{
/* Else we've got some float mode source being extracted into
a different float mode destination -- this combination of
@@ -1330,7 +1330,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -1375,7 +1375,7 @@ store_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
&& unit > BITS_PER_UNIT
&& maybe_gt (bitpos + bitsdone - thispos + unit, bitregion_end + 1)
&& !REG_P (op0)
- && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
+ && (!SUBREG_P (op0) || !REG_P (SUBREG_REG (op0))))
{
unit = unit / 2;
continue;
@@ -1520,7 +1520,7 @@ extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
/* If op0 is a register, we need it in EXT_MODE to make it
acceptable to the format of ext(z)v. */
- if (GET_CODE (op0) == SUBREG && op0_mode.require () != ext_mode)
+ if (SUBREG_P (op0) && op0_mode.require () != ext_mode)
return NULL_RTX;
if (REG_P (op0) && op0_mode.require () != ext_mode)
op0 = gen_lowpart_SUBREG (ext_mode, op0);
@@ -1604,7 +1604,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
if (tmode == VOIDmode)
tmode = mode;
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
{
bitnum += SUBREG_BYTE (op0) * BITS_PER_UNIT;
op0 = SUBREG_REG (op0);
@@ -1764,7 +1764,7 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
/* If we got a SUBREG, force it into a register since we
aren't going to be able to do another SUBREG on it. */
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (imode, op0);
}
else
@@ -2250,7 +2250,7 @@ extract_split_bit_field (rtx op0, opt_scalar_int_mode op0_mode,
/* Make sure UNIT isn't larger than BITS_PER_WORD, we can only handle that
much at a time. */
- if (REG_P (op0) || GET_CODE (op0) == SUBREG)
+ if (REG_P (op0) || SUBREG_P (op0))
unit = BITS_PER_WORD;
else
unit = MIN (MEM_ALIGN (op0), BITS_PER_WORD);
@@ -2477,7 +2477,7 @@ expand_shift_1 (enum tree_code code, machine_mode mode, rtx shifted,
op1 = gen_int_shift_amount (mode,
(unsigned HOST_WIDE_INT) INTVAL (op1)
% GET_MODE_BITSIZE (scalar_mode));
- else if (GET_CODE (op1) == SUBREG
+ else if (SUBREG_P (op1)
&& subreg_lowpart_p (op1)
&& SCALAR_INT_MODE_P (GET_MODE (SUBREG_REG (op1)))
&& SCALAR_INT_MODE_P (GET_MODE (op1)))
@@ -3349,7 +3349,7 @@ expand_mult_const (machine_mode mode, rtx op0, HOST_WIDE_INT val,
we've set the inner register and must properly indicate that. */
tem = op0, nmode = mode;
accum_inner = accum;
- if (GET_CODE (accum) == SUBREG)
+ if (SUBREG_P (accum))
{
accum_inner = SUBREG_REG (accum);
nmode = GET_MODE (accum_inner);
diff --git a/gcc/expr.c b/gcc/expr.c
index d020627203b..cb933203a2c 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -227,7 +227,7 @@ convert_move (rtx to, rtx from, int unsignedp)
TO here. */
scalar_int_mode to_int_mode;
- if (GET_CODE (from) == SUBREG
+ if (SUBREG_P (from)
&& SUBREG_PROMOTED_VAR_P (from)
&& is_a <scalar_int_mode> (to_mode, &to_int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (from))
@@ -238,7 +238,7 @@ convert_move (rtx to, rtx from, int unsignedp)
from_mode = to_int_mode;
}
- gcc_assert (GET_CODE (to) != SUBREG || !SUBREG_PROMOTED_VAR_P (to));
+ gcc_assert (!SUBREG_P (to) || !SUBREG_PROMOTED_VAR_P (to));
if (to_mode == from_mode
|| (from_mode == VOIDmode && CONSTANT_P (from)))
@@ -437,7 +437,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
so that we always generate the same set of insns for
better cse'ing; if an intermediate assignment occurred,
we won't be doing the operation directly on the SUBREG. */
- if (optimize > 0 && GET_CODE (from) == SUBREG)
+ if (optimize > 0 && SUBREG_P (from))
from = force_reg (from_mode, from);
emit_unop_insn (code, to, from, equiv_code);
return;
@@ -519,7 +519,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
convert_move (to, gen_lowpart (word_mode, from), 0);
return;
@@ -538,7 +538,7 @@ convert_mode_scalar (rtx to, rtx from, int unsignedp)
&& ! mode_dependent_address_p (XEXP (from, 0),
MEM_ADDR_SPACE (from)))
|| REG_P (from)
- || GET_CODE (from) == SUBREG))
+ || SUBREG_P (from)))
from = force_reg (from_mode, from);
if (REG_P (from) && REGNO (from) < FIRST_PSEUDO_REGISTER
&& !targetm.hard_regno_mode_ok (REGNO (from), to_mode))
@@ -656,7 +656,7 @@ convert_modes (machine_mode mode, machine_mode oldmode, rtx x, int unsignedp)
/* If FROM is a SUBREG that indicates that we have already done at least
the required extension, strip it. */
- if (GET_CODE (x) == SUBREG
+ if (SUBREG_P (x)
&& SUBREG_PROMOTED_VAR_P (x)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& (GET_MODE_PRECISION (subreg_promoted_mode (x))
@@ -3587,7 +3587,7 @@ emit_move_ccmode (machine_mode mode, rtx x, rtx y)
static bool
undefined_operand_subword_p (const_rtx op, int i)
{
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
return false;
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_int64 offset = i * UNITS_PER_WORD + subreg_memory_offset (op);
@@ -3656,7 +3656,7 @@ emit_move_multi_word (machine_mode mode, rtx x, rtx y)
gcc_assert (xpart && ypart);
- need_clobber |= (GET_CODE (xpart) == SUBREG);
+ need_clobber |= (SUBREG_P (xpart));
last_insn = emit_move_insn (xpart, ypart);
}
@@ -4759,7 +4759,7 @@ optimize_bitfield_assignment_op (poly_uint64 pbitsize,
offset1 = (offset1 - bitpos) / BITS_PER_UNIT;
str_rtx = adjust_address (str_rtx, str_mode, offset1);
}
- else if (!REG_P (str_rtx) && GET_CODE (str_rtx) != SUBREG)
+ else if (!REG_P (str_rtx) && !SUBREG_P (str_rtx))
return false;
/* If the bit field covers the whole REG/MEM, store_field
@@ -5554,7 +5554,7 @@ store_expr (tree exp, rtx target, int call_param_p,
return NULL_RTX;
}
- else if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ else if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -6953,7 +6953,7 @@ store_field (rtx target, poly_int64 bitsize, poly_int64 bitpos,
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
|| REG_P (target)
- || GET_CODE (target) == SUBREG
+ || SUBREG_P (target)
/* If the field isn't aligned enough to store as an ordinary memref,
store it as a bit field. */
|| (mode != BLKmode
@@ -7605,7 +7605,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
/* If this is a subreg of a hard register, declare it unsafe, otherwise,
find the underlying pseudo. */
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
x = SUBREG_REG (x);
if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER)
@@ -7749,7 +7749,7 @@ safe_from_p (const_rtx x, tree exp, int top_p)
with it. */
if (exp_rtl)
{
- if (GET_CODE (exp_rtl) == SUBREG)
+ if (SUBREG_P (exp_rtl))
{
exp_rtl = SUBREG_REG (exp_rtl);
if (REG_P (exp_rtl)
@@ -8518,7 +8518,7 @@ expand_expr_real_2 (sepops ops, rtx target, machine_mode tmode,
a promoted SUBREG, clear that indication since we now
have to do the proper extension. */
if (TYPE_UNSIGNED (TREE_TYPE (treeop0)) != unsignedp
- && GET_CODE (op0) == SUBREG)
+ && SUBREG_P (op0))
SUBREG_PROMOTED_VAR_P (op0) = 0;
return REDUCE_BIT_FIELD (op0);
@@ -10678,7 +10678,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
for (int i = 0; i < 2; i++)
{
rtx op = read_complex_part (op0, i != 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = force_reg (GET_MODE (op), op);
rtx temp = gen_lowpart_common (GET_MODE_INNER (mode1),
op);
@@ -10803,7 +10803,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
(which we know to be the width of a basic mode), then
storing into memory, and changing the mode to BLKmode. */
if (mode1 == VOIDmode
- || REG_P (op0) || GET_CODE (op0) == SUBREG
+ || REG_P (op0) || SUBREG_P (op0)
|| (mode1 != BLKmode && ! direct_load[(int) mode1]
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
&& GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT
@@ -11114,7 +11114,7 @@ expand_expr_real_1 (tree exp, rtx target, machine_mode tmode,
GET_MODE_PRECISION (GET_MODE (op0)))
&& !COMPLEX_MODE_P (GET_MODE (op0)))
{
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
op0 = force_reg (GET_MODE (op0), op0);
temp = gen_lowpart_common (mode, op0);
if (temp)
@@ -12271,7 +12271,7 @@ do_tablejump (rtx index, machine_mode mode, rtx range, rtx table_label,
sign-extended subreg, and RANGE does not have the sign bit set, then
we have a value that is valid for both sign and zero extension. In
this case, we get better code if we sign extend. */
- if (GET_CODE (index) == SUBREG
+ if (SUBREG_P (index)
&& SUBREG_PROMOTED_VAR_P (index)
&& SUBREG_PROMOTED_SIGNED_P (index)
&& ((width = GET_MODE_PRECISION (as_a <scalar_int_mode> (mode)))
diff --git a/gcc/final.c b/gcc/final.c
index fefc4874b24..7e5a574a5bb 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -2798,17 +2798,17 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
&& insn != last_ignored_compare)
{
rtx src1, src2;
- if (GET_CODE (SET_SRC (set)) == SUBREG)
+ if (SUBREG_P (SET_SRC (set)))
SET_SRC (set) = alter_subreg (&SET_SRC (set), true);
src1 = SET_SRC (set);
src2 = NULL_RTX;
if (GET_CODE (SET_SRC (set)) == COMPARE)
{
- if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 0)))
XEXP (SET_SRC (set), 0)
= alter_subreg (&XEXP (SET_SRC (set), 0), true);
- if (GET_CODE (XEXP (SET_SRC (set), 1)) == SUBREG)
+ if (SUBREG_P (XEXP (SET_SRC (set), 1)))
XEXP (SET_SRC (set), 1)
= alter_subreg (&XEXP (SET_SRC (set), 1), true);
if (XEXP (SET_SRC (set), 1)
@@ -3318,7 +3318,7 @@ cleanup_subreg_operands (rtx_insn *insn)
already if we are inside a match_operator expression that
matches the else clause. Instead we test the underlying
expression directly. */
- if (GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.operand_loc[i]))
{
recog_data.operand[i] = alter_subreg (recog_data.operand_loc[i], true);
changed = true;
@@ -3331,7 +3331,7 @@ cleanup_subreg_operands (rtx_insn *insn)
for (i = 0; i < recog_data.n_dups; i++)
{
- if (GET_CODE (*recog_data.dup_loc[i]) == SUBREG)
+ if (SUBREG_P (*recog_data.dup_loc[i]))
{
*recog_data.dup_loc[i] = alter_subreg (recog_data.dup_loc[i], true);
changed = true;
@@ -4042,7 +4042,7 @@ mark_symbol_refs_as_used (rtx x)
void
output_operand (rtx x, int code ATTRIBUTE_UNUSED)
{
- if (x && GET_CODE (x) == SUBREG)
+ if (x && SUBREG_P (x))
x = alter_subreg (&x, true);
/* X must not be a pseudo reg. */
diff --git a/gcc/function.c b/gcc/function.c
index 8274975ce33..bde93aa00e7 100644
--- a/gcc/function.c
+++ b/gcc/function.c
@@ -3209,7 +3209,7 @@ assign_parm_setup_reg (struct assign_parm_data_all *all, tree parm,
/* If op1 is a hard register that is likely spilled, first
force it into a pseudo, otherwise combiner might extend
its lifetime too much. */
- if (GET_CODE (t) == SUBREG)
+ if (SUBREG_P (t))
t = SUBREG_REG (t);
if (REG_P (t)
&& HARD_REGISTER_P (t)
diff --git a/gcc/fwprop.c b/gcc/fwprop.c
index 137864cb61b..4d5b72e70e1 100644
--- a/gcc/fwprop.c
+++ b/gcc/fwprop.c
@@ -738,7 +738,7 @@ propagate_rtx (rtx x, machine_mode mode, rtx old_rtx, rtx new_rtx,
flags = 0;
if (REG_P (new_rtx)
|| CONSTANT_P (new_rtx)
- || (GET_CODE (new_rtx) == SUBREG
+ || (SUBREG_P (new_rtx)
&& REG_P (SUBREG_REG (new_rtx))
&& !paradoxical_subreg_p (new_rtx)))
flags |= PR_CAN_APPEAR;
@@ -1165,7 +1165,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
/* Only consider subregs... */
machine_mode use_mode = GET_MODE (use_reg);
- if (GET_CODE (use_reg) != SUBREG
+ if (!SUBREG_P (use_reg)
|| !REG_P (SET_DEST (def_set)))
return false;
@@ -1178,7 +1178,7 @@ forward_propagate_subreg (df_ref use, rtx_insn *def_insn, rtx def_set)
these SUBREGs just say how to treat the register. */
use_insn = DF_REF_INSN (use);
src = SET_SRC (def_set);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& REG_P (SUBREG_REG (src))
&& REGNO (SUBREG_REG (src)) >= FIRST_PSEUDO_REGISTER
&& GET_MODE (SUBREG_REG (src)) == use_mode
@@ -1327,17 +1327,17 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
/* If def and use are subreg, check if they match. */
reg = DF_REF_REG (use);
- if (GET_CODE (reg) == SUBREG && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ if (SUBREG_P (reg) && SUBREG_P (SET_DEST (def_set)))
{
if (maybe_ne (SUBREG_BYTE (SET_DEST (def_set)), SUBREG_BYTE (reg)))
return false;
}
/* Check if the def had a subreg, but the use has the whole reg. */
- else if (REG_P (reg) && GET_CODE (SET_DEST (def_set)) == SUBREG)
+ else if (REG_P (reg) && SUBREG_P (SET_DEST (def_set)))
return false;
/* Check if the use has a subreg, but the def had the whole reg. Unlike the
previous case, the optimization is possible and often useful indeed. */
- else if (GET_CODE (reg) == SUBREG && REG_P (SET_DEST (def_set)))
+ else if (SUBREG_P (reg) && REG_P (SET_DEST (def_set)))
reg = SUBREG_REG (reg);
/* Make sure that we can treat REG as having the same mode as the
@@ -1406,7 +1406,7 @@ forward_propagate_and_simplify (df_ref use, rtx_insn *def_insn, rtx def_set)
set_reg_equal = (note == NULL_RTX
&& REG_P (SET_DEST (use_set))
&& !REG_P (src)
- && !(GET_CODE (src) == SUBREG
+ && !(SUBREG_P (src)
&& REG_P (SUBREG_REG (src)))
&& !reg_mentioned_p (SET_DEST (use_set),
SET_SRC (use_set))
diff --git a/gcc/gcse-common.c b/gcc/gcse-common.c
index e6e4b642b58..0e40adb44af 100644
--- a/gcc/gcse-common.c
+++ b/gcc/gcse-common.c
@@ -40,7 +40,7 @@ canon_list_insert (rtx dest, const_rtx x ATTRIBUTE_UNUSED, void *data)
int bb;
modify_pair pair;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/gcse.c b/gcc/gcse.c
index ff2771bdc04..43a0e29eaf7 100644
--- a/gcc/gcse.c
+++ b/gcc/gcse.c
@@ -984,7 +984,7 @@ mems_conflict_for_gcse_p (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
struct mem_conflict_info *mci = (struct mem_conflict_info *) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -1478,7 +1478,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
@@ -3381,7 +3381,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
const_rtx set = single_set_gcse (insn);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 82ed58f4960..1d9baea9f44 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -103,7 +103,7 @@ process_define_predicate (md_rtx_info *info)
(define_predicate "basereg_operand"
(match_operand 0 "register_operand")
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
})
@@ -112,7 +112,7 @@ process_define_predicate (md_rtx_info *info)
static inline int basereg_operand_1(rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
return REG_POINTER (op);
}
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index e0c9522057a..b93b692cb43 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -905,7 +905,7 @@ noce_emit_move_insn (rtx x, rtx y)
start_sequence ();
/* Check that the SET_SRC is reasonable before calling emit_move_insn,
otherwise construct a suitable SET pattern ourselves. */
- insn = (OBJECT_P (y) || CONSTANT_P (y) || GET_CODE (y) == SUBREG)
+ insn = (OBJECT_P (y) || CONSTANT_P (y) || SUBREG_P (y))
? emit_move_insn (x, y)
: emit_insn (gen_rtx_SET (x, y));
seq = get_insns ();
@@ -1720,7 +1720,7 @@ noce_emit_cmove (struct noce_if_info *if_info, rtx x, enum rtx_code code,
if (reload_completed)
return NULL_RTX;
- if (GET_CODE (vtrue) == SUBREG && GET_CODE (vfalse) == SUBREG)
+ if (SUBREG_P (vtrue) && SUBREG_P (vfalse))
{
rtx reg_vtrue = SUBREG_REG (vtrue);
rtx reg_vfalse = SUBREG_REG (vfalse);
@@ -3335,7 +3335,7 @@ bb_ok_for_noce_convert_multiple_sets (basic_block test_bb)
return false;
if (!(REG_P (src)
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& subreg_lowpart_p (src))))
return false;
@@ -3710,7 +3710,7 @@ check_cond_move_block (basic_block bb,
modified earlier in the block. */
if ((REG_P (src)
&& vals->get (src))
- || (GET_CODE (src) == SUBREG && REG_P (SUBREG_REG (src))
+ || (SUBREG_P (src) && REG_P (SUBREG_REG (src))
&& vals->get (SUBREG_REG (src))))
return FALSE;
diff --git a/gcc/internal-fn.c b/gcc/internal-fn.c
index 10673769958..58fcc5de017 100644
--- a/gcc/internal-fn.c
+++ b/gcc/internal-fn.c
@@ -658,7 +658,7 @@ expand_arith_overflow_result_store (tree lhs, rtx target,
static void
expand_ubsan_result_store (rtx target, rtx res)
{
- if (GET_CODE (target) == SUBREG && SUBREG_PROMOTED_VAR_P (target))
+ if (SUBREG_P (target) && SUBREG_PROMOTED_VAR_P (target))
/* If this is a scalar in a register that is stored in a wider mode
than the declared mode, compute the result into its declared mode
and then convert to the wider mode. Our value is the computed
@@ -2898,7 +2898,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
guarantee that the instruction will leave the upper bits of the
register in the state required by SUBREG_PROMOTED_SIGN. */
rtx dest = lhs_rtx;
- if (dest && GET_CODE (dest) == SUBREG && SUBREG_PROMOTED_VAR_P (dest))
+ if (dest && SUBREG_P (dest) && SUBREG_PROMOTED_VAR_P (dest))
dest = NULL_RTX;
create_output_operand (&ops[0], dest, insn_data[icode].operand[0].mode);
@@ -2926,7 +2926,7 @@ expand_direct_optab_fn (internal_fn fn, gcall *stmt, direct_optab optab,
If the return value has a nonintegral type, its mode must match
the instruction result. */
- if (GET_CODE (lhs_rtx) == SUBREG && SUBREG_PROMOTED_VAR_P (lhs_rtx))
+ if (SUBREG_P (lhs_rtx) && SUBREG_PROMOTED_VAR_P (lhs_rtx))
{
/* If this is a scalar in a register that is stored in a wider
mode than the declared mode, compute the result into its
diff --git a/gcc/ira-build.c b/gcc/ira-build.c
index c7457fa4431..200ed52ad55 100644
--- a/gcc/ira-build.c
+++ b/gcc/ira-build.c
@@ -1850,7 +1850,7 @@ create_insn_allocnos (rtx x, rtx outer, bool output_p)
if ((a = ira_curr_regno_allocno_map[regno]) == NULL)
{
a = ira_create_allocno (regno, false, ira_curr_loop_tree_node);
- if (outer != NULL && GET_CODE (outer) == SUBREG)
+ if (outer != NULL && SUBREG_P (outer))
{
machine_mode wmode = GET_MODE (outer);
if (partial_subreg_p (ALLOCNO_WMODE (a), wmode))
diff --git a/gcc/ira-conflicts.c b/gcc/ira-conflicts.c
index 813a6d4103c..fc471bb8770 100644
--- a/gcc/ira-conflicts.c
+++ b/gcc/ira-conflicts.c
@@ -207,7 +207,7 @@ allocnos_conflict_for_copy_p (ira_allocno_t a1, ira_allocno_t a2)
/* Check that X is REG or SUBREG of REG. */
#define REG_SUBREG_P(x) \
- (REG_P (x) || (GET_CODE (x) == SUBREG && REG_P (SUBREG_REG (x))))
+ (REG_P (x) || (SUBREG_P (x) && REG_P (SUBREG_REG (x))))
/* Return X if X is a REG, otherwise it should be SUBREG of REG and
the function returns the reg in this case. *OFFSET will be set to
@@ -220,7 +220,7 @@ go_through_subreg (rtx x, int *offset)
*offset = 0;
if (REG_P (x))
return x;
- ira_assert (GET_CODE (x) == SUBREG);
+ ira_assert (SUBREG_P (x));
reg = SUBREG_REG (x);
ira_assert (REG_P (reg));
if (REGNO (reg) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index c49f84d621f..1838a0ea538 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1297,11 +1297,11 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& known_eq (GET_MODE_SIZE (GET_MODE (dest)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))))
dest = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& known_eq (GET_MODE_SIZE (GET_MODE (src)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))))
src = SUBREG_REG (src);
@@ -1404,7 +1404,7 @@ record_operand_costs (rtx_insn *insn, enum reg_class *pref)
{
memcpy (op_costs[i], init_cost, struct_costs_size);
- if (GET_CODE (recog_data.operand[i]) == SUBREG)
+ if (SUBREG_P (recog_data.operand[i]))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
if (MEM_P (recog_data.operand[i]))
@@ -1542,7 +1542,7 @@ scan_one_insn (rtx_insn *insn)
{
rtx op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)
{
diff --git a/gcc/ira-emit.c b/gcc/ira-emit.c
index 255af307b3c..846dd5d501b 100644
--- a/gcc/ira-emit.c
+++ b/gcc/ira-emit.c
@@ -941,7 +941,7 @@ emit_move_list (move_t list, int freq)
if ((set = single_set (insn)) != NULL_RTX)
{
dest = SET_DEST (set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
ira_assert (REG_P (dest));
regno = REGNO (dest);
diff --git a/gcc/ira-lives.c b/gcc/ira-lives.c
index 2029027125a..f1fae3c1ec7 100644
--- a/gcc/ira-lives.c
+++ b/gcc/ira-lives.c
@@ -416,7 +416,7 @@ mark_ref_live (df_ref ref)
rtx reg = DF_REF_REG (ref);
rtx orig_reg = reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -545,11 +545,11 @@ mark_ref_dead (df_ref def)
if (DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)
- && (GET_CODE (orig_reg) != SUBREG
+ && (!SUBREG_P (orig_reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER
|| !read_modify_subreg_p (orig_reg)))
return;
@@ -573,7 +573,7 @@ make_pseudo_conflict (rtx reg, enum reg_class cl, rtx dreg, rtx orig_dreg,
rtx orig_reg = reg;
ira_allocno_t a;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || REGNO (reg) < FIRST_PSEUDO_REGISTER)
@@ -646,7 +646,7 @@ check_and_make_def_conflict (int alt, int def, enum reg_class def_cl)
if (def_cl == NO_REGS)
return;
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) < FIRST_PSEUDO_REGISTER)
@@ -766,7 +766,7 @@ mark_hard_reg_early_clobbers (rtx_insn *insn, bool live_p)
{
rtx dreg = DF_REF_REG (def);
- if (GET_CODE (dreg) == SUBREG)
+ if (SUBREG_P (dreg))
dreg = SUBREG_REG (dreg);
if (! REG_P (dreg) || REGNO (dreg) >= FIRST_PSEUDO_REGISTER)
continue;
@@ -875,7 +875,7 @@ ira_implicitly_set_insn_hard_regs (HARD_REG_SET *set,
{
op = recog_data.operand[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
if (GET_CODE (op) == SCRATCH
@@ -934,7 +934,7 @@ process_single_reg_class_operands (bool in_p, int freq)
operand_a = NULL;
- if (GET_CODE (operand) == SUBREG)
+ if (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand)
@@ -1337,7 +1337,7 @@ process_bb_node_lives (ira_loop_tree_node_t loop_tree_node)
{
rtx ureg = DF_REF_REG (use);
- if (GET_CODE (ureg) == SUBREG)
+ if (SUBREG_P (ureg))
ureg = SUBREG_REG (ureg);
if (! REG_P (ureg) || REGNO (ureg) >= FIRST_PSEUDO_REGISTER)
continue;
diff --git a/gcc/ira.c b/gcc/ira.c
index ac3493f202f..84bff57fc95 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -3323,7 +3323,7 @@ set_paradoxical_subreg (rtx_insn *insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST)
{
const_rtx subreg = *iter;
- if (GET_CODE (subreg) == SUBREG)
+ if (SUBREG_P (subreg))
{
const_rtx reg = SUBREG_REG (subreg);
if (REG_P (reg) && paradoxical_subreg_p (subreg))
@@ -4225,7 +4225,7 @@ build_insn_chain (void)
conservative and treat the definition as a partial
definition of the full register rather than a full
definition of a specific part of the register. */
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)
&& get_subreg_tracking_sizes (reg, &outer_size,
&inner_size, &start))
@@ -4321,7 +4321,7 @@ build_insn_chain (void)
|| pseudo_for_reload_consideration_p (regno))
{
HOST_WIDE_INT outer_size, inner_size, start;
- if (GET_CODE (reg) == SUBREG
+ if (SUBREG_P (reg)
&& !DF_REF_FLAGS_IS_SET (use,
DF_REF_SIGN_EXTRACT
| DF_REF_ZERO_EXTRACT)
diff --git a/gcc/jump.c b/gcc/jump.c
index ce5cee523c3..d6f4741e9f0 100644
--- a/gcc/jump.c
+++ b/gcc/jump.c
@@ -1690,7 +1690,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int reg_x = -1, reg_y = -1;
@@ -1728,7 +1728,7 @@ rtx_renumbered_equal_p (const_rtx x, const_rtx y)
reg_x = reg_renumber[reg_x];
}
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
reg_y = REGNO (SUBREG_REG (y));
byte_y = SUBREG_BYTE (y);
@@ -1900,7 +1900,7 @@ true_regnum (const_rtx x)
return reg_renumber[REGNO (x)];
return REGNO (x);
}
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
int base = true_regnum (SUBREG_REG (x));
if (base >= 0
@@ -1924,7 +1924,7 @@ true_regnum (const_rtx x)
unsigned int
reg_or_subregno (const_rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
return REGNO (reg);
diff --git a/gcc/loop-invariant.c b/gcc/loop-invariant.c
index 644ecfc6fbb..a69eec6cda5 100644
--- a/gcc/loop-invariant.c
+++ b/gcc/loop-invariant.c
@@ -1269,7 +1269,7 @@ get_pressure_class_and_nregs (rtx_insn *insn, int *nregs)
/* Considered invariant insns have only one set. */
gcc_assert (set != NULL_RTX);
reg = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (MEM_P (reg))
{
@@ -1793,7 +1793,7 @@ move_invariant_reg (class loop *loop, unsigned invno)
need to create a temporary register. */
set = single_set (inv->insn);
reg = dest = SET_DEST (set);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
regno = REGNO (reg);
@@ -2060,7 +2060,7 @@ static void
mark_reg_store (rtx reg, const_rtx setter ATTRIBUTE_UNUSED,
void *data ATTRIBUTE_UNUSED)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
diff --git a/gcc/loop-iv.c b/gcc/loop-iv.c
index 2274cc3075b..5c39106170b 100644
--- a/gcc/loop-iv.c
+++ b/gcc/loop-iv.c
@@ -219,7 +219,7 @@ simple_reg_p (rtx reg)
{
unsigned r;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
if (!subreg_lowpart_p (reg))
return false;
@@ -338,7 +338,7 @@ iv_get_reaching_def (rtx_insn *insn, rtx reg, df_ref *def)
*def = NULL;
if (!simple_reg_p (reg))
return GRD_INVALID;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
gcc_assert (REG_P (reg));
@@ -680,7 +680,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
(set x':DI (plus:DI y:DI 1))
(set x:SI (subreg:SI (x':DI)). */
- if (GET_CODE (op0) != SUBREG)
+ if (!SUBREG_P (op0))
return false;
if (GET_MODE (SUBREG_REG (op0)) != outer_mode)
return false;
@@ -705,7 +705,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
return false;
}
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
if (!subreg_lowpart_p (next))
return false;
@@ -737,7 +737,7 @@ get_biv_step_1 (df_ref def, scalar_int_mode outer_mode, rtx reg,
outer_step))
return false;
- if (GET_CODE (next) == SUBREG)
+ if (SUBREG_P (next))
{
scalar_int_mode amode;
if (!is_a <scalar_int_mode> (GET_MODE (next), &amode)
@@ -1119,7 +1119,7 @@ iv_analyze_op (rtx_insn *insn, scalar_int_mode mode, rtx op, class rtx_iv *iv)
if (function_invariant_p (op))
res = GRD_INVARIANT;
- else if (GET_CODE (op) == SUBREG)
+ else if (SUBREG_P (op))
{
scalar_int_mode inner_mode;
if (!subreg_lowpart_p (op)
@@ -1175,7 +1175,7 @@ iv_analyze (rtx_insn *insn, scalar_int_mode mode, rtx val, class rtx_iv *iv)
following insns. */
if (simple_reg_p (val))
{
- if (GET_CODE (val) == SUBREG)
+ if (SUBREG_P (val))
reg = SUBREG_REG (val);
else
reg = val;
@@ -1321,7 +1321,7 @@ altered_reg_used (const_rtx x, bitmap alt)
static void
mark_altered (rtx expr, const_rtx by ATTRIBUTE_UNUSED, void *alt)
{
- if (GET_CODE (expr) == SUBREG)
+ if (SUBREG_P (expr))
expr = SUBREG_REG (expr);
if (!REG_P (expr))
return;
@@ -1502,7 +1502,7 @@ implies_p (rtx a, rtx b)
op1 = XEXP (a, 1);
if (REG_P (op0)
- || (GET_CODE (op0) == SUBREG
+ || (SUBREG_P (op0)
&& REG_P (SUBREG_REG (op0))))
{
rtx r = simplify_replace_rtx (b, op0, op1);
@@ -1511,7 +1511,7 @@ implies_p (rtx a, rtx b)
}
if (REG_P (op1)
- || (GET_CODE (op1) == SUBREG
+ || (SUBREG_P (op1)
&& REG_P (SUBREG_REG (op1))))
{
rtx r = simplify_replace_rtx (b, op1, op0);
diff --git a/gcc/loop-unroll.c b/gcc/loop-unroll.c
index 63fccd23fae..b75d13492c5 100644
--- a/gcc/loop-unroll.c
+++ b/gcc/loop-unroll.c
@@ -1419,7 +1419,7 @@ analyze_insn_to_expand_var (class loop *loop, rtx_insn *insn)
return NULL;
if (!REG_P (dest)
- && !(GET_CODE (dest) == SUBREG
+ && !(SUBREG_P (dest)
&& REG_P (SUBREG_REG (dest))))
return NULL;
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index e1418e5ec51..ea09cd39cc1 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -300,7 +300,7 @@ init_lower_subreg (void)
static bool
simple_move_operand (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!OBJECT_P (x))
@@ -492,7 +492,7 @@ find_decomposable_subregs (rtx *loc, enum classify_move_insn *pcmi)
FOR_EACH_SUBRTX_VAR (iter, array, *loc, NONCONST)
{
rtx x = *iter;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx inner = SUBREG_REG (x);
unsigned int regno, outer_size, inner_size, outer_words, inner_words;
@@ -698,7 +698,7 @@ simplify_gen_subreg_concatn (machine_mode outermode, rtx op,
If OP is a SUBREG of a CONCATN, then it must be a simple mode
change with the same size and offset 0, or it must extract a
part. We shouldn't see anything else here. */
- if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == CONCATN)
+ if (SUBREG_P (op) && GET_CODE (SUBREG_REG (op)) == CONCATN)
{
rtx op2;
@@ -757,7 +757,7 @@ resolve_reg_p (rtx x)
static bool
resolve_subreg_p (rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
return resolve_reg_p (SUBREG_REG (x));
}
@@ -933,7 +933,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
}
}
- if (GET_CODE (src) == SUBREG
+ if (SUBREG_P (src)
&& resolve_reg_p (SUBREG_REG (src))
&& (maybe_ne (SUBREG_BYTE (src), 0)
|| maybe_ne (orig_size, GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))))
@@ -947,7 +947,7 @@ resolve_simple_move (rtx set, rtx_insn *insn)
/* Similarly if we are copying to a SUBREG of a decomposed reg where
the SUBREG is larger than word size. */
- if (GET_CODE (dest) == SUBREG
+ if (SUBREG_P (dest)
&& resolve_reg_p (SUBREG_REG (dest))
&& (maybe_ne (SUBREG_BYTE (dest), 0)
|| maybe_ne (orig_size,
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index e2a0c0afe3d..65ccbf3798f 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -162,7 +162,7 @@ static int new_insn_uid_start;
static inline rtx *
strip_subreg (rtx *loc)
{
- return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc;
+ return loc && SUBREG_P (*loc) ? &SUBREG_REG (*loc) : loc;
}
/* Return hard regno of REGNO or if it is was not assigned to a hard
@@ -269,7 +269,7 @@ in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class)
&& curr_insn_set != NULL
&& ((OBJECT_P (SET_SRC (curr_insn_set))
&& ! CONSTANT_P (SET_SRC (curr_insn_set)))
- || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ || (SUBREG_P (SET_SRC (curr_insn_set))
&& OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set)))
&& ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set)))))))
/* When we don't know what class will be used finally for reload
@@ -601,7 +601,7 @@ get_reload_reg (enum op_type type, machine_mode mode, rtx original,
GET_MODE_SIZE (mode)))
continue;
reg = lowpart_subreg (mode, reg, GET_MODE (reg));
- if (reg == NULL_RTX || GET_CODE (reg) != SUBREG)
+ if (reg == NULL_RTX || !SUBREG_P (reg))
continue;
}
*result_reg = reg;
@@ -680,7 +680,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (x == y)
return true;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)))))
+ && (REG_P (y) || (SUBREG_P (y) && REG_P (SUBREG_REG (y)))))
{
int j;
@@ -717,7 +717,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (code == REG && REG_P (y))
return REGNO (x) == REGNO (y);
- if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
+ if (code == REG && SUBREG_P (y) && REG_P (SUBREG_REG (y))
&& x == SUBREG_REG (y))
return true;
if (REG_P (y) && code == SUBREG && REG_P (SUBREG_REG (x))
@@ -829,7 +829,7 @@ narrow_reload_pseudo_class (rtx reg, enum reg_class cl)
registers for several reloads of one insn. */
if (INSN_UID (curr_insn) >= new_insn_uid_start)
return;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start)
return;
@@ -946,7 +946,7 @@ match_reload (signed char out, signed char *ins, signed char *outs,
rtx_insn *clobber = emit_clobber (new_out_reg);
LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1;
LRA_SUBREG_P (new_in_reg) = 1;
- if (GET_CODE (in_rtx) == SUBREG)
+ if (SUBREG_P (in_rtx))
{
rtx subreg_reg = SUBREG_REG (in_rtx);
@@ -1125,7 +1125,7 @@ emit_spill_move (bool to_p, rtx mem_pseudo, rtx val)
if (! MEM_P (val))
{
val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo),
- GET_CODE (val) == SUBREG
+ SUBREG_P (val)
? SUBREG_REG (val) : val);
LRA_SUBREG_P (val) = 1;
}
@@ -1156,9 +1156,9 @@ check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED)
lra_assert (curr_insn_set != NULL_RTX);
dreg = dest = SET_DEST (curr_insn_set);
sreg = src = SET_SRC (curr_insn_set);
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dreg = SUBREG_REG (dest);
- if (GET_CODE (src) == SUBREG)
+ if (SUBREG_P (src))
sreg = SUBREG_REG (src);
if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg)))
return false;
@@ -1355,7 +1355,7 @@ process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **aft
machine_mode mode;
bool subreg_p, before_p = false;
- subreg_p = GET_CODE (*loc) == SUBREG;
+ subreg_p = SUBREG_P (*loc);
if (subreg_p)
{
reg = SUBREG_REG (*loc);
@@ -1483,7 +1483,7 @@ simplify_operand_subreg (int nop, machine_mode reg_mode)
before = after = NULL;
- if (GET_CODE (operand) != SUBREG)
+ if (!SUBREG_P (operand))
return false;
mode = GET_MODE (operand);
@@ -1961,7 +1961,7 @@ process_alt_operands (int only_alternative)
operand_reg[nop] = reg = op;
biggest_mode[nop] = GET_MODE (op);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
biggest_mode[nop] = wider_subreg_mode (op);
operand_reg[nop] = reg = SUBREG_REG (op);
@@ -2600,7 +2600,7 @@ process_alt_operands (int only_alternative)
if (curr_static_id->operand[nop].strict_low
&& REG_P (op)
&& hard_regno[nop] < 0
- && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG
+ && SUBREG_P (*curr_id->operand_loc[nop])
&& ira_class_hard_regs_num[this_alternative] > 0
&& (!targetm.hard_regno_mode_ok
(ira_class_hard_regs[this_alternative][0],
@@ -2904,7 +2904,7 @@ process_alt_operands (int only_alternative)
if (curr_insn_set != NULL_RTX && n_operands == 2
/* Prevent processing non-move insns. */
- && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG
+ && (SUBREG_P (SET_SRC (curr_insn_set))
|| SET_SRC (curr_insn_set) == no_subreg_reg_operand[1])
&& ((! curr_alt_win[0] && ! curr_alt_win[1]
&& REG_P (no_subreg_reg_operand[0])
@@ -3338,7 +3338,7 @@ process_address_1 (int nop, bool check_only_p,
&& get_constraint_type (cn) == CT_FIXED_FORM
&& constraint_satisfied_p (op, cn)))
decompose_mem_address (&ad, op);
- else if (GET_CODE (op) == SUBREG
+ else if (SUBREG_P (op)
&& MEM_P (SUBREG_REG (op)))
decompose_mem_address (&ad, SUBREG_REG (op));
else
@@ -3886,7 +3886,7 @@ curr_insn_transform (bool check_only_p)
continue;
old = op = *curr_id->operand_loc[i];
- if (GET_CODE (old) == SUBREG)
+ if (SUBREG_P (old))
old = SUBREG_REG (old);
subst = get_equiv_with_elimination (old, curr_insn);
original_subreg_reg_mode[i] = VOIDmode;
@@ -3896,7 +3896,7 @@ curr_insn_transform (bool check_only_p)
equiv_substition_p[i] = true;
subst = copy_rtx (subst);
lra_assert (REG_P (old));
- if (GET_CODE (op) != SUBREG)
+ if (!SUBREG_P (op))
*curr_id->operand_loc[i] = subst;
else
{
@@ -4154,7 +4154,7 @@ curr_insn_transform (bool check_only_p)
enum reg_class new_class;
rtx reg = *curr_id->operand_loc[i];
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER)
@@ -4176,7 +4176,7 @@ curr_insn_transform (bool check_only_p)
rtx subreg = NULL_RTX;
machine_mode mode = curr_operand_mode[i];
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4272,10 +4272,10 @@ curr_insn_transform (bool check_only_p)
&& (curr_insn_set == NULL_RTX
|| !((REG_P (SET_SRC (curr_insn_set))
|| MEM_P (SET_SRC (curr_insn_set))
- || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG)
+ || SUBREG_P (SET_SRC (curr_insn_set)))
&& (REG_P (SET_DEST (curr_insn_set))
|| MEM_P (SET_DEST (curr_insn_set))
- || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG))))
+ || SUBREG_P (SET_DEST (curr_insn_set))))))
optional_p = true;
else if (goal_alt_matched[i][0] != -1
&& curr_static_id->operand[i].type == OP_OUT
@@ -4355,7 +4355,7 @@ curr_insn_transform (bool check_only_p)
loc = curr_id->operand_loc[i];
mode = curr_operand_mode[i];
- if (GET_CODE (*loc) == SUBREG)
+ if (SUBREG_P (*loc))
{
reg = SUBREG_REG (*loc);
poly_int64 byte = SUBREG_BYTE (*loc);
@@ -4485,7 +4485,7 @@ curr_insn_transform (bool check_only_p)
lra_assert (REG_P (reg));
regno = REGNO (reg);
op = *curr_id->operand_loc[i]; /* Substitution. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
op = SUBREG_REG (op);
gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start);
bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op));
@@ -4948,7 +4948,7 @@ lra_constraints (bool first_p)
/* The equivalence pseudo could be set up as SUBREG in a
case when it is a call restore insn in a mode
different from the pseudo mode. */
- if (GET_CODE (dest_reg) == SUBREG)
+ if (SUBREG_P (dest_reg))
dest_reg = SUBREG_REG (dest_reg);
if ((REG_P (dest_reg)
&& (x = get_equiv (dest_reg)) != dest_reg
@@ -6765,7 +6765,7 @@ fix_bb_live_info (bitmap live, bitmap removed_pseudos)
static int
get_regno (rtx reg)
{
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg))
return REGNO (reg);
@@ -6950,7 +6950,7 @@ remove_inheritance_pseudos (bitmap remove_pseudos)
&& (restore_rtx
= lra_reg_info[dregno].restore_rtx) != NULL_RTX)
{
- if (GET_CODE (SET_DEST (set)) == SUBREG)
+ if (SUBREG_P (SET_DEST (set)))
SUBREG_REG (SET_DEST (set)) = restore_rtx;
else
SET_DEST (set) = restore_rtx;
diff --git a/gcc/lra-eliminations.c b/gcc/lra-eliminations.c
index 943da888848..a9d650dab7e 100644
--- a/gcc/lra-eliminations.c
+++ b/gcc/lra-eliminations.c
@@ -287,7 +287,7 @@ move_plus_up (rtx x)
rtx subreg_reg;
machine_mode x_mode, subreg_reg_mode;
- if (GET_CODE (x) != SUBREG || !subreg_lowpart_p (x))
+ if (!SUBREG_P (x) || !subreg_lowpart_p (x))
return x;
subreg_reg = SUBREG_REG (x);
x_mode = GET_MODE (x);
@@ -932,7 +932,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -943,7 +943,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg) && (ep = get_elimination (reg)) != NULL)
@@ -964,7 +964,7 @@ eliminate_regs_in_insn (rtx_insn *insn, bool replace_p, bool first_p,
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
}
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), to_rtx);
/* If we have a nonzero offset, and the source is already a
simple REG, the following transformation would increase
diff --git a/gcc/lra.c b/gcc/lra.c
index d7593998f97..f7790f2e154 100644
--- a/gcc/lra.c
+++ b/gcc/lra.c
@@ -384,9 +384,9 @@ lra_emit_add (rtx x, rtx y, rtx z)
base = a1;
index = a2;
}
- if ((base != NULL_RTX && ! (REG_P (base) || GET_CODE (base) == SUBREG))
+ if ((base != NULL_RTX && ! (REG_P (base) || SUBREG_P (base)))
|| (index != NULL_RTX
- && ! (REG_P (index) || GET_CODE (index) == SUBREG))
+ && ! (REG_P (index) || SUBREG_P (index)))
|| (disp != NULL_RTX && ! CONSTANT_P (disp))
|| (scale != NULL_RTX && ! CONSTANT_P (scale)))
{
@@ -1459,7 +1459,7 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x,
code = GET_CODE (x);
mode = GET_MODE (x);
subreg_p = false;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
mode = wider_subreg_mode (x);
if (read_modify_subreg_p (x))
diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index d706e02faf7..5e3bacb1e18 100644
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -212,7 +212,7 @@ reg_becomes_live (rtx reg, const_rtx setter ATTRIBUTE_UNUSED, void *live)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg))
@@ -360,7 +360,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
copy_reg = SET_DEST (return_copy_pat);
if (REG_P (copy_reg))
copy_start = REGNO (copy_reg);
- else if (GET_CODE (copy_reg) == SUBREG
+ else if (SUBREG_P (copy_reg)
&& REG_P (SUBREG_REG (copy_reg)))
copy_start = REGNO (SUBREG_REG (copy_reg));
else
diff --git a/gcc/modulo-sched.c b/gcc/modulo-sched.c
index c355594bb6b..4ebd514daed 100644
--- a/gcc/modulo-sched.c
+++ b/gcc/modulo-sched.c
@@ -1477,7 +1477,7 @@ sms_schedule (void)
&& !single_set (insn) && GET_CODE (PATTERN (insn)) != USE
&& !reg_mentioned_p (count_reg, insn))
|| (INSN_P (insn) && (set = single_set (insn))
- && GET_CODE (SET_DEST (set)) == SUBREG))
+ && SUBREG_P (SET_DEST (set))))
break;
}
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 06bcaab1f55..9692ded0f38 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -208,7 +208,7 @@ widen_operand (rtx op, machine_mode mode, machine_mode oldmode,
a promoted object differs from our extension. */
if (! no_extend
|| !is_a <scalar_int_mode> (mode, &int_mode)
- || (GET_CODE (op) == SUBREG && SUBREG_PROMOTED_VAR_P (op)
+ || (SUBREG_P (op) && SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_CHECK_PROMOTED_SIGN (op, unsignedp)))
return convert_modes (mode, oldmode, op, unsignedp);
diff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c
index e4737670883..429a44a4762 100644
--- a/gcc/postreload-gcse.c
+++ b/gcc/postreload-gcse.c
@@ -618,7 +618,7 @@ find_mem_conflicts (rtx dest, const_rtx setter ATTRIBUTE_UNUSED,
{
rtx mem_op = (rtx) data;
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -733,7 +733,7 @@ record_last_set_info (rtx dest, const_rtx setter ATTRIBUTE_UNUSED, void *data)
{
rtx_insn *last_set_insn = (rtx_insn *) data;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (REG_P (dest))
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 728aa9b0ed5..8f2c3448eb4 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -1418,7 +1418,7 @@ reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED)
int i;
machine_mode mode = GET_MODE (dst);
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
{
regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
GET_MODE (SUBREG_REG (dst)),
@@ -1670,7 +1670,7 @@ move2add_record_mode (rtx reg)
int regno, nregs;
machine_mode mode = GET_MODE (reg);
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
{
regno = subreg_regno (reg);
nregs = subreg_nregs (reg);
@@ -2188,7 +2188,7 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
return;
}
- if (GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (dst))
regno = subreg_regno (dst);
else if (REG_P (dst))
regno = REGNO (dst);
diff --git a/gcc/read-rtl.c b/gcc/read-rtl.c
index 3b5d9997603..3dcf35b8f17 100644
--- a/gcc/read-rtl.c
+++ b/gcc/read-rtl.c
@@ -255,7 +255,7 @@ find_int (const char *name)
static void
apply_int_iterator (rtx x, unsigned int index, int value)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
SUBREG_BYTE (x) = value;
else
XINT (x, index) = value;
diff --git a/gcc/recog.c b/gcc/recog.c
index dffe8bfde75..56bd5716a87 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -1087,7 +1087,7 @@ address_operand (rtx op, machine_mode mode)
int
register_operand (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
rtx sub = SUBREG_REG (op);
@@ -1360,7 +1360,7 @@ memory_operand (rtx op, machine_mode mode)
return 0;
inner = op;
- if (GET_CODE (inner) == SUBREG)
+ if (SUBREG_P (inner))
inner = SUBREG_REG (inner);
return (MEM_P (inner) && general_operand (op, mode));
@@ -1374,7 +1374,7 @@ indirect_operand (rtx op, machine_mode mode)
{
/* Before reload, a SUBREG isn't in memory (see memory_operand, above). */
if (! reload_completed
- && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op)))
+ && SUBREG_P (op) && MEM_P (SUBREG_REG (op)))
{
if (mode != VOIDmode && GET_MODE (op) != mode)
return 0;
@@ -2603,7 +2603,7 @@ constrain_operands (int strict, alternative_mask alternatives)
if (UNARY_P (op))
op = XEXP (op, 0);
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
if (REG_P (SUBREG_REG (op))
&& REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
diff --git a/gcc/ree.c b/gcc/ree.c
index e4de9743e4c..ddd31ab6c06 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -467,7 +467,7 @@ get_defs (rtx_insn *insn, rtx reg, vec<rtx_insn *> *dest)
FOR_EACH_INSN_USE (use, insn)
{
- if (GET_CODE (DF_REF_REG (use)) == SUBREG)
+ if (SUBREG_P (DF_REF_REG (use)))
return NULL;
if (REGNO (DF_REF_REG (use)) == REGNO (reg))
break;
diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index c730b324cc0..45b0b35160a 100644
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -492,7 +492,7 @@ check_asm_stack_operands (rtx_insn *insn)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
recog_data.operand[i] = SUBREG_REG (recog_data.operand[i]);
@@ -510,7 +510,7 @@ check_asm_stack_operands (rtx_insn *insn)
rtx clobber = XVECEXP (body, 0, i);
rtx reg = XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
reg = SUBREG_REG (reg);
if (STACK_REG_P (reg))
@@ -2139,7 +2139,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
/* Strip SUBREGs here to make the following code simpler. */
for (i = 0; i < recog_data.n_operands; i++)
- if (GET_CODE (recog_data.operand[i]) == SUBREG
+ if (SUBREG_P (recog_data.operand[i])
&& REG_P (SUBREG_REG (recog_data.operand[i])))
{
recog_data.operand_loc[i] = & SUBREG_REG (recog_data.operand[i]);
@@ -2163,7 +2163,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (note, 0);
rtx *loc = & XEXP (note, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
@@ -2196,7 +2196,7 @@ subst_asm_stack_regs (rtx_insn *insn, stack_ptr regstack)
rtx reg = XEXP (clobber, 0);
rtx *loc = & XEXP (clobber, 0);
- if (GET_CODE (reg) == SUBREG && REG_P (SUBREG_REG (reg)))
+ if (SUBREG_P (reg) && REG_P (SUBREG_REG (reg)))
{
loc = & SUBREG_REG (reg);
reg = SUBREG_REG (reg);
diff --git a/gcc/regcprop.c b/gcc/regcprop.c
index a18c24f4797..680cf15e719 100644
--- a/gcc/regcprop.c
+++ b/gcc/regcprop.c
@@ -189,7 +189,7 @@ kill_value_regno (unsigned int regno, unsigned int nregs,
static void
kill_value (const_rtx x, struct value_data *vd)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
{
rtx tmp = simplify_subreg (GET_MODE (x), SUBREG_REG (x),
GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
@@ -541,13 +541,13 @@ replace_oldest_value_addr (rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reginfo.c b/gcc/reginfo.c
index 4832affd436..22129db915a 100644
--- a/gcc/reginfo.c
+++ b/gcc/reginfo.c
@@ -1109,7 +1109,7 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
case SET:
/* Count a set of the destination if it is a register. */
for (dest = SET_DEST (x);
- GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART
+ SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART
|| GET_CODE (dest) == ZERO_EXTRACT;
dest = XEXP (dest, 0))
;
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 3b144f5e38b..0ce4d180880 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1055,7 +1055,7 @@ note_sets_clobbers (rtx x, const_rtx set, void *data)
enum rtx_code code = *(enum rtx_code *)data;
class du_head *chain;
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
x = SUBREG_REG (x);
if (!REG_P (x) || GET_CODE (set) != code)
return;
@@ -1291,13 +1291,13 @@ scan_rtx_address (rtx_insn *insn, rtx *loc, enum reg_class cl,
rtx *locB = NULL;
enum rtx_code index_code = SCRATCH;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
diff --git a/gcc/reload.c b/gcc/reload.c
index 72cc38a0e09..e1f8329297c 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -840,7 +840,7 @@ reload_inner_reg_of_subreg (rtx x, machine_mode mode, bool output)
rtx inner;
/* Only SUBREGs are problematical. */
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
inner = SUBREG_REG (x);
@@ -1051,7 +1051,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
no choice, so we hope we do get the right register class there. */
scalar_int_mode inner_mode;
- if (in != 0 && GET_CODE (in) == SUBREG
+ if (in != 0 && SUBREG_P (in)
&& (subreg_lowpart_p (in) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (in)),
inmode, rclass)
@@ -1149,7 +1149,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
entitled to clobber it all (except in the case of a word mode subreg
or of a STRICT_LOW_PART, in that latter case the constraint should
label it input-output.) */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& (subreg_lowpart_p (out) || strict_low)
&& targetm.can_change_mode_class (GET_MODE (SUBREG_REG (out)),
outmode, rclass)
@@ -1232,13 +1232,13 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
/* If IN is a SUBREG of a hard register, make a new REG. This
simplifies some of the cases below. */
- if (in != 0 && GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))
+ if (in != 0 && SUBREG_P (in) && REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
in = gen_rtx_REG (GET_MODE (in), subreg_regno (in));
/* Similarly for OUT. */
- if (out != 0 && GET_CODE (out) == SUBREG
+ if (out != 0 && SUBREG_P (out)
&& REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER
&& ! dont_remove_subreg)
@@ -1270,12 +1270,12 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
#ifdef LIMIT_RELOAD_CLASS
if (in_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (inmode, rclass);
- else if (in != 0 && GET_CODE (in) == SUBREG)
+ else if (in != 0 && SUBREG_P (in))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (in)), rclass);
if (out_subreg_loc)
rclass = LIMIT_RELOAD_CLASS (outmode, rclass);
- if (out != 0 && GET_CODE (out) == SUBREG)
+ if (out != 0 && SUBREG_P (out))
rclass = LIMIT_RELOAD_CLASS (GET_MODE (SUBREG_REG (out)), rclass);
#endif
@@ -1351,7 +1351,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (subreg_in_class == NO_REGS
&& in != 0
&& (REG_P (in)
- || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
+ || (SUBREG_P (in) && REG_P (SUBREG_REG (in))))
&& reg_or_subregno (in) < FIRST_PSEUDO_REGISTER)
subreg_in_class = REGNO_REG_CLASS (reg_or_subregno (in));
/* If a memory location is needed for the copy, make one. */
@@ -1383,7 +1383,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
if (out != 0
&& (REG_P (out)
- || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
+ || (SUBREG_P (out) && REG_P (SUBREG_REG (out))))
&& reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
&& (targetm.secondary_memory_needed
(outmode, rclass, REGNO_REG_CLASS (reg_or_subregno (out)))))
@@ -1597,7 +1597,7 @@ push_reload (rtx in, rtx out, rtx *inloc, rtx *outloc,
Is there any simple coherent way to describe the two together?
What's going on here. */
&& (in != out
- || (GET_CODE (in) == SUBREG
+ || (SUBREG_P (in)
&& (known_equal_after_align_up
(GET_MODE_SIZE (GET_MODE (in)),
GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))),
@@ -1951,7 +1951,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
respectively refers to a hard register. */
/* Find the inside of any subregs. */
- while (GET_CODE (out) == SUBREG)
+ while (SUBREG_P (out))
{
if (REG_P (SUBREG_REG (out))
&& REGNO (SUBREG_REG (out)) < FIRST_PSEUDO_REGISTER)
@@ -1961,7 +1961,7 @@ find_dummy_reload (rtx real_in, rtx real_out, rtx *inloc, rtx *outloc,
GET_MODE (out));
out = SUBREG_REG (out);
}
- while (GET_CODE (in) == SUBREG)
+ while (SUBREG_P (in))
{
if (REG_P (SUBREG_REG (in))
&& REGNO (SUBREG_REG (in)) < FIRST_PSEUDO_REGISTER)
@@ -2134,7 +2134,7 @@ hard_reg_set_here_p (unsigned int beg_regno, unsigned int end_regno, rtx x)
{
rtx op0 = SET_DEST (x);
- while (GET_CODE (op0) == SUBREG)
+ while (SUBREG_P (op0))
op0 = SUBREG_REG (op0);
if (REG_P (op0))
{
@@ -2204,7 +2204,7 @@ operands_match_p (rtx x, rtx y)
if (x == y)
return 1;
if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x))))
- && (REG_P (y) || (GET_CODE (y) == SUBREG
+ && (REG_P (y) || (SUBREG_P (y)
&& REG_P (SUBREG_REG (y)))))
{
int j;
@@ -2222,7 +2222,7 @@ operands_match_p (rtx x, rtx y)
else
i = REGNO (x);
- if (GET_CODE (y) == SUBREG)
+ if (SUBREG_P (y))
{
j = REGNO (SUBREG_REG (y));
if (j >= FIRST_PSEUDO_REGISTER)
@@ -2836,7 +2836,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* If we now have a simple operand where we used to have a
PLUS or MULT, re-recognize and try again. */
if ((OBJECT_P (*recog_data.operand_loc[i])
- || GET_CODE (*recog_data.operand_loc[i]) == SUBREG)
+ || SUBREG_P (*recog_data.operand_loc[i]))
&& (GET_CODE (recog_data.operand[i]) == MULT
|| GET_CODE (recog_data.operand[i]) == PLUS))
{
@@ -3073,7 +3073,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
the REG or MEM (or maybe even a constant) within.
(Constants can occur as a result of reg_equiv_constant.) */
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
{
/* Offset only matters when operand is a REG and
it is a hard reg. This is because it is passed
@@ -3692,7 +3692,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
it's costly to reload it, so reload the input instead. */
if (small_register_class_p (this_alternative[i])
&& (REG_P (recog_data.operand[j])
- || GET_CODE (recog_data.operand[j]) == SUBREG))
+ || SUBREG_P (recog_data.operand[j])))
{
losers++;
this_alternative_win[j] = 0;
@@ -3907,7 +3907,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
/* Reloads of SUBREGs of CONSTANT RTXs are handled later in
push_reload so we have to let them pass here. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
subreg = op;
op = SUBREG_REG (op);
@@ -4086,7 +4086,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -4136,7 +4136,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
{
operand = *recog_data.operand_loc[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if (REG_P (operand))
{
@@ -4163,7 +4163,7 @@ find_reloads (rtx_insn *insn, int replace, int ind_levels, int live_known,
rtx operand = recog_data.operand[i];
- while (GET_CODE (operand) == SUBREG)
+ while (SUBREG_P (operand))
operand = SUBREG_REG (operand);
if ((MEM_P (operand)
|| (REG_P (operand)
@@ -5505,7 +5505,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
rtx op0 = orig_op0;
rtx op1 = orig_op1;
- if (GET_CODE (op0) == SUBREG)
+ if (SUBREG_P (op0))
{
op0 = SUBREG_REG (op0);
code0 = GET_CODE (op0);
@@ -5518,7 +5518,7 @@ find_reloads_address_1 (machine_mode mode, addr_space_t as,
GET_MODE (orig_op0))));
}
- if (GET_CODE (op1) == SUBREG)
+ if (SUBREG_P (op1))
{
op1 = SUBREG_REG (op1);
code1 = GET_CODE (op1);
@@ -6362,7 +6362,7 @@ find_replacement (rtx *loc)
return reloadreg;
}
- else if (reloadreg && GET_CODE (*loc) == SUBREG
+ else if (reloadreg && SUBREG_P (*loc)
&& r->where == &SUBREG_REG (*loc))
{
if (r->mode != VOIDmode && GET_MODE (reloadreg) != r->mode)
@@ -6455,7 +6455,7 @@ refers_to_regno_for_reload_p (unsigned int regno, unsigned int endregno,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -6531,9 +6531,9 @@ reg_overlap_mentioned_for_reload_p (rtx x, rtx in)
/* If either argument is a constant, then modifying X cannot affect IN. */
if (CONSTANT_P (x) || CONSTANT_P (in))
return 0;
- else if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
+ else if (SUBREG_P (x) && MEM_P (SUBREG_REG (x)))
return refers_to_mem_for_reload_p (in);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
regno = REGNO (SUBREG_REG (x));
if (regno < FIRST_PSEUDO_REGISTER)
@@ -6942,7 +6942,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (pat) == SET || GET_CODE (pat) == CLOBBER)
{
rtx dest = SET_DEST (pat);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
@@ -6981,7 +6981,7 @@ find_equiv_reg (rtx goal, rtx_insn *insn, enum reg_class rclass, int other,
if (GET_CODE (v1) == SET || GET_CODE (v1) == CLOBBER)
{
rtx dest = SET_DEST (v1);
- while (GET_CODE (dest) == SUBREG
+ while (SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT
|| GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 2747f0b2e53..5cc8bb5cada 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -3270,7 +3270,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
if (plus_cst_src)
{
rtx reg = XEXP (plus_cst_src, 0);
- if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
+ if (SUBREG_P (reg) && subreg_lowpart_p (reg))
reg = SUBREG_REG (reg);
if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
@@ -3282,7 +3282,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
rtx reg = XEXP (plus_cst_src, 0);
poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1));
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
@@ -3292,7 +3292,7 @@ eliminate_regs_in_insn (rtx_insn *insn, int replace)
offset += ep->offset;
offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
- if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
+ if (SUBREG_P (XEXP (plus_cst_src, 0)))
to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
to_rtx);
/* If we have a nonzero offset, and the source is already
@@ -3721,7 +3721,7 @@ mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
/* A SUBREG of a hard register here is just changing its mode. We should
not see a SUBREG of an eliminable hard register, but check just in
case. */
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
dest = SUBREG_REG (dest);
if (dest == hard_frame_pointer_rtx)
@@ -4422,7 +4422,7 @@ strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr)
rather than simplifying it to another hard register, then the
mode change cannot be properly represented. For example, OTHER
might be valid in its current mode, but not in the new one. */
- if (GET_CODE (tem) == SUBREG
+ if (SUBREG_P (tem)
&& REG_P (other)
&& HARD_REGISTER_P (other))
return false;
@@ -4829,7 +4829,7 @@ forget_old_reloads_1 (rtx x, const_rtx setter,
/* note_stores does give us subregs of hard regs,
subreg_regno_offset requires a hard reg. */
- while (GET_CODE (x) == SUBREG)
+ while (SUBREG_P (x))
{
/* We ignore the subreg offset when calculating the regno,
because we are using the entire underlying hard register
@@ -5589,10 +5589,10 @@ gen_reload_chain_without_interm_reg_p (int r1, int r2)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -6281,7 +6281,7 @@ choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx)
static rtx
replaced_subreg (rtx x)
{
- if (GET_CODE (x) == SUBREG)
+ if (SUBREG_P (x))
return find_replacement (&SUBREG_REG (x));
return x;
}
@@ -6467,7 +6467,7 @@ choose_reload_regs (class insn_chain *chain)
regno = REGNO (rld[r].in_reg);
mode = GET_MODE (rld[r].in_reg);
}
- else if (GET_CODE (rld[r].in_reg) == SUBREG
+ else if (SUBREG_P (rld[r].in_reg)
&& REG_P (SUBREG_REG (rld[r].in_reg)))
{
regno = REGNO (SUBREG_REG (rld[r].in_reg));
@@ -6493,7 +6493,7 @@ choose_reload_regs (class insn_chain *chain)
/* This won't work, since REGNO can be a pseudo reg number.
Also, it takes much more hair to keep track of all the things
that can invalidate an inherited reload of part of a pseudoreg. */
- else if (GET_CODE (rld[r].in) == SUBREG
+ else if (SUBREG_P (rld[r].in)
&& REG_P (SUBREG_REG (rld[r].in)))
regno = subreg_regno (rld[r].in);
#endif
@@ -6663,7 +6663,7 @@ choose_reload_regs (class insn_chain *chain)
Make a new REG since this might be used in an
address and not all machines support SUBREGs
there. */
- gcc_assert (GET_CODE (equiv) == SUBREG);
+ gcc_assert (SUBREG_P (equiv));
regno = subreg_regno (equiv);
equiv = gen_rtx_REG (rld[r].mode, regno);
/* If we choose EQUIV as the reload register, but the
@@ -6914,7 +6914,7 @@ choose_reload_regs (class insn_chain *chain)
check_reg = rld[r].reg_rtx;
else if (reload_override_in[r]
&& (REG_P (reload_override_in[r])
- || GET_CODE (reload_override_in[r]) == SUBREG))
+ || SUBREG_P (reload_override_in[r])))
check_reg = reload_override_in[r];
else
continue;
@@ -7131,7 +7131,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
determine whether a secondary reload is needed. */
if (reload_override_in[j]
&& (REG_P (rl->in_reg)
- || (GET_CODE (rl->in_reg) == SUBREG
+ || (SUBREG_P (rl->in_reg)
&& REG_P (SUBREG_REG (rl->in_reg)))))
{
oldequiv = old;
@@ -7141,7 +7141,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
oldequiv = old;
else if (REG_P (oldequiv))
oldequiv_reg = oldequiv;
- else if (GET_CODE (oldequiv) == SUBREG)
+ else if (SUBREG_P (oldequiv))
oldequiv_reg = SUBREG_REG (oldequiv);
reloadreg = reload_reg_rtx_for_input[j];
@@ -7163,7 +7163,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
/* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
OLDEQUIV. */
- while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
+ while (SUBREG_P (oldequiv) && GET_MODE (oldequiv) != mode)
oldequiv = SUBREG_REG (oldequiv);
if (GET_MODE (oldequiv) != VOIDmode
&& mode != GET_MODE (oldequiv))
@@ -7342,7 +7342,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
not in the right mode. */
tmp = oldequiv;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7351,14 +7351,14 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (oldequiv) == SUBREG)
+ || SUBREG_P (oldequiv))
real_oldequiv = rl->in;
else
real_oldequiv = reg_equiv_mem (REGNO (tmp));
}
tmp = old;
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER
@@ -7367,7 +7367,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
{
if (! reg_equiv_mem (REGNO (tmp))
|| num_not_at_initial_offset
- || GET_CODE (old) == SUBREG)
+ || SUBREG_P (old))
real_old = rl->in;
else
real_old = reg_equiv_mem (REGNO (tmp));
@@ -7542,7 +7542,7 @@ emit_input_reload_insns (class insn_chain *chain, struct reload *rl,
&& REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
&& (reg_equiv_memory_loc (REGNO (oldequiv)) != 0
|| reg_equiv_constant (REGNO (oldequiv)) != 0))
- || (GET_CODE (oldequiv) == SUBREG
+ || (SUBREG_P (oldequiv)
&& REG_P (SUBREG_REG (oldequiv))
&& (REGNO (SUBREG_REG (oldequiv))
>= FIRST_PSEUDO_REGISTER)
@@ -7949,7 +7949,7 @@ do_output_reload (class insn_chain *chain, struct reload *rl, int j)
return;
}
/* Likewise for a SUBREG of an operand that dies. */
- else if (GET_CODE (old) == SUBREG
+ else if (SUBREG_P (old)
&& REG_P (SUBREG_REG (old))
&& (note = find_reg_note (insn, REG_UNUSED,
SUBREG_REG (old))) != 0)
@@ -8098,7 +8098,7 @@ emit_reload_insns (class insn_chain *chain)
{
rtx reg = rld[r].in_reg;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (REG_P (reg)
@@ -8507,10 +8507,10 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
if (GET_CODE (in) == PLUS
&& (REG_P (XEXP (in, 0))
- || GET_CODE (XEXP (in, 0)) == SUBREG
+ || SUBREG_P (XEXP (in, 0))
|| MEM_P (XEXP (in, 0)))
&& (REG_P (XEXP (in, 1))
- || GET_CODE (XEXP (in, 1)) == SUBREG
+ || SUBREG_P (XEXP (in, 1))
|| CONSTANT_P (XEXP (in, 1))
|| MEM_P (XEXP (in, 1))))
{
@@ -8569,7 +8569,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
code = optab_handler (add_optab, GET_MODE (out));
- if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
+ if (CONSTANT_P (op1) || MEM_P (op1) || SUBREG_P (op1)
|| (REG_P (op1)
&& REGNO (op1) >= FIRST_PSEUDO_REGISTER)
|| (code != CODE_FOR_nothing
@@ -8661,7 +8661,7 @@ gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
fatal_insn ("failure trying to reload:", set);
}
/* If IN is a simple operand, use gen_move_insn. */
- else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
+ else if (OBJECT_P (in) || SUBREG_P (in))
{
tem = emit_insn (gen_move_insn (out, in));
/* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
@@ -8714,7 +8714,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
/* Get the raw pseudo-register referred to. */
- while (GET_CODE (reg) == SUBREG)
+ while (SUBREG_P (reg))
reg = SUBREG_REG (reg);
substed = reg_equiv_memory_loc (REGNO (reg));
@@ -8731,7 +8731,7 @@ delete_output_reload (rtx_insn *insn, int j, int last_reload_reg,
if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg)
reg2 = XEXP (rld[k].in_reg, 0);
- while (GET_CODE (reg2) == SUBREG)
+ while (SUBREG_P (reg2))
reg2 = SUBREG_REG (reg2);
if (rtx_equal_p (reg2, reg))
{
diff --git a/gcc/resource.c b/gcc/resource.c
index c4bcfd7dc71..3c3d6a1c6e4 100644
--- a/gcc/resource.c
+++ b/gcc/resource.c
@@ -90,10 +90,10 @@ update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
int i;
if (!REG_P (dest)
- && (GET_CODE (dest) != SUBREG || !REG_P (SUBREG_REG (dest))))
+ && (!SUBREG_P (dest) || !REG_P (SUBREG_REG (dest))))
return;
- if (GET_CODE (dest) == SUBREG)
+ if (SUBREG_P (dest))
{
first_regno = subreg_regno (dest);
last_regno = first_regno + subreg_nregs (dest);
@@ -291,7 +291,7 @@ mark_referenced_resources (rtx x, struct resources *res,
if (GET_CODE (x) == ZERO_EXTRACT
|| GET_CODE (x) == STRICT_LOW_PART)
mark_referenced_resources (x, res, false);
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
x = SUBREG_REG (x);
if (MEM_P (x))
mark_referenced_resources (XEXP (x, 0), res, false);
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index c33d6cbc967..69095f8e38a 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -1027,7 +1027,7 @@ unsigned_reg_p (rtx op)
&& TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op))))
return true;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_SIGN (op))
return true;
@@ -1155,7 +1155,7 @@ reg_referenced_p (const_rtx x, const_rtx body)
if (GET_CODE (SET_DEST (body)) != CC0
&& GET_CODE (SET_DEST (body)) != PC
&& !REG_P (SET_DEST (body))
- && ! (GET_CODE (SET_DEST (body)) == SUBREG
+ && ! (SUBREG_P (SET_DEST (body))
&& REG_P (SUBREG_REG (SET_DEST (body)))
&& !read_modify_subreg_p (SET_DEST (body)))
&& reg_overlap_mentioned_p (x, SET_DEST (body)))
@@ -1401,7 +1401,7 @@ modified_in_p (const_rtx x, const_rtx insn)
bool
read_modify_subreg_p (const_rtx x)
{
- if (GET_CODE (x) != SUBREG)
+ if (!SUBREG_P (x))
return false;
poly_uint64 isize = GET_MODE_SIZE (GET_MODE (SUBREG_REG (x)));
poly_uint64 osize = GET_MODE_SIZE (GET_MODE (x));
@@ -1606,7 +1606,7 @@ set_noop_p (const_rtx set)
if (GET_CODE (dst) == STRICT_LOW_PART)
dst = XEXP (dst, 0);
- if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG)
+ if (SUBREG_P (src) && SUBREG_P (dst))
{
if (maybe_ne (SUBREG_BYTE (src), SUBREG_BYTE (dst)))
return 0;
@@ -1748,7 +1748,7 @@ refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x,
/* Note setting a SUBREG counts as referring to the REG it is in for
a pseudo but not for hard registers since we can
treat each word individually. */
- && ((GET_CODE (SET_DEST (x)) == SUBREG
+ && ((SUBREG_P (SET_DEST (x))
&& loc != &SUBREG_REG (SET_DEST (x))
&& REG_P (SUBREG_REG (SET_DEST (x)))
&& REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER
@@ -1912,7 +1912,7 @@ note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data)
{
rtx dest = SET_DEST (x);
- while ((GET_CODE (dest) == SUBREG
+ while ((SUBREG_P (dest)
&& (!REG_P (SUBREG_REG (dest))
|| REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER))
|| GET_CODE (dest) == ZERO_EXTRACT
@@ -2010,7 +2010,7 @@ note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data)
(*fun) (&XEXP (dest, 2), data);
}
- while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART)
+ while (SUBREG_P (dest) || GET_CODE (dest) == STRICT_LOW_PART)
dest = XEXP (dest, 0);
if (MEM_P (dest))
@@ -2072,7 +2072,7 @@ covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno)
{
unsigned int regno, endregno;
- if (GET_CODE (dest) == SUBREG && !read_modify_subreg_p (dest))
+ if (SUBREG_P (dest) && !read_modify_subreg_p (dest))
dest = SUBREG_REG (dest);
if (!REG_P (dest))
@@ -3090,7 +3090,7 @@ replace_rtx (rtx x, rtx from, rtx to, bool all_regs)
gcc_assert (GET_MODE (x) == GET_MODE (from));
return to;
}
- else if (GET_CODE (x) == SUBREG)
+ else if (SUBREG_P (x))
{
rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to, all_regs);
@@ -6208,7 +6208,7 @@ get_base_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
@@ -6225,7 +6225,7 @@ get_index_term (rtx *inner)
inner = strip_address_mutations (&XEXP (*inner, 0));
if (REG_P (*inner)
|| MEM_P (*inner)
- || GET_CODE (*inner) == SUBREG
+ || SUBREG_P (*inner)
|| GET_CODE (*inner) == SCRATCH)
return inner;
return 0;
diff --git a/gcc/rtlhooks.c b/gcc/rtlhooks.c
index 0ce3d1ec637..d410cd55094 100644
--- a/gcc/rtlhooks.c
+++ b/gcc/rtlhooks.c
@@ -51,7 +51,7 @@ gen_lowpart_general (machine_mode mode, rtx x)
return result;
/* Handle SUBREGs and hard REGs that were rejected by
simplify_gen_subreg. */
- else if (REG_P (x) || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || SUBREG_P (x))
{
result = gen_lowpart_common (mode, copy_to_reg (x));
gcc_assert (result != 0);
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index 5cb4a462ce9..247c3dbbe3f 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -2089,7 +2089,7 @@ mark_insn_reg_birth (rtx insn, rtx reg, bool clobber_p, bool unused_p)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2148,7 +2148,7 @@ mark_reg_death (rtx reg)
{
int regno;
- if (GET_CODE (reg) == SUBREG)
+ if (SUBREG_P (reg))
reg = SUBREG_REG (reg);
if (! REG_P (reg))
@@ -2423,7 +2423,7 @@ sched_analyze_1 (class deps_desc *deps, rtx x, rtx_insn *insn)
return;
}
- while (GET_CODE (dest) == STRICT_LOW_PART || GET_CODE (dest) == SUBREG
+ while (GET_CODE (dest) == STRICT_LOW_PART || SUBREG_P (dest)
|| GET_CODE (dest) == ZERO_EXTRACT)
{
if (GET_CODE (dest) == STRICT_LOW_PART
@@ -3457,7 +3457,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
}
tmp = SET_DEST (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if (REG_P (tmp))
dest_regno = REGNO (tmp);
@@ -3465,7 +3465,7 @@ sched_analyze_insn (class deps_desc *deps, rtx x, rtx_insn *insn)
goto end_call_group;
tmp = SET_SRC (set);
- if (GET_CODE (tmp) == SUBREG)
+ if (SUBREG_P (tmp))
tmp = SUBREG_REG (tmp);
if ((GET_CODE (tmp) == PLUS
|| GET_CODE (tmp) == MINUS)
diff --git a/gcc/sched-rgn.c b/gcc/sched-rgn.c
index 59ee6a0a57c..f30b8d3f94c 100644
--- a/gcc/sched-rgn.c
+++ b/gcc/sched-rgn.c
@@ -1672,7 +1672,7 @@ check_live_1 (int src, rtx x)
if (reg == 0)
return 1;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
@@ -1755,7 +1755,7 @@ update_live_1 (int src, rtx x)
if (reg == 0)
return;
- while (GET_CODE (reg) == SUBREG
+ while (SUBREG_P (reg)
|| GET_CODE (reg) == ZERO_EXTRACT
|| GET_CODE (reg) == STRICT_LOW_PART)
reg = XEXP (reg, 0);
diff --git a/gcc/sel-sched.c b/gcc/sel-sched.c
index f127ff74599..e99c9002471 100644
--- a/gcc/sel-sched.c
+++ b/gcc/sel-sched.c
@@ -811,7 +811,7 @@ count_occurrences_equiv (const_rtx what, const_rtx where)
return 0;
count += 1;
}
- else if (GET_CODE (x) == SUBREG
+ else if (SUBREG_P (x)
&& (!REG_P (SUBREG_REG (x))
|| REGNO (SUBREG_REG (x)) == REGNO (what)))
/* ??? Do not support substituting regs inside subregs. In that case,
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 603bc456354..02f37535b0d 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -826,7 +826,7 @@ simplify_truncation (machine_mode mode, rtx op,
/* (truncate:A (subreg:B (truncate:C X) 0)) is
(truncate:A X). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& SCALAR_INT_MODE_P (op_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (op)), &subreg_mode)
@@ -1300,7 +1300,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* (float_truncate:SF (subreg:DF (float_truncate:SF X) 0))
is (float_truncate:SF x). */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& subreg_lowpart_p (op)
&& GET_CODE (SUBREG_REG (op)) == FLOAT_TRUNCATE)
return SUBREG_REG (op);
@@ -1474,7 +1474,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a sign extension of a subreg of a promoted
variable, where the promotion is sign-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_SIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1537,7 +1537,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& ! POINTERS_EXTEND_UNSIGNED
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -1557,7 +1557,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
/* Check for a zero extension of a subreg of a promoted
variable, where the promotion is zero-extended, and the
target mode is the same as the variable's promotion. */
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
&& SUBREG_PROMOTED_VAR_P (op)
&& SUBREG_PROMOTED_UNSIGNED_P (op)
&& !paradoxical_subreg_p (mode, GET_MODE (SUBREG_REG (op))))
@@ -1667,7 +1667,7 @@ simplify_unary_operation_1 (enum rtx_code code, machine_mode mode, rtx op)
&& POINTERS_EXTEND_UNSIGNED > 0
&& mode == Pmode && GET_MODE (op) == ptr_mode
&& (CONSTANT_P (op)
- || (GET_CODE (op) == SUBREG
+ || (SUBREG_P (op)
&& REG_P (SUBREG_REG (op))
&& REG_POINTER (SUBREG_REG (op))
&& GET_MODE (SUBREG_REG (op)) == Pmode))
@@ -2791,7 +2791,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
mode size to (rotate A CX). */
if (GET_CODE (op1) == ASHIFT
- || GET_CODE (op1) == SUBREG)
+ || SUBREG_P (op1))
{
opleft = op1;
opright = op0;
@@ -2813,13 +2813,13 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
/* Same, but for ashift that has been "simplified" to a wider mode
by simplify_shift_const. */
- if (GET_CODE (opleft) == SUBREG
+ if (SUBREG_P (opleft)
&& is_a <scalar_int_mode> (mode, &int_mode)
&& is_a <scalar_int_mode> (GET_MODE (SUBREG_REG (opleft)),
&inner_mode)
&& GET_CODE (SUBREG_REG (opleft)) == ASHIFT
&& GET_CODE (opright) == LSHIFTRT
- && GET_CODE (XEXP (opright, 0)) == SUBREG
+ && SUBREG_P (XEXP (opright, 0))
&& known_eq (SUBREG_BYTE (opleft), SUBREG_BYTE (XEXP (opright, 0)))
&& GET_MODE_SIZE (int_mode) < GET_MODE_SIZE (inner_mode)
&& rtx_equal_p (XEXP (SUBREG_REG (opleft), 0),
@@ -6046,7 +6046,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
Only applies for vectors of two elements. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == SUBREG
+ && SUBREG_P (op1)
&& GET_MODE (op1) == GET_MODE (op0)
&& GET_MODE (SUBREG_REG (op1)) == GET_MODE (XEXP (op0, 0))
&& paradoxical_subreg_p (op1)
@@ -6070,7 +6070,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat:outer x:inner y:inner) if N == 1,
or (vec_concat:outer y:inner x:inner) if N == 2. */
if (GET_CODE (op1) == VEC_DUPLICATE
- && GET_CODE (op0) == SUBREG
+ && SUBREG_P (op0)
&& GET_MODE (op0) == GET_MODE (op1)
&& GET_MODE (SUBREG_REG (op0)) == GET_MODE (XEXP (op1, 0))
&& paradoxical_subreg_p (op0)
@@ -6541,7 +6541,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Changing mode twice with SUBREG => just change it once,
or not at all if changing back op starting mode. */
- if (GET_CODE (op) == SUBREG)
+ if (SUBREG_P (op))
{
machine_mode innermostmode = GET_MODE (SUBREG_REG (op));
poly_uint64 innermostsize = GET_MODE_SIZE (innermostmode);
@@ -6761,7 +6761,7 @@ simplify_gen_subreg (machine_mode outermode, rtx op,
if (newx)
return newx;
- if (GET_CODE (op) == SUBREG
+ if (SUBREG_P (op)
|| GET_CODE (op) == CONCAT
|| GET_MODE (op) == VOIDmode)
return NULL_RTX;
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 87879b5f0f9..19b0b40c2b6 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -691,7 +691,7 @@ dead_debug_insert_temp (struct dead_debug_local *debug, unsigned int uregno,
cleanup_auto_inc_dec (src, VOIDmode),
GET_MODE (dest));
}
- else if (GET_CODE (dest) == SUBREG)
+ else if (SUBREG_P (dest))
{
/* We should be setting REG here. Lose. */
if (REGNO (SUBREG_REG (dest)) != REGNO (reg))
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 353df6b6618..1d425d1acd9 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -975,7 +975,7 @@ use_narrower_mode_test (rtx x, const_rtx subreg)
< GET_MODE_PRECISION (as_a <scalar_int_mode> (op1_mode)))
{
poly_uint64 byte = subreg_lowpart_offset (mode, op1_mode);
- if (GET_CODE (op1) == SUBREG || GET_CODE (op1) == CONCAT)
+ if (SUBREG_P (op1) || GET_CODE (op1) == CONCAT)
{
if (!simplify_subreg (mode, op1, op1_mode, byte))
return false;
@@ -1142,7 +1142,7 @@ adjust_mems (rtx loc, const_rtx old_rtx, void *data)
tem = gen_rtx_raw_SUBREG (GET_MODE (loc), addr, SUBREG_BYTE (loc));
finish_subreg:
if (MAY_HAVE_DEBUG_BIND_INSNS
- && GET_CODE (tem) == SUBREG
+ && SUBREG_P (tem)
&& (GET_CODE (SUBREG_REG (tem)) == PLUS
|| GET_CODE (SUBREG_REG (tem)) == MINUS
|| GET_CODE (SUBREG_REG (tem)) == MULT
@@ -6470,7 +6470,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
/* Try harder, when passing address of a constant
pool integer it can be easily read back. */
item = XEXP (item, 1);
- if (GET_CODE (item) == SUBREG)
+ if (SUBREG_P (item))
item = SUBREG_REG (item);
gcc_assert (GET_CODE (item) == VALUE);
val = CSELIB_VAL_PTR (item);
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 01/18] Fix CONST_DOUBLE_AS_FLOAT_P comment.
2019-08-06 3:11 ` Arvind Sankar
2019-08-06 3:11 ` [PATCH v2 03/18] Use CONST_INT_P macro Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 14/18] Use LABEL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh LABEL_REF Arvind Sankar
` (15 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* rtl.h: Fix comment for CONST_DOUBLE_AS_FLOAT_P and move
it together with the other CONST_DOUBLE predicates.
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 039ab05f951..28b5a82d651 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -814,6 +814,10 @@ struct GTY(()) rtvec_def {
#define CONST_DOUBLE_AS_INT_P(X) \
(GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == VOIDmode)
+/* Predicate yielding true iff X is an rtx for a floating point const. */
+#define CONST_DOUBLE_AS_FLOAT_P(X) \
+ (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
+
/* Predicate yielding true iff X is an rtx for a integer const. */
#if TARGET_SUPPORTS_WIDE_INT
#define CONST_SCALAR_INT_P(X) \
@@ -823,10 +827,6 @@ struct GTY(()) rtvec_def {
(CONST_INT_P (X) || CONST_DOUBLE_AS_INT_P (X))
#endif
-/* Predicate yielding true iff X is an rtx for a double-int. */
-#define CONST_DOUBLE_AS_FLOAT_P(X) \
- (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
-
/* Predicate yielding nonzero iff X is a label insn. */
#define LABEL_P(X) (GET_CODE (X) == CODE_LABEL)
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 04/18] Use CONST_WIDE_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_WIDE_INT_P
2019-08-06 3:11 ` Arvind Sankar
` (9 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 10/18] Use CONST_STRING_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_STRING Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 02/18] Use CONST_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_INT Arvind Sankar
` (6 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* config/darwin.c: Convert GET_CODE (..) == CONST_WIDE_INT
to CONST_WIDE_INT_P (..).
* config/s390/s390.c: Likewise.
* rtlanal.c: Likewise.
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index d38867e4227..6eaccd73a9f 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -1751,19 +1751,19 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
{
if (GET_MODE_SIZE (mode) == 8
&& (CONST_INT_P (x)
- || GET_CODE (x) == CONST_WIDE_INT
+ || CONST_WIDE_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE))
return darwin_sections[literal8_section];
else if (GET_MODE_SIZE (mode) == 4
&& (CONST_INT_P (x)
- || GET_CODE (x) == CONST_WIDE_INT
+ || CONST_WIDE_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE))
return darwin_sections[literal4_section];
else if (HAVE_GAS_LITERAL16
&& TARGET_64BIT
&& GET_MODE_SIZE (mode) == 16
&& (CONST_INT_P (x)
- || GET_CODE (x) == CONST_WIDE_INT
+ || CONST_WIDE_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE
|| GET_CODE (x) == CONST_VECTOR))
return darwin_sections[literal16_section];
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index c863514325a..4c55707367d 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -4187,7 +4187,7 @@ legitimate_reload_constant_p (rtx op)
return true;
/* Accept double-word operands that can be split. */
- if (GET_CODE (op) == CONST_WIDE_INT
+ if (CONST_WIDE_INT_P (op)
|| (CONST_INT_P (op)
&& trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)))
{
@@ -4418,7 +4418,7 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
/* Reload might have pulled a constant out of the literal pool.
Force it back in. */
if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
- || GET_CODE (mem) == CONST_WIDE_INT
+ || CONST_WIDE_INT_P (mem)
|| GET_CODE (mem) == CONST_VECTOR
|| GET_CODE (mem) == CONST)
mem = force_const_mem (GET_MODE (reg), mem);
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 268a38799d6..7da11b399ba 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -6051,7 +6051,7 @@ split_double (rtx value, rtx *first, rtx *second)
}
}
}
- else if (GET_CODE (value) == CONST_WIDE_INT)
+ else if (CONST_WIDE_INT_P (value))
{
/* All of this is scary code and needs to be converted to
properly work with any size integer. */
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 10/18] Use CONST_STRING_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_STRING
2019-08-06 3:11 ` Arvind Sankar
` (8 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 07/18] Add CONST_VECTOR_P rtx_code predicate Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 04/18] Use CONST_WIDE_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_WIDE_INT_P Arvind Sankar
` (7 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* config/avr/avr.c: Convert GET_CODE (..) == CONST_STRING to
CONST_STRING_P (..).
* dwarf2out.c: Likewise.
* genattrtab.c: Likewise.
* gensupport.c: Likewise.
4 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/gcc/config/avr/avr.c b/gcc/config/avr/avr.c
index 760e9371a01..015d36728a3 100644
--- a/gcc/config/avr/avr.c
+++ b/gcc/config/avr/avr.c
@@ -2965,7 +2965,7 @@ avr_print_operand (FILE *file, rtx x, int code)
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val);
fprintf (file, "0x%lx", val);
}
- else if (GET_CODE (x) == CONST_STRING)
+ else if (CONST_STRING_P (x))
fputs (XSTR (x, 0), file);
else if (code == 'j')
fputs (cond_string (GET_CODE (x)), file);
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index c84885a24bb..7417551b120 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -18421,7 +18421,7 @@ loc_list_from_tree_1 (tree loc, int want_address,
val &= GET_MODE_MASK (DECL_MODE (loc));
ret = int_loc_descriptor (val);
}
- else if (GET_CODE (rtl) == CONST_STRING)
+ else if (CONST_STRING_P (rtl))
{
expansion_failed (loc, NULL_RTX, "CONST_STRING");
return 0;
@@ -19687,7 +19687,7 @@ add_const_value_attribute (dw_die_ref die, rtx rtl)
return false;
case MEM:
- if (GET_CODE (XEXP (rtl, 0)) == CONST_STRING
+ if (CONST_STRING_P (XEXP (rtl, 0))
&& MEM_READONLY_P (rtl)
&& GET_MODE (rtl) == BLKmode)
{
@@ -20165,7 +20165,7 @@ add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p)
the location. */
rtl = rtl_for_decl_location (decl);
- if (rtl && (CONSTANT_P (rtl) || GET_CODE (rtl) == CONST_STRING)
+ if (rtl && (CONSTANT_P (rtl) || CONST_STRING_P (rtl))
&& add_const_value_attribute (die, rtl))
return true;
@@ -20186,7 +20186,7 @@ add_location_or_const_value_attribute (dw_die_ref die, tree decl, bool cache_p)
rtl = NOTE_VAR_LOCATION_LOC (node->loc);
if (GET_CODE (rtl) == EXPR_LIST)
rtl = XEXP (rtl, 0);
- if ((CONSTANT_P (rtl) || GET_CODE (rtl) == CONST_STRING)
+ if ((CONSTANT_P (rtl) || CONST_STRING_P (rtl))
&& add_const_value_attribute (die, rtl))
return true;
}
@@ -29855,7 +29855,7 @@ resolve_one_addr (rtx *addr)
{
rtx rtl = *addr;
- if (GET_CODE (rtl) == CONST_STRING)
+ if (CONST_STRING_P (rtl))
{
size_t len = strlen (XSTR (rtl, 0)) + 1;
tree t = build_string (len, XSTR (rtl, 0));
@@ -29960,7 +29960,7 @@ optimize_one_addr_into_implicit_ptr (dw_loc_descr_ref loc)
offset = INTVAL (XEXP (XEXP (rtl, 0), 1));
rtl = XEXP (XEXP (rtl, 0), 0);
}
- if (GET_CODE (rtl) == CONST_STRING)
+ if (CONST_STRING_P (rtl))
{
size_t len = strlen (XSTR (rtl, 0)) + 1;
tree t = build_string (len, XSTR (rtl, 0));
diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c
index cdf0b5c12dc..6b24323f112 100644
--- a/gcc/genattrtab.c
+++ b/gcc/genattrtab.c
@@ -739,7 +739,7 @@ check_attr_test (file_location loc, rtx exp, attr_desc *attr)
else
{
for (av = attr2->first_value; av; av = av->next)
- if (GET_CODE (av->value) == CONST_STRING
+ if (CONST_STRING_P (av->value)
&& ! strcmp (XSTR (exp, 1), XSTR (av->value, 0)))
break;
@@ -892,7 +892,7 @@ check_attr_value (file_location loc, rtx exp, class attr_desc *attr)
}
for (av = attr->first_value; av; av = av->next)
- if (GET_CODE (av->value) == CONST_STRING
+ if (CONST_STRING_P (av->value)
&& ! strcmp (XSTR (av->value, 0), XSTR (exp, 0)))
break;
@@ -5000,7 +5000,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (dfa_file,
"extern int internal_dfa_insn_code_%s (rtx_insn *);\n",
XSTR (val->value, 0));
@@ -5012,7 +5012,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (latency_file,
"extern int insn_default_latency_%s (rtx_insn *);\n",
XSTR (val->value, 0));
@@ -5024,7 +5024,7 @@ make_automaton_attrs (void)
{
if (val == tune_attr->default_val)
continue;
- gcc_assert (GET_CODE (val->value) == CONST_STRING);
+ gcc_assert (CONST_STRING_P (val->value));
fprintf (attr_file,
"extern int internal_dfa_insn_code_%s (rtx_insn *);\n"
"extern int insn_default_latency_%s (rtx_insn *);\n",
diff --git a/gcc/gensupport.c b/gcc/gensupport.c
index 1aab7119901..c26057079fd 100644
--- a/gcc/gensupport.c
+++ b/gcc/gensupport.c
@@ -683,7 +683,7 @@ is_predicable (class queue_elem *elem)
|| strcmp (XSTR (SET_DEST (sub), 0), "predicable") != 0)
break;
sub = SET_SRC (sub);
- if (GET_CODE (sub) == CONST_STRING)
+ if (CONST_STRING_P (sub))
{
value = XSTR (sub, 0);
goto found;
@@ -775,7 +775,7 @@ has_subst_attribute (class queue_elem *elem, class queue_elem *subst_elem)
|| strcmp (XSTR (SET_DEST (cur_attr), 0), subst_name) != 0)
break;
cur_attr = SET_SRC (cur_attr);
- if (GET_CODE (cur_attr) == CONST_STRING)
+ if (CONST_STRING_P (cur_attr))
{
value = XSTR (cur_attr, 0);
goto found;
@@ -1415,7 +1415,7 @@ alter_attrs_for_insn (rtx insn)
if (strcmp (XSTR (SET_DEST (sub), 0), "predicable") == 0)
{
sub = SET_SRC (sub);
- if (GET_CODE (sub) == CONST_STRING)
+ if (CONST_STRING_P (sub))
{
predicable_idx = i;
XSTR (sub, 0) = "ce_enabled";
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 08/18] Use CONST_VECTOR_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_VECTOR
2019-08-06 3:11 ` Arvind Sankar
` (6 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 13/18] Use MEM_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh MEM Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 07/18] Add CONST_VECTOR_P rtx_code predicate Arvind Sankar
` (9 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* common.md: Convert GET_CODE (..) == CONST_VECTOR to
CONST_VECTOR_P (..).
* config/aarch64/aarch64.c: Likewise.
* config/alpha/alpha.c: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/simdext.md: Likewise.
* config/arm/arm.c: Likewise.
* config/bfin/bfin.md: Likewise.
* config/darwin.c: Likewise.
* config/gcn/gcn-valu.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/i386/i386-expand.c: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/predicates.md: Likewise.
* config/i386/sse.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/mips/mips.c: Likewise.
* config/nds32/nds32-dspext.md: Likewise.
* config/nds32/predicates.md: Likewise.
* config/rs6000/predicates.md: Likewise.
* config/rs6000/rs6000-p8swap.c: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/s390/s390.c: Likewise.
* config/spu/predicates.md: Likewise.
* config/spu/spu.c: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilepro/tilepro.c: Likewise.
* dwarf2out.c: Likewise.
* emit-rtl.c: Likewise.
* explow.c: Likewise.
* rtlanal.c: Likewise.
* simplify-rtx.c: Likewise.
* varasm.c: Likewise.
32 files changed, 112 insertions(+), 112 deletions(-)
diff --git a/gcc/common.md b/gcc/common.md
index 42c574029b5..ee93f203bd2 100644
--- a/gcc/common.md
+++ b/gcc/common.md
@@ -80,14 +80,14 @@
(define_constraint "E"
"Matches a floating-point constant."
(ior (match_test "CONST_DOUBLE_AS_FLOAT_P (op)")
- (match_test "GET_CODE (op) == CONST_VECTOR
+ (match_test "CONST_VECTOR_P (op)
&& GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT")))
;; There is no longer a distinction between "E" and "F".
(define_constraint "F"
"Matches a floating-point constant."
(ior (match_test "CONST_DOUBLE_AS_FLOAT_P (op)")
- (match_test "GET_CODE (op) == CONST_VECTOR
+ (match_test "CONST_VECTOR_P (op)
&& GET_MODE_CLASS (GET_MODE (op)) == MODE_VECTOR_FLOAT")))
(define_constraint "X"
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 68ad4858c76..9bdbc198dae 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -3429,7 +3429,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm,
}
emit_insn (gen_vec_duplicate (dest, op));
}
- else if (GET_CODE (imm) == CONST_VECTOR
+ else if (CONST_VECTOR_P (imm)
&& !GET_MODE_NUNITS (GET_MODE (imm)).is_constant ())
aarch64_expand_sve_const_vector (dest, imm);
else
@@ -7503,7 +7503,7 @@ aarch64_const_vec_all_in_range_p (rtx vec,
HOST_WIDE_INT minval,
HOST_WIDE_INT maxval)
{
- if (GET_CODE (vec) != CONST_VECTOR
+ if (!CONST_VECTOR_P (vec)
|| GET_MODE_CLASS (GET_MODE (vec)) != MODE_VECTOR_INT)
return false;
@@ -13203,7 +13203,7 @@ aarch64_legitimate_constant_p (machine_mode mode, rtx x)
/* Support CSE and rematerialization of common constants. */
if (CONST_INT_P (x)
|| (CONST_DOUBLE_P (x) && GET_MODE_CLASS (mode) == MODE_FLOAT)
- || GET_CODE (x) == CONST_VECTOR)
+ || CONST_VECTOR_P (x))
return true;
/* Do not allow vector struct mode constants for Advanced SIMD.
@@ -14621,7 +14621,7 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info,
scalar_mode elt_mode = GET_MODE_INNER (mode);
rtx base, step;
unsigned int n_elts;
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& CONST_VECTOR_DUPLICATE_P (op))
n_elts = CONST_VECTOR_NPATTERNS (op);
else if ((vec_flags & VEC_SVE_DATA)
@@ -14636,7 +14636,7 @@ aarch64_simd_valid_immediate (rtx op, simd_immediate_info *info,
*info = simd_immediate_info (elt_mode, base, step);
return true;
}
- else if (GET_CODE (op) == CONST_VECTOR
+ else if (CONST_VECTOR_P (op)
&& CONST_VECTOR_NUNITS (op).is_constant (&n_elts))
/* N_ELTS set above. */;
else
@@ -15096,7 +15096,7 @@ aarch64_simd_make_constant (rtx vals)
int n_const = 0;
int i;
- if (GET_CODE (vals) == CONST_VECTOR)
+ if (CONST_VECTOR_P (vals))
const_vec = vals;
else if (GET_CODE (vals) == PARALLEL)
{
@@ -16548,7 +16548,7 @@ aarch64_expand_sve_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
rtx sel_reg = force_reg (sel_mode, sel);
/* Check if the sel only references the first values vector. */
- if (GET_CODE (sel) == CONST_VECTOR
+ if (CONST_VECTOR_P (sel)
&& aarch64_const_vec_all_in_range_p (sel, 0, nunits - 1))
{
emit_unspec2 (target, UNSPEC_TBL, op0, sel_reg);
@@ -16570,7 +16570,7 @@ aarch64_expand_sve_vec_perm (rtx target, rtx op0, rtx op1, rtx sel)
rtx res0 = gen_reg_rtx (data_mode);
rtx res1 = gen_reg_rtx (data_mode);
rtx neg_num_elems = aarch64_simd_gen_const_vector_dup (sel_mode, -nunits);
- if (GET_CODE (sel) != CONST_VECTOR
+ if (!CONST_VECTOR_P (sel)
|| !aarch64_const_vec_all_in_range_p (sel, 0, 2 * nunits - 1))
{
rtx max_sel = aarch64_simd_gen_const_vector_dup (sel_mode,
@@ -18754,7 +18754,7 @@ int
aarch64_vec_fpconst_pow_of_2 (rtx x)
{
int nelts;
- if (GET_CODE (x) != CONST_VECTOR
+ if (!CONST_VECTOR_P (x)
|| !CONST_VECTOR_NUNITS (x).is_constant (&nelts))
return -1;
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index 132af0b592a..f0e4061fb00 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -1623,7 +1623,7 @@ alpha_preferred_reload_class(rtx x, enum reg_class rclass)
/* These sorts of constants we can easily drop to memory. */
if (CONST_SCALAR_INT_P (x)
|| CONST_DOUBLE_P (x)
- || GET_CODE (x) == CONST_VECTOR)
+ || CONST_VECTOR_P (x))
{
if (rclass == FLOAT_REGS)
return NO_REGS;
@@ -2112,7 +2112,7 @@ alpha_emit_set_long_const (rtx target, HOST_WIDE_INT c1)
static HOST_WIDE_INT
alpha_extract_integer (rtx x)
{
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
x = simplify_subreg (DImode, x, GET_MODE (x), 0);
gcc_assert (CONST_INT_P (x));
@@ -2248,7 +2248,7 @@ alpha_expand_mov (machine_mode mode, rtx *operands)
/* Split large integers. */
if (CONST_INT_P (operands[1])
- || GET_CODE (operands[1]) == CONST_VECTOR)
+ || CONST_VECTOR_P (operands[1]))
{
if (alpha_split_const_mov (mode, operands))
return true;
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index abdb51fbb31..d9225440c3f 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -10105,7 +10105,7 @@ arc_split_move (rtx *operands)
}
if (TARGET_PLUS_QMACW
- && GET_CODE (operands[1]) == CONST_VECTOR)
+ && CONST_VECTOR_P (operands[1]))
{
HOST_WIDE_INT intval0, intval1;
if (GET_MODE (operands[1]) == V2SImode)
diff --git a/gcc/config/arc/simdext.md b/gcc/config/arc/simdext.md
index 9e4b9ba2628..53a0a90ef3b 100644
--- a/gcc/config/arc/simdext.md
+++ b/gcc/config/arc/simdext.md
@@ -1365,7 +1365,7 @@
mov%? %0, %1
ld%U1%V1 %0,%1
st%U0%V0 %1,%0"
- "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
+ "reload_completed && CONST_VECTOR_P (operands[1])"
[(set (match_dup 0) (match_dup 2))]
{
HOST_WIDE_INT intval = INTVAL (XVECEXP (operands[1], 0, 1)) << 16;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 81286cadf32..a6b493f2973 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -12002,7 +12002,7 @@ neon_valid_immediate (rtx op, machine_mode mode, int inverse,
unsigned char bytes[16];
int immtype = -1, matches;
unsigned int invmask = inverse ? 0xff : 0;
- bool vector = GET_CODE (op) == CONST_VECTOR;
+ bool vector = CONST_VECTOR_P (op);
if (vector)
n_elts = CONST_VECTOR_NUNITS (op);
@@ -12352,7 +12352,7 @@ neon_vdup_constant (rtx vals)
machine_mode inner_mode = GET_MODE_INNER (mode);
rtx x;
- if (GET_CODE (vals) != CONST_VECTOR || GET_MODE_SIZE (inner_mode) > 4)
+ if (!CONST_VECTOR_P (vals) || GET_MODE_SIZE (inner_mode) > 4)
return NULL_RTX;
if (!const_vec_duplicate_p (vals, &x))
@@ -12385,7 +12385,7 @@ neon_make_constant (rtx vals)
int n_const = 0;
int i;
- if (GET_CODE (vals) == CONST_VECTOR)
+ if (CONST_VECTOR_P (vals))
const_vec = vals;
else if (GET_CODE (vals) == PARALLEL)
{
@@ -12793,7 +12793,7 @@ coproc_secondary_reload_class (machine_mode mode, rtx x, bool wb)
/* The neon move patterns handle all legitimate vector and struct
addresses. */
if (TARGET_NEON
- && (MEM_P (x) || GET_CODE (x) == CONST_VECTOR)
+ && (MEM_P (x) || CONST_VECTOR_P (x))
&& (GET_MODE_CLASS (mode) == MODE_VECTOR_INT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT
|| VALID_NEON_STRUCT_MODE (mode)))
@@ -23060,7 +23060,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
{
int i, units;
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
units = CONST_VECTOR_NUNITS (x);
size = GET_MODE_UNIT_SIZE (mode);
@@ -26982,7 +26982,7 @@ arm_emit_vector_const (FILE *file, rtx x)
int i;
const char * pattern;
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
switch (GET_MODE (x))
{
@@ -28000,7 +28000,7 @@ arm_output_addr_const_extra (FILE *fp, rtx x)
fputc (')', fp);
return TRUE;
}
- else if (GET_CODE (x) == CONST_VECTOR)
+ else if (CONST_VECTOR_P (x))
return arm_emit_vector_const (fp, x);
return FALSE;
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index b2b5f04d6c5..517ee4baa39 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -653,7 +653,7 @@
%0 = %1;
%0 = %1%!
%0 = %1%!"
- "reload_completed && GET_CODE (operands[1]) == CONST_VECTOR"
+ "reload_completed && CONST_VECTOR_P (operands[1])"
[(set (match_dup 0) (high:SI (match_dup 2)))
(set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 3)))]
{
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 3076650abaa..8ccbad46310 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -1765,7 +1765,7 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
&& (CONST_INT_P (x)
|| CONST_WIDE_INT_P (x)
|| CONST_DOUBLE_P (x)
- || GET_CODE (x) == CONST_VECTOR))
+ || CONST_VECTOR_P (x)))
return darwin_sections[literal16_section];
else if (MACHOPIC_INDIRECT
&& (GET_CODE (x) == SYMBOL_REF
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index df0fe33878b..e6a95bf6fb4 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2322,7 +2322,7 @@
rtx fma = gen_reg_rtx (<MODE>mode);
rtx rcp;
- bool is_rcp = (GET_CODE (operands[1]) == CONST_VECTOR
+ bool is_rcp = (CONST_VECTOR_P (operands[1])
&& real_identical
(CONST_DOUBLE_REAL_VALUE
(CONST_VECTOR_ELT (operands[1], 0)), &dconstm1));
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 8bc1e6b50be..b4c5f228373 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -561,7 +561,7 @@ gcn_operand_part (machine_mode mode, rtx op, int n)
gcc_assert (REGNO (op) + n < FIRST_PSEUDO_REGISTER);
return gen_rtx_REG (V64SImode, REGNO (op) + n);
}
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
int units = GET_MODE_NUNITS (mode);
rtvec v = rtvec_alloc (units);
@@ -734,7 +734,7 @@ gcn_inline_fp_constant_p (rtx x, bool allow_vector)
&& allow_vector)
{
int n;
- if (GET_CODE (x) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (x))
return 0;
n = gcn_inline_fp_constant_p (CONST_VECTOR_ELT (x, 0), false);
if (!n)
@@ -799,7 +799,7 @@ gcn_fp_constant_p (rtx x, bool allow_vector)
&& allow_vector)
{
int n;
- if (GET_CODE (x) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (x))
return false;
n = gcn_fp_constant_p (CONST_VECTOR_ELT (x, 0), false);
if (!n)
@@ -828,7 +828,7 @@ gcn_inline_constant_p (rtx x)
return INTVAL (x) >= -16 && INTVAL (x) < 64;
if (CONST_DOUBLE_P (x))
return gcn_inline_fp_constant_p (x, false);
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
{
int n;
if (!vgpr_vector_mode_p (GET_MODE (x)))
@@ -890,7 +890,7 @@ gcn_constant_p (rtx x)
bool
gcn_inline_constant64_p (rtx x)
{
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
{
if (!vgpr_vector_mode_p (GET_MODE (x)))
return false;
@@ -950,7 +950,7 @@ gcn_legitimate_constant_p (machine_mode, rtx x)
static bool
single_cst_vector_p (rtx x)
{
- if (GET_CODE (x) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (x))
return false;
for (int i = 1; i < 64; i++)
if (CONST_VECTOR_ELT (x, i) != CONST_VECTOR_ELT (x, 0))
@@ -1352,7 +1352,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
&& !gcn_ssrc_register_operand (x1, DImode)))
return false;
}
- else if (GET_CODE (x1) == CONST_VECTOR
+ else if (CONST_VECTOR_P (x1)
&& CONST_INT_P (CONST_VECTOR_ELT (x1, 0))
&& single_cst_vector_p (x1))
{
@@ -5676,7 +5676,7 @@ print_operand (FILE *file, rtx x, int code)
return;
}
rtx val = XEXP (x0, 1);
- if (GET_CODE (val) == CONST_VECTOR)
+ if (CONST_VECTOR_P (val))
val = CONST_VECTOR_ELT (val, 0);
if (!CONST_INT_P (val))
{
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index f6e6d68eed2..0741c47bdb6 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -963,11 +963,11 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
to cast them temporarily to integer vectors. */
if (op1
&& !TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL
- && (SUBREG_P (op2) || GET_CODE (op2) == CONST_VECTOR)
+ && (SUBREG_P (op2) || CONST_VECTOR_P (op2))
&& GET_MODE_CLASS (GET_MODE (SUBREG_REG (op1))) == MODE_VECTOR_FLOAT
&& GET_MODE_SIZE (GET_MODE (SUBREG_REG (op1))) == GET_MODE_SIZE (mode)
&& SUBREG_BYTE (op1) == 0
- && (GET_CODE (op2) == CONST_VECTOR
+ && (CONST_VECTOR_P (op2)
|| (GET_MODE (SUBREG_REG (op1)) == GET_MODE (SUBREG_REG (op2))
&& SUBREG_BYTE (op2) == 0))
&& can_create_pseudo_p ())
@@ -982,7 +982,7 @@ ix86_expand_vector_logical_operator (enum rtx_code code, machine_mode mode,
case E_V4DFmode:
case E_V8DFmode:
dst = gen_reg_rtx (GET_MODE (SUBREG_REG (op1)));
- if (GET_CODE (op2) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op2))
{
op2 = gen_lowpart (GET_MODE (dst), op2);
op2 = force_reg (GET_MODE (dst), op2);
@@ -5128,7 +5128,7 @@ ix86_split_to_parts (rtx operand, rtx *parts, machine_mode mode)
return size;
}
- if (GET_CODE (operand) == CONST_VECTOR)
+ if (CONST_VECTOR_P (operand))
{
scalar_int_mode imode = int_mode_for_mode (mode).require ();
/* Caution: if we looked through a constant pool memory above,
@@ -19504,7 +19504,7 @@ const_vector_equal_evenodd_p (rtx op)
{
machine_mode mode = GET_MODE (op);
int i, nunits = GET_MODE_NUNITS (mode);
- if (GET_CODE (op) != CONST_VECTOR
+ if (!CONST_VECTOR_P (op)
|| nunits != CONST_VECTOR_NUNITS (op))
return false;
for (i = 0; i < nunits; i += 2)
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index e278d9c76df..180a0a1c88d 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -12942,7 +12942,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
/* We have patterns that allow zero sets of memory, for instance.
In 64-bit mode, we should probably support all 8-byte vectors,
since we can in fact encode that into an immediate. */
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
{
if (x != CONST0_RTX (GET_MODE (x)))
output_operand_lossage ("invalid vector immediate");
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 5e8f6710137..d36ded363c2 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1017,7 +1017,7 @@
unsigned n_elts;
op = avoid_constant_pool_reference (op);
- if (GET_CODE (op) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (op))
return false;
n_elts = CONST_VECTOR_NUNITS (op);
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 3391724fd8d..a8a529ec18e 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -8634,7 +8634,7 @@
lo insns have =m and 0C constraints. */
: (operands[2] != const0_rtx
|| (!rtx_equal_p (dest, operands[3])
- && GET_CODE (operands[3]) != CONST_VECTOR))))
+ && !CONST_VECTOR_P (operands[3])))))
dest = gen_reg_rtx (<ssehalfvecmode>mode);
switch (INTVAL (operands[2]))
{
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index e1206e2b10e..6896b299ba1 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -5581,7 +5581,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
return;
case 'v':
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
x = simplify_subreg (DImode, x, GET_MODE (x), 0);
break;
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 7f14a077d8d..96dff88c77d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1880,7 +1880,7 @@ mips_symbol_binds_local_p (const_rtx x)
bool
mips_const_vector_bitimm_set_p (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == CONST_VECTOR && op != CONST0_RTX (mode))
+ if (CONST_VECTOR_P (op) && op != CONST0_RTX (mode))
{
unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
@@ -1902,7 +1902,7 @@ mips_const_vector_bitimm_set_p (rtx op, machine_mode mode)
bool
mips_const_vector_bitimm_clr_p (rtx op, machine_mode mode)
{
- if (GET_CODE (op) == CONST_VECTOR && op != CONSTM1_RTX (mode))
+ if (CONST_VECTOR_P (op) && op != CONSTM1_RTX (mode))
{
unsigned HOST_WIDE_INT val = ~UINTVAL (CONST_VECTOR_ELT (op, 0));
int vlog2 = exact_log2 (val & GET_MODE_MASK (GET_MODE_INNER (mode)));
@@ -1927,7 +1927,7 @@ mips_const_vector_same_val_p (rtx op, machine_mode mode)
int i, nunits = GET_MODE_NUNITS (mode);
rtx first;
- if (GET_CODE (op) != CONST_VECTOR || GET_MODE (op) != mode)
+ if (!CONST_VECTOR_P (op) || GET_MODE (op) != mode)
return false;
first = CONST_VECTOR_ELT (op, 0);
@@ -9026,7 +9026,7 @@ mips_print_operand (FILE *file, rtx op, int letter)
switch (letter)
{
case 'E':
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
gcc_assert (mips_const_vector_same_val_p (op, GET_MODE (op)));
op = CONST_VECTOR_ELT (op, 0);
@@ -9059,7 +9059,7 @@ mips_print_operand (FILE *file, rtx op, int letter)
break;
case 'B':
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
gcc_assert (mips_const_vector_same_val_p (op, GET_MODE (op)));
op = CONST_VECTOR_ELT (op, 0);
@@ -9092,7 +9092,7 @@ mips_print_operand (FILE *file, rtx op, int letter)
break;
case 'V':
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
machine_mode mode = GET_MODE_INNER (GET_MODE (op));
unsigned HOST_WIDE_INT val = UINTVAL (CONST_VECTOR_ELT (op, 0));
diff --git a/gcc/config/nds32/nds32-dspext.md b/gcc/config/nds32/nds32-dspext.md
index 116cb7f599a..578c623504b 100644
--- a/gcc/config/nds32/nds32-dspext.md
+++ b/gcc/config/nds32/nds32-dspext.md
@@ -29,7 +29,7 @@
/* If operands[1] is a large constant and cannot be performed
by a single instruction, we need to split it. */
- if (GET_CODE (operands[1]) == CONST_VECTOR
+ if (CONST_VECTOR_P (operands[1])
&& !satisfies_constraint_CVs2 (operands[1])
&& !satisfies_constraint_CVhi (operands[1]))
{
diff --git a/gcc/config/nds32/predicates.md b/gcc/config/nds32/predicates.md
index 79ae8ea2a34..9983eb4c409 100644
--- a/gcc/config/nds32/predicates.md
+++ b/gcc/config/nds32/predicates.md
@@ -129,7 +129,7 @@
{
/* If the constant op does NOT satisfy Is20 nor Ihig,
we cannot perform move behavior by a single instruction. */
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !satisfies_constraint_CVs2 (op)
&& !satisfies_constraint_CVhi (op))
return false;
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 4e77063249a..62bf292b42b 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -1045,7 +1045,7 @@
return 1;
/* Allow easy vector constants. */
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& easy_vector_constant (op, mode))
return 1;
diff --git a/gcc/config/rs6000/rs6000-p8swap.c b/gcc/config/rs6000/rs6000-p8swap.c
index c3b98315503..ffe5d9a925f 100644
--- a/gcc/config/rs6000/rs6000-p8swap.c
+++ b/gcc/config/rs6000/rs6000-p8swap.c
@@ -595,7 +595,7 @@ const_load_sequence_p (swap_web_entry *insn_entry, rtx insn)
if (SYMBOL_REF_P (const_vector)
&& CONSTANT_POOL_ADDRESS_P (const_vector))
const_vector = get_pool_constant (const_vector);
- if (GET_CODE (const_vector) != CONST_VECTOR)
+ if (!CONST_VECTOR_P (const_vector))
return false;
}
}
@@ -1116,7 +1116,7 @@ swap_const_vector_halves (rtx *op_ptr)
int i;
rtx op = *op_ptr;
enum rtx_code code = GET_CODE (op);
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
int units = GET_MODE_NUNITS (GET_MODE (op));
rtx_vector_builder builder (GET_MODE (op), units, 1);
@@ -1371,7 +1371,7 @@ adjust_vperm (rtx_insn *insn)
constant. */
if (SYMBOL_REF_P (const_vector))
const_vector = get_pool_constant (const_vector);
- gcc_assert (GET_CODE (const_vector) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (const_vector));
/* Create an adjusted mask from the initial mask. */
unsigned int new_mask[16], i, val;
@@ -1851,7 +1851,7 @@ replace_swapped_load_constant (swap_web_entry *insn_entry, rtx swap_insn)
constant. */
if (SYMBOL_REF_P (const_vector))
const_vector = get_pool_constant (const_vector);
- gcc_assert (GET_CODE (const_vector) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (const_vector));
rtx new_mem;
enum machine_mode mode = GET_MODE (const_vector);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1650adda137..d84e743c1af 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6004,7 +6004,7 @@ xxspltib_constant_p (rtx op,
}
/* Handle (const_vector [...]). */
- else if (GET_CODE (op) == CONST_VECTOR)
+ else if (CONST_VECTOR_P (op))
{
if (mode != V16QImode && mode != V8HImode && mode != V4SImode
&& mode != V2DImode)
@@ -11814,7 +11814,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass)
/* If this is a vector constant that can be formed with a few Altivec
instructions, we want altivec registers. */
- if (GET_CODE (x) == CONST_VECTOR && easy_vector_constant (x, mode))
+ if (CONST_VECTOR_P (x) && easy_vector_constant (x, mode))
return ALTIVEC_REGS;
/* If this is an integer constant that can easily be loaded into
@@ -12316,7 +12316,7 @@ rs6000_output_move_128bit (rtx operands[])
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
|| CONST_DOUBLE_P (src)
- || GET_CODE (src) == CONST_VECTOR))
+ || CONST_VECTOR_P (src)))
{
if (dest_gpr_p)
return "#";
@@ -14646,8 +14646,8 @@ rs6000_emit_vector_cond_expr (rtx dest, rtx op_true, rtx op_false,
/* Optimize vec1 == vec2, to know the mask generates -1/0. */
if (GET_MODE_CLASS (dest_mode) == MODE_VECTOR_INT
- && (GET_CODE (op_true) == CONST_VECTOR
- || GET_CODE (op_false) == CONST_VECTOR))
+ && (CONST_VECTOR_P (op_true)
+ || CONST_VECTOR_P (op_false)))
{
rtx constant_0 = CONST0_RTX (dest_mode);
rtx constant_m1 = CONSTM1_RTX (dest_mode);
@@ -24116,7 +24116,7 @@ rs6000_legitimate_constant_p (machine_mode mode, rtx x)
if (CONST_DOUBLE_P (x))
return easy_fp_constant (x, mode);
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
return easy_vector_constant (x, mode);
return true;
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index ff6d41ea6f0..31fc179645d 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2494,7 +2494,7 @@ s390_bytemask_vector_p (rtx op, unsigned *mask)
int nunit, unit_size;
if (!VECTOR_MODE_P (GET_MODE (op))
- || GET_CODE (op) != CONST_VECTOR
+ || !CONST_VECTOR_P (op)
|| !CONST_INT_P (XVECEXP (op, 0, 0)))
return false;
@@ -4040,7 +4040,7 @@ legitimate_pic_operand_p (rtx op)
static bool
s390_legitimate_constant_p (machine_mode mode, rtx op)
{
- if (TARGET_VX && VECTOR_MODE_P (mode) && GET_CODE (op) == CONST_VECTOR)
+ if (TARGET_VX && VECTOR_MODE_P (mode) && CONST_VECTOR_P (op))
{
if (GET_MODE_SIZE (mode) != 16)
return 0;
@@ -4419,7 +4419,7 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
Force it back in. */
if (CONST_INT_P (mem) || CONST_DOUBLE_P (mem)
|| CONST_WIDE_INT_P (mem)
- || GET_CODE (mem) == CONST_VECTOR
+ || CONST_VECTOR_P (mem)
|| GET_CODE (mem) == CONST)
mem = force_const_mem (GET_MODE (reg), mem);
@@ -9285,7 +9285,7 @@ s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align)
{
int i;
machine_mode inner_mode;
- gcc_assert (GET_CODE (exp) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (exp));
inner_mode = GET_MODE_INNER (GET_MODE (exp));
for (i = 0; i < XVECLEN (exp, 0); i++)
diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md
index 6a2b38eadef..2b51d015cf3 100644
--- a/gcc/config/spu/predicates.md
+++ b/gcc/config/spu/predicates.md
@@ -65,7 +65,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (CONST_INT_P (op) || GET_CODE (op) == CONST_VECTOR)
+ if (CONST_INT_P (op) || CONST_VECTOR_P (op))
return arith_immediate_p (op, mode, -0x200, 0x1ff);
return 0;
})
@@ -76,7 +76,7 @@
if (spu_reg_operand (op, mode))
return 1;
if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
return logical_immediate_p (op, mode);
return 0;
})
@@ -87,7 +87,7 @@
if (spu_reg_operand (op, mode))
return 1;
if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
return logical_immediate_p (op, mode)
|| iohl_immediate_p (op, mode);
return 0;
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index b2ca39a6fb0..fe893b62a9e 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -1277,7 +1277,7 @@ print_operand (FILE * file, rtx x, int code)
case IC_IL1s:
if (xcode == HIGH)
x = XEXP (x, 0);
- if (GET_CODE (x) == CONST_VECTOR)
+ if (CONST_VECTOR_P (x))
x = CONST_VECTOR_ELT (x, 0);
output_addr_const (file, x);
if (xcode == HIGH)
@@ -3173,7 +3173,7 @@ classify_immediate (rtx op, machine_mode mode)
/* A V4SI const_vector with all identical symbols is ok. */
if (!flag_pic
&& mode == V4SImode
- && GET_CODE (op) == CONST_VECTOR
+ && CONST_VECTOR_P (op)
&& !CONST_INT_P (CONST_VECTOR_ELT (op, 0))
&& !CONST_DOUBLE_P (CONST_VECTOR_ELT (op, 0)))
op = unwrap_const_vec_duplicate (op);
@@ -3287,7 +3287,7 @@ static int
const_vector_immediate_p (rtx x)
{
int i;
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
for (i = 0; i < GET_MODE_NUNITS (GET_MODE (x)); i++)
if (!CONST_INT_P (CONST_VECTOR_ELT (x, i))
&& !CONST_DOUBLE_P (CONST_VECTOR_ELT (x, i)))
@@ -3303,9 +3303,9 @@ logical_immediate_p (rtx op, machine_mode mode)
int i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3335,9 +3335,9 @@ iohl_immediate_p (rtx op, machine_mode mode)
int i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3367,9 +3367,9 @@ arith_immediate_p (rtx op, machine_mode mode,
int bytes, i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3408,9 +3408,9 @@ exp2_immediate_p (rtx op, machine_mode mode, int low, int high)
int bytes, i, j;
gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
- || GET_CODE (op) == CONST_VECTOR);
+ || CONST_VECTOR_P (op));
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& !const_vector_immediate_p (op))
return 0;
@@ -3496,7 +3496,7 @@ spu_legitimate_constant_p (machine_mode mode, rtx x)
|| GET_CODE (CONST_VECTOR_ELT (x, 0)) == CONST))
return const_vec_duplicate_p (x);
- if (GET_CODE (x) == CONST_VECTOR
+ if (CONST_VECTOR_P (x)
&& !const_vector_immediate_p (x))
return 0;
return 1;
@@ -5067,7 +5067,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
val >>= 8;
}
}
- else if (GET_CODE (x) == CONST_VECTOR)
+ else if (CONST_VECTOR_P (x))
{
int units;
rtx elt;
@@ -6355,7 +6355,7 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
}
else if (CONST_INT_P (op))
v = INTVAL (op);
- else if (GET_CODE (op) == CONST_VECTOR
+ else if (CONST_VECTOR_P (op)
&& CONST_INT_P (CONST_VECTOR_ELT (op, 0)))
v = INTVAL (CONST_VECTOR_ELT (op, 0));
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index cdc7561e54e..b6cf8115c13 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -5299,7 +5299,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
i = INTVAL (x);
else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
- else if (GET_CODE (x) == CONST_VECTOR
+ else if (CONST_VECTOR_P (x)
&& CONST_INT_P (CONST_VECTOR_ELT (x, 0)))
i = INTVAL (CONST_VECTOR_ELT (x, 0));
else
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 6473ff20fff..f2e24858970 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -4619,7 +4619,7 @@ tilepro_print_operand (FILE *file, rtx x, int code)
i = INTVAL (x);
else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
- else if (GET_CODE (x) == CONST_VECTOR
+ else if (CONST_VECTOR_P (x)
&& CONST_INT_P (CONST_VECTOR_ELT (x, 0)))
i = INTVAL (CONST_VECTOR_ELT (x, 0));
else
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index 63cb01c8198..c84885a24bb 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -16813,7 +16813,7 @@ loc_descriptor (rtx rtl, machine_mode mode,
if (mode == VOIDmode
|| CONST_SCALAR_INT_P (XEXP (rtl, 0))
|| CONST_DOUBLE_AS_FLOAT_P (XEXP (rtl, 0))
- || GET_CODE (XEXP (rtl, 0)) == CONST_VECTOR)
+ || CONST_VECTOR_P (XEXP (rtl, 0)))
{
loc_result = loc_descriptor (XEXP (rtl, 0), mode, initialized);
break;
diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c
index a667cdab94e..7a811548149 100644
--- a/gcc/emit-rtl.c
+++ b/gcc/emit-rtl.c
@@ -1596,7 +1596,7 @@ gen_lowpart_common (machine_mode mode, rtx x)
return gen_rtx_fmt_e (GET_CODE (x), int_mode, XEXP (x, 0));
}
else if (GET_CODE (x) == SUBREG || REG_P (x)
- || GET_CODE (x) == CONCAT || GET_CODE (x) == CONST_VECTOR
+ || GET_CODE (x) == CONCAT || CONST_VECTOR_P (x)
|| CONST_DOUBLE_AS_FLOAT_P (x) || CONST_SCALAR_INT_P (x)
|| CONST_POLY_INT_P (x))
return lowpart_subreg (mode, x, innermode);
@@ -6004,7 +6004,7 @@ gen_vec_duplicate (machine_mode mode, rtx x)
/* A subroutine of const_vec_series_p that handles the case in which:
- (GET_CODE (X) == CONST_VECTOR
+ (CONST_VECTOR_P (X)
&& CONST_VECTOR_NPATTERNS (X) == 1
&& !CONST_VECTOR_DUPLICATE_P (X))
diff --git a/gcc/explow.c b/gcc/explow.c
index c74c689aead..3253898b66e 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -122,7 +122,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
{
rtx cst = get_pool_constant (XEXP (x, 0));
- if (GET_CODE (cst) == CONST_VECTOR
+ if (CONST_VECTOR_P (cst)
&& GET_MODE_INNER (GET_MODE (cst)) == mode)
{
cst = gen_lowpart (mode, cst);
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index 7da11b399ba..c33d6cbc967 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -2850,7 +2850,7 @@ may_trap_p_1 (const_rtx x, unsigned flags)
return flag_trapping_math;
if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx))
return 1;
- if (GET_CODE (XEXP (x, 1)) == CONST_VECTOR)
+ if (CONST_VECTOR_P (XEXP (x, 1)))
{
/* For CONST_VECTOR, return 1 if any element is or might be zero. */
unsigned int n_elts;
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 9359a3cdb4d..603bc456354 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -1736,7 +1736,7 @@ simplify_const_unary_operation (enum rtx_code code, machine_mode mode,
}
if (CONST_SCALAR_INT_P (op) || CONST_DOUBLE_AS_FLOAT_P (op))
return gen_const_vec_duplicate (mode, op);
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& (CONST_VECTOR_DUPLICATE_P (op)
|| CONST_VECTOR_NUNITS (op).is_constant ()))
{
@@ -1752,7 +1752,7 @@ simplify_const_unary_operation (enum rtx_code code, machine_mode mode,
}
if (VECTOR_MODE_P (mode)
- && GET_CODE (op) == CONST_VECTOR
+ && CONST_VECTOR_P (op)
&& known_eq (GET_MODE_NUNITS (mode), CONST_VECTOR_NUNITS (op)))
{
gcc_assert (GET_MODE (op) == op_mode);
@@ -3642,7 +3642,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
if (vec_duplicate_p (trueop0, &elt0))
return elt0;
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
return CONST_VECTOR_ELT (trueop0, INTVAL (XVECEXP
(trueop1, 0, 0)));
@@ -3725,7 +3725,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
because they are all the same. */
return gen_vec_duplicate (mode, elt0);
- if (GET_CODE (trueop0) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0))
{
unsigned n_elts = XVECLEN (trueop1, 0);
rtvec v = rtvec_alloc (n_elts);
@@ -3968,10 +3968,10 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
gcc_assert (GET_MODE_INNER (mode) == op1_mode);
unsigned int n_elts, in_n_elts;
- if ((GET_CODE (trueop0) == CONST_VECTOR
+ if ((CONST_VECTOR_P (trueop0)
|| CONST_SCALAR_INT_P (trueop0)
|| CONST_DOUBLE_AS_FLOAT_P (trueop0))
- && (GET_CODE (trueop1) == CONST_VECTOR
+ && (CONST_VECTOR_P (trueop1)
|| CONST_SCALAR_INT_P (trueop1)
|| CONST_DOUBLE_AS_FLOAT_P (trueop1))
&& GET_MODE_NUNITS (mode).is_constant (&n_elts)
@@ -4084,8 +4084,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
{
if (VECTOR_MODE_P (mode)
&& code != VEC_CONCAT
- && GET_CODE (op0) == CONST_VECTOR
- && GET_CODE (op1) == CONST_VECTOR)
+ && CONST_VECTOR_P (op0)
+ && CONST_VECTOR_P (op1))
{
bool step_ok_p;
if (CONST_VECTOR_STEPPED_P (op0)
@@ -4145,8 +4145,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
gcc_assert (n_elts >= 2);
if (n_elts == 2)
{
- gcc_assert (GET_CODE (op0) != CONST_VECTOR);
- gcc_assert (GET_CODE (op1) != CONST_VECTOR);
+ gcc_assert (!CONST_VECTOR_P (op0));
+ gcc_assert (!CONST_VECTOR_P (op1));
RTVEC_ELT (v, 0) = op0;
RTVEC_ELT (v, 1) = op1;
@@ -4157,8 +4157,8 @@ simplify_const_binary_operation (enum rtx_code code, machine_mode mode,
unsigned op1_n_elts = GET_MODE_NUNITS (GET_MODE (op1)).to_constant ();
unsigned i;
- gcc_assert (GET_CODE (op0) == CONST_VECTOR);
- gcc_assert (GET_CODE (op1) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (op0));
+ gcc_assert (CONST_VECTOR_P (op1));
gcc_assert (op0_n_elts + op1_n_elts == n_elts);
for (i = 0; i < op0_n_elts; ++i)
@@ -5833,7 +5833,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
if (VECTOR_MODE_P (GET_MODE (op1))
&& GET_CODE (op0) == NE
&& GET_CODE (XEXP (op0, 0)) == NOT
- && GET_CODE (XEXP (op0, 1)) == CONST_VECTOR)
+ && CONST_VECTOR_P (XEXP (op0, 1)))
{
rtx cv = XEXP (op0, 1);
int nunits;
@@ -5937,8 +5937,8 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
rtx trueop0 = avoid_constant_pool_reference (op0);
rtx trueop1 = avoid_constant_pool_reference (op1);
- if (GET_CODE (trueop0) == CONST_VECTOR
- && GET_CODE (trueop1) == CONST_VECTOR)
+ if (CONST_VECTOR_P (trueop0)
+ && CONST_VECTOR_P (trueop1))
{
rtvec v = rtvec_alloc (n_elts);
unsigned int i;
@@ -6001,7 +6001,7 @@ simplify_ternary_operation (enum rtx_code code, machine_mode mode,
with (vec_concat (X) (B)) if N == 1 or
(vec_concat (A) (X)) if N == 2. */
if (GET_CODE (op0) == VEC_DUPLICATE
- && GET_CODE (op1) == CONST_VECTOR
+ && CONST_VECTOR_P (op1)
&& known_eq (CONST_VECTOR_NUNITS (op1), 2)
&& known_eq (GET_MODE_NUNITS (GET_MODE (op0)), 2)
&& IN_RANGE (sel, 1, 2))
@@ -6177,7 +6177,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
/* Unpack the value. */
- if (GET_CODE (op) == CONST_VECTOR)
+ if (CONST_VECTOR_P (op))
{
num_elem = CEIL (inner_bytes, GET_MODE_UNIT_SIZE (innermode));
elem_bitsize = GET_MODE_UNIT_BITSIZE (innermode);
@@ -6195,7 +6195,7 @@ simplify_immed_subreg (fixed_size_mode outermode, rtx op,
for (elem = 0; elem < num_elem; elem++)
{
unsigned char * vp;
- rtx el = (GET_CODE (op) == CONST_VECTOR
+ rtx el = (CONST_VECTOR_P (op)
? CONST_VECTOR_ELT (op, first_elem + elem)
: op);
@@ -6511,7 +6511,7 @@ simplify_subreg (machine_mode outermode, rtx op,
if (CONST_SCALAR_INT_P (op)
|| CONST_DOUBLE_AS_FLOAT_P (op)
|| CONST_FIXED_P (op)
- || GET_CODE (op) == CONST_VECTOR)
+ || CONST_VECTOR_P (op))
{
/* simplify_immed_subreg deconstructs OP into bytes and constructs
the result from bytes, so it only works if the sizes of the modes
@@ -6528,7 +6528,7 @@ simplify_subreg (machine_mode outermode, rtx op,
/* Handle constant-sized outer modes and variable-sized inner modes. */
unsigned HOST_WIDE_INT first_elem;
- if (GET_CODE (op) == CONST_VECTOR
+ if (CONST_VECTOR_P (op)
&& is_a <fixed_size_mode> (outermode, &fs_outermode)
&& constant_multiple_p (byte, GET_MODE_UNIT_SIZE (innermode),
&first_elem))
diff --git a/gcc/varasm.c b/gcc/varasm.c
index 0e833b9bc58..e6263f09226 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -3973,7 +3973,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align)
case MODE_VECTOR_BOOL:
{
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
/* Pick the smallest integer mode that contains at least one
whole element. Often this is byte_mode and contains more
@@ -4008,7 +4008,7 @@ output_constant_pool_2 (fixed_size_mode mode, rtx x, unsigned int align)
scalar_mode submode = GET_MODE_INNER (mode);
unsigned int subalign = MIN (align, GET_MODE_BITSIZE (submode));
- gcc_assert (GET_CODE (x) == CONST_VECTOR);
+ gcc_assert (CONST_VECTOR_P (x));
units = GET_MODE_NUNITS (mode);
for (i = 0; i < units; i++)
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 06/18] Use CONST_DOUBLE_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_DOUBLE
2019-08-06 3:11 ` Arvind Sankar
` (3 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 15/18] Use LABEL_REF_P macro Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 12/18] Use SUBREG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SUBREG Arvind Sankar
` (12 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* config/aarch64/aarch64.c: Convert
GET_CODE (..) == CONST_DOUBLE to CONST_DOUBLE_P (..).
* config/aarch64/aarch64.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/arc.md: Likewise.
* config/arc/fpx.md: Likewise.
* config/bfin/bfin.md: Likewise.
* config/c6x/c6x.h: Likewise.
* config/c6x/c6x.md: Likewise.
* config/cr16/predicates.md: Likewise.
* config/cris/cris.c: Likewise.
* config/cris/cris.md: Likewise.
* config/csky/csky.c: Likewise.
* config/darwin.c: Likewise.
* config/fr30/fr30.c: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/frv.h: Likewise.
* config/gcn/gcn-valu.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/vect.md: Likewise.
* config/iq2000/iq2000.md: Likewise.
* config/lm32/lm32.c: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.md: Likewise.
* config/m68k/predicates.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/mips/mips.c: Likewise.
* config/mips/mips.md: Likewise.
* config/mmix/mmix.c: Likewise.
* config/mmix/predicates.md: Likewise.
* config/nds32/constraints.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/nds32.c: Likewise.
* config/nds32/nds32.h: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c: Likewise.
* config/s390/s390.c: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/predicates.md: Likewise.
* config/spu/spu.c: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilepro/tilepro.c: Likewise.
* config/v850/predicates.md: Likewise.
* config/v850/v850.c: Likewise.
* config/vax/vax.c: Likewise.
* config/vax/vax.md: Likewise.
* config/visium/visium.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* defaults.h: Likewise.
* genpreds.c: Likewise.
* recog.c: Likewise.
* reg-stack.c: Likewise.
59 files changed, 161 insertions(+), 161 deletions(-)
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index a526b8be522..68ad4858c76 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -7057,7 +7057,7 @@ aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *intval)
}
scalar_float_mode mode;
- if (GET_CODE (value) != CONST_DOUBLE
+ if (!CONST_DOUBLE_P (value)
|| !is_a <scalar_float_mode> (GET_MODE (value), &mode)
|| GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
/* Only support up to DF mode. */
@@ -7097,7 +7097,7 @@ aarch64_float_const_rtx_p (rtx x)
mov/movk pairs over ldr/adrp pairs. */
unsigned HOST_WIDE_INT ival;
- if (GET_CODE (x) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (x)
&& SCALAR_FLOAT_MODE_P (mode)
&& aarch64_reinterpret_float_as_int (x, &ival))
{
@@ -7136,7 +7136,7 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode)
scalar_int_mode imode;
unsigned HOST_WIDE_INT ival;
- if (GET_CODE (x) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (x)
&& SCALAR_FLOAT_MODE_P (mode))
{
if (!aarch64_reinterpret_float_as_int (x, &ival))
@@ -14426,7 +14426,7 @@ aarch64_sve_float_arith_immediate_p (rtx x, bool negate_p)
REAL_VALUE_TYPE r;
if (!const_vec_duplicate_p (x, &elt)
- || GET_CODE (elt) != CONST_DOUBLE)
+ || !CONST_DOUBLE_P (elt))
return false;
r = *CONST_DOUBLE_REAL_VALUE (elt);
@@ -14452,7 +14452,7 @@ aarch64_sve_float_mul_immediate_p (rtx x)
/* GCC will never generate a multiply with an immediate of 2, so there is no
point testing for it (even though it is a valid constant). */
return (const_vec_duplicate_p (x, &elt)
- && GET_CODE (elt) == CONST_DOUBLE
+ && CONST_DOUBLE_P (elt)
&& real_equal (CONST_DOUBLE_REAL_VALUE (elt), &dconsthalf));
}
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 873f2760cce..1fe96d5f772 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1246,7 +1246,7 @@
}
if (GET_CODE (operands[0]) == MEM
- && ! (GET_CODE (operands[1]) == CONST_DOUBLE
+ && ! (CONST_DOUBLE_P (operands[1])
&& aarch64_float_const_zero_rtx_p (operands[1])))
operands[1] = force_reg (<MODE>mode, operands[1]);
}
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 486053c98ca..abdb51fbb31 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -2390,7 +2390,7 @@ arc_double_limm_p (rtx value)
{
HOST_WIDE_INT low, high;
- gcc_assert (GET_CODE (value) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (value));
if (TARGET_DPFP)
return true;
@@ -4692,7 +4692,7 @@ arc_print_operand (FILE *file, rtx x, int code)
fputs (reg_names[REGNO (x)+1], file);
}
else if (CONST_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE)
+ || CONST_DOUBLE_P (x))
{
rtx first, second, word;
@@ -4712,7 +4712,7 @@ arc_print_operand (FILE *file, rtx x, int code)
{
char str[30];
- gcc_assert (GET_CODE (x) == CONST_DOUBLE
+ gcc_assert (CONST_DOUBLE_P (x)
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT);
real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1);
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 7cd47338ec2..63b65d533a4 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -5637,7 +5637,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
"
if (TARGET_DPFP)
{
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[2]))
{
rtx first, second, tmp;
split_double (operands[2], &first, &second);
@@ -5671,13 +5671,13 @@ core_3, archs4x, archs4xd, archs4xd_slow"
"
if (TARGET_DPFP)
{
- if (TARGET_FP_DP_AX && (GET_CODE (operands[1]) == CONST_DOUBLE))
+ if (TARGET_FP_DP_AX && (CONST_DOUBLE_P (operands[1])))
operands[1] = force_reg (DFmode, operands[1]);
- if ((GET_CODE (operands[1]) == CONST_DOUBLE)
- || GET_CODE (operands[2]) == CONST_DOUBLE)
+ if ((CONST_DOUBLE_P (operands[1]))
+ || CONST_DOUBLE_P (operands[2]))
{
rtx first, second, tmp;
- int const_index = ((GET_CODE (operands[1]) == CONST_DOUBLE) ? 1 : 2);
+ int const_index = ((CONST_DOUBLE_P (operands[1])) ? 1 : 2);
split_double (operands[const_index], &first, &second);
tmp = force_reg (SImode, TARGET_BIG_ENDIAN ? first : second);
emit_insn (gen_subdf3_insn (operands[0], operands[1],
@@ -5709,7 +5709,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
"
if (TARGET_DPFP)
{
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[2]))
{
rtx first, second, tmp;
split_double (operands[2], &first, &second);
diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md
index 0d0230baff0..e13e10bf7df 100644
--- a/gcc/config/arc/fpx.md
+++ b/gcc/config/arc/fpx.md
@@ -239,7 +239,7 @@
(use (match_dup 2))
]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
+ !(CONST_DOUBLE_P (operands[2]) && CONST_INT_P (operands[3]))"
"@
daddh%F0%F1 0,%H2,%L2
daddh%F0%F1 0,%3,%L2"
@@ -263,7 +263,7 @@
(use (match_dup 2))
]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
+ !(CONST_DOUBLE_P (operands[2]) && CONST_INT_P (operands[3]))"
"@
dmulh%F0%F1 0,%H2,%L2
dmulh%F0%F1 0,%3, %L2"
@@ -294,8 +294,8 @@
; different USE pairs.
(use (match_dup 2))]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3])) &&
- !(GET_CODE(operands[1]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
+ !(CONST_DOUBLE_P (operands[2]) && CONST_INT_P (operands[3])) &&
+ !(CONST_DOUBLE_P (operands[1]) && CONST_INT_P (operands[3]))"
"@
dsubh%F0%F1 0,%H2,%L2
dsubh%F0%F1 0,%3,%L2
@@ -553,7 +553,7 @@
(plus:DF (match_dup 1)
(match_dup 2)))])]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
+ !(CONST_DOUBLE_P (operands[2]) && CONST_INT_P (operands[3]))"
"@
daddh%F0%F1 %H6, %H2, %L2
daddh%F0%F1 %H6, %3, %L2"
@@ -576,7 +576,7 @@
(mult:DF (match_dup 1)
(match_dup 2)))])]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
+ !(CONST_DOUBLE_P (operands[2]) && CONST_INT_P (operands[3]))"
"@
dmulh%F0%F1 %H6, %H2, %L2
dmulh%F0%F1 %H6, %3, %L2"
@@ -604,8 +604,8 @@
(minus:DF (match_dup 1)
(match_dup 2)))])]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3])) &&
- !(GET_CODE(operands[1]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
+ !(CONST_DOUBLE_P (operands[2]) && CONST_INT_P (operands[3])) &&
+ !(CONST_DOUBLE_P (operands[1]) && CONST_INT_P (operands[3]))"
"@
dsubh%F0%F1 %H6, %H2, %L2
dsubh%F0%F1 %H6, %3, %L2
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 2adc3273901..b2b5f04d6c5 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -850,7 +850,7 @@
{
long values;
- gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (operands[1]));
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), values);
diff --git a/gcc/config/c6x/c6x.h b/gcc/config/c6x/c6x.h
index c605b73fe5a..06f85e41d76 100644
--- a/gcc/config/c6x/c6x.h
+++ b/gcc/config/c6x/c6x.h
@@ -369,7 +369,7 @@ struct c6x_args {
\f
/* Addressing Modes. */
-#define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE)
+#define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && !CONST_DOUBLE_P (x))
#define MAX_REGS_PER_ADDRESS 2
#define HAVE_PRE_DECREMENT 1
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 56cd0c5e8d6..3707e80697c 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -550,7 +550,7 @@
{
long values;
- gcc_assert (GET_CODE (operands[1]) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (operands[1]));
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (operands[1]), values);
diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md
index 755ad8fca5e..b1e3193889f 100644
--- a/gcc/config/cr16/predicates.md
+++ b/gcc/config/cr16/predicates.md
@@ -32,7 +32,7 @@
(define_predicate "u4bits_operand"
(match_code "const_int,const_double")
{
- if (GET_CODE (op) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op))
return cr16_const_double_ok (op);
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 4)) ? 1 : 0;
})
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 88de088fc9f..67d7c316841 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -1003,7 +1003,7 @@ cris_print_operand (FILE *file, rtx x, int code)
case 'M':
/* Print the least significant part of operand. */
- if (GET_CODE (operand) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operand))
{
fprintf (file, HOST_WIDE_INT_PRINT_HEX, CONST_DOUBLE_LOW (x));
return;
@@ -2914,7 +2914,7 @@ cris_split_movdx (rtx *operands)
operand_subword (src, !reverse, TRUE, mode)));
}
/* Constant-to-reg copy. */
- else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
+ else if (CONST_INT_P (src) || CONST_DOUBLE_P (src))
{
rtx words[2];
split_double (src, &words[0], &words[1]);
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 12421bf2c3b..0c7ac21b2c7 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -509,7 +509,7 @@
resulting subreg sets when using the construct from mcore (as of FSF
CVS, version -r 1.5), and it believes that the high part (the last one
emitted) is the final value. */
- if ((CONST_INT_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
+ if ((CONST_INT_P (operands[1]) || CONST_DOUBLE_P (operands[1]))
&& ! reload_completed
&& ! reload_in_progress)
{
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 5e8b14e7665..85850c8be1f 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -4013,13 +4013,13 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
}
/* The situation mov integer to reg. */
else if (CONST_INT_P (src) ||
- (GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode))
+ (CONST_DOUBLE_P (src) && GET_MODE (src) == SFmode))
{
HOST_WIDE_INT x, y;
const REAL_VALUE_TYPE *d;
long l;
- if (GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode)
+ if (CONST_DOUBLE_P (src) && GET_MODE (src) == SFmode)
{
d = CONST_DOUBLE_REAL_VALUE (src);
REAL_VALUE_TO_TARGET_SINGLE (*d, l);
@@ -4141,7 +4141,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "lrw\t%0, %x1\t";
}
- else if (GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode)
+ else if (CONST_DOUBLE_P (src) && GET_MODE (src) == SFmode)
{
const REAL_VALUE_TYPE *d;
long l;
@@ -4290,7 +4290,7 @@ csky_output_movedouble (rtx operands[],
else
return "ld.w\t%0, %1\n\tld.w\t%R0, %R1";
}
- else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
+ else if (CONST_INT_P (src) || CONST_DOUBLE_P (src))
{
split_double (src, operands + 2, operands + 3);
@@ -4416,7 +4416,7 @@ csky_output_ck801_movedouble (rtx operands[],
else
return "ld.w\t%0, %1\n\tld.w\t%R0, %R1";
}
- else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
+ else if (CONST_INT_P (src) || CONST_DOUBLE_P (src))
{
split_double (src, operands + 2, operands + 3);
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 6eaccd73a9f..3076650abaa 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -1752,19 +1752,19 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
if (GET_MODE_SIZE (mode) == 8
&& (CONST_INT_P (x)
|| CONST_WIDE_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE))
+ || CONST_DOUBLE_P (x)))
return darwin_sections[literal8_section];
else if (GET_MODE_SIZE (mode) == 4
&& (CONST_INT_P (x)
|| CONST_WIDE_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE))
+ || CONST_DOUBLE_P (x)))
return darwin_sections[literal4_section];
else if (HAVE_GAS_LITERAL16
&& TARGET_64BIT
&& GET_MODE_SIZE (mode) == 16
&& (CONST_INT_P (x)
|| CONST_WIDE_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE
+ || CONST_DOUBLE_P (x)
|| GET_CODE (x) == CONST_VECTOR))
return darwin_sections[literal16_section];
else if (MACHOPIC_INDIRECT
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
index 54e5766241f..e31d4f1266d 100644
--- a/gcc/config/fr30/fr30.c
+++ b/gcc/config/fr30/fr30.c
@@ -603,7 +603,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
return;
case 'F':
- if (GET_CODE (x) != CONST_DOUBLE)
+ if (!CONST_DOUBLE_P (x))
output_operand_lossage ("fr30_print_operand: invalid %%F code");
else
{
@@ -879,7 +879,7 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending)
int
fr30_const_double_is_zero (rtx operand)
{
- if (operand == NULL || GET_CODE (operand) != CONST_DOUBLE)
+ if (operand == NULL || !CONST_DOUBLE_P (operand))
return 0;
return real_equal (CONST_DOUBLE_REAL_VALUE (operand), &dconst0);
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index bccd1efa58a..c3d9408f21b 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -2738,7 +2738,7 @@ frv_print_operand (FILE * file, rtx x, int code)
else if (CONST_INT_P (x))
value = INTVAL (x);
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
{
if (GET_MODE (x) == SFmode)
{
@@ -2976,7 +2976,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'x':
/* Print constant in hex. */
- if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_INT_P (x) || CONST_DOUBLE_P (x))
{
fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
break;
@@ -2989,7 +2989,7 @@ frv_print_operand (FILE * file, rtx x, int code)
fputs (reg_names [REGNO (x)], file);
else if (CONST_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE)
+ || CONST_DOUBLE_P (x))
fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
else if (frv_const_unspec_p (x, &unspec))
@@ -4253,7 +4253,7 @@ output_move_single (rtx operands[], rtx insn)
}
else if (CONST_INT_P (src)
- || GET_CODE (src) == CONST_DOUBLE)
+ || CONST_DOUBLE_P (src))
{
/* gpr <- integer/floating constant */
HOST_WIDE_INT value;
@@ -4459,7 +4459,7 @@ output_move_double (rtx operands[], rtx insn)
}
else if (CONST_INT_P (src)
- || GET_CODE (src) == CONST_DOUBLE)
+ || CONST_DOUBLE_P (src))
return "#";
}
@@ -6641,7 +6641,7 @@ frv_legitimate_constant_p (machine_mode mode, rtx x)
return LEGITIMATE_PIC_OPERAND_P (x);
/* All of the integer constants are ok. */
- if (GET_CODE (x) != CONST_DOUBLE)
+ if (!CONST_DOUBLE_P (x))
return TRUE;
/* double integer constants are ok. */
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 219153368ae..7e108211e7b 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1471,7 +1471,7 @@ __asm__("\n" \
operands when generating position independent code. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
( CONST_INT_P (X) \
- || GET_CODE (X) == CONST_DOUBLE \
+ || CONST_DOUBLE_P (X) \
|| (GET_CODE (X) == HIGH && CONST_INT_P (XEXP (X, 0))) \
|| got12_operand (X, VOIDmode)) \
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index b8ecd299cc0..df0fe33878b 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2353,7 +2353,7 @@
rtx fma = gen_reg_rtx (<MODE>mode);
rtx rcp;
- bool is_rcp = (GET_CODE (operands[1]) == CONST_DOUBLE
+ bool is_rcp = (CONST_DOUBLE_P (operands[1])
&& real_identical (CONST_DOUBLE_REAL_VALUE (operands[1]),
&dconstm1));
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 674eed31bc3..8bc1e6b50be 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -826,7 +826,7 @@ gcn_inline_constant_p (rtx x)
{
if (CONST_INT_P (x))
return INTVAL (x) >= -16 && INTVAL (x) < 64;
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
return gcn_inline_fp_constant_p (x, false);
if (GET_CODE (x) == CONST_VECTOR)
{
@@ -5809,8 +5809,8 @@ print_operand (FILE *file, rtx x, int code)
if either operand is floating point, otherwise assume SImode. */
if (mode == VOIDmode)
{
- if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE
- || GET_CODE (XEXP (x, 1)) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (XEXP (x, 0))
+ || CONST_DOUBLE_P (XEXP (x, 1)))
mode = SFmode;
else
mode = SImode;
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index e9ee4c707bd..e1206e2b10e 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -1709,7 +1709,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
return true;
}
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
{
/* Don't word-swap when reading in the constant. */
emit_move_insn (gen_rtx_REG (DImode, REGNO (op0)),
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index 2f8615ed131..8a73129813a 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -1306,7 +1306,7 @@
rtx op2 = XVECEXP (operands[1], 0, 1);
rtx x;
- if (GET_CODE (op1) == CONST_DOUBLE && GET_CODE (op2) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op1) && CONST_DOUBLE_P (op2))
{
x = gen_rtx_CONST_VECTOR (V2SFmode, XVEC (operands[1], 0));
emit_move_insn (operands[0], x);
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index 580f22c0d28..fac0f65159d 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -830,7 +830,7 @@
&& !reload_completed
&& GET_CODE (operands[0]) == MEM
&& (GET_CODE (operands[1]) == MEM
- || GET_CODE (operands[1]) == CONST_DOUBLE))
+ || CONST_DOUBLE_P (operands[1])))
operands[1] = copy_to_mode_reg (SFmode, operands[1]);
/* Take care of reg <- SF constant */
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 2b04d48f97e..294f0f46439 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -521,7 +521,7 @@ lm32_print_operand (FILE * file, rtx op, int letter)
output_address (GET_MODE (op), XEXP (op, 0));
else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
fprintf (file, "%s", reg_names[0]);
- else if (GET_CODE (op) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (op))
{
if ((CONST_DOUBLE_LOW (op) != 0) || (CONST_DOUBLE_HIGH (op) != 0))
output_operand_lossage ("only 0.0 can be loaded as an immediate");
@@ -905,7 +905,7 @@ nonpic_symbol_mentioned_p (rtx x)
/* We don't want to look into the possible MEM location of a
CONST_DOUBLE, since we're not going to use it, in general. */
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
return 0;
if (GET_CODE (x) == UNSPEC)
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index ac18aa286c8..13e5675040e 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -1092,7 +1092,7 @@ gen_split_move_double (rtx operands[])
}
/* Reg = constant. */
- else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
+ else if (CONST_INT_P (src) || CONST_DOUBLE_P (src))
{
rtx words[2];
split_double (src, &words[0], &words[1]);
@@ -2140,7 +2140,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
fputs (reg_names[REGNO (x)+1], file);
}
else if (CONST_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE)
+ || CONST_DOUBLE_P (x))
{
rtx first, second;
@@ -2156,7 +2156,7 @@ m32r_print_operand (FILE * file, rtx x, int code)
{
char str[30];
- if (GET_CODE (x) != CONST_DOUBLE
+ if (!CONST_DOUBLE_P (x)
|| GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT)
fatal_insn ("bad insn for 'A'", x);
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index fa0e5d2f718..4f757403f7e 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -3325,7 +3325,7 @@ handle_move_double (rtx operands[2],
}
else if (optype1 == CNSTOP)
{
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
{
long l[3];
@@ -4185,7 +4185,7 @@ notice_update_cc (rtx exp, rtx insn)
&& GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
&& (GET_CODE (SET_SRC (exp)) == REG
|| GET_CODE (SET_SRC (exp)) == MEM
- || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE))
+ || CONST_DOUBLE_P (SET_SRC (exp))))
CC_STATUS_INIT;
else if (SET_DEST (exp) != pc_rtx)
{
@@ -4508,20 +4508,20 @@ print_operand (FILE *file, rtx op, int letter)
&& INTVAL (XEXP (op, 0)) >= -0x8000))
fprintf (file, MOTOROLA ? ".l" : ":l");
}
- else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode)
+ else if (CONST_DOUBLE_P (op) && GET_MODE (op) == SFmode)
{
long l;
REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), l);
asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF);
}
- else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode)
+ else if (CONST_DOUBLE_P (op) && GET_MODE (op) == XFmode)
{
long l[3];
REAL_VALUE_TO_TARGET_LONG_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF,
l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF);
}
- else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode)
+ else if (CONST_DOUBLE_P (op) && GET_MODE (op) == DFmode)
{
long l[2];
REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (op), l);
@@ -5293,7 +5293,7 @@ m68k_preferred_reload_class (rtx x, enum reg_class rclass)
return DATA_REGS;
/* ??? Do we really need this now? */
- if (GET_CODE (x) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (x)
&& GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT)
{
if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass))
@@ -5562,7 +5562,7 @@ sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
return OP_TYPE_IMM_L;
}
- if (GET_CODE (op) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op))
{
switch (GET_MODE (op))
{
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index d3c41028fae..4ed3111c439 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1171,7 +1171,7 @@
return "f%$move%.x %1,%0";
else if (ADDRESS_REG_P (operands[1]))
return "move%.l %1,%-\;f%$move%.s %+,%0";
- else if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (operands[1]))
return output_move_const_single (operands);
return "f%$move%.s %f1,%0";
}
@@ -1324,7 +1324,7 @@
output_asm_insn ("move%.l %1,%-", operands);
return "f%&move%.d %+,%0";
}
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
return output_move_const_double (operands);
return "f%&move%.d %f1,%0";
}
@@ -1443,7 +1443,7 @@
output_asm_insn ("move%.l %1,%-", operands);
return "fmove%.x %+,%0";
}
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
return "fmove%.x %1,%0";
return "fmove%.x %f1,%0";
}
@@ -1482,7 +1482,7 @@
output_asm_insn ("move%.l %1,%-", operands);
return "fmove%.x %+,%0";
}
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
return "fmove%.x %1,%0";
return "fmove%.x %f1,%0";
}
@@ -1538,7 +1538,7 @@
output_asm_insn ("move%.l %1,%-", operands);
return "fmove%.d %+,%0";
}
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
return output_move_const_double (operands);
return "fmove%.d %f1,%0";
}
@@ -3360,7 +3360,7 @@
(match_operand:DF 2 "general_operand" "fmG")))]
"TARGET_68881"
{
- if (GET_CODE (operands[2]) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (operands[2])
&& floating_exact_log2 (operands[2]) && !TUNE_68040_60)
{
int i = floating_exact_log2 (operands[2]);
@@ -7494,7 +7494,7 @@
return "f%$move%.x %1,%0";
else if (ADDRESS_REG_P (operands[1]))
return "move%.l %1,%-\;f%$move%.s %+,%0";
- else if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (operands[1]))
return output_move_const_single (operands);
return "f%$move%.s %f1,%0";
}
@@ -7530,7 +7530,7 @@
output_asm_insn ("move%.l %1,%-", operands);
return "f%&move%.d %+,%0";
}
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
return output_move_const_double (operands);
return "f%&move%.d %f1,%0";
}
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index efda85872d1..a90bf61a948 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -95,7 +95,7 @@
&& (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
#else
return (CONST_INT_P (op)
- || (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
+ || (CONST_DOUBLE_P (op) && CONST_DOUBLE_HIGH (op) == 0));
#endif
})
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 8c249ab2b61..21d15e0a6bb 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -3203,7 +3203,7 @@ mcore_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
static bool
mcore_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
- return GET_CODE (x) != CONST_DOUBLE;
+ return !CONST_DOUBLE_P (x);
}
/* Helper function for `mcore_legitimate_address_p'. */
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 0569572337d..529d54cefc4 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -245,7 +245,7 @@ microblaze_const_double_ok (rtx op, machine_mode mode)
{
REAL_VALUE_TYPE d;
- if (GET_CODE (op) != CONST_DOUBLE)
+ if (!CONST_DOUBLE_P (op))
return 0;
if (GET_MODE (op) == VOIDmode)
@@ -3768,7 +3768,7 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
if (microblaze_cannot_force_const_mem(mode, x))
return false;
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
{
return microblaze_const_double_ok (x, GET_MODE (x));
}
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index e0535b18b7f..7f14a077d8d 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -21802,7 +21802,7 @@ mips_msa_vec_parallel_const_half (machine_mode mode, bool high_p)
static inline bool
mips_constant_elt_p (rtx x)
{
- return CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE;
+ return CONST_INT_P (x) || CONST_DOUBLE_P (x);
}
/* A subroutine of mips_expand_vec_init, expand via broadcast. */
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index e17b1d522f0..8393e8b4362 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -7447,7 +7447,7 @@
UNSPEC_CONSTTABLE_FLOAT)]
"TARGET_MIPS16"
{
- gcc_assert (GET_CODE (operands[0]) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (operands[0]));
assemble_real (*CONST_DOUBLE_REAL_VALUE (operands[0]),
as_a <scalar_float_mode> (GET_MODE (operands[0])),
GET_MODE_BITSIZE (GET_MODE (operands[0])));
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index bf443613d84..5da6713b5a2 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -1064,7 +1064,7 @@ mmix_constant_address_p (rtx x)
if ((GET_CODE (x0) == SYMBOL_REF
|| GET_CODE (x0) == LABEL_REF)
&& (CONST_INT_P (x1)
- || (GET_CODE (x1) == CONST_DOUBLE
+ || (CONST_DOUBLE_P (x1)
&& GET_MODE (x1) == VOIDmode)))
addend = mmix_intval (x1);
else
@@ -1437,7 +1437,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
/* We don't get here anymore for CONST_DOUBLE, because DImode
isn't expressed as CONST_DOUBLE, and DFmode is handled
elsewhere. */
- gcc_assert (GET_CODE (x) != CONST_DOUBLE);
+ gcc_assert (!CONST_DOUBLE_P (x));
assemble_integer_with_op ("\tOCTA\t", x);
return true;
}
@@ -1705,7 +1705,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
case 'I':
/* Output the constant. Note that we use this for floats as well. */
if (!CONST_INT_P (x)
- && (GET_CODE (x) != CONST_DOUBLE
+ && (!CONST_DOUBLE_P (x)
|| (GET_MODE (x) != VOIDmode && GET_MODE (x) != DFmode
&& GET_MODE (x) != SFmode)))
fatal_insn ("MMIX Internal: Expected a constant, not this", x);
@@ -2749,10 +2749,10 @@ mmix_intval (const_rtx x)
/* We make a little song and dance because converting to long long in
gcc-2.7.2 is broken. I still want people to be able to use it for
cross-compilation to MMIX. */
- if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == VOIDmode)
+ if (CONST_DOUBLE_P (x) && GET_MODE (x) == VOIDmode)
return CONST_DOUBLE_HIGH (x);
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
{
if (GET_MODE (x) == DFmode)
{
diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md
index c572b7b07b1..f74c771f30f 100644
--- a/gcc/config/mmix/predicates.md
+++ b/gcc/config/mmix/predicates.md
@@ -113,7 +113,7 @@
if ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
&& (CONST_INT_P (XEXP (op, 1))
- || (GET_CODE (XEXP (op, 1)) == CONST_DOUBLE
+ || (CONST_DOUBLE_P (XEXP (op, 1))
&& GET_MODE (XEXP (op, 1)) == VOIDmode)))
return 1;
/* Fall through. */
diff --git a/gcc/config/nds32/constraints.md b/gcc/config/nds32/constraints.md
index b5010c0edb7..be1860e8117 100644
--- a/gcc/config/nds32/constraints.md
+++ b/gcc/config/nds32/constraints.md
@@ -273,7 +273,7 @@
(define_constraint "Chig"
"The immediate value that can be simply set high 20-bit"
(and (match_code "high")
- (match_test "GET_CODE (XEXP (op, 0)) == CONST_DOUBLE")))
+ (match_test "CONST_DOUBLE_P (XEXP (op, 0))")))
(define_constraint "Izeb"
"The immediate value 0xff"
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index 8d02ce5a77b..d99a70a2b62 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -506,7 +506,7 @@ bool
nds32_const_double_range_ok_p (rtx op, machine_mode mode,
HOST_WIDE_INT lower, HOST_WIDE_INT upper)
{
- if (GET_CODE (op) != CONST_DOUBLE
+ if (!CONST_DOUBLE_P (op)
|| GET_MODE (op) != mode)
return false;
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index c3a9d27f137..5b1dfedf30d 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -3578,7 +3578,7 @@ nds32_print_operand (FILE *stream, rtx x, int code)
break;
case HIGH:
- if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (XEXP (x, 0)))
{
const REAL_VALUE_TYPE *rv;
long val;
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index 6e62258f8d3..60a5f19cfd8 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -1440,7 +1440,7 @@ enum reg_class
#define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode)
#define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode)
-#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE)
+#define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && !CONST_DOUBLE_P (x))
#define MAX_REGS_PER_ADDRESS 3
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 565221e7fb2..ff5bfedd06d 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -2384,7 +2384,7 @@ pa_singlemove_string (rtx *operands)
return "stw %r1,%0";
if (GET_CODE (operands[1]) == MEM)
return "ldw %1,%0";
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
{
long i;
@@ -6055,7 +6055,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
a few patterns that accept constant double operands. */
if (flag_pic
&& FP_REG_CLASS_P (rclass)
- && (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE))
+ && (CONST_INT_P (x) || CONST_DOUBLE_P (x)))
{
switch (mode)
{
@@ -10364,7 +10364,7 @@ pa_legitimate_constant_p (machine_mode mode, rtx x)
if (tls_referenced_p (x))
return false;
- if (TARGET_64BIT && GET_CODE (x) == CONST_DOUBLE)
+ if (TARGET_64BIT && CONST_DOUBLE_P (x))
return false;
if (TARGET_64BIT
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 4174d590efb..0ce8b635411 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3837,7 +3837,7 @@
"fG,*rG,f,*r,*r,RT,o,RQ,f,*r"))]
"(register_operand (operands[0], DFmode)
|| reg_or_0_operand (operands[1], DFmode))
- && !(GET_CODE (operands[1]) == CONST_DOUBLE
+ && !(CONST_DOUBLE_P (operands[1])
&& GET_CODE (operands[0]) == MEM)
&& !TARGET_64BIT
&& !TARGET_SOFT_FLOAT"
@@ -4291,7 +4291,7 @@
{
/* Don't output a 64-bit constant, since we can't trust the assembler to
handle it correctly. */
- if (GET_CODE (operands[2]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[2]))
operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
else if (HOST_BITS_PER_WIDE_INT > 32
&& CONST_INT_P (operands[2]))
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 53be7e7752a..4fcd9ed33d5 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -537,7 +537,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
if (REG_P (operands[op]))
optype = REGOP;
else if (CONST_INT_P (operands[op])
- || GET_CODE (operands[op]) == CONST_DOUBLE)
+ || CONST_DOUBLE_P (operands[op]))
optype = CNSTOP;
else if (GET_CODE (XEXP (operands[op], 0)) == POST_INC)
optype = POPOP;
@@ -583,7 +583,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
optype = OFFSOP;
}
- if (GET_CODE (operands[op]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[op]))
{
gcc_assert (GET_MODE (operands[op]) != VOIDmode);
REAL_VALUE_TO_TARGET_DOUBLE
@@ -606,7 +606,7 @@ pdp11_expand_operands (rtx *operands, rtx exops[][2],
exops[i][op] = adjust_address (operands[op], HImode, w * 2);
else if (optype == CNSTOP)
{
- if (GET_CODE (operands[op]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[op]))
{
sh = 16 - (w & 1) * 16;
exops[i][op] = gen_rtx_CONST_INT (HImode, (sval[w / 2] >> sh) & 0xffff);
@@ -801,7 +801,7 @@ pdp11_asm_print_operand (FILE *file, rtx x, int code)
fprintf (file, "%s", reg_names[REGNO (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
- else if (GET_CODE (x) == CONST_DOUBLE && FLOAT_MODE_P (GET_MODE (x)))
+ else if (CONST_DOUBLE_P (x) && FLOAT_MODE_P (GET_MODE (x)))
{
REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), sval);
if (TARGET_DEC_ASM)
@@ -2376,7 +2376,7 @@ pdp11_file_end (void)
static bool
pdp11_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
- return GET_CODE (x) != CONST_DOUBLE || legitimate_const_double_p (x);
+ return !CONST_DOUBLE_P (x) || legitimate_const_double_p (x);
}
/* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 4c55707367d..ff6d41ea6f0 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -4181,7 +4181,7 @@ legitimate_reload_constant_p (rtx op)
return true;
/* Accept floating-point zero operands that fit into a single GPR. */
- if (GET_CODE (op) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (op)
&& s390_float_const_zero_p (op)
&& GET_MODE_SIZE (GET_MODE (op)) <= UNITS_PER_WORD)
return true;
@@ -4214,7 +4214,7 @@ legitimate_reload_fp_constant_p (rtx op)
can be used. Prior to z196 the load fp zero instruction caused a
performance penalty if the result is used as BFP number. */
if (TARGET_Z196
- && GET_CODE (op) == CONST_DOUBLE
+ && CONST_DOUBLE_P (op)
&& s390_float_const_zero_p (op))
return true;
@@ -4417,7 +4417,7 @@ s390_reload_symref_address (rtx reg, rtx mem, rtx scratch, bool tomem)
{
/* Reload might have pulled a constant out of the literal pool.
Force it back in. */
- if (CONST_INT_P (mem) || GET_CODE (mem) == CONST_DOUBLE
+ if (CONST_INT_P (mem) || CONST_DOUBLE_P (mem)
|| CONST_WIDE_INT_P (mem)
|| GET_CODE (mem) == CONST_VECTOR
|| GET_CODE (mem) == CONST)
@@ -9269,7 +9269,7 @@ s390_output_pool_entry (rtx exp, machine_mode mode, unsigned int align)
{
case MODE_FLOAT:
case MODE_DECIMAL_FLOAT:
- gcc_assert (GET_CODE (exp) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (exp));
assemble_real (*CONST_DOUBLE_REAL_VALUE (exp),
as_a <scalar_float_mode> (mode), align);
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index dfaeab55142..3e2ffcff0f1 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -4803,7 +4803,7 @@ broken_move (rtx_insn *insn)
&& XINT (SET_SRC (pat), 1) == UNSPEC_MOVA
&& GET_CODE (XVECEXP (SET_SRC (pat), 0, 0)) == CONST))
&& ! (TARGET_SH2E
- && GET_CODE (SET_SRC (pat)) == CONST_DOUBLE
+ && CONST_DOUBLE_P (SET_SRC (pat))
&& (fp_zero_operand (SET_SRC (pat))
|| fp_one_operand (SET_SRC (pat)))
/* In general we don't know the current setting of fpscr, so
@@ -9102,7 +9102,7 @@ nonpic_symbol_mentioned_p (rtx x)
/* We don't want to look into the possible MEM location of a
CONST_DOUBLE, since we're not going to use it, in general. */
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
return false;
if (GET_CODE (x) == UNSPEC
@@ -11442,7 +11442,7 @@ sh_movsf_ie_ra_split_p (rtx op0, rtx op1, rtx op2)
if (rtx_equal_p (op0, op1))
return true;
/* fy, FQ, reg */
- if (GET_CODE (op1) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (op1)
&& ! satisfies_constraint_G (op1)
&& ! satisfies_constraint_H (op1)
&& REG_P (op0)
@@ -11517,7 +11517,7 @@ sh_legitimate_constant_p (machine_mode mode, rtx x)
&& SYMBOLIC_CONST_P (XEXP (XEXP (x, 0), 0)))))
return false;
- return GET_CODE (x) != CONST_DOUBLE
+ return !CONST_DOUBLE_P (x)
|| mode == DFmode || mode == SFmode
|| mode == DImode || GET_MODE (x) == VOIDmode;
}
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 0204872eae7..37bfc02de98 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1372,7 +1372,7 @@ extern bool current_function_interrupt;
#define IS_NON_EXPLICIT_CONSTANT_P(OP) \
(CONSTANT_P (OP) \
&& !CONST_INT_P (OP) \
- && GET_CODE (OP) != CONST_DOUBLE \
+ && !CONST_DOUBLE_P (OP) \
&& (!flag_pic \
|| (LEGITIMATE_PIC_OPERAND_P (OP) \
&& !PIC_ADDR_P (OP) \
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index e19e8fdffb3..09c3312f955 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -401,7 +401,7 @@
return true;
/* Allow FP constants to be built in integer registers. */
- if (mclass == MODE_FLOAT && GET_CODE (op) == CONST_DOUBLE)
+ if (mclass == MODE_FLOAT && CONST_DOUBLE_P (op))
return true;
if (mclass == MODE_VECTOR_INT && const_all_ones_operand (op, mode))
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index dc833072f8c..7326d83a96f 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2138,7 +2138,7 @@ v9_regcmp_p (enum rtx_code code)
int
fp_sethi_p (rtx op)
{
- if (GET_CODE (op) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op))
{
long i;
@@ -2156,7 +2156,7 @@ fp_sethi_p (rtx op)
int
fp_mov_p (rtx op)
{
- if (GET_CODE (op) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op))
{
long i;
@@ -2177,7 +2177,7 @@ fp_high_losum_p (rtx op)
/* The constraints calling this should only be in
SFmode move insns, so any constant which cannot
be moved using a single insn will do. */
- if (GET_CODE (op) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op))
{
long i;
@@ -9644,7 +9644,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
output_addr_const (file, XEXP (x, 1));
fputc (')', file);
}
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
output_operand_lossage ("floating-point constant not a valid immediate operand");
else
output_addr_const (file, x);
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 14ce445d1e2..60220904346 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2384,7 +2384,7 @@ visl")
"(register_operand (operands[0], SFmode)
|| register_or_zero_or_all_ones_operand (operands[1], SFmode))"
{
- if (GET_CODE (operands[1]) == CONST_DOUBLE
+ if (CONST_DOUBLE_P (operands[1])
&& (which_alternative == 3
|| which_alternative == 4
|| which_alternative == 5))
diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md
index 0d4314be398..6a2b38eadef 100644
--- a/gcc/config/spu/predicates.md
+++ b/gcc/config/spu/predicates.md
@@ -75,7 +75,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
+ if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode);
return 0;
@@ -86,7 +86,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
+ if (CONST_INT_P (op) || CONST_DOUBLE_P (op)
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode)
|| iohl_immediate_p (op, mode);
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index e6b25ab3b98..b2ca39a6fb0 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -3175,7 +3175,7 @@ classify_immediate (rtx op, machine_mode mode)
&& mode == V4SImode
&& GET_CODE (op) == CONST_VECTOR
&& !CONST_INT_P (CONST_VECTOR_ELT (op, 0))
- && GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_DOUBLE)
+ && !CONST_DOUBLE_P (CONST_VECTOR_ELT (op, 0)))
op = unwrap_const_vec_duplicate (op);
switch (GET_CODE (op))
@@ -3206,7 +3206,7 @@ classify_immediate (rtx op, machine_mode mode)
case CONST_VECTOR:
for (i = 0; i < GET_MODE_NUNITS (mode); i++)
if (!CONST_INT_P (CONST_VECTOR_ELT (op, i))
- && GET_CODE (CONST_VECTOR_ELT (op, i)) != CONST_DOUBLE)
+ && !CONST_DOUBLE_P (CONST_VECTOR_ELT (op, i)))
return IC_POOL;
/* Fall through. */
@@ -3290,7 +3290,7 @@ const_vector_immediate_p (rtx x)
gcc_assert (GET_CODE (x) == CONST_VECTOR);
for (i = 0; i < GET_MODE_NUNITS (GET_MODE (x)); i++)
if (!CONST_INT_P (CONST_VECTOR_ELT (x, i))
- && GET_CODE (CONST_VECTOR_ELT (x, i)) != CONST_DOUBLE)
+ && !CONST_DOUBLE_P (CONST_VECTOR_ELT (x, i)))
return 0;
return 1;
}
@@ -3302,7 +3302,7 @@ logical_immediate_p (rtx op, machine_mode mode)
unsigned char arr[16];
int i, j;
- gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3334,7 +3334,7 @@ iohl_immediate_p (rtx op, machine_mode mode)
unsigned char arr[16];
int i, j;
- gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3366,7 +3366,7 @@ arith_immediate_p (rtx op, machine_mode mode,
unsigned char arr[16];
int bytes, i, j;
- gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3407,7 +3407,7 @@ exp2_immediate_p (rtx op, machine_mode mode, int low, int high)
unsigned char arr[16];
int bytes, i, j;
- gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || CONST_DOUBLE_P (op)
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -5030,12 +5030,12 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
memset (arr, 0, 16);
mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : mode;
if (CONST_INT_P (x)
- || (GET_CODE (x) == CONST_DOUBLE
+ || (CONST_DOUBLE_P (x)
&& (mode == SFmode || mode == DFmode)))
{
gcc_assert (mode != VOIDmode && mode != BLKmode);
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
val = const_double_to_hwint (x);
else
val = INTVAL (x);
@@ -5052,7 +5052,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
j = (j == first) ? 0 : j + 1;
}
}
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
{
val = CONST_DOUBLE_LOW (x);
for (i = 15; i >= 8; i--)
@@ -5076,9 +5076,9 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
for (i = 0; i < units; i++)
{
elt = CONST_VECTOR_ELT (x, i);
- if (CONST_INT_P (elt) || GET_CODE (elt) == CONST_DOUBLE)
+ if (CONST_INT_P (elt) || CONST_DOUBLE_P (elt))
{
- if (GET_CODE (elt) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (elt))
val = const_double_to_hwint (elt);
else
val = INTVAL (elt);
@@ -5651,7 +5651,7 @@ void
spu_builtin_splats (rtx ops[])
{
machine_mode mode = GET_MODE (ops[0]);
- if (CONST_INT_P (ops[1]) || GET_CODE (ops[1]) == CONST_DOUBLE)
+ if (CONST_INT_P (ops[1]) || CONST_DOUBLE_P (ops[1]))
{
unsigned char arr[16];
constant_to_array (GET_MODE_INNER (mode), ops[1], arr);
@@ -5984,7 +5984,7 @@ spu_expand_vector_init (rtx target, rtx vals)
{
x = XVECEXP (vals, 0, i);
if (!(CONST_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE
+ || CONST_DOUBLE_P (x)
|| CONST_FIXED_P (x)))
++n_var;
else
@@ -6025,7 +6025,7 @@ spu_expand_vector_init (rtx target, rtx vals)
{
x = XVECEXP (constant_parts_rtx, 0, i);
if (!(CONST_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE
+ || CONST_DOUBLE_P (x)
|| CONST_FIXED_P (x)))
XVECEXP (constant_parts_rtx, 0, i) = first_constant;
}
@@ -6045,7 +6045,7 @@ spu_expand_vector_init (rtx target, rtx vals)
{
x = XVECEXP (vals, 0, i);
if (!(CONST_INT_P (x)
- || GET_CODE (x) == CONST_DOUBLE
+ || CONST_DOUBLE_P (x)
|| CONST_FIXED_P (x)))
{
if (!register_operand (x, GET_MODE (x)))
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index 6da91390b18..cdc7561e54e 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -5255,7 +5255,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
HOST_WIDE_INT i;
if (CONST_INT_P (x))
i = INTVAL (x);
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
else
{
@@ -5297,7 +5297,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
HOST_WIDE_INT i;
if (CONST_INT_P (x))
i = INTVAL (x);
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
else if (GET_CODE (x) == CONST_VECTOR
&& CONST_INT_P (CONST_VECTOR_ELT (x, 0)))
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index f86461f07d4..6473ff20fff 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -4523,7 +4523,7 @@ tilepro_print_operand (FILE *file, rtx x, int code)
HOST_WIDE_INT i;
if (CONST_INT_P (x))
i = INTVAL (x);
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
else
{
@@ -4617,7 +4617,7 @@ tilepro_print_operand (FILE *file, rtx x, int code)
HOST_WIDE_INT i;
if (CONST_INT_P (x))
i = INTVAL (x);
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
i = CONST_DOUBLE_LOW (x);
else if (GET_CODE (x) == CONST_VECTOR
&& CONST_INT_P (CONST_VECTOR_ELT (x, 0)))
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index d662ad0308d..66edd7cbe09 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -25,7 +25,7 @@
if (CONST_INT_P (op))
return INTVAL (op) == 0;
- else if (GET_CODE (op) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (op))
return satisfies_constraint_G (op);
else
@@ -477,7 +477,7 @@
(define_predicate "const_float_1_operand"
(match_code "const_double")
{
- if (GET_CODE (op) != CONST_DOUBLE
+ if (!CONST_DOUBLE_P (op)
|| mode != GET_MODE (op)
|| (mode != DFmode && mode != SFmode))
return 0;
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index bf9fbea608d..ea2222cca1d 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -264,7 +264,7 @@ v850_function_arg_advance (cumulative_args_t cum_v, machine_mode mode,
static void
const_double_split (rtx x, HOST_WIDE_INT * p_high, HOST_WIDE_INT * p_low)
{
- if (GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (x))
{
long t[2];
@@ -843,7 +843,7 @@ output_move_single (rtx * operands)
return "movhi hi(%1),%.,%0\n\tmovea lo(%1),%0,%0";
}
- else if (GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode)
+ else if (CONST_DOUBLE_P (src) && GET_MODE (src) == SFmode)
{
HOST_WIDE_INT high, low;
@@ -901,7 +901,7 @@ output_move_single (rtx * operands)
else if (CONST_INT_P (src) && INTVAL (src) == 0)
return "%S0st%W0 %.,%0";
- else if (GET_CODE (src) == CONST_DOUBLE
+ else if (CONST_DOUBLE_P (src)
&& CONST0_RTX (GET_MODE (dst)) == src)
return "%S0st%W0 %.,%0";
}
@@ -3020,7 +3020,7 @@ v850_issue_rate (void)
static bool
v850_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
- return (GET_CODE (x) == CONST_DOUBLE
+ return (CONST_DOUBLE_P (x)
|| !(GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c
index 9559ffb9bb4..3cee73c2e23 100644
--- a/gcc/config/vax/vax.c
+++ b/gcc/config/vax/vax.c
@@ -536,14 +536,14 @@ print_operand (FILE *file, rtx x, int code)
fprintf (file, "%s", reg_names[REGNO (x)]);
else if (MEM_P (x))
output_address (GET_MODE (x), XEXP (x, 0));
- else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == SFmode)
+ else if (CONST_DOUBLE_P (x) && GET_MODE (x) == SFmode)
{
char dstr[30];
real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x),
sizeof (dstr), 0, 1);
fprintf (file, "$0f%s", dstr);
}
- else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) == DFmode)
+ else if (CONST_DOUBLE_P (x) && GET_MODE (x) == DFmode)
{
char dstr[30];
real_to_decimal (dstr, CONST_DOUBLE_REAL_VALUE (x),
@@ -632,7 +632,7 @@ vax_float_literal (rtx c)
REAL_VALUE_TYPE s;
int i;
- if (GET_CODE (c) != CONST_DOUBLE)
+ if (!CONST_DOUBLE_P (c))
return false;
mode = GET_MODE (c);
@@ -1149,12 +1149,12 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
return "clrq %0";
if (TARGET_QMATH && optimize_size
&& (CONST_INT_P (operands[1])
- || GET_CODE (operands[1]) == CONST_DOUBLE))
+ || CONST_DOUBLE_P (operands[1])))
{
unsigned HOST_WIDE_INT hval, lval;
int n;
- if (GET_CODE (operands[1]) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (operands[1]))
{
gcc_assert (HOST_BITS_PER_WIDE_INT != 64);
@@ -1217,7 +1217,7 @@ vax_output_int_move (rtx insn ATTRIBUTE_UNUSED, rtx *operands,
|| !illegal_addsub_di_memory_operand (operands[0], DImode))
&& ((CONST_INT_P (operands[1])
&& (unsigned HOST_WIDE_INT) INTVAL (operands[1]) >= 64)
- || GET_CODE (operands[1]) == CONST_DOUBLE))
+ || CONST_DOUBLE_P (operands[1])))
{
hi[0] = operands[0];
hi[1] = operands[1];
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md
index 298f3393d2d..4017a72e08f 100644
--- a/gcc/config/vax/vax.md
+++ b/gcc/config/vax/vax.md
@@ -488,7 +488,7 @@
(sign_extend:DI
(match_operand:SI 2 "nonimmediate_operand" "nrmT")))
(match_operand:DI 3 "immediate_operand" "F")))]
- "GET_CODE (operands[3]) == CONST_DOUBLE
+ "CONST_DOUBLE_P (operands[3])
&& CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)"
"*
{
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 48e02e04689..3362843f488 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -2232,7 +2232,7 @@ visium_expand_copysign (rtx *operands, machine_mode mode)
gcc_assert (mode == SFmode);
/* First get all the non-sign bits of op1. */
- if (GET_CODE (op1) == CONST_DOUBLE)
+ if (CONST_DOUBLE_P (op1))
{
if (real_isneg (CONST_DOUBLE_REAL_VALUE (op1)))
op1 = simplify_unary_operation (ABS, mode, op1, mode);
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 802323c2f8e..ba983ad3ac9 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -2453,7 +2453,7 @@ print_operand (FILE *file, rtx x, int letter)
printx (file, INTVAL (x));
fputs (letter == 't' ? "@h" : "@l", file);
}
- else if (GET_CODE (x) == CONST_DOUBLE)
+ else if (CONST_DOUBLE_P (x))
{
if (GET_MODE (x) == SFmode)
{
@@ -2489,7 +2489,7 @@ print_operand (FILE *file, rtx x, int letter)
break;
case 'y':
- if (GET_CODE (x) == CONST_DOUBLE &&
+ if (CONST_DOUBLE_P (x) &&
GET_MODE (x) == SFmode)
{
long l;
@@ -2636,7 +2636,7 @@ xtensa_output_literal (FILE *file, rtx x, machine_mode mode, int labelno)
switch (GET_MODE_CLASS (mode))
{
case MODE_FLOAT:
- gcc_assert (GET_CODE (x) == CONST_DOUBLE);
+ gcc_assert (CONST_DOUBLE_P (x));
switch (mode)
{
diff --git a/gcc/defaults.h b/gcc/defaults.h
index af7ea185f1e..f4bdc7b0247 100644
--- a/gcc/defaults.h
+++ b/gcc/defaults.h
@@ -1170,7 +1170,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
/* For most ports anything that evaluates to a constant symbolic
or integer value is acceptable as a constant address. */
#ifndef CONSTANT_ADDRESS_P
-#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && GET_CODE (X) != CONST_DOUBLE)
+#define CONSTANT_ADDRESS_P(X) (CONSTANT_P (X) && !CONST_DOUBLE_P (X))
#endif
#ifndef MAX_FIXED_MODE_SIZE
diff --git a/gcc/genpreds.c b/gcc/genpreds.c
index 556c4bdd869..82ed58f4960 100644
--- a/gcc/genpreds.c
+++ b/gcc/genpreds.c
@@ -1247,14 +1247,14 @@ write_tm_constrs_h (void)
error ("you can't use lval or hval");
#else
if (needs_hval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode == VOIDmode)"
" hval = CONST_DOUBLE_HIGH (op);");
if (needs_lval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode == VOIDmode)"
" lval = CONST_DOUBLE_LOW (op);");
#endif
if (needs_rval)
- puts (" if (GET_CODE (op) == CONST_DOUBLE && mode != VOIDmode)"
+ puts (" if (CONST_DOUBLE_P (op) && mode != VOIDmode)"
" rval = CONST_DOUBLE_REAL_VALUE (op);");
write_predicate_stmts (c->exp);
diff --git a/gcc/recog.c b/gcc/recog.c
index a9f584bc0dc..dffe8bfde75 100644
--- a/gcc/recog.c
+++ b/gcc/recog.c
@@ -1213,7 +1213,7 @@ const_scalar_int_operand (rtx op, machine_mode mode)
int
const_double_operand (rtx op, machine_mode mode)
{
- return (GET_CODE (op) == CONST_DOUBLE)
+ return (CONST_DOUBLE_P (op))
&& (GET_MODE (op) == mode || mode == VOIDmode);
}
#else
diff --git a/gcc/reg-stack.c b/gcc/reg-stack.c
index 710f14a9544..c730b324cc0 100644
--- a/gcc/reg-stack.c
+++ b/gcc/reg-stack.c
@@ -908,7 +908,7 @@ emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg)
i1src = XEXP (i1src, 0);
if (REG_P (i1dest)
&& REGNO (i1dest) == FIRST_STACK_REG
- && (MEM_P (i1src) || GET_CODE (i1src) == CONST_DOUBLE)
+ && (MEM_P (i1src) || CONST_DOUBLE_P (i1src))
&& !side_effects_p (i1src)
&& hard_regno == FIRST_STACK_REG + 1
&& i1 != BB_HEAD (current_block))
@@ -949,7 +949,7 @@ emit_swap_insn (rtx_insn *insn, stack_ptr regstack, rtx reg)
%st to %st(1), consider swapping them. */
if (REG_P (i2dest)
&& REGNO (i2dest) == FIRST_STACK_REG
- && (MEM_P (i2src) || GET_CODE (i2src) == CONST_DOUBLE)
+ && (MEM_P (i2src) || CONST_DOUBLE_P (i2src))
/* Ensure i2 doesn't have other side-effects. */
&& !side_effects_p (i2src)
/* And that the two instructions can actually be
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 02/18] Use CONST_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_INT
2019-08-06 3:11 ` Arvind Sankar
` (10 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 04/18] Use CONST_WIDE_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_WIDE_INT_P Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 05/18] Use CONST_FIXED_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_FIXED Arvind Sankar
` (5 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* combine.c: Convert GET_CODE (..) == CONST_INT to
CONST_INT_P (..).
* config/aarch64/aarch64.c: Likewise.
* config/aarch64/predicates.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/arc.h: Likewise.
* config/arc/fpx.md: Likewise.
* config/arc/predicates.md: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/bfin.md: Likewise.
* config/bfin/predicates.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/c6x/predicates.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cr16/cr16.h: Likewise.
* config/cr16/cr16.md: Likewise.
* config/cr16/predicates.md: Likewise.
* config/cris/cris.md: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.md: Likewise.
* config/csky/predicates.md: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.c: Likewise.
* config/epiphany/epiphany.h: Likewise.
* config/fr30/fr30.c: Likewise.
* config/fr30/fr30.h: Likewise.
* config/fr30/fr30.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/frv.h: Likewise.
* config/frv/frv.md: Likewise.
* config/frv/predicates.md: Likewise.
* config/ft32/constraints.md: Likewise.
* config/ft32/predicates.md: Likewise.
* config/gcn/gcn-valu.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/gcn/gcn.md: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.h: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/ia64.md: Likewise.
* config/ia64/predicates.md: Likewise.
* config/ia64/vect.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/iq2000/iq2000.h: Likewise.
* config/iq2000/iq2000.md: Likewise.
* config/iq2000/predicates.md: Likewise.
* config/lm32/lm32.c: Likewise.
* config/lm32/lm32.h: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32c/muldiv.md: Likewise.
* config/m32c/predicates.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.h: Likewise.
* config/m68k/m68k.md: Likewise.
* config/m68k/predicates.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/microblaze/microblaze.md: Likewise.
* config/microblaze/predicates.md: Likewise.
* config/mmix/mmix.c: Likewise.
* config/mmix/mmix.md: Likewise.
* config/mmix/predicates.md: Likewise.
* config/moxie/moxie.c: Likewise.
* config/moxie/predicates.md: Likewise.
* config/msp430/msp430.c: Likewise.
* config/msp430/msp430.md: Likewise.
* config/nds32/nds32-cost.c: Likewise.
* config/nds32/nds32-intrinsic.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-memory-manipulation.c: Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-pipelines-auxiliary.c: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/nds32-utils.c: Likewise.
* config/nds32/nds32.c: Likewise.
* config/nios2/nios2.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.h: Likewise.
* config/pa/pa.md: Likewise.
* config/pa/predicates.md: Likewise.
* config/pdp11/pdp11.c: Likewise.
* config/pdp11/pdp11.md: Likewise.
* config/pru/pru.c: Likewise.
* config/pru/pru.md: Likewise.
* config/riscv/riscv.c: Likewise.
* config/riscv/riscv.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rx/rx.c: Likewise.
* config/rx/rx.md: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.md: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/constraints.md: Likewise.
* config/spu/predicates.md: Likewise.
* config/spu/spu-builtins.md: Likewise.
* config/spu/spu.c: Likewise.
* config/spu/spu.md: Likewise.
* config/stormy16/predicates.md: Likewise.
* config/v850/predicates.md: Likewise.
* config/v850/v850.c: Likewise.
* config/v850/v850.md: Likewise.
* config/visium/visium.c: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.h: Likewise.
* cse.c: Likewise.
* dwarf2out.c: Likewise.
* explow.c: Likewise.
* expr.c: Likewise.
* genrecog.c: Likewise.
* ree.c: Likewise.
* reload1.c: Likewise.
* tree-ssa-address.c: Likewise.
* var-tracking.c: Likewise.
124 files changed, 933 insertions(+), 933 deletions(-)
diff --git a/gcc/combine.c b/gcc/combine.c
index f7b1ebc8cc0..1c59ab54a40 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -5361,7 +5361,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
constant. It may be better to try splitting (plus (mult B -C) A)
instead if this isn't a multiply by a power of two. */
if (set_src && code == MINUS && GET_CODE (XEXP (x, 1)) == MULT
- && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 1), 1))
&& !pow2p_hwi (INTVAL (XEXP (XEXP (x, 1), 1))))
{
machine_mode mode = GET_MODE (x);
@@ -5382,7 +5382,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
if (!set_src
&& (GET_CODE (XEXP (x, 0)) == MULT
|| (GET_CODE (XEXP (x, 0)) == ASHIFT
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))))
return loc;
default:
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 5bf182ccc0c..a526b8be522 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -2807,7 +2807,7 @@ aarch64_internal_mov_immediate (rtx dest, rtx imm, bool generate,
bool
aarch64_mov128_immediate (rtx imm)
{
- if (GET_CODE (imm) == CONST_INT)
+ if (CONST_INT_P (imm))
return true;
gcc_assert (CONST_WIDE_INT_NUNITS (imm) == 2);
@@ -7148,7 +7148,7 @@ aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode)
imode = int_mode_for_mode (mode).require ();
}
- else if (GET_CODE (x) == CONST_INT
+ else if (CONST_INT_P (x)
&& is_a <scalar_int_mode> (mode, &imode))
ival = INTVAL (x);
else
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 10100ca830a..9f2e139899f 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -265,7 +265,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
/* FALLTHRU */
@@ -287,7 +287,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
/* FALLTHRU */
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 3c4d89cdd08..486053c98ca 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -90,7 +90,7 @@ HARD_REG_SET overrideregs;
/* Check if an rtx fits in the store instruction format. Loads can
handle any constant. */
#define RTX_OK_FOR_OFFSET_P(MODE, X) \
- (GET_CODE (X) == CONST_INT \
+ (CONST_INT_P (X) \
&& SMALL_INT_RANGE (INTVAL (X), (GET_MODE_SIZE (MODE) - 1) & (~0x03), \
(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1) & 3 \
? 0 \
@@ -4179,7 +4179,7 @@ output_shift (rtx *operands)
default: gcc_unreachable ();
}
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
output_asm_insn ("and.f lp_count,%2, 0x1f", operands);
goto shiftloop;
@@ -4436,7 +4436,7 @@ arc_print_operand (FILE *file, rtx x, int code)
switch (code)
{
case 'Z':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "%d",exact_log2(INTVAL (x) + 1) - 1 );
else
output_operand_lossage ("invalid operand to %%Z code");
@@ -4444,7 +4444,7 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
case 'z':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "%d",exact_log2 (INTVAL (x) & 0xffffffff));
else
output_operand_lossage ("invalid operand to %%z code");
@@ -4452,7 +4452,7 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
case 'c':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "%ld", INTVAL (x) );
else
output_operand_lossage ("invalid operands to %%c code");
@@ -4460,7 +4460,7 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
case 'M':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "%d",exact_log2(~INTVAL (x)) );
else
output_operand_lossage ("invalid operand to %%M code");
@@ -4468,14 +4468,14 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
case 'p':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "%d", exact_log2 (INTVAL (x) & -INTVAL (x)));
else
output_operand_lossage ("invalid operand to %%p code");
return;
case 's':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
{
HOST_WIDE_INT i = INTVAL (x);
HOST_WIDE_INT s = exact_log2 (i & -i);
@@ -4691,7 +4691,7 @@ arc_print_operand (FILE *file, rtx x, int code)
else
fputs (reg_names[REGNO (x)+1], file);
}
- else if (GET_CODE (x) == CONST_INT
+ else if (CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE)
{
rtx first, second, word;
@@ -5004,7 +5004,7 @@ arc_print_operand_address (FILE *file , rtx addr)
}
gcc_assert (GET_CODE (c) == PLUS);
gcc_assert (GET_CODE (XEXP (c, 0)) == SYMBOL_REF);
- gcc_assert (GET_CODE (XEXP (c, 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (c, 1)));
output_address (VOIDmode, XEXP (addr, 0));
@@ -5861,7 +5861,7 @@ arc_rtx_costs (rtx x, machine_mode mode, int outer_code,
}
*total = COSTS_N_INSNS (1);
}
- else if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ else if (!CONST_INT_P (XEXP (x, 1)))
*total = COSTS_N_INSNS (16);
else
{
@@ -6014,7 +6014,7 @@ arc_legitimate_pic_addr_p (rtx addr)
if (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (addr, 1)))
return false;
addr = XEXP (addr, 0);
}
@@ -6306,13 +6306,13 @@ arc_output_pic_addr_const (FILE * file, rtx x, int code)
case PLUS:
/* FIXME: Not needed here. */
/* Some assemblers need integer constants to appear last (eg masm). */
- if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 0)))
{
arc_output_pic_addr_const (file, XEXP (x, 1), code);
fprintf (file, "+");
arc_output_pic_addr_const (file, XEXP (x, 0), code);
}
- else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ else if (CONST_INT_P (XEXP (x, 1)))
{
arc_output_pic_addr_const (file, XEXP (x, 0), code);
if (INTVAL (XEXP (x, 1)) >= 0)
@@ -6332,7 +6332,7 @@ arc_output_pic_addr_const (FILE * file, rtx x, int code)
arc_output_pic_addr_const (file, XEXP (x, 0), code);
fprintf (file, "-");
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) < 0)
{
fprintf (file, "(");
@@ -6669,7 +6669,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict)
return true;
if (legitimate_small_data_address_p (x))
return true;
- if (GET_CODE (x) == CONST_INT && LARGE_INT (INTVAL (x)))
+ if (CONST_INT_P (x) && LARGE_INT (INTVAL (x)))
return true;
/* When we compile for size avoid const (@sym + offset)
@@ -10967,7 +10967,7 @@ compact_memory_operand_p (rtx op, machine_mode mode,
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| (COMPACT_GP_REG_P (REGNO (plus0)) && !av2short)
|| (IN_RANGE (REGNO (plus0), 0, 31) && av2short))
- && (GET_CODE (plus1) == CONST_INT))
+ && (CONST_INT_P (plus1)))
{
bool valid = false;
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 4a9dd07f558..377e29d3547 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -842,7 +842,7 @@ extern int arc_initial_elimination_offset(int from, int to);
#define CONSTANT_ADDRESS_P(X) \
(flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST))
+ || CONST_INT_P (X) || GET_CODE (X) == CONST))
/* Is the argument a const_int rtx, containing an exact power of 2 */
#define IS_POWEROF2_P(X) (! ( (X) & ((X) - 1)) && (X))
diff --git a/gcc/config/arc/fpx.md b/gcc/config/arc/fpx.md
index 09c7b354715..0d0230baff0 100644
--- a/gcc/config/arc/fpx.md
+++ b/gcc/config/arc/fpx.md
@@ -239,7 +239,7 @@
(use (match_dup 2))
]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+ !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
"@
daddh%F0%F1 0,%H2,%L2
daddh%F0%F1 0,%3,%L2"
@@ -263,7 +263,7 @@
(use (match_dup 2))
]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+ !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
"@
dmulh%F0%F1 0,%H2,%L2
dmulh%F0%F1 0,%3, %L2"
@@ -294,8 +294,8 @@
; different USE pairs.
(use (match_dup 2))]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT) &&
- !(GET_CODE(operands[1]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+ !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3])) &&
+ !(GET_CODE(operands[1]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
"@
dsubh%F0%F1 0,%H2,%L2
dsubh%F0%F1 0,%3,%L2
@@ -553,7 +553,7 @@
(plus:DF (match_dup 1)
(match_dup 2)))])]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+ !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
"@
daddh%F0%F1 %H6, %H2, %L2
daddh%F0%F1 %H6, %3, %L2"
@@ -576,7 +576,7 @@
(mult:DF (match_dup 1)
(match_dup 2)))])]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+ !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
"@
dmulh%F0%F1 %H6, %H2, %L2
dmulh%F0%F1 %H6, %3, %L2"
@@ -604,8 +604,8 @@
(minus:DF (match_dup 1)
(match_dup 2)))])]
"TARGET_DPFP &&
- !(GET_CODE(operands[2]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT) &&
- !(GET_CODE(operands[1]) == CONST_DOUBLE && GET_CODE(operands[3]) == CONST_INT)"
+ !(GET_CODE(operands[2]) == CONST_DOUBLE && CONST_INT_P (operands[3])) &&
+ !(GET_CODE(operands[1]) == CONST_DOUBLE && CONST_INT_P (operands[3]))"
"@
dsubh%F0%F1 %H6, %H2, %L2
dsubh%F0%F1 %H6, %3, %L2
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index e0013b32f0f..0c2926dc5e1 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -222,7 +222,7 @@
if ((GET_CODE (plus0) == REG)
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus0)))
- && (GET_CODE (plus1) == CONST_INT))
+ && (CONST_INT_P (plus1)))
{
off = INTVAL (plus1);
@@ -244,7 +244,7 @@
if ((GET_CODE (plus0) == REG)
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| SP_REG_P (REGNO (plus0)))
- && (GET_CODE (plus1) == CONST_INT))
+ && (CONST_INT_P (plus1)))
{
off = INTVAL (plus1);
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 319d7e2a035..dea2ee7cde5 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -190,7 +190,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
base == reg ? NULL_RTX : reg,
picreg);
- if (GET_CODE (addr) == CONST_INT)
+ if (CONST_INT_P (addr))
{
gcc_assert (! reload_in_progress && ! reload_completed);
addr = force_reg (Pmode, addr);
@@ -2743,7 +2743,7 @@ bfin_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (REG_P (XEXP (x, 0))
&& bfin_valid_reg_p (REGNO (XEXP (x, 0)), strict, mode, PLUS)
&& ((GET_CODE (XEXP (x, 1)) == UNSPEC && mode == SImode)
- || (GET_CODE (XEXP (x, 1)) == CONST_INT
+ || (CONST_INT_P (XEXP (x, 1))
&& bfin_valid_add (mode, INTVAL (XEXP (x, 1))))))
return true;
break;
@@ -2802,7 +2802,7 @@ bfin_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
sym = XEXP (x, 0);
x = XEXP (x, 1);
if (GET_CODE (sym) != SYMBOL_REF
- || GET_CODE (x) != CONST_INT)
+ || !CONST_INT_P (x))
return true;
offset = INTVAL (x);
@@ -2861,7 +2861,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
if (mode == SImode)
{
if (GET_CODE (op0) == MULT
- && GET_CODE (XEXP (op0, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (op0, 1)))
{
HOST_WIDE_INT val = INTVAL (XEXP (op0, 1));
if (val == 2 || val == 4)
@@ -2886,7 +2886,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
else if (mode == DImode)
{
*total = 6 * cost2;
- if (GET_CODE (op1) != CONST_INT
+ if (!CONST_INT_P (op1)
|| !satisfies_constraint_Ks7 (op1))
*total += rtx_cost (op1, mode, PLUS, 1, speed);
if (GET_CODE (op0) != REG
@@ -2930,7 +2930,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
if ((GET_CODE (op0) == LSHIFTRT && GET_CODE (op1) == ASHIFT)
|| (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == ZERO_EXTEND)
|| (GET_CODE (op0) == ASHIFT && GET_CODE (op1) == LSHIFTRT)
- || (GET_CODE (op0) == AND && GET_CODE (op1) == CONST_INT))
+ || (GET_CODE (op0) == AND && CONST_INT_P (op1)))
{
*total = cost2;
return true;
@@ -2967,7 +2967,7 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
case SIGN_EXTRACT:
if (outer_code == SET
&& XEXP (x, 1) == const1_rtx
- && GET_CODE (XEXP (x, 2)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 2)))
{
*total = 2 * cost2;
return true;
@@ -3051,7 +3051,7 @@ analyze_push_multiple_operation (rtx op)
if (GET_CODE (dest) != PLUS
|| ! REG_P (XEXP (dest, 0))
|| REGNO (XEXP (dest, 0)) != REG_SP
- || GET_CODE (XEXP (dest, 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (dest, 1))
|| INTVAL (XEXP (dest, 1)) != -i * 4)
return 0;
@@ -3126,7 +3126,7 @@ analyze_pop_multiple_operation (rtx op)
else if (GET_CODE (src) != PLUS
|| ! REG_P (XEXP (src, 0))
|| REGNO (XEXP (src, 0)) != REG_SP
- || GET_CODE (XEXP (src, 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (src, 1))
|| INTVAL (XEXP (src, 1)) != (i - 1) * 4)
return 0;
@@ -3230,9 +3230,9 @@ bfin_expand_cpymem (rtx dst, rtx src, rtx count_exp, rtx align_exp)
HOST_WIDE_INT align = 0;
unsigned HOST_WIDE_INT count = 0;
- if (GET_CODE (align_exp) == CONST_INT)
+ if (CONST_INT_P (align_exp))
align = INTVAL (align_exp);
- if (GET_CODE (count_exp) == CONST_INT)
+ if (CONST_INT_P (count_exp))
{
count = INTVAL (count_exp);
#if 0
@@ -4247,7 +4247,7 @@ harmless_null_pointer_p (rtx mem, int np_reg)
&& REG_P (XEXP (mem, 0)) && (int) REGNO (XEXP (mem, 0)) == np_reg)
{
mem = XEXP (mem, 1);
- if (GET_CODE (mem) == CONST_INT && INTVAL (mem) > 0)
+ if (CONST_INT_P (mem) && INTVAL (mem) > 0)
return true;
}
return false;
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 6ac208d04a5..2adc3273901 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -828,14 +828,14 @@
"reload_completed
/* Always split symbolic operands; split integer constants that are
too large for a single instruction. */
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| (INTVAL (operands[1]) < -32768
|| INTVAL (operands[1]) >= 65536
|| (INTVAL (operands[1]) >= 32768 && PREG_P (operands[0]))))"
[(set (match_dup 0) (high:SI (match_dup 1)))
(set (match_dup 0) (lo_sum:SI (match_dup 0) (match_dup 1)))]
{
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& split_load_immediate (operands))
DONE;
/* ??? Do something about TARGET_LOW_64K. */
@@ -1092,7 +1092,7 @@
xops[6] = gen_reg_rtx (SImode);
xops[7] = gen_rtx_REG (BImode, REG_CC);
if (!register_operand (xops[4], SImode)
- && (GET_CODE (xops[4]) != CONST_INT
+ && (!CONST_INT_P (xops[4])
|| !satisfies_constraint_Ks7 (xops[4])))
xops[4] = force_reg (SImode, xops[4]);
if (!reg_overlap_mentioned_p (operands[0], operands[1])
@@ -1101,7 +1101,7 @@
emit_insn (gen_add_with_carry (xops[0], xops[2], xops[4], xops[7]));
emit_insn (gen_movbisi (xops[6], xops[7]));
if (!register_operand (xops[5], SImode)
- && (GET_CODE (xops[5]) != CONST_INT
+ && (!CONST_INT_P (xops[5])
|| !satisfies_constraint_Ks7 (xops[5])))
xops[5] = force_reg (SImode, xops[5]);
if (xops[5] != const0_rtx)
@@ -1640,7 +1640,7 @@
(match_operand:SI 2 "nonmemory_operand" "")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
@@ -1689,7 +1689,7 @@
(match_operand:SI 2 "const_int_operand" "")))]
""
{
- if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
+ if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 16)
FAIL;
})
@@ -1699,7 +1699,7 @@
(match_operand:SI 2 "const_int_operand" "")))]
""
{
- if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 16)
+ if (!CONST_INT_P (operands[2]) || INTVAL (operands[2]) != 16)
FAIL;
emit_insn (gen_rotl16 (operands[0], operands[1]));
DONE;
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index adf89e17d0b..04eb584df0f 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -153,7 +153,7 @@
return (REG_P (op1)
&& (REGNO (op1) == FRAME_POINTER_REGNUM
|| REGNO (op1) == STACK_POINTER_REGNUM)
- && GET_CODE (op2) == CONST_INT);
+ && CONST_INT_P (op2));
})
;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
@@ -164,7 +164,7 @@
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
|| GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
;; Returns 1 if OP is a plain constant or matched by symbolic_operand.
(define_predicate "symbolic_or_const_operand"
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index f6c9bbfc674..62fab8376be 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1346,7 +1346,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
base == reg ? NULL_RTX : reg,
picreg);
- if (GET_CODE (addr) == CONST_INT)
+ if (CONST_INT_P (addr))
{
gcc_assert (! reload_in_progress && ! reload_completed);
addr = force_reg (Pmode, addr);
@@ -2150,12 +2150,12 @@ c6x_print_operand (FILE *file, rtx x, int code)
return;
case 'k':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
v = INTVAL (x);
fprintf (file, "%s", reg_names[v]);
return;
case 'K':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
v = INTVAL (x);
gcc_assert ((v & 1) == 0);
fprintf (file, "%s:%s", reg_names[v + 1], reg_names[v]);
@@ -2165,7 +2165,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
case 'S':
case 'f':
case 'F':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
v = INTVAL (x);
for (i = 0; i < 32; i++)
{
@@ -2191,12 +2191,12 @@ c6x_print_operand (FILE *file, rtx x, int code)
return;
case 'n':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
output_addr_const (file, GEN_INT (-INTVAL (x)));
return;
case 'r':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
v = INTVAL (x);
if (v < 0)
v = -v;
@@ -2204,7 +2204,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
return;
case 'R':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
v = INTVAL (x);
if (v < 0)
v = -v;
@@ -2212,7 +2212,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
return;
case 'd':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
v = INTVAL (x);
fputs (v == 2 ? "h" : v == 4 ? "w" : "d", file);
return;
@@ -2232,7 +2232,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
{
x = XEXP (x, 0);
gcc_assert (GET_CODE (x) == PLUS);
- gcc_assert (GET_CODE (XEXP (x, 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (x, 1)));
v = INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
@@ -2432,7 +2432,7 @@ c6x_legitimate_address_p_1 (machine_mode mode, rtx x, bool strict,
&& (GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == SYMBOL_REF
|| GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == LABEL_REF))
return !no_large_offset;
- if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (x, 1)))
return false;
off = INTVAL (XEXP (x, 1));
@@ -6010,7 +6010,7 @@ c6x_function_end (FILE *file, const char *fname)
static bool
shift_p (rtx x, enum rtx_code code, int amount)
{
- return (GET_CODE (x) == code && GET_CODE (XEXP (x, 1)) == CONST_INT
+ return (GET_CODE (x) == code && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) == amount);
}
@@ -6057,7 +6057,7 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
&& GET_CODE (XEXP (x, 0)) == LSHIFTRT
&& GET_MODE (XEXP (x, 0)) == GET_MODE_2XWIDER_MODE (mode).require ()
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == MULT
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& INTVAL (XEXP (XEXP (x, 0), 1)) == GET_MODE_BITSIZE (mode))
{
rtx mul = XEXP (XEXP (x, 0), 0);
@@ -6100,7 +6100,7 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD
&& INTEGRAL_MODE_P (mode)
&& GET_CODE (op0) == MULT
- && GET_CODE (XEXP (op0, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (op0, 1))
&& (INTVAL (XEXP (op0, 1)) == 2
|| INTVAL (XEXP (op0, 1)) == 4
|| (code == PLUS && INTVAL (XEXP (op0, 1)) == 8)))
@@ -6261,7 +6261,7 @@ static bool
c6x_output_ttype (rtx x)
{
/* Use special relocations for symbol references. */
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
fputs ("\t.ehtype\t", asm_out_file);
else
fputs ("\t.word\t", asm_out_file);
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index f9bf9ba99ab..56cd0c5e8d6 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -801,7 +801,7 @@
rtx tmpreg = operands[2];
if (GET_CODE (addr) == PLUS && XEXP (addr, 0) == stack_pointer_rtx
- && GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (addr, 1)))
{
unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
val &= GET_MODE_SIZE (<MODE>mode) - 1;
@@ -840,7 +840,7 @@
: operand_subword_force (operands[0], 0, DImode));
if (GET_CODE (addr) == PLUS && XEXP (addr, 0) == stack_pointer_rtx
- && GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (addr, 1)))
{
unsigned HOST_WIDE_INT val = INTVAL (XEXP (addr, 1));
val &= GET_MODE_SIZE (<MODE>mode) - 1;
@@ -1293,8 +1293,8 @@
rtx table = operands[3];
rtx fail = operands[4];
- gcc_assert (GET_CODE (operands[1]) == CONST_INT);
- gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+ gcc_assert (CONST_INT_P (operands[1]));
+ gcc_assert (CONST_INT_P (operands[2]));
if (!reg_or_ucst4_operand (range, SImode))
range = force_reg (SImode, range);
diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md
index e625ae909d3..ea360f95543 100644
--- a/gcc/config/c6x/predicates.md
+++ b/gcc/config/c6x/predicates.md
@@ -86,7 +86,7 @@
(match_test "GET_CODE (XEXP (op,0)) == PLUS
&& (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
|| GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
(define_predicate "const_int_or_symbolic_operand"
(ior (match_operand 0 "symbolic_operand")
@@ -188,7 +188,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
offset = INTVAL (XEXP (op, 1));
op = XEXP (op, 0);
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 42b9e041fd0..9c9c4779eb2 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -68,12 +68,12 @@
/* Nonzero if the rtx X is a signed const int of n bits. */
#define RTX_SIGNED_INT_FITS_N_BITS(X, n) \
- ((GET_CODE (X) == CONST_INT \
+ ((CONST_INT_P (X) \
&& SIGNED_INT_FITS_N_BITS (INTVAL (X), n)) ? 1 : 0)
/* Nonzero if the rtx X is an unsigned const int of n bits. */
#define RTX_UNSIGNED_INT_FITS_N_BITS(X, n) \
- ((GET_CODE (X) == CONST_INT \
+ ((CONST_INT_P (X) \
&& UNSIGNED_INT_FITS_N_BITS (INTVAL (X), n)) ? 1 : 0)
/* Structure for stack computations. */
@@ -783,9 +783,9 @@ cr16_decompose_const (rtx x, int *code, enum data_model_type *data,
case PLUS:
case MINUS:
/* Look into the tree nodes. */
- if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 0)))
cr16_decompose_const (XEXP (x, 1), code, data, treat_as_const);
- else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ else if (CONST_INT_P (XEXP (x, 1)))
cr16_decompose_const (XEXP (x, 0), code, data, treat_as_const);
return;
default:
@@ -1106,7 +1106,7 @@ cr16_decompose_address (rtx addr, struct cr16_address *out,
return CR16_INVALID;
}
/* Now check if the operand 1 of operand 0 is const_int. */
- if (GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
{
disp = XEXP (XEXP (addr, 0), 1);
if (debug_print)
@@ -1164,7 +1164,7 @@ legitimate_pic_operand_p (rtx x)
if (GET_CODE (XEXP (x, 0)) == PLUS
&& (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF)
- && (GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT))
+ && (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return 0;
break;
case MEM:
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index ae528ca80cc..91e96ba67b3 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -340,11 +340,11 @@ enum reg_class
/* This check is for sbit/cbit instruction. */
#define OK_FOR_Z(OP) \
- ((GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == CONST_INT) \
+ ((GET_CODE (OP) == MEM && CONST_INT_P (XEXP (OP, 0))) \
|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
&& GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
- && GET_CODE (XEXP ((XEXP (OP, 0)), 1)) == CONST_INT))
+ && CONST_INT_P (XEXP ((XEXP (OP, 0)), 1))))
/* Stack layout and calling conventions. */
#define STACK_GROWS_DOWNWARD 1
@@ -417,7 +417,7 @@ struct cumulative_args
(GET_CODE (X) == LABEL_REF \
|| GET_CODE (X) == SYMBOL_REF \
|| GET_CODE (X) == CONST \
- || GET_CODE (X) == CONST_INT)
+ || CONST_INT_P (X))
#define MAX_REGS_PER_ADDRESS 2
diff --git a/gcc/config/cr16/cr16.md b/gcc/config/cr16/cr16.md
index 1df9e38f0e8..6f87c734151 100644
--- a/gcc/config/cr16/cr16.md
+++ b/gcc/config/cr16/cr16.md
@@ -414,14 +414,14 @@
(match_operand:QI 2 "nonmemory_operand" "")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* If the constant is not in range, try placing it in a reg */
if (!UNSIGNED_INT_FITS_N_BITS(INTVAL (operands[2]),<shImmBits>))
operands[2] = copy_to_mode_reg(QImode, operands[2]);
}
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
}
)
@@ -486,14 +486,14 @@
(match_operand:QI 2 "reg_or_int_operand" "")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* If the constant is not in range, try placing it in a reg */
if (!UNSIGNED_INT_FITS_N_BITS(INTVAL (operands[2]),<shImmBits>))
operands[2] = copy_to_mode_reg(QImode, operands[2]);
}
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2]));
}
)
@@ -935,7 +935,7 @@
(clobber (match_operand:SI 2 "register_operand" "+r"))]
"flag_pic == FAR_PIC"
{
- if (GET_CODE (operands[0]) != CONST_INT)
+ if (!CONST_INT_P (operands[0]))
return "loadd\t%g0, %2 \n\tjal %2";
else
return "jal %2";
@@ -955,7 +955,7 @@
perform checks on const_int code addresses as it
assumes all const_int are data addresses.
*/
- if (GET_CODE (operands[0]) != CONST_INT)
+ if (!CONST_INT_P (operands[0]))
return "bal (ra), %a0";
else
operands[4] = GEN_INT ((INTVAL (operands[0]))>>1);
@@ -1010,7 +1010,7 @@
(clobber (match_operand:SI 3 "register_operand" "+r"))]
"flag_pic == FAR_PIC"
{
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
return "loadd\t%g1, %3 \n\tjal %3";
else
return "jal %3";
@@ -1031,7 +1031,7 @@
perform checks on const_int code addresses as it
assumes all const_int are data addresses.
*/
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
return "bal (ra), %a1";
else
{
diff --git a/gcc/config/cr16/predicates.md b/gcc/config/cr16/predicates.md
index 7336f6d1be1..755ad8fca5e 100644
--- a/gcc/config/cr16/predicates.md
+++ b/gcc/config/cr16/predicates.md
@@ -117,7 +117,7 @@
(define_predicate "call_imm_operand"
(match_operand 0 "immediate_operand")
{
- if (GET_CODE (op) != CONST_INT) return 1;
+ if (!CONST_INT_P (op)) return 1;
return (UNSIGNED_INT_FITS_N_BITS(INTVAL (op), 24)) ? 1 : 0;
})
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 23c760c1a4d..12421bf2c3b 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1453,7 +1453,7 @@
if (GET_CODE (indreg) == POST_INC)
indreg = XEXP (indreg, 0);
if (!REG_P (indreg)
- || GET_CODE (operands[2]) != CONST_INT
+ || !CONST_INT_P (operands[2])
|| !REG_P (operands[0])
|| REGNO (operands[0]) != 0
|| INTVAL (operands[2]) > CRIS_SP_REGNUM
@@ -1481,7 +1481,7 @@
if (GET_CODE (indreg) == POST_INC)
indreg = XEXP (indreg, 0);
if (!REG_P (indreg)
- || GET_CODE (operands[2]) != CONST_INT
+ || !CONST_INT_P (operands[2])
|| !REG_P (operands[1])
|| REGNO (operands[1]) != 0
|| INTVAL (operands[2]) > CRIS_SP_REGNUM
@@ -3442,7 +3442,7 @@
(match_operand:SI 2 "nonmemory_operand" "r,i")))]
"TARGET_V32"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* Constant operands are zero-extended, so only 32-bit operands
may be negative. */
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 3cfa13e22cd..5e8b14e7665 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -3325,7 +3325,7 @@ csky_print_operand_address (FILE *stream,
decompose_csky_address (x, &addr);
- if (addr.label && addr.disp && GET_CODE (addr.disp) == CONST_INT)
+ if (addr.label && addr.disp && CONST_INT_P (addr.disp))
{
fprintf (stream, "[");
csky_output_constpool_label (stream, addr.label);
@@ -3337,7 +3337,7 @@ csky_print_operand_address (FILE *stream,
csky_output_constpool_label (stream, addr.label);
fprintf (stream, "]");
}
- else if (addr.symbol && addr.disp && GET_CODE (addr.disp) == CONST_INT)
+ else if (addr.symbol && addr.disp && CONST_INT_P (addr.disp))
{
fprintf (stream, "[");
output_addr_const (stream, addr.symbol);
@@ -3349,7 +3349,7 @@ csky_print_operand_address (FILE *stream,
output_addr_const (stream, addr.symbol);
fprintf (stream, "]");
}
- else if (addr.disp && GET_CODE (addr.disp) == CONST_INT)
+ else if (addr.disp && CONST_INT_P (addr.disp))
fprintf (stream, "(%s, %d)",
reg_names[REGNO (addr.base)], (int) INTVAL (addr.disp));
else if (addr.disp && GET_CODE (addr.disp) == UNSPEC)
@@ -4012,7 +4012,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
}
}
/* The situation mov integer to reg. */
- else if (GET_CODE (src) == CONST_INT ||
+ else if (CONST_INT_P (src) ||
(GET_CODE (src) == CONST_DOUBLE && GET_MODE (src) == SFmode))
{
HOST_WIDE_INT x, y;
@@ -4127,7 +4127,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
gcc_unreachable ();
}
}
- else if (GET_CODE (src) == CONST_INT)
+ else if (CONST_INT_P (src))
{
if (REGNO (dst) > 7)
return "lrw\t%0, %x1\t";
@@ -4290,7 +4290,7 @@ csky_output_movedouble (rtx operands[],
else
return "ld.w\t%0, %1\n\tld.w\t%R0, %R1";
}
- else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
+ else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
{
split_double (src, operands + 2, operands + 3);
@@ -4416,7 +4416,7 @@ csky_output_ck801_movedouble (rtx operands[],
else
return "ld.w\t%0, %1\n\tld.w\t%R0, %R1";
}
- else if (GET_CODE (src) == CONST_INT || GET_CODE (src) == CONST_DOUBLE)
+ else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE)
{
split_double (src, operands + 2, operands + 3);
@@ -4733,7 +4733,7 @@ csky_symbolic_address_p (rtx x)
x = XEXP (x, 0);
return ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (x, 0)) == LABEL_REF)
- && GET_CODE (XEXP (x, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (x, 1)));
default:
return 0;
}
@@ -4749,7 +4749,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
bool invert;
rtx cc_reg = gen_rtx_REG (CCmode, CSKY_CC_REGNUM);
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
{
HOST_WIDE_INT val = INTVAL (op1);
@@ -4787,7 +4787,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
}
}
- if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
+ if (CONSTANT_P (op1) && !CONST_INT_P (op1))
op1 = force_reg (GET_MODE (op1), op1);
/* cmpnei: 0-31 (K immediate)
@@ -4802,7 +4802,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
/* Fall through. */
/* Use normal condition, cmpne. */
case NE:
- if (GET_CODE (op1) == CONST_INT
+ if (CONST_INT_P (op1)
&& (TARGET_MINI_REGISTERS
? !csky_literal_K_operand (op1, SImode)
: !csky_literal_I_operand (op1, SImode)))
@@ -4816,7 +4816,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
/* Fall through. */
/* Use normal condition, reversed cmplt. */
case GT:
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
op1 = force_reg (SImode, op1);
break;
@@ -4828,7 +4828,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
/* Use normal condition, cmplt. */
case LT:
/* covered by btsti x,31. */
- if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0
+ if (CONST_INT_P (op1) && INTVAL (op1) != 0
&& (TARGET_MINI_REGISTERS
? !csky_literal_J_operand (op1, SImode)
: !csky_literal_Uk_operand (op1, SImode)))
@@ -4838,13 +4838,13 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
/* Use inverted condition, cmple. */
case GTU:
/* We coped with unsigned > 0 above. */
- gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
+ gcc_assert (!CONST_INT_P (op1) || INTVAL (op1) != 0);
code = LEU;
invert = true;
/* Fall through. */
/* Use normal condition, reversed cmphs. */
case LEU:
- if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
+ if (CONST_INT_P (op1) && INTVAL (op1) != 0)
op1 = force_reg (SImode, op1);
break;
@@ -4855,7 +4855,7 @@ csky_emit_compare (enum rtx_code code, rtx op0, rtx op1)
/* Fall through. */
/* Use normal condition, cmphs. */
case GEU:
- if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0
+ if (CONST_INT_P (op1) && INTVAL (op1) != 0
&& (TARGET_MINI_REGISTERS
? !csky_literal_J_operand (op1, SImode)
: !csky_literal_Uk_operand (op1, SImode)))
@@ -5774,7 +5774,7 @@ csky_legitimize_pic_address (rtx orig, rtx reg, bool gotrel_p)
offset = csky_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
base == reg ? 0 : reg, gotrel_p);
- if (GET_CODE (offset) == CONST_INT)
+ if (CONST_INT_P (offset))
return plus_constant (Pmode, base, INTVAL (offset));
return gen_rtx_PLUS (Pmode, base, offset);
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 13c33e205f3..7a8b382c1d8 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -262,7 +262,7 @@
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (HImode, operands[1]);
else if (CONSTANT_P (operands[1])
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| (! CSKY_CONST_OK_FOR_I (INTVAL (operands[1]))
&& ! CSKY_CONST_OK_FOR_Ub (INTVAL (operands[1]))
&& ! CSKY_CONST_OK_FOR_Uc (INTVAL (operands[1]))))
@@ -303,7 +303,7 @@
if (can_create_pseudo_p () && GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (QImode, operands[1]);
else if (CONSTANT_P (operands[1])
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| (! CSKY_CONST_OK_FOR_I (INTVAL (operands[1]))
&& ! CSKY_CONST_OK_FOR_Ub (INTVAL (operands[1]))
&& ! CSKY_CONST_OK_FOR_Uc (INTVAL (operands[1]))))
@@ -2054,7 +2054,7 @@
int regno, count, i;
rtx base,src;
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
|| GET_CODE (operands[1]) != MEM
@@ -2092,7 +2092,7 @@
/* Support only storing a constant number of registers to memory and
only if at least two registers. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > CSKY_MAX_MULTIPLE_STLD
|| GET_CODE (operands[0]) != MEM
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index 7e0f8d04a0a..0c67e4e9cbf 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -52,7 +52,7 @@
|| GET_MODE (SET_SRC (elt)) != SImode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
- || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
|| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
return 0;
}
@@ -93,7 +93,7 @@
|| GET_MODE (SET_DEST (elt)) != SImode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
- || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
|| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
return 0;
}
@@ -175,7 +175,7 @@
{
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+ if (CONST_INT_P (op) && INTVAL (op) == 0)
return 1;
return 0;
})
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 5ac092583ba..d38867e4227 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -759,7 +759,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
base = machopic_indirect_data_reference (XEXP (orig, 0), reg);
orig = machopic_indirect_data_reference (XEXP (orig, 1),
(base == reg ? 0 : reg));
- if (MACHOPIC_INDIRECT && (GET_CODE (orig) == CONST_INT))
+ if (MACHOPIC_INDIRECT && (CONST_INT_P (orig)))
result = plus_constant (Pmode, base, INTVAL (orig));
else
result = gen_rtx_PLUS (Pmode, base, orig);
@@ -1036,7 +1036,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
base = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
orig = machopic_legitimize_pic_address (XEXP (orig, 1),
Pmode, (base == reg ? 0 : reg));
- if (GET_CODE (orig) == CONST_INT)
+ if (CONST_INT_P (orig))
{
pic_ref = plus_constant (Pmode, base, INTVAL (orig));
is_complex = 1;
@@ -1750,19 +1750,19 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED)
{
if (GET_MODE_SIZE (mode) == 8
- && (GET_CODE (x) == CONST_INT
+ && (CONST_INT_P (x)
|| GET_CODE (x) == CONST_WIDE_INT
|| GET_CODE (x) == CONST_DOUBLE))
return darwin_sections[literal8_section];
else if (GET_MODE_SIZE (mode) == 4
- && (GET_CODE (x) == CONST_INT
+ && (CONST_INT_P (x)
|| GET_CODE (x) == CONST_WIDE_INT
|| GET_CODE (x) == CONST_DOUBLE))
return darwin_sections[literal4_section];
else if (HAVE_GAS_LITERAL16
&& TARGET_64BIT
&& GET_MODE_SIZE (mode) == 16
- && (GET_CODE (x) == CONST_INT
+ && (CONST_INT_P (x)
|| GET_CODE (x) == CONST_WIDE_INT
|| GET_CODE (x) == CONST_DOUBLE
|| GET_CODE (x) == CONST_VECTOR))
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index 657a8886ac7..11f188f13e0 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -1411,9 +1411,9 @@ epiphany_print_operand_address (FILE *file, machine_mode /*mode*/, rtx addr)
}
break;
case PLUS :
- if (GET_CODE (XEXP (addr, 0)) == CONST_INT)
+ if (CONST_INT_P (XEXP (addr, 0)))
offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1);
- else if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ else if (CONST_INT_P (XEXP (addr, 1)))
offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
else
base = XEXP (addr, 0), index = XEXP (addr, 1);
diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h
index 8ebdbfe42f2..38f6cac5a59 100644
--- a/gcc/config/epiphany/epiphany.h
+++ b/gcc/config/epiphany/epiphany.h
@@ -603,14 +603,14 @@ typedef struct GTY (()) machine_function
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST)
+ || CONST_INT_P (X) || GET_CODE (X) == CONST)
#define RTX_OK_FOR_OFFSET_P(MODE, X) \
RTX_OK_FOR_OFFSET_1 (GET_MODE_CLASS (MODE) == MODE_VECTOR_INT \
&& epiphany_vect_align == 4 \
? (machine_mode) SImode : (machine_mode) (MODE), X)
#define RTX_OK_FOR_OFFSET_1(MODE, X) \
- (GET_CODE (X) == CONST_INT \
+ (CONST_INT_P (X) \
&& !(INTVAL (X) & (GET_MODE_SIZE (MODE) - 1)) \
&& INTVAL (X) >= -2047 * (int) GET_MODE_SIZE (MODE) \
&& INTVAL (X) <= 2047 * (int) GET_MODE_SIZE (MODE))
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
index d21fc45e3f1..54e5766241f 100644
--- a/gcc/config/fr30/fr30.c
+++ b/gcc/config/fr30/fr30.c
@@ -579,7 +579,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
case 'A':
/* Print a signed byte value as an unsigned value. */
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
output_operand_lossage ("fr30_print_operand: invalid operand to %%A code");
else
{
@@ -594,7 +594,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
return;
case 'x':
- if (GET_CODE (x) != CONST_INT
+ if (!CONST_INT_P (x)
|| INTVAL (x) < 16
|| INTVAL (x) > 32)
output_operand_lossage ("fr30_print_operand: invalid %%x code");
@@ -645,7 +645,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
if (GET_CODE (XEXP (x0, 0)) != REG
|| REGNO (XEXP (x0, 0)) < FRAME_POINTER_REGNUM
|| REGNO (XEXP (x0, 0)) > STACK_POINTER_REGNUM
- || GET_CODE (XEXP (x0, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (x0, 1)))
{
fprintf (stderr, "bad INDEXed address:");
debug_rtx (x);
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
index bfcaa49d812..85cd49a2ed1 100644
--- a/gcc/config/fr30/fr30.h
+++ b/gcc/config/fr30/fr30.h
@@ -558,14 +558,14 @@ enum reg_class
&& ((MODE) == SImode || (MODE) == SFmode) \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
- && GET_CODE (XEXP (X, 1)) == CONST_INT \
+ && CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 << 6) - 4)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
- && GET_CODE (XEXP (X, 1)) == CONST_INT \
+ && CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 << 9) - 4)) \
goto LABEL; \
} \
@@ -580,7 +580,7 @@ enum reg_class
&& ((MODE) == SImode || (MODE) == SFmode) \
&& GET_CODE (XEXP (X, 0)) == REG \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
- && GET_CODE (XEXP (X, 1)) == CONST_INT \
+ && CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 << 6) - 4)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
@@ -588,7 +588,7 @@ enum reg_class
&& GET_CODE (XEXP (X, 0)) == REG \
&& (REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
|| REGNO (XEXP (X, 0)) == ARG_POINTER_REGNUM) \
- && GET_CODE (XEXP (X, 1)) == CONST_INT \
+ && CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 << 9) - 4)) \
goto LABEL; \
} \
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index dcdf6dd1e97..5a369cfa249 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -656,7 +656,7 @@
if ( GET_CODE (operands[2]) == REG
|| GET_CODE (operands[2]) == SUBREG)
emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
- else if (GET_CODE (operands[2]) != CONST_INT)
+ else if (!CONST_INT_P (operands[2]))
emit_insn (gen_addsi_big_int (operands[0], operands[1], operands[2]));
else if (INTVAL (operands[2]) >= -16
&& INTVAL (operands[2]) <= 15
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 1fb58d1298a..20873856906 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -24,7 +24,7 @@
(match_code "const_int")
{
return
- (GET_CODE (op) == CONST_INT
+ (CONST_INT_P (op)
&& INTVAL (op) >= -512
&& INTVAL (op) <= 508
&& ((INTVAL (op) & 3) == 0));
@@ -117,7 +117,7 @@
{
return
(GET_CODE (op) == REG
- || (GET_CODE (op) == CONST_INT
+ || (CONST_INT_P (op)
&& INTVAL (op) >= -16
&& INTVAL (op) <= 15));
})
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index f0c9351f083..bccd1efa58a 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -569,7 +569,7 @@ frv_const_unspec_p (rtx x, struct frv_unspec *unspec)
{
unspec->offset = 0;
x = XEXP (x, 0);
- if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
{
unspec->offset += INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
@@ -2190,7 +2190,7 @@ frv_expand_block_move (rtx operands[])
rtx orig_src = operands[1];
rtx bytes_rtx = operands[2];
rtx align_rtx = operands[3];
- int constp = (GET_CODE (bytes_rtx) == CONST_INT);
+ int constp = (CONST_INT_P (bytes_rtx));
int align;
int bytes;
int offset;
@@ -2212,7 +2212,7 @@ frv_expand_block_move (rtx operands[])
return FALSE;
/* This should be a fixed size alignment. */
- gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+ gcc_assert (CONST_INT_P (align_rtx));
align = INTVAL (align_rtx);
@@ -2288,7 +2288,7 @@ frv_expand_block_clear (rtx operands[])
rtx orig_dest = operands[0];
rtx bytes_rtx = operands[1];
rtx align_rtx = operands[3];
- int constp = (GET_CODE (bytes_rtx) == CONST_INT);
+ int constp = (CONST_INT_P (bytes_rtx));
int align;
int bytes;
int offset;
@@ -2303,7 +2303,7 @@ frv_expand_block_clear (rtx operands[])
return FALSE;
/* This should be a fixed size alignment. */
- gcc_assert (GET_CODE (align_rtx) == CONST_INT);
+ gcc_assert (CONST_INT_P (align_rtx));
align = INTVAL (align_rtx);
@@ -2540,7 +2540,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
case PLUS:
x0 = XEXP (x, 0);
x1 = XEXP (x, 1);
- if (GET_CODE (x0) == CONST_INT)
+ if (CONST_INT_P (x0))
{
x0 = XEXP (x, 1);
x1 = XEXP (x, 0);
@@ -2557,7 +2557,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
{
if (!x1)
x1 = const0_rtx;
- else if (GET_CODE (x1) != CONST_INT)
+ else if (!CONST_INT_P (x1))
fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
}
@@ -2735,7 +2735,7 @@ frv_print_operand (FILE * file, rtx x, int code)
if (code != 0 && !ISALPHA (code))
value = 0;
- else if (GET_CODE (x) == CONST_INT)
+ else if (CONST_INT_P (x))
value = INTVAL (x);
else if (GET_CODE (x) == CONST_DOUBLE)
@@ -2850,7 +2850,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'g':
/* Print appropriate GOT function. */
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
fatal_insn ("bad insn to frv_print_operand, 'g' modifier:", x);
fputs (unspec_got_name (INTVAL (x)), file);
break;
@@ -2881,15 +2881,15 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'i':
/* For jump instructions, print 'i' if the operand is a constant or
is an expression that adds a constant. */
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fputs ("i", file);
else
{
- if (GET_CODE (x) == CONST_INT
+ if (CONST_INT_P (x)
|| (GET_CODE (x) == PLUS
- && (GET_CODE (XEXP (x, 1)) == CONST_INT
- || GET_CODE (XEXP (x, 0)) == CONST_INT)))
+ && (CONST_INT_P (XEXP (x, 1))
+ || CONST_INT_P (XEXP (x, 0)))))
fputs ("i", file);
}
break;
@@ -2950,7 +2950,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'P':
/* Print PIC label using operand as the number. */
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
fatal_insn ("bad insn to frv_print_operand, P modifier:", x);
fprintf (file, ".LCF%ld", (long)INTVAL (x));
@@ -2964,7 +2964,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'z':
/* If value is 0, print gr0, otherwise it must be a register. */
- if (GET_CODE (x) == CONST_INT && INTVAL (x) == 0)
+ if (CONST_INT_P (x) && INTVAL (x) == 0)
fputs (reg_names[GPR_R0], file);
else if (GET_CODE (x) == REG)
@@ -2976,7 +2976,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'x':
/* Print constant in hex. */
- if (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE)
+ if (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE)
{
fprintf (file, "%s0x%.4lx", IMMEDIATE_PREFIX, (long) value);
break;
@@ -2988,7 +2988,7 @@ frv_print_operand (FILE * file, rtx x, int code)
if (GET_CODE (x) == REG)
fputs (reg_names [REGNO (x)], file);
- else if (GET_CODE (x) == CONST_INT
+ else if (CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE)
fprintf (file, "%s%ld", IMMEDIATE_PREFIX, (long) value);
@@ -4042,7 +4042,7 @@ frv_emit_movsi (rtx dest, rtx src)
sym = XEXP (sym, 0);
if (GET_CODE (sym) == PLUS
&& GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
- && GET_CODE (XEXP (sym, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (sym, 1)))
sym = XEXP (sym, 0);
if (GET_CODE (sym) == SYMBOL_REF)
goto handle_sym;
@@ -4252,13 +4252,13 @@ output_move_single (rtx operands[], rtx insn)
}
}
- else if (GET_CODE (src) == CONST_INT
+ else if (CONST_INT_P (src)
|| GET_CODE (src) == CONST_DOUBLE)
{
/* gpr <- integer/floating constant */
HOST_WIDE_INT value;
- if (GET_CODE (src) == CONST_INT)
+ if (CONST_INT_P (src))
value = INTVAL (src);
else if (mode == SFmode)
@@ -4458,7 +4458,7 @@ output_move_double (rtx operands[], rtx insn)
return "#";
}
- else if (GET_CODE (src) == CONST_INT
+ else if (CONST_INT_P (src)
|| GET_CODE (src) == CONST_DOUBLE)
return "#";
}
@@ -4828,7 +4828,7 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
(clobber (<ccr_reg>))]) */
/* Handle various cases of conditional move involving two constants. */
- if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
+ if (CONST_INT_P (src1) && CONST_INT_P (src2))
{
HOST_WIDE_INT value1 = INTVAL (src1);
HOST_WIDE_INT value2 = INTVAL (src2);
@@ -4859,10 +4859,10 @@ frv_emit_cond_move (rtx dest, rtx test_rtx, rtx src1, rtx src2)
register. */
else
{
- if (GET_CODE (src1) == CONST_INT && INTVAL (src1) != 0)
+ if (CONST_INT_P (src1) && INTVAL (src1) != 0)
src1 = force_reg (GET_MODE (dest), src1);
- if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
+ if (CONST_INT_P (src2) && INTVAL (src2) != 0)
src2 = force_reg (GET_MODE (dest), src2);
}
@@ -4907,7 +4907,7 @@ frv_split_cond_move (rtx operands[])
const0_rtx)));
/* Handle various cases of conditional move involving two constants. */
- if (GET_CODE (src1) == CONST_INT && GET_CODE (src2) == CONST_INT)
+ if (CONST_INT_P (src1) && CONST_INT_P (src2))
{
HOST_WIDE_INT value1 = INTVAL (src1);
HOST_WIDE_INT value2 = INTVAL (src2);
@@ -5074,7 +5074,7 @@ frv_split_minmax (rtx operands[])
/* If are taking the min/max of a nonzero constant, load that first, and
then do a conditional move of the other value. */
- if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
+ if (CONST_INT_P (src2) && INTVAL (src2) != 0)
{
gcc_assert (!rtx_equal_p (dest, src1));
@@ -5731,7 +5731,7 @@ frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
if (dump_file)
{
- if (GET_CODE (value) == CONST_INT)
+ if (CONST_INT_P (value))
fprintf (dump_file, "Register %s will hold %ld\n",
reg_names[ REGNO (reg)], (long)INTVAL (value));
@@ -5936,7 +5936,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
{
op0 = XEXP (src, 0);
op1 = XEXP (src, 1);
- if (GET_CODE (op0) == SIGN_EXTEND && GET_CODE (op1) == CONST_INT)
+ if (GET_CODE (op0) == SIGN_EXTEND && CONST_INT_P (op1))
{
op1 = frv_ifcvt_load_value (op1, insn);
if (op1)
@@ -8516,7 +8516,7 @@ frv_int_to_acc (enum insn_code icode, int opnum, rtx opval)
if ((i & ACC_MASK) == i)
global_regs[i + ACC_FIRST] = global_regs[i + ACCG_FIRST] = 1;
- if (GET_CODE (opval) != CONST_INT)
+ if (!CONST_INT_P (opval))
{
error ("accumulator is not a constant integer");
return NULL_RTX;
@@ -8569,7 +8569,7 @@ frv_matching_accg_mode (machine_mode mode)
static rtx
frv_io_address_cookie (rtx address)
{
- return (GET_CODE (address) == CONST_INT
+ return (CONST_INT_P (address)
? GEN_INT (INTVAL (address) / 8 * 8)
: const0_rtx);
}
@@ -8605,7 +8605,7 @@ frv_read_iacc_argument (machine_mode mode, tree call,
rtx op;
op = frv_read_argument (call, index);
- if (GET_CODE (op) != CONST_INT
+ if (!CONST_INT_P (op)
|| INTVAL (op) < 0
|| INTVAL (op) > IACC_LAST - IACC_FIRST
|| ((INTVAL (op) * 4) & (GET_MODE_SIZE (mode) - 1)) != 0)
@@ -8631,7 +8631,7 @@ frv_read_iacc_argument (machine_mode mode, tree call,
static int
frv_check_constant_argument (enum insn_code icode, int opnum, rtx opval)
{
- if (GET_CODE (opval) != CONST_INT)
+ if (!CONST_INT_P (opval))
{
error ("%qs expects a constant argument", insn_data[icode].name);
return FALSE;
@@ -8764,7 +8764,7 @@ frv_expand_cut_builtin (enum insn_code icode, tree call, rtx target)
if (! op0)
return NULL_RTX;
- if (icode == CODE_FOR_mdcutssi || GET_CODE (op1) == CONST_INT)
+ if (icode == CODE_FOR_mdcutssi || CONST_INT_P (op1))
{
if (! frv_check_constant_argument (icode, 2, op1))
return NULL_RTX;
diff --git a/gcc/config/frv/frv.h b/gcc/config/frv/frv.h
index 501515ca263..219153368ae 100644
--- a/gcc/config/frv/frv.h
+++ b/gcc/config/frv/frv.h
@@ -1470,9 +1470,9 @@ __asm__("\n" \
define this macro if all constants (including `SYMBOL_REF') can be immediate
operands when generating position independent code. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
- ( GET_CODE (X) == CONST_INT \
+ ( CONST_INT_P (X) \
|| GET_CODE (X) == CONST_DOUBLE \
- || (GET_CODE (X) == HIGH && GET_CODE (XEXP (X, 0)) == CONST_INT) \
+ || (GET_CODE (X) == HIGH && CONST_INT_P (XEXP (X, 0))) \
|| got12_operand (X, VOIDmode)) \
\f
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index 6e8db59fdd9..b33c272075a 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -2707,7 +2707,7 @@
""
"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
emit_insn (gen_mulsidi3_const (operands[0], operands[1], operands[2]));
DONE;
@@ -2740,7 +2740,7 @@
""
"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
emit_insn (gen_umulsidi3_const (operands[0], operands[1], operands[2]));
DONE;
@@ -5304,9 +5304,9 @@
rtx reg2;
rtx reg3;
- gcc_assert (GET_CODE (operands[1]) == CONST_INT);
+ gcc_assert (CONST_INT_P (operands[1]));
- gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+ gcc_assert (CONST_INT_P (operands[2]));
/* If we can't generate an immediate instruction, promote to register. */
if (! IN_RANGE (INTVAL (range), -2048, 2047))
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index d89c759da3a..02e5ce97789 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -109,7 +109,7 @@
(define_predicate "gpr_or_int12_operand"
(match_code "reg,subreg,const_int,const")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return IN_RANGE (INTVAL (op), -2048, 2047);
if (got12_operand (op, mode))
@@ -140,7 +140,7 @@
{
int regno;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return IN_RANGE (INTVAL (op), -2048, 2047);
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -169,7 +169,7 @@
(define_predicate "gpr_or_int10_operand"
(match_code "reg,subreg,const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return IN_RANGE (INTVAL (op), -512, 511);
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -194,7 +194,7 @@
(define_predicate "gpr_or_int_operand"
(match_code "reg,subreg,const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return TRUE;
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -469,7 +469,7 @@
if (!integer_register_operand (XEXP (addr, 0), Pmode))
return FALSE;
- if (GET_CODE (XEXP (addr, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (addr, 1)))
return FALSE;
return TRUE;
@@ -490,7 +490,7 @@
(define_predicate "int12_operand"
(match_code "const_int")
{
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return FALSE;
return IN_RANGE (INTVAL (op), -2048, 2047);
@@ -522,7 +522,7 @@
return FALSE;
op = XEXP (op, 0);
- if (GET_CODE (op) == PLUS && GET_CODE (XEXP (op, 1)) == CONST_INT)
+ if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
op = XEXP (op, 0);
return GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == LABEL_REF;
@@ -1025,7 +1025,7 @@
if (got12_operand (addr1, VOIDmode))
return TRUE;
- if (GET_CODE (addr1) != CONST_INT)
+ if (!CONST_INT_P (addr1))
return FALSE;
if ((INTVAL (addr1) & 7) != 0)
@@ -1066,7 +1066,7 @@
(define_predicate "call_operand"
(match_code "reg,subreg,const_int,const,symbol_ref")
{
- if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
+ if (GET_MODE (op) != mode && mode != VOIDmode && !CONST_INT_P (op))
return FALSE;
if (GET_CODE (op) == SYMBOL_REF)
@@ -1085,7 +1085,7 @@
(define_predicate "sibcall_operand"
(match_code "reg,subreg,const_int,const")
{
- if (GET_MODE (op) != mode && mode != VOIDmode && GET_CODE (op) != CONST_INT)
+ if (GET_MODE (op) != mode && mode != VOIDmode && !CONST_INT_P (op))
return FALSE;
/* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
@@ -1101,7 +1101,7 @@
(define_predicate "upper_int16_operand"
(match_code "const_int")
{
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return FALSE;
return ((INTVAL (op) & 0xffff) == 0);
@@ -1112,7 +1112,7 @@
(define_predicate "uint16_operand"
(match_code "const_int")
{
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return FALSE;
return IN_RANGE (INTVAL (op), 0, 0xffff);
@@ -1131,7 +1131,7 @@
return GET_MODE (op) == SImode
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT;
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1));
}
return c == SYMBOL_REF || c == CONST_INT;
@@ -1441,7 +1441,7 @@
(define_predicate "fpr_or_int6_operand"
(match_code "reg,subreg,const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return IN_RANGE (INTVAL (op), -32, 31);
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -1466,7 +1466,7 @@
(define_predicate "int6_operand"
(match_code "const_int")
{
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return FALSE;
return IN_RANGE (INTVAL (op), -32, 31);
@@ -1477,7 +1477,7 @@
(define_predicate "int5_operand"
(match_code "const_int")
{
- return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), -16, 15);
+ return CONST_INT_P (op) && IN_RANGE (INTVAL (op), -16, 15);
})
;; Return 1 if operand is a 5-bit unsigned immediate.
@@ -1485,7 +1485,7 @@
(define_predicate "uint5_operand"
(match_code "const_int")
{
- return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 31);
+ return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 0, 31);
})
;; Return 1 if operand is a 4-bit unsigned immediate.
@@ -1493,7 +1493,7 @@
(define_predicate "uint4_operand"
(match_code "const_int")
{
- return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 15);
+ return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 0, 15);
})
;; Return 1 if operand is a 1-bit unsigned immediate (0 or 1).
@@ -1501,7 +1501,7 @@
(define_predicate "uint1_operand"
(match_code "const_int")
{
- return GET_CODE (op) == CONST_INT && IN_RANGE (INTVAL (op), 0, 1);
+ return CONST_INT_P (op) && IN_RANGE (INTVAL (op), 0, 1);
})
;; Return 1 if operand is a valid ACC register number.
diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md
index cb72132d600..6f2d49b3d4d 100644
--- a/gcc/config/ft32/constraints.md
+++ b/gcc/config/ft32/constraints.md
@@ -28,14 +28,14 @@
(match_test "(!ft32_is_mem_pm(op))")
(ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF")
(match_test "GET_CODE (XEXP (op, 0)) == LABEL_REF")
- (match_test "GET_CODE (XEXP (op, 0)) == CONST_INT")
+ (match_test "CONST_INT_P (XEXP (op, 0))")
(and (match_test "(GET_CODE (XEXP (op, 0)) == PLUS)")
(ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF")
(match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF")
- (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == CONST_INT"))
+ (match_test "CONST_INT_P (XEXP (XEXP (op, 0), 0))"))
(ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == SYMBOL_REF")
(match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == LABEL_REF")
- (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))))
+ (match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))))
(define_memory_constraint "B"
"An offset address."
@@ -56,7 +56,7 @@
(match_test "ft32_is_mem_pm(op) && (
(GET_CODE (XEXP (op, 0)) == SYMBOL_REF) ||
(GET_CODE (XEXP (op, 0)) == LABEL_REF) ||
- (GET_CODE (XEXP (op, 0)) == CONST_INT) ||
+ (CONST_INT_P (XEXP (op, 0))) ||
(GET_CODE (XEXP (op, 0)) == CONST))"
)))
diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md
index a3178a1f5b5..89cf0b587b9 100644
--- a/gcc/config/ft32/predicates.md
+++ b/gcc/config/ft32/predicates.md
@@ -39,7 +39,7 @@
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return 1;
return general_operand (op, mode);
diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index 66b822962ae..b8ecd299cc0 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2640,12 +2640,12 @@
(match_operand:SI 2 "")]
""
{
- if (GET_CODE (operands[1]) != CONST_INT
- || GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[1])
+ || !CONST_INT_P (operands[2]))
{
rtx _0_1_2_3 = gen_rtx_REG (V64SImode, VGPR_REGNO (1));
rtx tmp = _0_1_2_3;
- if (GET_CODE (operands[1]) != CONST_INT
+ if (!CONST_INT_P (operands[1])
|| INTVAL (operands[1]) != 0)
{
tmp = gen_reg_rtx (V64SImode);
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 7df22c8286f..674eed31bc3 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -824,7 +824,7 @@ gcn_fp_constant_p (rtx x, bool allow_vector)
bool
gcn_inline_constant_p (rtx x)
{
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
return INTVAL (x) >= -16 && INTVAL (x) < 64;
if (GET_CODE (x) == CONST_DOUBLE)
return gcn_inline_fp_constant_p (x, false);
@@ -903,7 +903,7 @@ gcn_inline_constant64_p (rtx x)
return true;
}
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
return false;
rtx val_lo = gcn_operand_part (DImode, x, 0);
@@ -921,7 +921,7 @@ gcn_constant64_p (rtx x)
if (!gcn_constant_p (x))
return false;
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
return true;
/* Negative numbers are only allowed if they can be encoded within src0,
@@ -1228,7 +1228,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
|| gcn_address_register_p (x1, SImode, strict))
return true;
else*/
- if (GET_CODE (x1) == CONST_INT)
+ if (CONST_INT_P (x1))
{
if (INTVAL (x1) >= 0 && INTVAL (x1) < (1 << 20)
/* The low bits of the offset are ignored, even when
@@ -1265,7 +1265,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
: !gcn_vec_address_register_p (x, DImode, strict))
return false;
- if (GET_CODE (x1) == CONST_INT)
+ if (CONST_INT_P (x1))
{
if (INTVAL (x1) >= 0 && INTVAL (x1) < (1 << 12)
/* The low bits of the offset are ignored, even when
@@ -1290,7 +1290,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
rtx base = XEXP (x, 0);
rtx offset = XEXP (x, 1);
- bool immediate_p = (GET_CODE (offset) == CONST_INT
+ bool immediate_p = (CONST_INT_P (offset)
/* Signed 13-bit immediate. */
&& INTVAL (offset) >= -(1 << 12)
&& INTVAL (offset) < (1 << 12)
@@ -1353,7 +1353,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
return false;
}
else if (GET_CODE (x1) == CONST_VECTOR
- && GET_CODE (CONST_VECTOR_ELT (x1, 0)) == CONST_INT
+ && CONST_INT_P (CONST_VECTOR_ELT (x1, 0))
&& single_cst_vector_p (x1))
{
x1 = CONST_VECTOR_ELT (x1, 0);
@@ -5245,7 +5245,7 @@ print_operand_address (FILE *file, rtx mem)
reg = XEXP (addr, 0);
offset = XEXP (addr, 1);
print_reg (file, reg);
- if (GET_CODE (offset) == CONST_INT)
+ if (CONST_INT_P (offset))
fprintf (file, " offset:" HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
else
abort ();
@@ -5354,7 +5354,7 @@ print_operand_address (FILE *file, rtx mem)
fprintf (file, ", ");
if (GET_CODE (offset) == REG)
print_reg (file, reg);
- else if (GET_CODE (offset) == CONST_INT)
+ else if (CONST_INT_P (offset))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
else
abort ();
@@ -5678,7 +5678,7 @@ print_operand (FILE *file, rtx x, int code)
rtx val = XEXP (x0, 1);
if (GET_CODE (val) == CONST_VECTOR)
val = CONST_VECTOR_ELT (val, 0);
- if (GET_CODE (val) != CONST_INT)
+ if (!CONST_INT_P (val))
{
output_operand_lossage ("invalid %%xn code");
return;
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index bbd2db29515..f4c8e8d1251 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -583,7 +583,7 @@
global_store_dwordx2\t%A0, %1%O0%g0"
"(reload_completed && !MEM_P (operands[0]) && !MEM_P (operands[1])
&& !gcn_sgpr_move_p (operands[0], operands[1]))
- || (GET_CODE (operands[1]) == CONST_INT && !gcn_constant64_p (operands[1]))"
+ || (CONST_INT_P (operands[1]) && !gcn_constant64_p (operands[1]))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))]
{
@@ -635,7 +635,7 @@
ds_read_b128\t%0, %A1%O1\;s_waitcnt\tlgkmcnt(0)"
"reload_completed
&& REG_P (operands[0])
- && (REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_INT)"
+ && (REG_P (operands[1]) || CONST_INT_P (operands[1]))"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index b68ee395a07..d64eda8a5e0 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -730,7 +730,7 @@ h8300_stack_offset_p (rtx x, int offset)
return (GET_CODE (x) == PLUS
&& XEXP (x, 0) == stack_pointer_rtx
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) == offset);
}
@@ -1502,7 +1502,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
}
break;
case 'G':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
break;
case 'S':
@@ -1631,7 +1631,7 @@ h8300_print_operand (FILE *file, rtx x, int code)
fputs (cond_string (reverse_condition (GET_CODE (x))), file);
break;
case 'm':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
switch (INTVAL (x))
{
case 1:
@@ -1654,39 +1654,39 @@ h8300_print_operand (FILE *file, rtx x, int code)
h8300_print_operand_address (file, VOIDmode, x);
break;
case 's':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "#%ld", (INTVAL (x)) & 0xff);
else
fprintf (file, "%s", byte_reg (x, 0));
break;
case 't':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
else
fprintf (file, "%s", byte_reg (x, 1));
break;
case 'w':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "#%ld", INTVAL (x) & 0xff);
else
fprintf (file, "%s",
byte_reg (x, TARGET_H8300 ? 2 : 0));
break;
case 'x':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff);
else
fprintf (file, "%s",
byte_reg (x, TARGET_H8300 ? 3 : 1));
break;
case 'y':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff);
else
fprintf (file, "%s", byte_reg (x, 0));
break;
case 'z':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff);
else
fprintf (file, "%s", byte_reg (x, 1));
@@ -2155,7 +2155,7 @@ h8300_get_index (rtx x, machine_mode mode, int *size)
rtx index;
if (GET_CODE (x) == AND
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& (factor == 0
|| INTVAL (XEXP (x, 1)) == 0xff * factor
|| INTVAL (XEXP (x, 1)) == 0xffff * factor))
@@ -2170,7 +2170,7 @@ h8300_get_index (rtx x, machine_mode mode, int *size)
}
if (GET_CODE (index) == MULT
- && GET_CODE (XEXP (index, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (index, 1))
&& (factor == 0 || factor == INTVAL (XEXP (index, 1))))
return XEXP (index, 0);
}
@@ -2260,7 +2260,7 @@ static unsigned int
h8300_constant_length (rtx constant)
{
/* Check for (@d:16,Reg). */
- if (GET_CODE (constant) == CONST_INT
+ if (CONST_INT_P (constant)
&& IN_RANGE (INTVAL (constant), -0x8000, 0x7fff))
return 2;
@@ -2285,7 +2285,7 @@ h8300_displacement_length (rtx addr, int size)
/* Check for @(d:2,Reg). */
if (register_operand (XEXP (addr, 0), VOIDmode)
- && GET_CODE (offset) == CONST_INT
+ && CONST_INT_P (offset)
&& (INTVAL (offset) == size
|| INTVAL (offset) == size * 2
|| INTVAL (offset) == size * 3))
@@ -2318,7 +2318,7 @@ h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass)
will fit into a 16-bit immediate field. */
if (TARGET_H8300SX
&& size == 4
- && GET_CODE (op) == CONST_INT
+ && CONST_INT_P (op)
&& IN_RANGE (INTVAL (op), 0, 0xffff))
return 2;
@@ -2682,7 +2682,7 @@ h8sx_emit_movmd (rtx dest, rtx src, rtx length,
if (!flag_omit_frame_pointer && optimize_size)
return false;
- if (GET_CODE (length) == CONST_INT)
+ if (CONST_INT_P (length))
{
rtx dest_reg, src_reg, first_dest, first_src;
HOST_WIDE_INT n;
@@ -2843,7 +2843,7 @@ compute_mov_length (rtx *operands)
if (REG_P (src))
return 4;
- if (GET_CODE (src) == CONST_INT)
+ if (CONST_INT_P (src))
{
if (src == const0_rtx)
return 4;
@@ -2954,7 +2954,7 @@ compute_mov_length (rtx *operands)
return 2;
}
- if (GET_CODE (src) == CONST_INT)
+ if (CONST_INT_P (src))
{
int val = INTVAL (src);
@@ -3020,7 +3020,7 @@ compute_mov_length (rtx *operands)
longest. */
if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG
- && GET_CODE (XEXP (addr, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (addr, 1))
&& INTVAL (XEXP (addr, 1)) > -32768
&& INTVAL (XEXP (addr, 1)) < 32767)
return base_length - 4;
@@ -3051,7 +3051,7 @@ output_plussi (rtx *operands)
if (GET_CODE (operands[2]) == REG)
return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
HOST_WIDE_INT n = INTVAL (operands[2]);
@@ -3067,7 +3067,7 @@ output_plussi (rtx *operands)
}
else
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
@@ -3110,7 +3110,7 @@ output_plussi (rtx *operands)
}
}
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
{
operands[2] = GEN_INT (-INTVAL (operands[2]));
return "sub.l\t%S2,%S0";
@@ -3135,7 +3135,7 @@ compute_plussi_length (rtx *operands)
if (GET_CODE (operands[2]) == REG)
return 6;
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
HOST_WIDE_INT n = INTVAL (operands[2]);
@@ -3151,7 +3151,7 @@ compute_plussi_length (rtx *operands)
}
else
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
@@ -3189,7 +3189,7 @@ compute_plussi_length (rtx *operands)
return 4;
}
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0)
return h8300_length_from_table (operands[0],
GEN_INT (-INTVAL (operands[2])),
&addl_length_table);
@@ -3215,7 +3215,7 @@ compute_plussi_cc (rtx *operands)
}
else
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& register_operand (operands[1], VOIDmode))
{
HOST_WIDE_INT intval = INTVAL (operands[2]);
@@ -3266,7 +3266,7 @@ output_logical_op (machine_mode mode, rtx *operands)
enum rtx_code code = GET_CODE (operands[3]);
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
- (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+ (unsigned HOST_WIDE_INT) ((CONST_INT_P (operands[2]))
/* Always use the full instruction if the
first operand is in memory. It is better
to use define_splits to generate the shorter
@@ -3447,7 +3447,7 @@ compute_logical_op_length (machine_mode mode, rtx *operands)
enum rtx_code code = GET_CODE (operands[3]);
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
- (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+ (unsigned HOST_WIDE_INT) ((CONST_INT_P (operands[2]))
/* Always use the full instruction if the
first operand is in memory. It is better
to use define_splits to generate the shorter
@@ -3593,7 +3593,7 @@ compute_logical_op_cc (machine_mode mode, rtx *operands)
enum rtx_code code = GET_CODE (operands[3]);
/* Pretend that every byte is affected if both operands are registers. */
const unsigned HOST_WIDE_INT intval =
- (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT)
+ (unsigned HOST_WIDE_INT) ((CONST_INT_P (operands[2]))
/* Always use the full instruction if the
first operand is in memory. It is better
to use define_splits to generate the shorter
@@ -3755,7 +3755,7 @@ h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
case ASHIFT:
case LSHIFTRT:
/* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return H8SX_SHIFT_BINARY;
/* Reject out-of-range shift amounts. */
@@ -3774,7 +3774,7 @@ h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op)
return H8SX_SHIFT_NONE;
case ROTATE:
- if (GET_CODE (op) == CONST_INT
+ if (CONST_INT_P (op)
&& (INTVAL (op) == 1
|| INTVAL (op) == 2
|| INTVAL (op) == GET_MODE_BITSIZE (mode) - 2
@@ -4610,7 +4610,7 @@ output_a_shift (rtx *operands)
/* This case must be taken care of by one of the two splitters
that convert a variable shift into a loop. */
- gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+ gcc_assert (CONST_INT_P (operands[2]));
n = INTVAL (operands[2]);
@@ -4776,7 +4776,7 @@ compute_a_shift_length (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
gcc_unreachable ();
}
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
/* Get the assembler code to do one shift. */
get_shift_alg (shift_type, shift_mode, 1, &info);
@@ -4926,7 +4926,7 @@ compute_a_shift_cc (rtx insn ATTRIBUTE_UNUSED, rtx *operands)
/* This case must be taken care of by one of the two splitters
that convert a variable shift into a loop. */
- gcc_assert (GET_CODE (operands[2]) == CONST_INT);
+ gcc_assert (CONST_INT_P (operands[2]));
n = INTVAL (operands[2]);
@@ -4990,7 +4990,7 @@ expand_a_rotate (rtx operands[])
/* We rotate in place. */
emit_move_insn (dst, src);
- if (GET_CODE (rotate_amount) != CONST_INT)
+ if (!CONST_INT_P (rotate_amount))
{
rtx counter = gen_reg_rtx (QImode);
rtx_code_label *start_label = gen_label_rtx ();
@@ -5068,7 +5068,7 @@ output_a_rotate (enum rtx_code code, rtx *operands)
int amount;
machine_mode mode = GET_MODE (dst);
- gcc_assert (GET_CODE (rotate_amount) == CONST_INT);
+ gcc_assert (CONST_INT_P (rotate_amount));
switch (mode)
{
@@ -5173,7 +5173,7 @@ compute_a_rotate_length (rtx *operands)
int amount;
unsigned int length = 0;
- gcc_assert (GET_CODE (amount_rtx) == CONST_INT);
+ gcc_assert (CONST_INT_P (amount_rtx));
amount = INTVAL (amount_rtx);
@@ -5629,7 +5629,7 @@ h8300_eightbit_constant_address_p (rtx x)
&& (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
return 1;
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
return 0;
addr = INTVAL (x);
@@ -5700,7 +5700,7 @@ byte_accesses_mergeable_p (rtx addr1, rtx addr2)
}
else if (GET_CODE (addr1) == PLUS
&& REG_P (XEXP (addr1, 0))
- && GET_CODE (XEXP (addr1, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (addr1, 1)))
{
reg1 = XEXP (addr1, 0);
offset1 = INTVAL (XEXP (addr1, 1));
@@ -5715,7 +5715,7 @@ byte_accesses_mergeable_p (rtx addr1, rtx addr2)
}
else if (GET_CODE (addr2) == PLUS
&& REG_P (XEXP (addr2, 0))
- && GET_CODE (XEXP (addr2, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (addr2, 1)))
{
reg2 = XEXP (addr2, 0);
offset2 = INTVAL (XEXP (addr2, 1));
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index e50521a7b64..7a676f7ba8d 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -478,7 +478,7 @@ struct cum_arg
#define CONSTANT_ADDRESS_P(X) \
(GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || (GET_CODE (X) == CONST_INT \
+ || (CONST_INT_P (X) \
/* We handle signed and unsigned offsets here. */ \
&& INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000) \
&& INTVAL (X) < (TARGET_H8300 ? 0x10000 : 0x1000000)) \
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 778d3e1d132..5f3b98da929 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -349,7 +349,7 @@
}
else
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
/* If either half is zero, use sub.w to clear that
half. */
@@ -395,7 +395,7 @@
case 9:
return "stmac macl,%0";
default:
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
int val = INTVAL (operands[1]);
@@ -2945,8 +2945,8 @@
{
if (TARGET_H8300SX)
{
- if (GET_CODE (operands[1]) == CONST_INT
- && GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[1])
+ && CONST_INT_P (operands[2])
&& INTVAL (operands[1]) <= 8
&& INTVAL (operands[2]) >= 0
&& INTVAL (operands[1]) + INTVAL (operands[2]) <= 8
@@ -2954,7 +2954,7 @@
{
/* If the source operand is zero, it's better to use AND rather
than BFST. Likewise OR if the operand is all ones. */
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
HOST_WIDE_INT mask = (1 << INTVAL (operands[1])) - 1;
if ((INTVAL (operands[3]) & mask) == 0)
@@ -3016,8 +3016,8 @@
{
if (TARGET_H8300SX)
{
- if (GET_CODE (operands[2]) == CONST_INT
- && GET_CODE (operands[3]) == CONST_INT
+ if (CONST_INT_P (operands[2])
+ && CONST_INT_P (operands[3])
&& INTVAL (operands[2]) <= 8
&& INTVAL (operands[3]) >= 0
&& INTVAL (operands[2]) + INTVAL (operands[3]) <= 8
@@ -3167,7 +3167,7 @@
(match_operand 4 "h8300_src_operand" "I,rQi")]))]
"TARGET_H8300SX
&& (GET_MODE (operands[3]) == GET_MODE (operands[4])
- || GET_CODE (operands[4]) == CONST_INT)
+ || CONST_INT_P (operands[4]))
&& GET_MODE_CLASS (GET_MODE (operands[3])) == MODE_INT
&& GET_MODE_SIZE (GET_MODE (operands[3])) <= 4"
"#"
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 70c6c5c1765..14b0604ed64 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -70,7 +70,7 @@
(define_predicate "nibble_operand"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT && TARGET_H8300SX
+ return (CONST_INT_P (op) && TARGET_H8300SX
&& INTVAL (op) >= 0 && INTVAL (op) <= 15);
})
@@ -186,7 +186,7 @@
(define_predicate "single_one_operand"
(match_code "const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
/* We really need to do this masking because 0x80 in QImode is
represented as -128 for example. */
@@ -203,7 +203,7 @@
(define_predicate "single_zero_operand"
(match_code "const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
/* We really need to do this masking because 0x80 in QImode is
represented as -128 for example. */
@@ -288,7 +288,7 @@
if (TARGET_H8300SX)
return 0;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
HOST_WIDE_INT value = INTVAL (op);
@@ -370,7 +370,7 @@
{
return (GET_CODE (op) == MEM
&& (GET_CODE (XEXP (op, 0)) == REG
- || GET_CODE (XEXP (op, 0)) == CONST_INT));
+ || CONST_INT_P (XEXP (op, 0))));
})
;; Return nonzero if X is a stack pointer.
@@ -401,7 +401,7 @@
(define_predicate "const_int_gt_2_operand"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
&& abs (INTVAL (op)) > 2);
})
@@ -411,7 +411,7 @@
(define_predicate "const_int_ge_8_operand"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
&& abs (INTVAL (op)) >= 8);
})
@@ -420,7 +420,7 @@
(define_predicate "const_int_qi_operand"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
&& (INTVAL (op) & 0xff) == INTVAL (op));
})
@@ -429,7 +429,7 @@
(define_predicate "const_int_hi_operand"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
&& (INTVAL (op) & 0xffff) == INTVAL (op));
})
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index a2a6c5cffa1..e9ee4c707bd 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -930,7 +930,7 @@ ia64_load_pair_ok (rtx dst, rtx src)
{
rtx adjust = XEXP (XEXP (XEXP (src, 0), 1), 1);
- if (GET_CODE (adjust) != CONST_INT
+ if (!CONST_INT_P (adjust)
|| INTVAL (adjust) != GET_MODE_SIZE (GET_MODE (src)))
return 0;
}
@@ -1074,7 +1074,7 @@ ia64_legitimate_constant_p (machine_mode mode, rtx x)
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
{
addend = INTVAL (XEXP (XEXP (op, 0), 1));
op = XEXP (XEXP (op, 0), 0);
@@ -1333,7 +1333,7 @@ ia64_expand_move (rtx op0, rtx op1)
if (GET_CODE (op1) == CONST
&& GET_CODE (XEXP (op1, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op1, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (op1, 0), 1)))
{
addend = INTVAL (XEXP (XEXP (op1, 0), 1));
sym = XEXP (XEXP (op1, 0), 0);
@@ -1531,7 +1531,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
}
else
{
- gcc_assert (GET_CODE (XEXP (offset, 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (offset, 1)));
if (INTVAL (XEXP (offset, 1)) < -256 + 8)
{
/* Again the postmodify cannot be made to match,
@@ -5495,7 +5495,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
case POST_MODIFY:
x = XEXP (XEXP (XEXP (x, 0), 1), 1);
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
value = INTVAL (x);
else
{
@@ -5539,7 +5539,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
return;
case 'T':
- if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
+ if (! TARGET_GNU_AS && CONST_INT_P (x))
{
fprintf (file, "0x%x", (int) INTVAL (x) & 0xffffffff);
return;
@@ -5547,7 +5547,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
break;
case 'U':
- if (! TARGET_GNU_AS && GET_CODE (x) == CONST_INT)
+ if (! TARGET_GNU_AS && CONST_INT_P (x))
{
const char *prefix = "0x";
if (INTVAL (x) & 0x80000000)
@@ -5574,7 +5574,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
fputs (reg_names[REGNO (x)], file);
else if (x == CONST0_RTX (GET_MODE (x)))
fputs ("r0", file);
- else if (GET_CODE (x) == CONST_INT)
+ else if (CONST_INT_P (x))
output_addr_const (file, x);
else
output_operand_lossage ("invalid %%r value");
@@ -5948,7 +5948,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
/* This can happen because of the ior/and/etc patterns that accept FP
registers as operands. If the third operand is a constant, then it
needs to be reloaded into a FP register. */
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
return GR_REGS;
/* This can happen because of register elimination in a muldi3 insn.
@@ -10076,7 +10076,7 @@ process_cfa_adjust_cfa (FILE *asm_out_file, rtx pat, rtx insn,
rtx op0 = XEXP (src, 0);
rtx op1 = XEXP (src, 1);
- gcc_assert (op0 == dest && GET_CODE (op1) == CONST_INT);
+ gcc_assert (op0 == dest && CONST_INT_P (op1));
if (INTVAL (op1) < 0)
{
@@ -10179,7 +10179,7 @@ process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
else
{
gcc_assert (GET_CODE (XEXP (dest, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (dest, 0), 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (XEXP (dest, 0), 1)));
base = XEXP (XEXP (dest, 0), 0);
off = INTVAL (XEXP (XEXP (dest, 0), 1));
}
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 037006cdbfa..5d55b190334 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -3237,7 +3237,7 @@
(match_operand:SI 2 "gr_reg_or_5bit_operand" "")))]
""
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
/* Why oh why didn't Intel arrange for SHIFT_COUNT_TRUNCATED? Now
we've got to get rid of stray bits outside the SImode register. */
@@ -3265,7 +3265,7 @@
""
{
rtx subtarget = gen_reg_rtx (DImode);
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
emit_insn (gen_extv (subtarget, gen_lowpart (DImode, operands[1]),
GEN_INT (32 - INTVAL (operands[2])), operands[2]));
else
@@ -3286,7 +3286,7 @@
""
{
rtx subtarget = gen_reg_rtx (DImode);
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
emit_insn (gen_extzv (subtarget, gen_lowpart (DImode, operands[1]),
GEN_INT (32 - INTVAL (operands[2])), operands[2]));
else
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index 4293bcbad2c..f3a34865055 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -45,7 +45,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
offset = INTVAL (XEXP (op, 1));
op = XEXP (op, 0);
@@ -110,7 +110,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
/* FALLTHRU */
@@ -133,7 +133,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
/* FALLTHRU */
@@ -184,7 +184,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
addend = INTVAL (XEXP (op, 1));
@@ -227,7 +227,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
/* We only allow certain offsets for certain tls models. */
@@ -267,7 +267,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (op, 1))
|| (INTVAL (XEXP (op, 1)) & 0x3fff) != 0)
return false;
op = XEXP (op, 0);
@@ -291,7 +291,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
/* FALLTHRU */
@@ -337,7 +337,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
- || GET_CODE (XEXP (op, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (op, 1)))
return false;
addend = INTVAL (XEXP (op, 1));
diff --git a/gcc/config/ia64/vect.md b/gcc/config/ia64/vect.md
index 2f17947a0e4..2f8615ed131 100644
--- a/gcc/config/ia64/vect.md
+++ b/gcc/config/ia64/vect.md
@@ -1024,7 +1024,7 @@
rtx op2 = XVECEXP (operands[1], 0, 1);
rtx x;
- if (GET_CODE (op1) == CONST_INT && GET_CODE (op2) == CONST_INT)
+ if (CONST_INT_P (op1) && CONST_INT_P (op2))
{
x = gen_rtx_CONST_VECTOR (V2SImode, XVEC (operands[1], 0));
emit_move_insn (operands[0], x);
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index c3be6fa0eca..fd290d096ae 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -328,7 +328,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
accept (subreg (const_int)) which will fail to reload. */
if (CONSTANT_ADDRESS_P (xinsn)
&& ! (iq2000_check_split (xinsn, mode))
- && ! (GET_CODE (xinsn) == CONST_INT && ! SMALL_INT (xinsn)))
+ && ! (CONST_INT_P (xinsn) && ! SMALL_INT (xinsn)))
return 1;
while (GET_CODE (xinsn) == SUBREG)
@@ -729,7 +729,7 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
rtx add_op1 = XEXP (op1, 1);
if (GET_CODE (XEXP (op1, 1)) == REG
- && GET_CODE (XEXP (op1, 0)) == CONST_INT)
+ && CONST_INT_P (XEXP (op1, 0)))
add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
operands[2] = add_op0;
@@ -959,7 +959,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
{
/* Comparisons against zero are simple branches. */
- if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
+ if (CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
return 0;
/* Test for beq/bne. */
@@ -972,10 +972,10 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
}
/* Make sure we can handle any constants given to us. */
- if (GET_CODE (cmp0) == CONST_INT)
+ if (CONST_INT_P (cmp0))
cmp0 = force_reg (mode, cmp0);
- if (GET_CODE (cmp1) == CONST_INT)
+ if (CONST_INT_P (cmp1))
{
HOST_WIDE_INT value = INTVAL (cmp1);
@@ -985,7 +985,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
}
/* See if we need to invert the result. */
- invert = (GET_CODE (cmp1) == CONST_INT
+ invert = (CONST_INT_P (cmp1)
? p_info->invert_const : p_info->invert_reg);
if (p_invert != (int *)0)
@@ -996,7 +996,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
/* Comparison to constants, may involve adding 1 to change a LT into LE.
Comparison between two registers, may involve switching operands. */
- if (GET_CODE (cmp1) == CONST_INT)
+ if (CONST_INT_P (cmp1))
{
if (p_info->const_add != 0)
{
@@ -1029,7 +1029,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
cmp1 = temp;
}
- if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
+ if (test == ITEST_NE && CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
reg = cmp0;
else
{
@@ -1086,7 +1086,7 @@ gen_conditional_branch (rtx operands[], machine_mode mode)
cmp1 = const0_rtx;
test_code = NE;
}
- else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
+ else if (CONST_INT_P (cmp1) && INTVAL (cmp1) != 0)
/* We don't want to build a comparison against a nonzero
constant. */
cmp1 = force_reg (mode, cmp1);
@@ -2639,7 +2639,7 @@ expand_one_builtin (enum insn_code icode, rtx target, tree exp,
arg[i] = CALL_EXPR_ARG (exp, i);
op[i] = expand_normal (arg[i]);
mode[i] = insn_data[icode].operand[i].mode;
- if (code[i] == CONST_INT && GET_CODE (op[i]) != CONST_INT)
+ if (code[i] == CONST_INT && !CONST_INT_P (op[i]))
error ("argument %qd is not a constant", i + 1);
if (code[i] == REG
&& ! (*insn_data[icode].operand[i].predicate) (op[i], mode[i]))
@@ -3012,7 +3012,7 @@ iq2000_print_operand_address (FILE * file, machine_mode mode, rtx addr)
case CONST_INT:
case CONST:
output_addr_const (file, addr);
- if (GET_CODE (addr) == CONST_INT)
+ if (CONST_INT_P (addr))
fprintf (file, "(%s)", reg_names [0]);
break;
@@ -3231,16 +3231,16 @@ iq2000_print_operand (FILE *file, rtx op, int letter)
fputs (s, file);
}
- else if (letter == 'x' && GET_CODE (op) == CONST_INT)
+ else if (letter == 'x' && CONST_INT_P (op))
fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL(op));
- else if (letter == 'X' && GET_CODE(op) == CONST_INT)
+ else if (letter == 'X' && CONST_INT_P (op))
fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & (INTVAL (op) >> 16));
- else if (letter == 'd' && GET_CODE(op) == CONST_INT)
+ else if (letter == 'd' && CONST_INT_P (op))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL(op)));
- else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+ else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
fputs (reg_names[GP_REG_FIRST], file);
else if (letter == 'd' || letter == 'x' || letter == 'X')
@@ -3370,7 +3370,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
case ASHIFTRT:
case LSHIFTRT:
if (mode == DImode)
- * total = COSTS_N_INSNS ((GET_CODE (XEXP (x, 1)) == CONST_INT) ? 4 : 12);
+ * total = COSTS_N_INSNS ((CONST_INT_P (XEXP (x, 1))) ? 4 : 12);
else
* total = COSTS_N_INSNS (1);
break;
diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index 89efdafe4e0..04a36ab35b1 100644
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -346,7 +346,7 @@ typedef struct iq2000_args
#define CONSTANT_ADDRESS_P(X) \
( (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
+ || CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
#define MAX_REGS_PER_ADDRESS 1
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index 3363a144dd3..580f22c0d28 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -703,7 +703,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], SImode)
&& !register_operand (operands[1], SImode)
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| INTVAL (operands[1]) != 0))
{
rtx temp = force_reg (SImode, operands[1]);
@@ -734,7 +734,7 @@
(match_operand:SI 1 "move_operand" "d,IKL,Mnis,R,m,dJ,dJ"))]
"(register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+ || (CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))"
"* return iq2000_move_1word (operands, insn, FALSE);"
[(set_attr "type" "move,arith,arith,load,load,store,store")
(set_attr "mode" "SI")
@@ -756,7 +756,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], HImode)
&& !register_operand (operands[1], HImode)
- && ((GET_CODE (operands[1]) != CONST_INT
+ && ((!CONST_INT_P (operands[1])
|| INTVAL (operands[1]) != 0)))
{
rtx temp = force_reg (HImode, operands[1]);
@@ -773,7 +773,7 @@
(match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
"(register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+ || (CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))"
"* return iq2000_move_1word (operands, insn, TRUE);"
[(set_attr "type" "move,arith,load,load,store,store")
(set_attr "mode" "HI")
@@ -795,7 +795,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], QImode)
&& !register_operand (operands[1], QImode)
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| INTVAL (operands[1]) != 0))
{
rtx temp = force_reg (QImode, operands[1]);
@@ -812,7 +812,7 @@
(match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ"))]
"(register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode)
- || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
+ || (CONST_INT_P (operands[1]) && INTVAL (operands[1]) == 0))"
"* return iq2000_move_1word (operands, insn, TRUE);"
[(set_attr "type" "move,arith,load,load,store,store")
(set_attr "mode" "QI")
@@ -914,7 +914,7 @@
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"sll\\t%0,%1,%2\";
@@ -939,7 +939,7 @@
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"sra\\t%0,%1,%2\";
@@ -964,7 +964,7 @@
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return \"srl\\t%0,%1,%2\";
@@ -1555,7 +1555,7 @@
{
register rtx target = operands[0];
- if (GET_CODE (target) == CONST_INT)
+ if (CONST_INT_P (target))
return \"li\\t%@,%0\\n\\tjalr\\t%2,%@\";
else if (CONSTANT_ADDRESS_P (target))
return \"jal\\t%0\";
@@ -1643,7 +1643,7 @@
{
register rtx target = operands[1];
- if (GET_CODE (target) == CONST_INT)
+ if (CONST_INT_P (target))
return \"li\\t%@,%1\\n\\tjalr\\t%3,%@\";
else if (CONSTANT_ADDRESS_P (target))
return \"jal\\t%1\";
@@ -1680,7 +1680,7 @@
{
register rtx target = operands[1];
- if (GET_CODE (target) == CONST_INT)
+ if (CONST_INT_P (target))
return \"li\\t%@,%1\\n\\tjalr\\t%4,%@\";
else if (CONSTANT_ADDRESS_P (target))
return \"jal\\t%1\";
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index 8d648cdb3d5..93fa4737648 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -23,7 +23,7 @@
(define_predicate "uns_arith_operand"
(match_code "reg,const_int,subreg")
{
- if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
+ if (CONST_INT_P (op) && SMALL_INT_UNSIGNED (op))
return 1;
return register_operand (op, mode);
@@ -35,7 +35,7 @@
(define_predicate "arith_operand"
(match_code "reg,const_int,subreg")
{
- if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
+ if (CONST_INT_P (op) && SMALL_INT (op))
return 1;
return register_operand (op, mode);
@@ -54,7 +54,7 @@
(define_predicate "small_int"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
+ return (CONST_INT_P (op) && SMALL_INT (op));
})
;; Return 1 if OP is a 32-bit integer which is too big to be loaded
@@ -65,7 +65,7 @@
{
HOST_WIDE_INT value;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return 0;
value = INTVAL (op);
@@ -140,12 +140,12 @@
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
if (GET_CODE (plus0) == REG
- && GET_CODE (plus1) == CONST_INT && SMALL_INT (plus1)
+ && CONST_INT_P (plus1) && SMALL_INT (plus1)
&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
return 1;
else if (GET_CODE (plus1) == REG
- && GET_CODE (plus0) == CONST_INT && SMALL_INT (plus0)
+ && CONST_INT_P (plus0) && SMALL_INT (plus0)
&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
return 1;
@@ -231,7 +231,7 @@
{
int intval;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return 0;
else
intval = INTVAL (op);
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 7ed9ac00f08..2b04d48f97e 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -227,12 +227,12 @@ gen_int_relational (enum rtx_code code,
else
{
/* We can't have const_ints in cmp0, other than 0. */
- if ((GET_CODE (cmp0) == CONST_INT) && (INTVAL (cmp0) != 0))
+ if ((CONST_INT_P (cmp0)) && (INTVAL (cmp0) != 0))
cmp0 = force_reg (mode, cmp0);
/* If the comparison is against an int not in legal range
move it into a register. */
- if (GET_CODE (cmp1) == CONST_INT)
+ if (CONST_INT_P (cmp1))
{
switch (code)
{
@@ -519,7 +519,7 @@ lm32_print_operand (FILE * file, rtx op, int letter)
output_addr_const (file, XEXP (op, 0));
else if (code == MEM)
output_address (GET_MODE (op), XEXP (op, 0));
- else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+ else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
fprintf (file, "%s", reg_names[0]);
else if (GET_CODE (op) == CONST_DOUBLE)
{
@@ -581,7 +581,7 @@ lm32_print_operand_address (FILE * file, rtx addr)
if (GET_CODE (arg0) == REG && CONSTANT_P (arg1))
{
- if (GET_CODE (arg1) == CONST_INT)
+ if (CONST_INT_P (arg1))
fprintf (file, "(%s+%ld)", reg_names[REGNO (arg0)],
INTVAL (arg1));
else
@@ -882,7 +882,7 @@ lm32_block_move_inline (rtx dest, rtx src, HOST_WIDE_INT length,
int
lm32_expand_block_move (rtx * operands)
{
- if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) <= 32))
+ if ((CONST_INT_P (operands[2])) && (INTVAL (operands[2]) <= 32))
{
lm32_block_move_inline (operands[0], operands[1], INTVAL (operands[2]),
INTVAL (operands[3]));
@@ -997,7 +997,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code,
/* FIXME: Guessing here. */
*total = COSTS_N_INSNS (LM32_NUM_REGS (mode) * 4);
}
- else if (small_mode && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ else if (small_mode && CONST_INT_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (INTVAL (XEXP (x, 1)));
}
@@ -1039,7 +1039,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (1);
else
{
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
int cycles = 0;
unsigned HOST_WIDE_INT i = INTVAL (XEXP (x, 1));
@@ -1217,7 +1217,7 @@ lm32_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool stric
&& REG_P (XEXP (x, 0))
&& ((strict && STRICT_REG_OK_FOR_BASE_P (XEXP (x, 0)))
|| (!strict && NONSTRICT_REG_OK_FOR_BASE_P (XEXP (x, 0))))
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& satisfies_constraint_K (XEXP ((x), 1)))
return true;
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index c330b176a6b..8e98e37d16a 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -306,7 +306,7 @@ enum reg_class
#define CONSTANT_ADDRESS_P(X) \
((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
+ || CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
#define MAX_REGS_PER_ADDRESS 1
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 91a5fe1e004..9c8a72e2a17 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -200,7 +200,7 @@
operands[1])));
DONE;
}
- else if (GET_CODE (operands[1]) == CONST_INT)
+ else if (CONST_INT_P (operands[1]))
{
if (!(satisfies_constraint_K (operands[1])
|| satisfies_constraint_L (operands[1])
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index d0d24bb5f2b..08e0542bd2b 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1846,7 +1846,7 @@ m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == REG
&& REGNO (XEXP (x, 0)) == FB_REGNO
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) < -128
|| INTVAL (XEXP (x, 1)) > (128 - GET_MODE_SIZE (mode))))
{
@@ -1885,7 +1885,7 @@ m32c_legitimize_reload_address (rtx * x,
if (GET_CODE (*x) == PLUS
&& GET_CODE (XEXP (*x, 0)) == REG
&& REGNO (XEXP (*x, 0)) == FB_REGNO
- && GET_CODE (XEXP (*x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (*x, 1))
&& (INTVAL (XEXP (*x, 1)) < -128
|| INTVAL (XEXP (*x, 1)) > (128 - GET_MODE_SIZE (mode))))
{
@@ -1908,8 +1908,8 @@ m32c_legitimize_reload_address (rtx * x,
&& GET_CODE (XEXP (*x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
&& REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
- && GET_CODE (XEXP (XEXP (*x, 0), 1)) == CONST_INT
- && GET_CODE (XEXP (*x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (*x, 0), 1))
+ && CONST_INT_P (XEXP (*x, 1))
)
{
if (type == RELOAD_OTHER)
@@ -2230,7 +2230,7 @@ m32c_rtx_costs (rtx x, machine_mode mode, int outer_code,
case ASHIFT:
case LSHIFTRT:
case ASHIFTRT:
- if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (x, 1)))
{
/* mov.b r1l, r1h */
*total += COSTS_N_INSNS (1);
@@ -2318,7 +2318,7 @@ m32c_address_cost (rtx addr, machine_mode mode ATTRIBUTE_UNUSED,
case REG:
return COSTS_N_INSNS(1);
case PLUS:
- if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (addr, 1)))
{
i = INTVAL (XEXP (addr, 1));
if (i == 0)
@@ -2598,7 +2598,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
code = 0;
}
/* 'x' and 'X' need to be ignored for non-immediates. */
- if ((code == 'x' || code == 'X') && GET_CODE (x) != CONST_INT)
+ if ((code == 'x' || code == 'X') && !CONST_INT_P (x))
code = 0;
encode_pattern (x);
@@ -3553,8 +3553,8 @@ m32c_expand_setmemhi(rtx *operands)
most common case. For counts 8..14 this actually results in
smaller code with no speed penalty because the half-sized
constant can be loaded with a shorter opcode. */
- if (GET_CODE (count) == CONST_INT
- && GET_CODE (val) == CONST_INT
+ if (CONST_INT_P (count)
+ && CONST_INT_P (val)
&& ! (INTVAL (count) & 1)
&& (INTVAL (count) > 1)
&& (INTVAL (val) <= 7 && INTVAL (val) >= -8))
@@ -3614,7 +3614,7 @@ m32c_expand_cpymemhi(rtx *operands)
srca = copy_to_mode_reg (Pmode, srca);
/* Similar to setmem, but we don't need to check the value. */
- if (GET_CODE (count) == CONST_INT
+ if (CONST_INT_P (count)
&& ! (INTVAL (count) & 1)
&& (INTVAL (count) > 1))
{
@@ -3732,7 +3732,7 @@ m32c_prepare_shift (rtx * operands, int scale, int shift_code)
shift_gen_func func = shift_gen_func_for (mode, shift_code);
rtx temp;
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
int maxc = TARGET_A24 && (mode == PSImode || mode == SImode) ? 32 : 8;
int count = INTVAL (operands[2]) * scale;
@@ -3844,7 +3844,7 @@ m32c_expand_neg_mulpsi3 (rtx * operands)
temp1 = gen_reg_rtx (SImode);
temp2 = gen_reg_rtx (SImode);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
scale = gen_reg_rtx (SImode);
emit_insn (gen_zero_extendpsisi2 (scale, operands[2]));
@@ -3866,8 +3866,8 @@ m32c_expand_movcc (rtx *operands)
if (GET_CODE (rel) != EQ && GET_CODE (rel) != NE)
return 1;
- if (GET_CODE (operands[2]) != CONST_INT
- || GET_CODE (operands[3]) != CONST_INT)
+ if (!CONST_INT_P (operands[2])
+ || !CONST_INT_P (operands[3]))
return 1;
if (GET_CODE (rel) == NE)
{
@@ -3896,7 +3896,7 @@ m32c_expand_insv (rtx *operands)
return 1;
/* Our insv opcode (bset, bclr) can only insert a one-bit constant. */
- if (GET_CODE (operands[3]) != CONST_INT)
+ if (!CONST_INT_P (operands[3]))
return 1;
if (INTVAL (operands[3]) != 0
&& INTVAL (operands[3]) != 1
diff --git a/gcc/config/m32c/muldiv.md b/gcc/config/m32c/muldiv.md
index 502baff9b65..4ce774c72e7 100644
--- a/gcc/config/m32c/muldiv.md
+++ b/gcc/config/m32c/muldiv.md
@@ -149,7 +149,7 @@
(mult:PSI (match_operand:PSI 1 "mra_operand" "%0")
(match_operand 2 "m32c_psi_scale" "Ilb")))]
"TARGET_A24"
- "if (GET_CODE (operands[2]) != CONST_INT
+ "if (!CONST_INT_P (operands[2])
|| ! m32c_psi_scale (operands[2], PSImode))
{
m32c_expand_neg_mulpsi3 (operands);
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index d3d307907ec..93cd9173f75 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -199,9 +199,9 @@
rtx pos = XEXP (op, 2);
return (GET_CODE (reg) == REG
&& REGNO (reg) == R1_REGNO
- && GET_CODE (size) == CONST_INT
+ && CONST_INT_P (size)
&& INTVAL (size) == 8
- && GET_CODE (pos) == CONST_INT
+ && CONST_INT_P (pos)
&& INTVAL (pos) == 8);
})
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index ca89f37935e..fa0e5d2f718 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1802,7 +1802,7 @@ output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos
operands[0] = countop;
operands[1] = dataop;
- if (GET_CODE (countop) == CONST_INT)
+ if (CONST_INT_P (countop))
{
register int count = INTVAL (countop);
/* If COUNT is bigger than size of storage unit in use,
@@ -1900,7 +1900,7 @@ m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address)
scale = 1;
if ((TARGET_68020 || TARGET_COLDFIRE)
&& GET_CODE (x) == MULT
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) == 2
|| INTVAL (XEXP (x, 1)) == 4
|| (INTVAL (XEXP (x, 1)) == 8
@@ -2031,7 +2031,7 @@ m68k_decompose_address (machine_mode mode, rtx x,
/* Check for (d16,An) (mode 5). */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach)
&& m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p))
{
@@ -2117,7 +2117,7 @@ m68k_decompose_address (machine_mode mode, rtx x,
{
/* Check for a nonzero base displacement. */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach))
{
address->offset = XEXP (x, 1);
@@ -2495,7 +2495,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
base == reg ? 0 : reg);
- if (GET_CODE (orig) == CONST_INT)
+ if (CONST_INT_P (orig))
pic_ref = plus_constant (Pmode, base, INTVAL (orig));
else
pic_ref = gen_rtx_PLUS (Pmode, base, orig);
@@ -2886,7 +2886,7 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
&& GET_CODE (XEXP (x, 1)) == REG
&& GET_CODE (XEXP (x, 0)) == MULT
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
|| INTVAL (XEXP (XEXP (x, 0), 1)) == 4
|| INTVAL (XEXP (XEXP (x, 0), 1)) == 8))
@@ -2907,7 +2907,7 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
}
if (TUNE_68000_10)
{
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
if (INTVAL (XEXP (x, 1)) < 16)
*total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2;
@@ -2920,13 +2920,13 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
return true;
}
/* A shift by a big integer takes an extra instruction. */
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) == 16))
{
*total = COSTS_N_INSNS (2); /* clrw;swap */
return true;
}
- if (GET_CODE (XEXP (x, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (x, 1))
&& !(INTVAL (XEXP (x, 1)) > 0
&& INTVAL (XEXP (x, 1)) <= 8))
{
@@ -3062,7 +3062,7 @@ output_move_simode_const (rtx *operands)
const char *
output_move_simode (rtx *operands)
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
return output_move_simode_const (operands);
else if ((GET_CODE (operands[1]) == SYMBOL_REF
|| GET_CODE (operands[1]) == CONST)
@@ -3078,7 +3078,7 @@ output_move_simode (rtx *operands)
const char *
output_move_himode (rtx *operands)
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (operands[1] == const0_rtx
&& (DATA_REG_P (operands[0])
@@ -3125,21 +3125,21 @@ output_move_qimode (rtx *operands)
if (operands[1] == const0_rtx)
return "clr%.b %0";
if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0]))
- && GET_CODE (operands[1]) == CONST_INT
+ && CONST_INT_P (operands[1])
&& (INTVAL (operands[1]) & 255) == 255)
{
CC_STATUS_INIT;
return "st %0";
}
}
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& DATA_REG_P (operands[0])
&& INTVAL (operands[1]) < 128
&& INTVAL (operands[1]) >= -128)
return "moveq %1,%0";
if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0]))
return "sub%.l %0,%0";
- if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
+ if (!CONST_INT_P (operands[1]) && CONSTANT_P (operands[1]))
return "move%.l %1,%0";
/* 68k family (including the 5200 ColdFire) does not support byte moves to
from address registers. */
@@ -3176,7 +3176,7 @@ output_move_strictqi (rtx *operands)
static const char *
singlemove_string (rtx *operands)
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
return output_move_simode_const (operands);
return "move%.l %1,%0";
}
@@ -3863,7 +3863,7 @@ static void
m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset)
{
*offset = 0;
- if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
{
*offset += INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
@@ -4094,14 +4094,14 @@ output_addsi3 (rtx *operands)
/* These insns can result from reloads to access
stack slots over 64k from the frame pointer. */
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
return "move%.l %2,%0\n\tadd%.l %1,%0";
if (GET_CODE (operands[2]) == REG)
return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
}
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) <= 8)
@@ -4503,7 +4503,7 @@ print_operand (FILE *file, rtx op, int letter)
output_address (GET_MODE (op), XEXP (op, 0));
if (letter == 'd' && ! TARGET_68020
&& CONSTANT_ADDRESS_P (XEXP (op, 0))
- && !(GET_CODE (XEXP (op, 0)) == CONST_INT
+ && !(CONST_INT_P (XEXP (op, 0))
&& INTVAL (XEXP (op, 0)) < 0x8000
&& INTVAL (XEXP (op, 0)) >= -0x8000))
fprintf (file, MOTOROLA ? ".l" : ":l");
@@ -4717,7 +4717,7 @@ print_operand_address (FILE *file, rtx addr)
{
/* A constant address. */
gcc_assert (address.offset == addr);
- if (GET_CODE (addr) == CONST_INT)
+ if (CONST_INT_P (addr))
{
/* (xxx).w or (xxx).l. */
if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff))
@@ -4938,7 +4938,7 @@ const char *
output_andsi3 (rtx *operands)
{
int logval;
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) | 0xffff) == -1
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0]))
@@ -4953,7 +4953,7 @@ output_andsi3 (rtx *operands)
return "clr%.w %0";
return "and%.w %2,%0";
}
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])))
@@ -4976,7 +4976,7 @@ const char *
output_iorsi3 (rtx *operands)
{
register int logval;
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) >> 16 == 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0]))
@@ -4990,7 +4990,7 @@ output_iorsi3 (rtx *operands)
return "mov%.w %2,%0";
return "or%.w %2,%0";
}
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])))
@@ -5012,7 +5012,7 @@ const char *
output_xorsi3 (rtx *operands)
{
register int logval;
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) >> 16 == 0
&& (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))
&& !TARGET_COLDFIRE)
@@ -5025,7 +5025,7 @@ output_xorsi3 (rtx *operands)
return "not%.w %0";
return "eor%.w %2,%0";
}
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0
&& (DATA_REG_P (operands[0])
|| offsettable_memref_p (operands[0])))
@@ -5287,7 +5287,7 @@ m68k_preferred_reload_class (rtx x, enum reg_class rclass)
return secondary_class;
/* Prefer to use moveq for in-range constants. */
- if (GET_CODE (x) == CONST_INT
+ if (CONST_INT_P (x)
&& reg_class_subset_p (DATA_REGS, rclass)
&& IN_RANGE (INTVAL (x), -0x80, 0x7f))
return DATA_REGS;
@@ -5522,7 +5522,7 @@ sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p)
return OP_TYPE_RN;
}
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
int ival;
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index fc65e524b13..4f7adbff060 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -631,7 +631,7 @@ __transfer_from_trampoline () \
#define CONSTANT_ADDRESS_P(X) \
((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
+ || CONST_INT_P (X) || GET_CODE (X) == CONST \
|| GET_CODE (X) == HIGH) \
&& m68k_legitimate_constant_p (Pmode, X))
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 31e8767e7e3..d3c41028fae 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -513,7 +513,7 @@
return "cmp%.l %d0,%d1";
}
if (ADDRESS_REG_P (operands[0])
- && GET_CODE (operands[1]) == CONST_INT
+ && CONST_INT_P (operands[1])
&& INTVAL (operands[1]) < 0x8000
&& INTVAL (operands[1]) >= -0x8000)
return "cmp%.w %1,%0";
@@ -1601,7 +1601,7 @@
{
if (GET_CODE (operands[0]) == REG
&& (GET_CODE (operands[1]) == MEM
- || GET_CODE (operands[1]) == CONST_INT))
+ || CONST_INT_P (operands[1])))
{
/* Must clear condition codes, since the move.w bases them on
the entire 16 bits, not just the desired 8 bits. */
@@ -1885,7 +1885,7 @@
{
CC_STATUS_INIT;
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& (unsigned) INTVAL (operands[1]) > 8)
{
rtx tmp = operands[1];
@@ -2389,14 +2389,14 @@
operands[1] = low, operands[2] = high;
xoperands[0] = operands[3];
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
else
xoperands[1] = operands[2];
output_asm_insn (output_move_simode (xoperands), xoperands);
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
return "addq%.l %1,%R0\;addx%.l %3,%0";
@@ -2541,7 +2541,7 @@
(match_operand:HI 2 "general_src_operand" "dn,rmSn")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* If the constant would be a negative number when interpreted as
HImode, make it negative. This is usually, but not always, done
@@ -2596,7 +2596,7 @@
(match_operand:HI 1 "general_src_operand" "dn,rmSn")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
/* If the constant would be a negative number when interpreted as
HImode, make it negative. This is usually, but not always, done
@@ -2645,7 +2645,7 @@
(match_dup 0)))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
/* If the constant would be a negative number when interpreted as
HImode, make it negative. This is usually, but not always, done
@@ -2694,7 +2694,7 @@
(match_operand:QI 2 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) >= 128)
operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
@@ -2717,7 +2717,7 @@
(match_operand:QI 1 "general_src_operand" "dn,dmSn")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (INTVAL (operands[1]) >= 128)
operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
@@ -2740,7 +2740,7 @@
(match_dup 0)))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (INTVAL (operands[1]) >= 128)
operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
@@ -2888,14 +2888,14 @@
operands[1] = low, operands[2] = high;
xoperands[0] = operands[3];
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1);
else
xoperands[1] = operands[2];
output_asm_insn (output_move_simode (xoperands), xoperands);
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
return "subq%.l %1,%R0\;subx%.l %3,%0";
@@ -3219,7 +3219,7 @@
{
operands[3] = gen_reg_rtx (SImode);
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff,
0, DImode);
@@ -3271,7 +3271,7 @@
"TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE"
{
operands[3] = gen_reg_rtx (SImode);
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* We have to adjust the operand order for the matching constraints. */
emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
@@ -3654,7 +3654,7 @@
{
if (ISA_HAS_MVS_MVZ
&& DATA_REG_P (operands[0])
- && GET_CODE (operands[2]) == CONST_INT)
+ && CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) == 0x000000ff)
return "mvz%.b %0,%0";
@@ -4563,7 +4563,7 @@
{
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
@@ -4833,7 +4833,7 @@
{
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
@@ -5105,7 +5105,7 @@
{
/* ??? This is a named pattern like this is not allowed to FAIL based
on its operands. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
&& INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
&& (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
@@ -5203,9 +5203,9 @@
(match_operand:SI 2 "general_operand" "dINO")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) == 16)
return "swap %0";
- else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
+ else if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 16)
{
operands[2] = GEN_INT (32 - INTVAL (operands[2]));
return "ror%.l %2,%0";
@@ -5220,7 +5220,7 @@
(match_operand:HI 2 "general_operand" "dIP")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 8)
{
operands[2] = GEN_INT (16 - INTVAL (operands[2]));
return "ror%.w %2,%0";
@@ -5235,7 +5235,7 @@
(match_operand:HI 1 "general_operand" "dIP")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 8)
+ if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) >= 8)
{
operands[1] = GEN_INT (16 - INTVAL (operands[1]));
return "ror%.w %1,%0";
@@ -5250,7 +5250,7 @@
(match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) >= 4)
{
operands[2] = GEN_INT (8 - INTVAL (operands[2]));
return "ror%.b %2,%0";
@@ -5265,7 +5265,7 @@
(match_operand:QI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) >= 4)
+ if (CONST_INT_P (operands[1]) && INTVAL (operands[1]) >= 4)
{
operands[1] = GEN_INT (8 - INTVAL (operands[1]));
return "ror%.b %1,%0";
@@ -5586,7 +5586,7 @@
(match_operand:SI 3 "nonmemory_operand" "dn")))]
"TARGET_68020 && TARGET_BITFIELD"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) != 32)
cc_status.flags |= CC_NOT_NEGATIVE;
@@ -5606,7 +5606,7 @@
(match_operand 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD
&& (INTVAL (operands[3]) == -1
- || (GET_CODE (operands[1]) == CONST_INT
+ || (CONST_INT_P (operands[1])
&& (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
{
CC_STATUS_INIT;
@@ -5644,7 +5644,7 @@
"
{
/* Special case initializing a field to all ones. */
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
if (exact_log2 (INTVAL (operands[3]) + 1) != INTVAL (operands[1]))
operands[3] = force_reg (SImode, operands[3]);
@@ -5680,7 +5680,7 @@
(match_operand:SI 3 "const_int_operand" "n")))]
"TARGET_68020 && TARGET_BITFIELD && IN_RANGE (INTVAL (operands[3]), 0, 31)"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) != 32)
cc_status.flags |= CC_NOT_NEGATIVE;
@@ -5723,10 +5723,10 @@
{
#if 0
/* These special cases are now recognized by a specific pattern. */
- if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2])
&& INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
return "move%.w %3,%0";
- if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[1]) && CONST_INT_P (operands[2])
&& INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
return "move%.b %3,%0";
#endif
@@ -5744,7 +5744,7 @@
"TARGET_68020 && TARGET_BITFIELD"
{
if (operands[1] == const1_rtx
- && GET_CODE (operands[2]) == CONST_INT)
+ && CONST_INT_P (operands[2]))
{
int width = GET_CODE (operands[0]) == REG ? 31 : 7;
return output_btst (operands,
@@ -5771,7 +5771,7 @@
&& !(CONST_INT_P (operands[2]) && !IN_RANGE (INTVAL (operands[2]), 0, 31))"
{
if (operands[1] == const1_rtx
- && GET_CODE (operands[2]) == CONST_INT)
+ && CONST_INT_P (operands[2]))
{
int width = GET_CODE (operands[0]) == REG ? 31 : 7;
return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index ad297883f85..efda85872d1 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -91,10 +91,10 @@
#if HOST_BITS_PER_WIDE_INT > 32
/* All allowed constants will fit a CONST_INT. */
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
&& (INTVAL (op) >= 0 && INTVAL (op) <= 0xffffffffL));
#else
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
|| (GET_CODE (op) == CONST_DOUBLE && CONST_DOUBLE_HIGH (op) == 0));
#endif
})
@@ -111,7 +111,7 @@
gcc_assert (GET_MODE_BITSIZE (mode) > 32);
/* All allowed constants will fit a CONST_INT. */
- return (GET_CODE (op) == CONST_INT
+ return (CONST_INT_P (op)
&& (INTVAL (op) >= (-0x7fffffff - 1) && INTVAL (op) <= 0x7fffffff));
})
@@ -152,7 +152,7 @@
op = XEXP (op, 0);
return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
- && GET_CODE (XEXP (op, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (op, 1)));
#if 0 /* Deleted, with corresponding change in m68k.h,
so as to fit the specs. No CONST_DOUBLE is ever symbolic. */
@@ -272,7 +272,7 @@
(define_predicate "pow2_m1_operand"
(match_code "const_int")
{
- return (GET_CODE (op) == CONST_INT && exact_log2 (INTVAL (op) + 1) >= 0);
+ return (CONST_INT_P (op) && exact_log2 (INTVAL (op) + 1) >= 0);
})
;; Used to detect valid targets for conditional branches
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 06f093eee12..8c249ab2b61 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -491,7 +491,7 @@ mcore_and_cost (rtx x)
{
HOST_WIDE_INT val;
- if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (x, 1)))
return 2;
val = INTVAL (XEXP (x, 1));
@@ -517,7 +517,7 @@ mcore_ior_cost (rtx x)
{
HOST_WIDE_INT val;
- if (GET_CODE (XEXP (x, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (x, 1)))
return 2;
val = INTVAL (XEXP (x, 1));
@@ -588,7 +588,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
rtx cc_reg = gen_rtx_REG (CCmode, CC_REG);
bool invert;
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
{
HOST_WIDE_INT val = INTVAL (op1);
@@ -617,7 +617,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
}
}
- if (CONSTANT_P (op1) && GET_CODE (op1) != CONST_INT)
+ if (CONSTANT_P (op1) && !CONST_INT_P (op1))
op1 = force_reg (SImode, op1);
/* cmpnei: 0-31 (K immediate)
@@ -631,7 +631,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
/* FALLTHRU */
case NE: /* Use normal condition, cmpne. */
- if (GET_CODE (op1) == CONST_INT && ! CONST_OK_FOR_K (INTVAL (op1)))
+ if (CONST_INT_P (op1) && ! CONST_OK_FOR_K (INTVAL (op1)))
op1 = force_reg (SImode, op1);
break;
@@ -641,7 +641,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
/* FALLTHRU */
case GT: /* Use normal condition, reversed cmplt. */
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
op1 = force_reg (SImode, op1);
break;
@@ -651,7 +651,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
/* FALLTHRU */
case LT: /* Use normal condition, cmplt. */
- if (GET_CODE (op1) == CONST_INT &&
+ if (CONST_INT_P (op1) &&
/* covered by btsti x,31. */
INTVAL (op1) != 0 &&
! CONST_OK_FOR_J (INTVAL (op1)))
@@ -660,13 +660,13 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
case GTU: /* Use inverted condition, cmple. */
/* We coped with unsigned > 0 above. */
- gcc_assert (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0);
+ gcc_assert (!CONST_INT_P (op1) || INTVAL (op1) != 0);
code = LEU;
invert = true;
/* FALLTHRU */
case LEU: /* Use normal condition, reversed cmphs. */
- if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
+ if (CONST_INT_P (op1) && INTVAL (op1) != 0)
op1 = force_reg (SImode, op1);
break;
@@ -676,7 +676,7 @@ mcore_gen_compare (enum rtx_code code, rtx op0, rtx op1)
/* FALLTHRU */
case GEU: /* Use normal condition, cmphs. */
- if (GET_CODE (op1) == CONST_INT && INTVAL (op1) != 0)
+ if (CONST_INT_P (op1) && INTVAL (op1) != 0)
op1 = force_reg (SImode, op1);
break;
@@ -700,7 +700,7 @@ mcore_symbolic_address_p (rtx x)
x = XEXP (x, 0);
return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (x, 0)) == LABEL_REF)
- && GET_CODE (XEXP (x, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (x, 1)));
default:
return 0;
}
@@ -1308,7 +1308,7 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
gcc_unreachable ();
}
}
- else if (GET_CODE (src) == CONST_INT)
+ else if (CONST_INT_P (src))
{
HOST_WIDE_INT x, y;
@@ -1399,7 +1399,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
else
return "ldw\t%0,%1\n\tldw\t%R0,%R1";
}
- else if (GET_CODE (src) == CONST_INT)
+ else if (CONST_INT_P (src))
{
if (TARGET_LITTLE_END)
{
@@ -1448,7 +1448,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
int
mcore_arith_S_operand (rtx op)
{
- if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (~INTVAL (op)))
+ if (CONST_INT_P (op) && CONST_OK_FOR_M (~INTVAL (op)))
return 1;
return 0;
@@ -1467,7 +1467,7 @@ mcore_expand_insv (rtx operands[])
/* To get width 1 insv, the test in store_bit_field() (expmed.c, line 191)
for width==1 must be removed. Look around line 368. This is something
we really want the md part to do. */
- if (width == 1 && GET_CODE (operands[3]) == CONST_INT)
+ if (width == 1 && CONST_INT_P (operands[3]))
{
/* Do directly with bseti or bclri. */
/* RBE: 2/97 consider only low bit of constant. */
@@ -1508,7 +1508,7 @@ mcore_expand_insv (rtx operands[])
immediates. */
/* If setting the entire field, do it directly. */
- if (GET_CODE (operands[3]) == CONST_INT
+ if (CONST_INT_P (operands[3])
&& INTVAL (operands[3]) == ((1 << width) - 1))
{
mreg = force_reg (SImode, GEN_INT (INTVAL (operands[3]) << posn));
@@ -1525,7 +1525,7 @@ mcore_expand_insv (rtx operands[])
gen_rtx_AND (SImode, operands[0], mreg)));
/* If the source is constant 0, we've nothing to add back. */
- if (GET_CODE (operands[3]) == CONST_INT && INTVAL (operands[3]) == 0)
+ if (CONST_INT_P (operands[3]) && INTVAL (operands[3]) == 0)
return 1;
/* XXX: Should we worry about more games with constant values?
@@ -1646,7 +1646,7 @@ mcore_expand_block_move (rtx *operands)
{
HOST_WIDE_INT align, bytes, max;
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
return false;
bytes = INTVAL (operands[2]);
@@ -2303,7 +2303,7 @@ is_cond_candidate (rtx insn)
GET_CODE (SUBREG_REG (src)) == REG)) &&
GET_MODE (src) == SImode)
return COND_MOV_INSN;
- else if (GET_CODE (src) == CONST_INT &&
+ else if (CONST_INT_P (src) &&
INTVAL (src) == 0)
return COND_CLR_INSN;
else if (GET_CODE (src) == PLUS &&
@@ -2311,14 +2311,14 @@ is_cond_candidate (rtx insn)
(GET_CODE (XEXP (src, 0)) == SUBREG &&
GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
GET_MODE (XEXP (src, 0)) == SImode &&
- GET_CODE (XEXP (src, 1)) == CONST_INT &&
+ CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == 1)
return COND_INC_INSN;
else if (((GET_CODE (src) == MINUS &&
- GET_CODE (XEXP (src, 1)) == CONST_INT &&
+ CONST_INT_P (XEXP (src, 1)) &&
INTVAL( XEXP (src, 1)) == 1) ||
(GET_CODE (src) == PLUS &&
- GET_CODE (XEXP (src, 1)) == CONST_INT &&
+ CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == -1)) &&
(GET_CODE (XEXP (src, 0)) == REG ||
(GET_CODE (XEXP (src, 0)) == SUBREG &&
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index c6893518dc0..71f0bc0b17c 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -335,7 +335,7 @@
""
"
{
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0
&& ! mcore_arith_S_operand (operands[2]))
{
HOST_WIDE_INT not_value = ~ INTVAL (operands[2]);
@@ -537,7 +537,7 @@
; ""
; "
;{
-; if (GET_CODE (operands[2]) != CONST_INT
+; if (!CONST_INT_P (operands[2])
; || INTVAL (operands[2]) != 1)
; FAIL;
;}")
@@ -685,7 +685,7 @@
/* Convert adds to subtracts if this makes loading the constant cheaper.
But only if we are allowed to generate new pseudos. */
if (! (reload_in_progress || reload_completed)
- && GET_CODE (operands[2]) == CONST_INT
+ && CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < -32)
{
HOST_WIDE_INT neg_value = - INTVAL (operands[2]);
@@ -716,7 +716,7 @@
;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
;; (match_operand:SI 2 "const_int_operand" "g")))]
-;; "GET_CODE(operands[2]) == CONST_INT
+;; "CONST_INT_P (operands[2])
;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
;; "*
@@ -774,7 +774,7 @@
;; [(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
;; (plus:SI (match_operand:SI 1 "mcore_arith_reg_operand" "%0")
;; (match_operand:SI 2 "const_int_operand" "g")))]
-;; "TARGET_RBETEST && GET_CODE(operands[2]) == CONST_INT
+;; "TARGET_RBETEST && CONST_INT_P (operands[2])
;; && ((INTVAL (operands[2]) > 32 && INTVAL(operands[2]) <= 64)
;; || (INTVAL (operands[2]) < -32 && INTVAL(operands[2]) >= -64))"
;; "*
@@ -881,7 +881,7 @@
(plus:DI (match_operand:DI 1 "mcore_arith_reg_operand" "0")
(match_operand:SI 2 "const_int_operand" "r")))
(clobber (reg:CC 17))]
- "GET_CODE (operands[2]) == CONST_INT
+ "CONST_INT_P (operands[2])
&& INTVAL (operands[2]) > 0 && ! (INTVAL (operands[2]) & 0x80000000)"
"*
{
@@ -1210,7 +1210,7 @@
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (HImode, operands[1]);
else if (CONSTANT_P (operands[1])
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| (! CONST_OK_FOR_I (INTVAL (operands[1]))
&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
&& ! CONST_OK_FOR_N (INTVAL (operands[1]))))
@@ -1243,7 +1243,7 @@
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (QImode, operands[1]);
else if (CONSTANT_P (operands[1])
- && (GET_CODE (operands[1]) != CONST_INT
+ && (!CONST_INT_P (operands[1])
|| (! CONST_OK_FOR_I (INTVAL (operands[1]))
&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
&& ! CONST_OK_FOR_N (INTVAL (operands[1]))))
@@ -1274,7 +1274,7 @@
{
if (GET_CODE (operands[0]) == MEM)
operands[1] = force_reg (DImode, operands[1]);
- else if (GET_CODE (operands[1]) == CONST_INT
+ else if (CONST_INT_P (operands[1])
&& ! CONST_OK_FOR_I (INTVAL (operands[1]))
&& ! CONST_OK_FOR_M (INTVAL (operands[1]))
&& ! CONST_OK_FOR_N (INTVAL (operands[1])))
@@ -1363,7 +1363,7 @@
/* Support only loading a constant number of registers from memory and
only if at least two registers. The last register must be r15. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM
|| XEXP (operands[1], 0) != stack_pointer_rtx
@@ -1401,7 +1401,7 @@
/* Support only storing a constant number of registers to memory and
only if at least two registers. The last register must be r15. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
|| XEXP (operands[0], 0) != stack_pointer_rtx
@@ -1855,8 +1855,8 @@
(ne (reg:CC 17) (const_int 0))
(match_operand:SI 1 "mcore_arith_O_operand" "O")
(match_operand:SI 2 "mcore_arith_O_operand" "O")))]
- " GET_CODE (operands[1]) == CONST_INT
- && GET_CODE (operands[2]) == CONST_INT
+ " CONST_INT_P (operands[1])
+ && CONST_INT_P (operands[2])
&& ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
|| (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
"* return mcore_output_cmov (operands, 1, NULL);"
@@ -1886,8 +1886,8 @@
(eq (reg:CC 17) (const_int 0))
(match_operand:SI 1 "mcore_arith_O_operand" "O")
(match_operand:SI 2 "mcore_arith_O_operand" "O")))]
- " GET_CODE (operands[1]) == CONST_INT
- && GET_CODE (operands[2]) == CONST_INT
+ " CONST_INT_P (operands[1])
+ && CONST_INT_P (operands[2])
&& ( (INTVAL (operands[1]) - INTVAL (operands[2]) == 1)
|| (INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
"* return mcore_output_cmov (operands, 0, NULL);"
@@ -1962,8 +1962,8 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_O_operand" "O")
(match_operand:SI 3 "mcore_arith_O_operand" "O")))]
- " GET_CODE (operands[2]) == CONST_INT
- && GET_CODE (operands[3]) == CONST_INT
+ " CONST_INT_P (operands[2])
+ && CONST_INT_P (operands[3])
&& ( (INTVAL (operands[2]) - INTVAL (operands[3]) == 1)
|| (INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
"*
@@ -2044,8 +2044,8 @@
(eq (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
(match_operand:SI 1 "mcore_arith_O_operand" "O")
(match_operand:SI 2 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[1]) == CONST_INT &&
- GET_CODE (operands[2]) == CONST_INT &&
+ "CONST_INT_P (operands[1]) &&
+ CONST_INT_P (operands[2]) &&
((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
(INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
"* return mcore_output_cmov(operands, 1, NULL);"
@@ -2075,8 +2075,8 @@
(eq (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
(match_operand:SI 1 "mcore_arith_O_operand" "O")
(match_operand:SI 2 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[1]) == CONST_INT &&
- GET_CODE (operands[2]) == CONST_INT &&
+ "CONST_INT_P (operands[1]) &&
+ CONST_INT_P (operands[2]) &&
((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
(INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
"* return mcore_output_cmov (operands, 0, NULL);"
@@ -2111,8 +2111,8 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_O_operand" "O")
(match_operand:SI 3 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[1]) == CONST_INT &&
- GET_CODE (operands[2]) == CONST_INT &&
+ "CONST_INT_P (operands[1]) &&
+ CONST_INT_P (operands[2]) &&
((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
(INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
"*
@@ -2152,8 +2152,8 @@
(ne (eq:SI (reg:CC 17) (const_int 0)) (const_int 0))
(match_operand:SI 1 "mcore_arith_O_operand" "O")
(match_operand:SI 2 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[1]) == CONST_INT &&
- GET_CODE (operands[2]) == CONST_INT &&
+ "CONST_INT_P (operands[1]) &&
+ CONST_INT_P (operands[2]) &&
((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
(INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
"* return mcore_output_cmov (operands, 0, NULL);"
@@ -2183,8 +2183,8 @@
(ne (ne:SI (reg:CC 17) (const_int 0)) (const_int 0))
(match_operand:SI 1 "mcore_arith_O_operand" "O")
(match_operand:SI 2 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[1]) == CONST_INT &&
- GET_CODE (operands[2]) == CONST_INT &&
+ "CONST_INT_P (operands[1]) &&
+ CONST_INT_P (operands[2]) &&
((INTVAL (operands[1]) - INTVAL (operands[2]) == 1) ||
(INTVAL (operands[2]) - INTVAL (operands[1]) == 1))"
"* return mcore_output_cmov (operands, 1, NULL);"
@@ -2218,8 +2218,8 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_O_operand" "O")
(match_operand:SI 3 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[2]) == CONST_INT &&
- GET_CODE (operands[3]) == CONST_INT &&
+ "CONST_INT_P (operands[2]) &&
+ CONST_INT_P (operands[3]) &&
((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
(INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
"*
@@ -2261,8 +2261,8 @@
(const_int 0))
(match_operand:SI 2 "mcore_arith_O_operand" "O")
(match_operand:SI 3 "mcore_arith_O_operand" "O")))]
- "GET_CODE (operands[2]) == CONST_INT &&
- GET_CODE (operands[3]) == CONST_INT &&
+ "CONST_INT_P (operands[2]) &&
+ CONST_INT_P (operands[3]) &&
((INTVAL (operands[2]) - INTVAL (operands[3]) == 1) ||
(INTVAL (operands[3]) - INTVAL (operands[2]) == 1))"
"*
@@ -2623,7 +2623,7 @@
(set (match_operand:SI 0 "mcore_arith_reg_operand" "=r")
(match_operand:SI 1 "mcore_arith_reg_operand" "+r"))
(set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
- "GET_CODE(operands[2]) == CONST_INT"
+ "CONST_INT_P (operands[2])"
"#"
[(set_attr "length" "4")])
@@ -2632,7 +2632,7 @@
(set (match_operand:SI 0 "mcore_arith_reg_operand" "")
(match_operand:SI 1 "mcore_arith_reg_operand" ""))
(set (match_dup 1) (plus:SI (match_dup 1) (match_operand 2 "mcore_arith_any_imm_operand" "")))])]
- "GET_CODE(operands[2]) == CONST_INT &&
+ "CONST_INT_P (operands[2]) &&
operands[0] != operands[1]"
[(set (match_dup 0) (match_dup 1))
(set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2)))])
@@ -2841,7 +2841,7 @@
if (GET_CODE (operands[3]) == REG)
{
- if (REGNO (operands[3]) == op0 && GET_CODE (operands[4]) == CONST_INT
+ if (REGNO (operands[3]) == op0 && CONST_INT_P (operands[4])
&& INTVAL (operands[4]) == 0)
return \"btsti %1,%2\\n\\tclrf %0\";
else if (GET_CODE (operands[4]) == REG)
@@ -2854,7 +2854,7 @@
gcc_unreachable ();
}
- else if (GET_CODE (operands[3]) == CONST_INT
+ else if (CONST_INT_P (operands[3])
&& INTVAL (operands[3]) == 0
&& GET_CODE (operands[4]) == REG)
return \"btsti %1,%2\\n\\tclrt %0\";
@@ -2978,7 +2978,7 @@
}
/* For small constant growth, we unroll the code. */
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& INTVAL (operands[1]) < 8 * STACK_UNITS_MAXSTEP)
{
HOST_WIDE_INT left = INTVAL(operands[1]);
@@ -3016,7 +3016,7 @@
emit_insn (gen_movsi (tmp, operands[1]));
emit_insn (gen_movsi (step, GEN_INT (STACK_UNITS_MAXSTEP)));
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
{
out_label = gen_label_rtx ();
test = gen_rtx_GEU (VOIDmode, step, tmp); /* quick out */
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index baf0e20acdc..344a1e0b14e 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -80,7 +80,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_J (INTVAL (op)))
+ if (CONST_INT_P (op) && CONST_OK_FOR_J (INTVAL (op)))
return 1;
return 0;
@@ -94,7 +94,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
+ if (CONST_INT_P (op) && CONST_OK_FOR_K (INTVAL (op)))
return 1;
return 0;
@@ -108,7 +108,7 @@
if (register_operand (op, mode))
return 1;
- if ( GET_CODE (op) == CONST_INT
+ if ( CONST_INT_P (op)
&& CONST_OK_FOR_K (INTVAL (op))
&& INTVAL (op) != 0)
return 1;
@@ -124,7 +124,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_M (INTVAL (op)))
+ if (CONST_INT_P (op) && CONST_OK_FOR_M (INTVAL (op)))
return 1;
return 0;
@@ -138,7 +138,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
if (CONST_OK_FOR_K (INTVAL (op)) || (mcore_num_zeros (INTVAL (op)) <= 2))
return 1;
@@ -156,7 +156,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_O (INTVAL (op)))
+ if (CONST_INT_P (op) && CONST_OK_FOR_O (INTVAL (op)))
return 1;
return 0;
@@ -170,7 +170,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && const_ok_for_mcore (INTVAL (op)))
+ if (CONST_INT_P (op) && const_ok_for_mcore (INTVAL (op)))
return 1;
return 0;
@@ -184,7 +184,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return 1;
return 0;
@@ -195,7 +195,7 @@
(define_predicate "mcore_literal_K_operand"
(match_code "const_int")
{
- if (GET_CODE (op) == CONST_INT && CONST_OK_FOR_K (INTVAL (op)))
+ if (CONST_INT_P (op) && CONST_OK_FOR_K (INTVAL (op)))
return 1;
return 0;
@@ -209,7 +209,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
/* The following has been removed because it precludes large constants from being
returned as valid source operands for and add/sub insn. While large
@@ -242,7 +242,7 @@
if (register_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+ if (CONST_INT_P (op) && INTVAL (op) == 0)
return 1;
return 0;
@@ -281,7 +281,7 @@
|| GET_MODE (SET_SRC (elt)) != SImode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
- || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
|| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1)) != i * 4)
return 0;
}
@@ -321,7 +321,7 @@
|| GET_MODE (SET_DEST (elt)) != SImode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
- || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
|| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1)) != i * 4)
return 0;
}
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index c2cbe3b016c..0569572337d 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -314,12 +314,12 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
if (GET_CODE (plus0) != REG)
return 0;
- if (GET_CODE (plus0) == REG && GET_CODE (plus1) == CONST_INT
+ if (GET_CODE (plus0) == REG && CONST_INT_P (plus1)
&& SMALL_INT (plus1))
{
return 1;
}
- else if (GET_CODE (plus1) == REG && GET_CODE (plus0) == CONST_INT)
+ else if (GET_CODE (plus1) == REG && CONST_INT_P (plus0))
{
return 1;
}
@@ -765,7 +765,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
info->type = ADDRESS_REG;
info->regA = xplus0;
- if (GET_CODE (xplus1) == CONST_INT)
+ if (CONST_INT_P (xplus1))
{
info->offset = xplus1;
return true;
@@ -803,7 +803,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
/* for (plus x const_int) just look at x. */
if (GET_CODE (xconst0) == PLUS
- && GET_CODE (XEXP (xconst0, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (xconst0, 1))
&& (SMALL_INT (XEXP (xconst0, 1))
|| GET_CODE (XEXP (xconst0, 0)) == UNSPEC))
{
@@ -929,7 +929,7 @@ bool
microblaze_constant_address_p (rtx x)
{
return ((GET_CODE (x) == LABEL_REF) || (GET_CODE (x) == SYMBOL_REF)
- || GET_CODE (x) == CONST_INT
+ || CONST_INT_P (x)
|| (GET_CODE (x) == CONST
&& ! (flag_pic && pic_address_needs_scratch (x))));
}
@@ -1256,7 +1256,7 @@ bool
microblaze_expand_block_move (rtx dest, rtx src, rtx length, rtx align_rtx)
{
- if (GET_CODE (length) == CONST_INT)
+ if (CONST_INT_P (length))
{
unsigned HOST_WIDE_INT bytes = UINTVAL (length);
unsigned int align = UINTVAL (align_rtx);
@@ -1346,7 +1346,7 @@ microblaze_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
}
else if (!TARGET_SOFT_MUL)
*total = COSTS_N_INSNS (1);
- else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ else if (CONST_INT_P (XEXP (x, 1)))
{
/* Add 1 to make shift slightly more expensive than add. */
*total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))) + 1;
@@ -1506,7 +1506,7 @@ pic_address_needs_scratch (rtx x)
p1 = XEXP (XEXP (x, 0), 1);
if ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
- && (GET_CODE (p1) == CONST_INT)
+ && (CONST_INT_P (p1))
&& (flag_pic == 2 || microblaze_tls_symbol_p (p0) || !SMALL_INT (p1)))
return 1;
}
@@ -2491,19 +2491,19 @@ print_operand (FILE * file, rtx op, int letter)
print_operand_address (file, op);
}
- else if (letter == 'x' && GET_CODE (op) == CONST_INT)
+ else if (letter == 'x' && CONST_INT_P (op))
fprintf (file, HOST_WIDE_INT_PRINT_HEX, 0xffff & INTVAL (op));
- else if (letter == 'X' && GET_CODE (op) == CONST_INT)
+ else if (letter == 'X' && CONST_INT_P (op))
fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (op));
- else if (letter == 'd' && GET_CODE (op) == CONST_INT)
+ else if (letter == 'd' && CONST_INT_P (op))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, (INTVAL (op)));
- else if (letter == 'z' && GET_CODE (op) == CONST_INT && INTVAL (op) == 0)
+ else if (letter == 'z' && CONST_INT_P (op) && INTVAL (op) == 0)
fputs (reg_names[GP_REG_FIRST], file);
- else if (letter == 's' && GET_CODE (op) == CONST_INT)
+ else if (letter == 's' && CONST_INT_P (op))
if (INTVAL (op) < 0)
fputs ("-1", file);
else
@@ -3388,7 +3388,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
if (!register_operand (op0, SImode)
&& !register_operand (op1, SImode)
- && (GET_CODE (op1) != CONST_INT || INTVAL (op1) != 0))
+ && (!CONST_INT_P (op1) || INTVAL (op1) != 0))
{
rtx temp = force_reg (SImode, op1);
emit_move_insn (op0, temp);
@@ -3431,7 +3431,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
p0 = XEXP (p0, 0);
}
- if (GET_CODE (p0) == UNSPEC && GET_CODE (p1) == CONST_INT
+ if (GET_CODE (p0) == UNSPEC && CONST_INT_P (p1)
&& flag_pic && TARGET_PIC_DATA_TEXT_REL)
{
result = gen_rtx_CONST (Pmode, p0);
@@ -3449,7 +3449,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
p0 = XEXP (XEXP (op1, 0), 0);
p1 = XEXP (XEXP (op1, 0), 1);
- if ((GET_CODE (p1) == CONST_INT)
+ if ((CONST_INT_P (p1))
&& ((GET_CODE (p0) == UNSPEC)
|| ((GET_CODE (p0) == SYMBOL_REF || GET_CODE (p0) == LABEL_REF)
&& (flag_pic == 2 || microblaze_tls_symbol_p (p0)
@@ -3471,12 +3471,12 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
int
microblaze_expand_shift (rtx operands[])
{
- gcc_assert ((GET_CODE (operands[2]) == CONST_INT)
+ gcc_assert ((CONST_INT_P (operands[2]))
|| (GET_CODE (operands[2]) == REG)
|| (GET_CODE (operands[2]) == SUBREG));
/* Shift by one -- generate pattern. */
- if ((GET_CODE (operands[2]) == CONST_INT) && (INTVAL (operands[2]) == 1))
+ if ((CONST_INT_P (operands[2])) && (INTVAL (operands[2]) == 1))
return 0;
/* Have barrel shifter and shift > 1: use it. */
@@ -3781,7 +3781,7 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
p0 = XEXP (XEXP (x, 0), 0);
p1 = XEXP (XEXP (x, 0), 1);
- if (GET_CODE(p1) == CONST_INT)
+ if (CONST_INT_P (p1))
{
/* Const offset from UNSPEC is not supported. */
if ((GET_CODE (p0) == UNSPEC))
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 1509e431859..39e447ba58f 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -920,7 +920,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], DImode)
&& !register_operand (operands[1], DImode)
- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+ && (((!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 0)
&& operands[1] != CONST0_RTX (DImode))))
{
@@ -1017,7 +1017,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d")
(match_operand:SI 1 "immediate_operand" "J,I,Mnis"))]
"(register_operand (operands[0], SImode) &&
- (GET_CODE (operands[1]) == CONST_INT &&
+ (CONST_INT_P (operands[1]) &&
(INTVAL (operands[1]) <= 32767 && INTVAL (operands[1]) >= -32768)))"
"@
addk\t%0,r0,r0
@@ -1072,7 +1072,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], HImode)
&& !register_operand (operands[1], HImode)
- && ((GET_CODE (operands[1]) != CONST_INT
+ && ((!CONST_INT_P (operands[1])
|| INTVAL (operands[1]) != 0)))
{
rtx temp = force_reg (HImode, operands[1]);
@@ -1112,7 +1112,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], QImode)
&& !register_operand (operands[1], QImode)
- && ((GET_CODE (operands[1]) != CONST_INT
+ && ((!CONST_INT_P (operands[1])
|| INTVAL (operands[1]) != 0)))
{
rtx temp = force_reg (QImode, operands[1]);
@@ -1181,7 +1181,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], SFmode)
&& !register_operand (operands[1], SFmode)
- && ( ((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+ && ( ((!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 0)
&& operands[1] != CONST0_RTX (SFmode))))
{
rtx temp = force_reg (SFmode, operands[1]);
@@ -1232,7 +1232,7 @@
if ((reload_in_progress | reload_completed) == 0
&& !register_operand (operands[0], DFmode)
&& !register_operand (operands[1], DFmode)
- && (((GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
+ && (((!CONST_INT_P (operands[1]) || INTVAL (operands[1]) != 0)
&& operands[1] != CONST0_RTX (DFmode))))
{
rtx temp = force_reg (DFmode, operands[1]);
@@ -1309,7 +1309,7 @@
""
{
/* Avoid recursion for trivial cases. */
- if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1)))
+ if (!((CONST_INT_P (operands [2])) && (INTVAL (operands[2]) == 1)))
if (microblaze_expand_shift (operands))
DONE;
}
@@ -1470,7 +1470,7 @@
""
{
/* Avoid recursion for trivial cases. */
- if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1)))
+ if (!((CONST_INT_P (operands [2])) && (INTVAL (operands[2]) == 1)))
if (microblaze_expand_shift (operands))
DONE;
}
@@ -1559,7 +1559,7 @@
""
{
/* Avoid recursion for trivial cases. */
- if (!((GET_CODE (operands [2]) == CONST_INT) && (INTVAL (operands[2]) == 1)))
+ if (!((CONST_INT_P (operands [2])) && (INTVAL (operands[2]) == 1)))
if (microblaze_expand_shift (operands))
DONE;
}
@@ -1940,7 +1940,7 @@
rtx neg_op0;
emit_move_insn (rtmp, retaddr);
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
{
neg_op0 = gen_reg_rtx (Pmode);
emit_insn (gen_negsi2 (neg_op0, operands[1]));
@@ -2134,7 +2134,7 @@
gen_rtx_CLOBBER (VOIDmode, target2);
return "brlid\tr15,%0\;%#";
}
- } else if (GET_CODE (target) == CONST_INT)
+ } else if (CONST_INT_P (target))
return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
else if (GET_CODE (target) == REG)
return "brald\tr15,%0\;%#";
@@ -2249,7 +2249,7 @@
return "bralid\tr15,%1\;%#";
}
}
- else if (GET_CODE (target) == CONST_INT)
+ else if (CONST_INT_P (target))
return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
else if (GET_CODE (target) == REG)
return "brald\tr15,%1\;%#";
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index 30f26aeb2f9..7ee237c556b 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -65,7 +65,7 @@
if ((GET_CODE(p0) == SYMBOL_REF
|| GET_CODE (p0) == LABEL_REF)
- && GET_CODE(p1) == CONST_INT)
+ && CONST_INT_P (p1))
{
return arith_plus_operand (p0, GET_MODE(p0));
}
@@ -101,7 +101,7 @@
(define_predicate "call_insn_simple_operand"
(and (match_test "CALL_INSN_OP (op)")
- (match_test "GET_CODE (op) == REG || GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST_INT")))
+ (match_test "GET_CODE (op) == REG || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
;; Return if OPERAND is valid as a source operand for a move instruction.
(define_predicate "move_src_operand"
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index 380ecde4480..bf443613d84 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -1063,7 +1063,7 @@ mmix_constant_address_p (rtx x)
if ((GET_CODE (x0) == SYMBOL_REF
|| GET_CODE (x0) == LABEL_REF)
- && (GET_CODE (x1) == CONST_INT
+ && (CONST_INT_P (x1)
|| (GET_CODE (x1) == CONST_DOUBLE
&& GET_MODE (x1) == VOIDmode)))
addend = mmix_intval (x1);
@@ -1395,7 +1395,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
keep as much compatibility as possible with mmixal syntax for
normal cases (i.e. without GNU extensions and C only). */
case 1:
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
{
/* There is no "unaligned byte" op or generic function to
which we can punt, so we have to handle this here. As
@@ -1412,7 +1412,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
return true;
case 2:
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
{
aligned_p = 0;
break;
@@ -1423,7 +1423,7 @@ mmix_assemble_integer (rtx x, unsigned int size, int aligned_p)
return true;
case 4:
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
{
aligned_p = 0;
break;
@@ -1599,7 +1599,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
return;
case 'B':
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
fatal_insn ("MMIX Internal: Expected a CONST_INT, not this", x);
fprintf (stream, "%d", (int) (INTVAL (x) & 0xff));
return;
@@ -1617,7 +1617,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
case 'L':
/* Lowpart. Must be CONST_INT or general register, and not the last
one, as that one cannot be part of a consecutive register pair. */
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
{
fprintf (stream, "#%lx",
(unsigned long) (INTVAL (x)
@@ -1677,7 +1677,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
case 'm':
/* Output the number minus 1. */
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
{
fatal_insn ("MMIX Internal: Bad value for 'm', not a CONST_INT",
x);
@@ -1704,7 +1704,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
case 'I':
/* Output the constant. Note that we use this for floats as well. */
- if (GET_CODE (x) != CONST_INT
+ if (!CONST_INT_P (x)
&& (GET_CODE (x) != CONST_DOUBLE
|| (GET_MODE (x) != VOIDmode && GET_MODE (x) != DFmode
&& GET_MODE (x) != SFmode)))
@@ -1729,7 +1729,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
return;
case 'W':
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
fatal_insn ("MMIX Internal: Expected a CONST_INT, not this", x);
fprintf (stream, "#%x", (int) (INTVAL (x) & 0xffff));
return;
@@ -2743,7 +2743,7 @@ mmix_output_condition (FILE *stream, const_rtx x, int reversed)
int64_t
mmix_intval (const_rtx x)
{
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
return INTVAL (x);
/* We make a little song and dance because converting to long long in
diff --git a/gcc/config/mmix/mmix.md b/gcc/config/mmix/mmix.md
index 8a0c311f893..bf28b63a16b 100644
--- a/gcc/config/mmix/mmix.md
+++ b/gcc/config/mmix/mmix.md
@@ -1192,7 +1192,7 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\;CSNN %0,$255,%2")
(plus:DI (mult:DI (match_operand:DI 1 "register_operand" "r")
(match_operand:DI 2 "const_int_operand" "n"))
(match_operand:DI 3 "mmix_reg_or_8bit_operand" "rI")))]
- "GET_CODE (operands[2]) == CONST_INT
+ "CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) == 2
|| INTVAL (operands[2]) == 4
|| INTVAL (operands[2]) == 8
diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md
index 1d446c54dc7..c572b7b07b1 100644
--- a/gcc/config/mmix/predicates.md
+++ b/gcc/config/mmix/predicates.md
@@ -112,7 +112,7 @@
op = XEXP (op, 0);
if ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
- && (GET_CODE (XEXP (op, 1)) == CONST_INT
+ && (CONST_INT_P (XEXP (op, 1))
|| (GET_CODE (XEXP (op, 1)) == CONST_DOUBLE
&& GET_MODE (XEXP (op, 1)) == VOIDmode)))
return 1;
diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c
index 0284f3c40a4..7f1bb5aac95 100644
--- a/gcc/config/moxie/moxie.c
+++ b/gcc/config/moxie/moxie.c
@@ -562,7 +562,7 @@ moxie_offset_address_p (rtx x)
if (GET_CODE (x) == PLUS)
{
x = XEXP (x, 1);
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
{
unsigned int v = INTVAL (x) & 0xFFFF8000;
return (v == 0xFFFF8000 || v == 0x00000000);
diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md
index 7c0c5b5b489..b7deba669ca 100644
--- a/gcc/config/moxie/predicates.md
+++ b/gcc/config/moxie/predicates.md
@@ -34,7 +34,7 @@
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1))
&& IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)), -32768, 32767))
return 1;
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index c7b774e71a6..c7f04a0bfa5 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -2617,7 +2617,7 @@ msp430_expand_delay_cycles (rtx arg)
/* extra cycles for MSP430X instructions */
#define CYCX(M,X) (msp430x ? (X) : (M))
- if (GET_CODE (arg) != CONST_INT)
+ if (!CONST_INT_P (arg))
{
error ("__delay_cycles() only takes constant arguments");
return NULL_RTX;
@@ -3609,7 +3609,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
fprintf (file, "#%ld", INTVAL (op) - 4);
return;
case 'I':
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
/* Inverse of constants */
int i = INTVAL (op);
@@ -3768,7 +3768,7 @@ msp430_print_operand (FILE * file, rtx op, int letter)
return;
case 'J':
- gcc_assert (GET_CODE (op) == CONST_INT);
+ gcc_assert (CONST_INT_P (op));
case 0:
break;
default:
diff --git a/gcc/config/msp430/msp430.md b/gcc/config/msp430/msp430.md
index f6d688950cb..b516ec15462 100644
--- a/gcc/config/msp430/msp430.md
+++ b/gcc/config/msp430/msp430.md
@@ -435,7 +435,7 @@
|| reg_overlap_mentioned_p (operands[3], operands[8]))
FAIL;
- if (GET_CODE (operands[5]) == CONST_INT)
+ if (CONST_INT_P (operands[5]))
operands[9] = GEN_INT (INTVAL (operands[5]) & 0xffff);
else
operands[9] = gen_rtx_ZERO_EXTEND (SImode, operands[5]);
diff --git a/gcc/config/nds32/nds32-cost.c b/gcc/config/nds32/nds32-cost.c
index 09b22cad494..010a5ce6402 100644
--- a/gcc/config/nds32/nds32-cost.c
+++ b/gcc/config/nds32/nds32-cost.c
@@ -171,7 +171,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
/* ALU_SHIFT */
*total = COSTS_N_INSNS (2);
- else if ((GET_CODE (op1) == CONST_INT
+ else if ((CONST_INT_P (op1)
&& satisfies_constraint_Is15 (op1))
|| REG_P (op1))
/* ADD instructions */
@@ -191,7 +191,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
|| GET_CODE (op1) == MULT || GET_CODE (op1) == LSHIFTRT)
/* ALU_SHIFT */
*total = COSTS_N_INSNS (2);
- else if ((GET_CODE (op0) == CONST_INT
+ else if ((CONST_INT_P (op0)
&& satisfies_constraint_Is15 (op0))
|| REG_P (op0))
/* SUB instructions */
@@ -227,7 +227,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
*total = cost;
else if (GET_CODE (op0) == ASHIFT || GET_CODE (op0) == LSHIFTRT)
*total = COSTS_N_INSNS (2);
- else if ((GET_CODE (op1) == CONST_INT
+ else if ((CONST_INT_P (op1)
&& satisfies_constraint_Iu15 (op1))
|| REG_P (op1))
/* AND, OR, XOR instructions */
@@ -250,7 +250,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
*total = cost;
else if (outer_code == PLUS || outer_code == MINUS)
*total = COSTS_N_INSNS (2);
- else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+ else if ((CONST_INT_P (XEXP (x, 1))
&& satisfies_constraint_Iu05 (XEXP (x, 1)))
|| REG_P (XEXP (x, 1)))
/* MUL instructions */
@@ -271,7 +271,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
|| outer_code == AND || outer_code == IOR
|| outer_code == XOR)
*total = COSTS_N_INSNS (2);
- else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+ else if ((CONST_INT_P (XEXP (x, 1))
&& satisfies_constraint_Iu05 (XEXP (x, 1)))
|| REG_P (XEXP (x, 1)))
/* SRL instructions */
@@ -287,7 +287,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
else if (outer_code == AND || outer_code == IOR
|| outer_code == XOR)
*total = COSTS_N_INSNS (2);
- else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+ else if ((CONST_INT_P (XEXP (x, 1))
&& satisfies_constraint_Iu05 (XEXP (x, 1)))
|| REG_P (XEXP (x, 1)))
/* SLL instructions */
@@ -301,7 +301,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
case ROTATERT:
if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (DImode))
*total = cost;
- else if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+ else if ((CONST_INT_P (XEXP (x, 1))
&& satisfies_constraint_Iu05 (XEXP (x, 1)))
|| REG_P (XEXP (x, 1)))
/* ROTR, SLL instructions */
@@ -315,7 +315,7 @@ nds32_rtx_costs_speed_prefer (rtx x ATTRIBUTE_UNUSED,
case LTU:
if (outer_code == SET)
{
- if ((GET_CODE (XEXP (x, 1)) == CONST_INT
+ if ((CONST_INT_P (XEXP (x, 1))
&& satisfies_constraint_Iu15 (XEXP (x, 1)))
|| REG_P (XEXP (x, 1)))
/* SLT, SLTI instructions */
diff --git a/gcc/config/nds32/nds32-intrinsic.c b/gcc/config/nds32/nds32-intrinsic.c
index c78dc935bf3..5c5a2babc0e 100644
--- a/gcc/config/nds32/nds32-intrinsic.c
+++ b/gcc/config/nds32/nds32-intrinsic.c
@@ -121,7 +121,7 @@ static int
nds32_check_constant_argument (enum insn_code icode, int opnum, rtx opval,
const char *name)
{
- if (GET_CODE (opval) != CONST_INT)
+ if (!CONST_INT_P (opval))
{
error ("invalid argument to built-in function %s", name);
return false;
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index eadd8417878..3e6371730d0 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -391,7 +391,7 @@ nds32_expand_cbranch (rtx *operands)
/* If operands[2] is (const_int 0),
we can use beqz,bnez,bgtz,bgez,bltz,or blez instructions.
So we have gcc generate original template rtx. */
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
if (INTVAL (operands[2]) == 0)
if ((code != GTU)
&& (code != GEU)
@@ -406,7 +406,7 @@ nds32_expand_cbranch (rtx *operands)
{
case GT:
case GTU:
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* GT reg_A, const_int => !(LT reg_A, const_int + 1) */
if (optimize_size || optimize == 0)
@@ -560,7 +560,7 @@ nds32_expand_cbranch (rtx *operands)
case LE:
case LEU:
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
/* LE reg_A, const_int => LT reg_A, const_int + 1 */
if (optimize_size || optimize == 0)
@@ -651,7 +651,7 @@ nds32_expand_cbranch (rtx *operands)
/* Put operands[2] into register if operands[2] is a large
const_int or ISAv2. */
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (!satisfies_constraint_Is11 (operands[2])
|| TARGET_ISA_V2))
operands[2] = force_reg (SImode, operands[2]);
@@ -675,7 +675,7 @@ nds32_expand_cstore (rtx *operands)
{
case EQ:
case NE:
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
/* reg_R = (reg_A == const_int_B)
--> xori reg_C, reg_A, const_int_B
@@ -743,7 +743,7 @@ nds32_expand_cstore (rtx *operands)
case GE:
case GEU:
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
/* reg_R = (reg_A >= const_int_B)
--> movi reg_C, const_int_B - 1
@@ -809,7 +809,7 @@ nds32_expand_cstore (rtx *operands)
case LE:
case LEU:
- if (GET_CODE (operands[3]) == CONST_INT)
+ if (CONST_INT_P (operands[3]))
{
/* reg_R = (reg_A <= const_int_B)
--> movi reg_C, const_int_B + 1
@@ -1518,7 +1518,7 @@ nds32_mem_format (rtx op)
if ((GET_CODE (op) == PLUS)
&& (GET_CODE (XEXP (op, 0)) == REG)
- && (GET_CODE (XEXP (op, 1)) == CONST_INT))
+ && (CONST_INT_P (XEXP (op, 1))))
{
val = INTVAL (XEXP (op, 1));
@@ -3535,7 +3535,7 @@ nds32_legitimize_pic_address (rtx x)
|| (GET_CODE (op0) == SYMBOL_REF
&& (CONSTANT_POOL_ADDRESS_P (op0)
|| SYMBOL_REF_LOCAL_P (op0))))
- && GET_CODE (op1) == CONST_INT)
+ && CONST_INT_P (op1))
{
pat = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op0), UNSPEC_GOTOFF);
pat = gen_rtx_PLUS (Pmode, pat, op1);
@@ -3544,7 +3544,7 @@ nds32_legitimize_pic_address (rtx x)
x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx);
}
else if (GET_CODE (op0) == SYMBOL_REF
- && GET_CODE (op1) == CONST_INT)
+ && CONST_INT_P (op1))
{
/* This is a constant offset from a @GOT symbol reference. */
addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, op0), UNSPEC_GOT);
diff --git a/gcc/config/nds32/nds32-memory-manipulation.c b/gcc/config/nds32/nds32-memory-manipulation.c
index b3f2cd69899..9f320118c1c 100644
--- a/gcc/config/nds32/nds32-memory-manipulation.c
+++ b/gcc/config/nds32/nds32-memory-manipulation.c
@@ -435,8 +435,8 @@ nds32_expand_cpymemsi_unroll (rtx dstmem, rtx srcmem,
5. The srcmem cannot be volatile memory access.
6. Known shared alignment not align to 4 byte in v3m since lmw/smw *NOT*
support unalign access with v3m configure. */
- if (GET_CODE (total_bytes) != CONST_INT
- || GET_CODE (alignment) != CONST_INT
+ if (!CONST_INT_P (total_bytes)
+ || !CONST_INT_P (alignment)
|| INTVAL (total_bytes) > maximum_bytes
|| MEM_VOLATILE_P (dstmem)
|| MEM_VOLATILE_P (srcmem)
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index 98d9508c06b..96810fabecd 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -56,7 +56,7 @@
5. operands[1] must be memory for sure.
6. operands[1] is not volatile memory access.
7. Do not cross $r15 register because it is not allocatable. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != REG
@@ -1905,7 +1905,7 @@
5. operands[1] must be register for sure.
6. operands[0] is not volatile memory access.
7. Do not cross $r15 register because it is not allocatable. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
diff --git a/gcc/config/nds32/nds32-pipelines-auxiliary.c b/gcc/config/nds32/nds32-pipelines-auxiliary.c
index 07ba0378783..09ad3d59af3 100644
--- a/gcc/config/nds32/nds32-pipelines-auxiliary.c
+++ b/gcc/config/nds32/nds32-pipelines-auxiliary.c
@@ -146,7 +146,7 @@ determine_access_direction (rtx_insn *insn)
gcc_assert (GET_CODE (plus_rtx) == PLUS);
offset_rtx = XEXP (plus_rtx, 1);
- if (GET_CODE (offset_rtx) == CONST_INT)
+ if (CONST_INT_P (offset_rtx))
{
if (INTVAL (offset_rtx) < 0)
return MEM_ACCESS_DIR_NEG;
@@ -1378,7 +1378,7 @@ nds32_e8_ex_to_ii_p (rtx_insn *producer, rtx_insn *consumer)
rtx src = SET_SRC (PATTERN (producer));
if ((REG_P (dest) || GET_CODE (dest) == SUBREG)
- && (GET_CODE (src) == CONST_INT || GET_CODE (src) == HIGH))
+ && (CONST_INT_P (src) || GET_CODE (src) == HIGH))
return false;
}
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index eef34904fe1..8d02ce5a77b 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -171,7 +171,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
{
offset = count * UNITS_PER_WORD;
elt = XEXP (SET_SRC (update_base), 1);
- if (GET_CODE (elt) != CONST_INT
+ if (!CONST_INT_P (elt)
|| (INTVAL (elt) != offset))
return false;
}
@@ -471,7 +471,7 @@ nds32_float_mem_operand_p (rtx op)
return false;
/* Restrict const range: (imm12s << 2) */
- if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (addr, 1)))
{
if ((mode == SImode || mode == SFmode)
&& NDS32_SINGLE_WORD_ALIGN_P (INTVAL (XEXP (addr, 1)))
diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c
index 3515e610456..96ee791de54 100644
--- a/gcc/config/nds32/nds32-utils.c
+++ b/gcc/config/nds32/nds32-utils.c
@@ -184,7 +184,7 @@ immed_offset_p (rtx mem_rtx)
/* (mem (plus (reg) (const_int))) */
if (GET_CODE (addr_rtx) == PLUS
- && GET_CODE (XEXP (addr_rtx, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (addr_rtx, 1)))
return true;
return false;
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index eba98126705..c3a9d27f137 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -3396,7 +3396,7 @@ nds32_print_operand (FILE *stream, rtx x, int code)
case 'e':
gcc_assert (MEM_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)));
fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1)));
/* No need to handle following process, so return immediately. */
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index 250c6ac4b08..6893ebb1528 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -3095,7 +3095,7 @@ r0rel_constant_p (rtx op)
else if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS)
return r0rel_constant_p (XEXP (XEXP (op, 0), 0));
- else if (GET_CODE (op) == CONST_INT
+ else if (CONST_INT_P (op)
&& SMALL_INT (INTVAL (op)))
return true;
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index c53a1ae9f26..3107ea58818 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -5271,7 +5271,7 @@ nvptx_expand_shuffle (tree exp, rtx target, machine_mode mode, int ignore)
rtx op = expand_expr (CALL_EXPR_ARG (exp, 2),
NULL_RTX, SImode, EXPAND_NORMAL);
- if (!REG_P (idx) && GET_CODE (idx) != CONST_INT)
+ if (!REG_P (idx) && !CONST_INT_P (idx))
idx = copy_to_mode_reg (SImode, idx);
rtx pat = nvptx_gen_shuffle (target, src, idx,
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index f54ca6e4abf..565221e7fb2 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -899,7 +899,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode,
base == reg ? 0 : reg);
- if (GET_CODE (orig) == CONST_INT)
+ if (CONST_INT_P (orig))
{
if (INT_14_BITS (orig))
return plus_constant (Pmode, base, INTVAL (orig));
@@ -1009,7 +1009,7 @@ mem_shadd_or_shadd_rtx_p (rtx x)
{
return ((GET_CODE (x) == ASHIFT
|| GET_CODE (x) == MULT)
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& ((GET_CODE (x) == ASHIFT
&& pa_shadd_constant_p (INTVAL (XEXP (x, 1))))
|| (GET_CODE (x) == MULT
@@ -1111,7 +1111,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* Note we must reject symbols which represent function addresses
since the assembler/linker can't handle arithmetic on plabels. */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
&& !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
|| GET_CODE (XEXP (x, 0)) == REG))
@@ -1251,7 +1251,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* If the index adds a large constant, try to scale the
constant so that it can be loaded with only one insn. */
- if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (idx, 1))
&& VAL_14_BITS_P (INTVAL (XEXP (idx, 1))
/ INTVAL (XEXP (XEXP (idx, 0), 1)))
&& INTVAL (XEXP (idx, 1)) % INTVAL (XEXP (XEXP (idx, 0), 1)) == 0)
@@ -1276,7 +1276,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
}
/* If B + C is still a valid base register, then add them. */
- if (GET_CODE (XEXP (idx, 1)) == CONST_INT
+ if (CONST_INT_P (XEXP (idx, 1))
&& INTVAL (XEXP (idx, 1)) <= 4096
&& INTVAL (XEXP (idx, 1)) >= -4096)
{
@@ -1285,7 +1285,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, base, XEXP (idx, 1)));
reg2 = XEXP (XEXP (idx, 0), 0);
- if (GET_CODE (reg2) != CONST_INT)
+ if (!CONST_INT_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
return force_reg (Pmode,
@@ -1357,7 +1357,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
and added to (reg). This allows more scaled indexed addresses. */
if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
&& mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
- && GET_CODE (XEXP (y, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (y, 1))
&& INTVAL (XEXP (y, 1)) >= -4096
&& INTVAL (XEXP (y, 1)) <= 4095)
{
@@ -1389,7 +1389,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
else if ((mode == DFmode || mode == SFmode)
&& GET_CODE (XEXP (y, 0)) == SYMBOL_REF
&& mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
- && GET_CODE (XEXP (y, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (y, 1))
&& INTVAL (XEXP (y, 1)) % (1 << INTVAL (XEXP (XEXP (x, 0), 1))) == 0)
{
int shift_val = INTVAL (XEXP (XEXP (x, 0), 1));
@@ -1414,7 +1414,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
GEN_INT (shift_val)),
force_reg (Pmode, XEXP (y, 0))));
}
- else if (GET_CODE (XEXP (y, 1)) == CONST_INT
+ else if (CONST_INT_P (XEXP (y, 1))
&& INTVAL (XEXP (y, 1)) >= -4096
&& INTVAL (XEXP (y, 1)) <= 4095)
{
@@ -1855,7 +1855,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
&& GET_CODE (operand0) == REG
&& REGNO (operand0) < FIRST_PSEUDO_REGISTER
&& REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
- && (GET_CODE (operand1) == MEM || GET_CODE (operand1) == CONST_INT))
+ && (GET_CODE (operand1) == MEM || CONST_INT_P (operand1)))
{
/* D might not fit in 14 bits either; for such cases load D into
scratch reg. */
@@ -1908,7 +1908,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
operand1 = legitimize_tls_address (operand1);
if (register_operand (operand1, mode)
- || (GET_CODE (operand1) == CONST_INT
+ || (CONST_INT_P (operand1)
&& pa_cint_ok_for_move (UINTVAL (operand1)))
|| (operand1 == CONST0_RTX (mode))
|| (GET_CODE (operand1) == HIGH
@@ -2035,7 +2035,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
{
/* Save away the constant part of the expression. */
const_part = XEXP (XEXP (operand1, 0), 1);
- gcc_assert (GET_CODE (const_part) == CONST_INT);
+ gcc_assert (CONST_INT_P (const_part));
/* Force the function label into memory. */
temp = force_const_mem (mode, XEXP (XEXP (operand1, 0), 0));
@@ -2095,7 +2095,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
needed to load the value is shorter. */
if (GET_CODE (operand1) == CONST
&& GET_CODE (XEXP (operand1, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operand1, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (operand1, 0), 1))
&& !INT_14_BITS (XEXP (XEXP (operand1, 0), 1)))
{
rtx x, m = force_const_mem (mode, operand1);
@@ -2175,7 +2175,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
}
operands[1] = tmp;
}
- else if (GET_CODE (operand1) != CONST_INT
+ else if (!CONST_INT_P (operand1)
|| !pa_cint_ok_for_move (UINTVAL (operand1)))
{
rtx temp;
@@ -2185,11 +2185,11 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
HOST_WIDE_INT insv = 0;
int insert = 0;
- if (GET_CODE (operand1) == CONST_INT)
+ if (CONST_INT_P (operand1))
value = INTVAL (operand1);
if (TARGET_64BIT
- && GET_CODE (operand1) == CONST_INT
+ && CONST_INT_P (operand1)
&& HOST_BITS_PER_WIDE_INT > 32
&& GET_MODE_BITSIZE (GET_MODE (operand0)) > 32)
{
@@ -2221,7 +2221,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* We don't directly split DImode constants on 32-bit targets
because PLUS uses an 11-bit immediate and the insn sequence
generated is not as efficient as the one using HIGH/LO_SUM. */
- if (GET_CODE (operand1) == CONST_INT
+ if (CONST_INT_P (operand1)
&& GET_MODE_BITSIZE (mode) <= BITS_PER_WORD
&& GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
&& !insert)
@@ -2397,7 +2397,7 @@ pa_singlemove_string (rtx *operands)
operands[1] = GEN_INT (i);
/* Fall through to CONST_INT case. */
}
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
intval = INTVAL (operands[1]);
@@ -3160,7 +3160,7 @@ compute_clrmem_length (rtx_insn *insn)
const char *
pa_output_and (rtx *operands)
{
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0)
{
unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
int ls0, ls1, ms0, p, len;
@@ -3210,7 +3210,7 @@ pa_output_and (rtx *operands)
const char *
pa_output_64bit_and (rtx *operands)
{
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
+ if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0)
{
unsigned HOST_WIDE_INT mask = INTVAL (operands[2]);
int ls0, ls1, ms0, p, len;
@@ -5320,36 +5320,36 @@ pa_print_operand (FILE *file, rtx x, int code)
}
return;
case 'k':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
fprintf (file, HOST_WIDE_INT_PRINT_DEC, ~INTVAL (x));
return;
case 'Q':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
fprintf (file, HOST_WIDE_INT_PRINT_DEC, 64 - (INTVAL (x) & 63));
return;
case 'L':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
fprintf (file, HOST_WIDE_INT_PRINT_DEC, 32 - (INTVAL (x) & 31));
return;
case 'o':
- gcc_assert (GET_CODE (x) == CONST_INT
+ gcc_assert (CONST_INT_P (x)
&& (INTVAL (x) == 1 || INTVAL (x) == 2 || INTVAL (x) == 3));
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
return;
case 'O':
- gcc_assert (GET_CODE (x) == CONST_INT && exact_log2 (INTVAL (x)) >= 0);
+ gcc_assert (CONST_INT_P (x) && exact_log2 (INTVAL (x)) >= 0);
fprintf (file, "%d", exact_log2 (INTVAL (x)));
return;
case 'p':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
fprintf (file, HOST_WIDE_INT_PRINT_DEC, 63 - (INTVAL (x) & 63));
return;
case 'P':
- gcc_assert (GET_CODE (x) == CONST_INT);
+ gcc_assert (CONST_INT_P (x));
fprintf (file, HOST_WIDE_INT_PRINT_DEC, 31 - (INTVAL (x) & 31));
return;
case 'I':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fputs ("i", file);
return;
case 'M':
@@ -5847,7 +5847,7 @@ static int div_milli[16][2];
int
pa_emit_hpdiv_const (rtx *operands, int unsignedp)
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& INTVAL (operands[2]) > 0
&& INTVAL (operands[2]) < 16
&& pa_magic_milli[INTVAL (operands[2])])
@@ -5881,7 +5881,7 @@ pa_output_div_insn (rtx *operands, int unsignedp, rtx_insn *insn)
/* If the divisor is a constant, try to use one of the special
opcodes .*/
- if (GET_CODE (operands[0]) == CONST_INT)
+ if (CONST_INT_P (operands[0]))
{
static char buf[100];
divisor = INTVAL (operands[0]);
@@ -6055,7 +6055,7 @@ pa_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
a few patterns that accept constant double operands. */
if (flag_pic
&& FP_REG_CLASS_P (rclass)
- && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
+ && (CONST_INT_P (x) || GET_CODE (x) == CONST_DOUBLE))
{
switch (mode)
{
@@ -8358,7 +8358,7 @@ pa_is_function_label_plus_const (rtx op)
return (GET_CODE (op) == PLUS
&& function_label_operand (XEXP (op, 0), VOIDmode)
- && GET_CODE (XEXP (op, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (op, 1)));
}
/* Output assembly code for a thunk to FUNCTION. */
@@ -8952,7 +8952,7 @@ pa_output_parallel_movb (rtx *operands, rtx_insn *insn)
{
/* Nothing in the delay slot, fake it by putting the combined
insn (the copy or add) in the delay slot of a bl. */
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
return "b %2\n\tldi %1,%0";
else
return "b %2\n\tcopy %1,%0";
@@ -8960,14 +8960,14 @@ pa_output_parallel_movb (rtx *operands, rtx_insn *insn)
else
{
/* Something in the delay slot, but we've got a long branch. */
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
return "ldi %1,%0\n\tb %2";
else
return "copy %1,%0\n\tb %2";
}
}
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
output_asm_insn ("ldi %1,%0", operands);
else
output_asm_insn ("copy %1,%0", operands);
@@ -10369,7 +10369,7 @@ pa_legitimate_constant_p (machine_mode mode, rtx x)
if (TARGET_64BIT
&& HOST_BITS_PER_WIDE_INT > 32
- && GET_CODE (x) == CONST_INT
+ && CONST_INT_P (x)
&& !reload_in_progress
&& !reload_completed
&& !LEGITIMATE_64BIT_CONST_INT_P (INTVAL (x))
@@ -10479,7 +10479,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
else
return false;
- if (GET_CODE (index) == CONST_INT)
+ if (CONST_INT_P (index))
{
if (INT_5_BITS (index))
return true;
@@ -10533,7 +10533,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
&& MODE_OK_FOR_SCALED_INDEXING_P (mode)
&& (strict ? STRICT_REG_OK_FOR_INDEX_P (XEXP (index, 0))
: REG_OK_FOR_INDEX_P (XEXP (index, 0)))
- && GET_CODE (XEXP (index, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (index, 1))
&& INTVAL (XEXP (index, 1))
== (HOST_WIDE_INT) GET_MODE_SIZE (mode)
&& borx_reg_operand (base, Pmode))
@@ -10570,7 +10570,7 @@ pa_legitimate_address_p (machine_mode mode, rtx x, bool strict)
return false;
}
- if (GET_CODE (x) == CONST_INT && INT_5_BITS (x))
+ if (CONST_INT_P (x) && INT_5_BITS (x))
return true;
return false;
@@ -10617,7 +10617,7 @@ pa_legitimize_reload_address (rtx ad, machine_mode mode,
if (optimize
&& GET_CODE (new_rtx) == PLUS
&& GET_CODE (XEXP (new_rtx, 0)) == REG
- && GET_CODE (XEXP (new_rtx, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (new_rtx, 1)))
{
offset = INTVAL (XEXP ((new_rtx), 1));
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index f38a6dce9f9..8de85da726d 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -768,7 +768,7 @@ extern int may_call_alloca;
#define CONSTANT_ADDRESS_P(X) \
((GET_CODE (X) == LABEL_REF \
|| (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
- || GET_CODE (X) == CONST_INT \
+ || CONST_INT_P (X) \
|| (GET_CODE (X) == CONST && !tls_referenced_p (X)) \
|| GET_CODE (X) == HIGH) \
&& (reload_in_progress || reload_completed \
@@ -1246,7 +1246,7 @@ do { \
fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
break; \
case PLUS: \
- gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
+ gcc_assert (CONST_INT_P (XEXP (addr, 1))); \
fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)), \
reg_names [REGNO (XEXP (addr, 0))]); \
break; \
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 3867a55bca8..4174d590efb 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -3202,7 +3202,7 @@
Else use the block move pattern. */
/* Undetermined size, use the library routine. */
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
FAIL;
size = INTVAL (operands[2]);
@@ -3390,7 +3390,7 @@
Else use the block move pattern. */
/* Undetermined size, use the library routine. */
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
FAIL;
size = INTVAL (operands[2]);
@@ -3557,7 +3557,7 @@
FAIL;
/* Undetermined size, use the library routine. */
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
FAIL;
size = INTVAL (operands[1]);
@@ -3671,7 +3671,7 @@
FAIL;
/* Undetermined size, use the library routine. */
- if (GET_CODE (operands[1]) != CONST_INT)
+ if (!CONST_INT_P (operands[1]))
FAIL;
size = INTVAL (operands[1]);
@@ -4294,7 +4294,7 @@
if (GET_CODE (operands[2]) == CONST_DOUBLE)
operands[2] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
else if (HOST_BITS_PER_WIDE_INT > 32
- && GET_CODE (operands[2]) == CONST_INT)
+ && CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffffffff);
if (which_alternative == 1)
output_asm_insn (\"copy %1,%0\", operands);
@@ -4556,7 +4556,7 @@
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI
(match_operand:QI 1 "move_src_operand" "r,RQ")))]
- "GET_CODE (operands[1]) != CONST_INT"
+ "!CONST_INT_P (operands[1])"
"@
{extru|extrw,u} %1,31,8,%0
ldb%M1 %1,%0"
@@ -4574,7 +4574,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI
(match_operand:QI 1 "move_src_operand" "r,RQ")))]
- "GET_CODE (operands[1]) != CONST_INT"
+ "!CONST_INT_P (operands[1])"
"@
{extru|extrw,u} %1,31,8,%0
ldb%M1 %1,%0"
@@ -4592,7 +4592,7 @@
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI
(match_operand:HI 1 "move_src_operand" "r,RQ")))]
- "GET_CODE (operands[1]) != CONST_INT"
+ "!CONST_INT_P (operands[1])"
"@
{extru|extrw,u} %1,31,16,%0
ldh%M1 %1,%0"
@@ -4610,7 +4610,7 @@
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(match_operand:QI 1 "move_src_operand" "r,RQ")))]
- "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
+ "TARGET_64BIT && !CONST_INT_P (operands[1])"
"@
extrd,u %1,63,8,%0
ldb%M1 %1,%0"
@@ -4628,7 +4628,7 @@
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(match_operand:HI 1 "move_src_operand" "r,RQ")))]
- "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
+ "TARGET_64BIT && !CONST_INT_P (operands[1])"
"@
extrd,u %1,63,16,%0
ldh%M1 %1,%0"
@@ -4646,7 +4646,7 @@
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI
(match_operand:SI 1 "move_src_operand" "r,RQ")))]
- "TARGET_64BIT && GET_CODE (operands[1]) != CONST_INT"
+ "TARGET_64BIT && !CONST_INT_P (operands[1])"
"@
extrd,u %1,63,32,%0
ldw%M1 %1,%0"
@@ -4937,7 +4937,7 @@
"!TARGET_64BIT"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) >= 0)
return \"addi %2,%R1,%R0\;{addc|add,c} %1,%%r0,%0\";
@@ -5020,7 +5020,7 @@
"!TARGET_64BIT"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) >= 0)
return \"addi %2,%R1,%R0\;{addco|add,c,tsv} %1,%%r0,%0\";
@@ -5152,7 +5152,7 @@
"!TARGET_64BIT"
"*
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (INTVAL (operands[1]) >= 0)
return \"subi %1,%R2,%R0\;{subb|sub,b} %%r0,%2,%0\";
@@ -5211,7 +5211,7 @@
"!TARGET_64BIT"
"*
{
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
if (INTVAL (operands[1]) >= 0)
return \"subi %1,%R2,%R0\;{subbo|sub,b,tsv} %%r0,%2,%0\";
@@ -5443,7 +5443,7 @@
operands[5] = gen_rtx_REG (SImode, 31);
operands[4] = gen_reg_rtx (SImode);
}
- if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 0))
+ if (CONST_INT_P (operands[2]) && pa_emit_hpdiv_const (operands, 0))
DONE;
}")
@@ -5504,7 +5504,7 @@
operands[5] = gen_rtx_REG (SImode, 31);
operands[4] = gen_reg_rtx (SImode);
}
- if (GET_CODE (operands[2]) == CONST_INT && pa_emit_hpdiv_const (operands, 1))
+ if (CONST_INT_P (operands[2]) && pa_emit_hpdiv_const (operands, 1))
DONE;
}")
@@ -6320,11 +6320,11 @@
""
"
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
emit_insn (gen_zvdep_imm32 (operands[0], operands[1], temp));
else
emit_insn (gen_zvdep32 (operands[0], operands[1], temp));
@@ -6419,11 +6419,11 @@
"TARGET_64BIT"
"
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx temp = gen_reg_rtx (DImode);
emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
emit_insn (gen_zvdep_imm64 (operands[0], operands[1], temp));
else
emit_insn (gen_zvdep64 (operands[0], operands[1], temp));
@@ -6518,7 +6518,7 @@
""
"
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_subsi3 (temp, GEN_INT (31), operands[2]));
@@ -6553,7 +6553,7 @@
"TARGET_64BIT"
"
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx temp = gen_reg_rtx (DImode);
emit_insn (gen_subdi3 (temp, GEN_INT (63), operands[2]));
@@ -6640,7 +6640,7 @@
""
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 31);
return \"{shd|shrpw} %1,%1,%2,%0\";
@@ -6658,7 +6658,7 @@
""
"
{
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx temp = gen_reg_rtx (SImode);
emit_insn (gen_subsi3 (temp, GEN_INT (32), operands[2]));
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index 90b578ed984..903fa82b858 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -254,7 +254,7 @@
return false;
if (REG_P (XEXP (op, 0)) && REG_OK_FOR_BASE_P (XEXP (op, 0)))
- return GET_CODE (XEXP (op, 1)) == CONST_INT;
+ return CONST_INT_P (XEXP (op, 1));
return false;
})
@@ -631,7 +631,7 @@
&& ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
- && GET_CODE (XEXP (op, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (op, 1)));
default:
break;
}
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 5f530a43000..53be7e7752a 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -910,7 +910,7 @@ print_operand_address (FILE *file, register rtx addr)
break;
default:
- if (!again && GET_CODE (addr) == CONST_INT)
+ if (!again && CONST_INT_P (addr))
{
/* Absolute (integer number) address. */
if (TARGET_DEC_ASM)
@@ -1122,7 +1122,7 @@ pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code,
}
else if (code == PLUS || code == MINUS)
{
- if (GET_CODE (src) == CONST_INT &&
+ if (CONST_INT_P (src) &&
(INTVAL (src) == 1 || INTVAL (src) == -1))
{
*total += rtx_cost (dest, mode, (enum rtx_code) outer_code, 0, speed);
@@ -1835,7 +1835,7 @@ output_addr_const_pdp11 (FILE *file, rtx x)
case PLUS:
/* Some assemblers need integer constants to appear last (e.g. masm). */
- if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 0)))
{
output_addr_const_pdp11 (file, XEXP (x, 1));
if (INTVAL (XEXP (x, 0)) >= 0)
@@ -1859,7 +1859,7 @@ output_addr_const_pdp11 (FILE *file, rtx x)
goto restart;
output_addr_const_pdp11 (file, XEXP (x, 0));
- if (GET_CODE (XEXP (x, 1)) != CONST_INT
+ if (!CONST_INT_P (XEXP (x, 1))
|| INTVAL (XEXP (x, 1)) >= 0)
fprintf (file, "-");
output_addr_const_pdp11 (file, XEXP (x, 1));
diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md
index be5ddc4c359..3b3815d19aa 100644
--- a/gcc/config/pdp11/pdp11.md
+++ b/gcc/config/pdp11/pdp11.md
@@ -1229,7 +1229,7 @@
"reload_completed"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL(operands[2]) == 1)
return \"inc\t%0\";
@@ -1417,7 +1417,7 @@
"reload_completed"
"*
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (INTVAL(operands[2]) == 1)
return \"dec\t%0\";
@@ -1783,7 +1783,7 @@
{
r = gen_reg_rtx (<QHSint:mname>);
emit_insn (gen_lshiftrt<mode>_sc (r, operands[1], const1_rtx));
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
n = gen_reg_rtx (HImode);
emit_insn (gen_addhi3 (n, operands [2], GEN_INT (-1)));
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index c764694f4f7..0cae5c5cfb7 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -2809,7 +2809,7 @@ pru_expand_delay_cycles (rtx arg)
{
HOST_WIDE_INT c, n;
- if (GET_CODE (arg) != CONST_INT)
+ if (!CONST_INT_P (arg))
{
error ("%<__delay_cycles%> only takes constant arguments");
return NULL_RTX;
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 53fa73dec03..03527d7def8 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -230,7 +230,7 @@
/* Support only loading a constant number of fixed-point registers from
memory. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[1]) != MEM
|| GET_CODE (operands[0]) != REG)
FAIL;
@@ -288,7 +288,7 @@
/* Support only storing a constant number of fixed-point registers to
memory. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[0]) != MEM
|| GET_CODE (operands[1]) != REG)
FAIL;
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 431e90a8957..ca868a2ddca 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1434,7 +1434,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
{
rtx reg;
- if (GET_CODE (src) == CONST_INT)
+ if (CONST_INT_P (src))
{
/* Apply the equivalent of PROMOTE_MODE here for constants to
improve cse. */
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 78260fcf6fd..edff6515354 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1557,7 +1557,7 @@
(match_operand:QI 2 "arith_operand" " rI")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2])
& (GET_MODE_BITSIZE (SImode) - 1));
@@ -1612,7 +1612,7 @@
(match_operand:QI 2 "arith_operand" " rI")))]
"TARGET_64BIT"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2])
& (GET_MODE_BITSIZE (DImode) - 1));
@@ -1668,7 +1668,7 @@
(match_operand:QI 2 "arith_operand" " rI"))))]
"TARGET_64BIT"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "<insn>%i2w\t%0,%1,%2";
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index d2caa118281..ada45f5bf54 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -940,7 +940,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
/* We sometimes get these without the CONST wrapper */
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 0)) == SYMBOL_REF
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 1)))
{
*addend = x;
return true;
@@ -986,7 +986,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
{
case PLUS:
if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
- && GET_CODE (XEXP (x, 0)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 0)))
{
*addend = x;
return true;
@@ -2338,7 +2338,7 @@ rl78_peep_movhi_p (rtx *operands)
a = XEXP (a, 0);
if (GET_CODE (a) == PLUS)
a = XEXP (a, 1);
- if (GET_CODE (a) == CONST_INT
+ if (CONST_INT_P (a)
&& INTVAL (a) & 1)
{
#if DEBUG_PEEP
@@ -2995,7 +2995,7 @@ transcode_memory_rtx (rtx m, rtx newbase, rtx_insn *before)
if (base == NULL_RTX)
return m;
- if (addendr && GET_CODE (addendr) == CONST_INT)
+ if (addendr && CONST_INT_P (addendr))
addend = INTVAL (addendr);
gcc_assert (REG_P (base));
@@ -3016,7 +3016,7 @@ transcode_memory_rtx (rtx m, rtx newbase, rtx_insn *before)
if (addend < 0
|| (addend > limit && REGNO (newbase) != BC_REG)
|| (addendr
- && (GET_CODE (addendr) != CONST_INT)
+ && (!CONST_INT_P (addendr))
&& ((REGNO (newbase) != BC_REG))
))
{
@@ -4426,7 +4426,7 @@ rl78_rtx_costs (rtx x,
case ASHIFT:
case ASHIFTRT:
case LSHIFTRT:
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
switch (INTVAL (XEXP (x, 1)))
{
@@ -4484,7 +4484,7 @@ rl78_sfr_p (rtx x)
{
if (MEM_P (x))
x = XEXP (x, 0);
- if (GET_CODE (x) != CONST_INT)
+ if (!CONST_INT_P (x))
return 0;
if ((INTVAL (x) & 0xFF00) != 0xFF00)
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 4080c82c05f..1650adda137 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -13301,7 +13301,7 @@ rs6000_call_template_1 (rtx *operands, unsigned int funop, bool sibcall)
else if (DEFAULT_ABI == ABI_DARWIN)
{
/* The cookie is in operand func+2. */
- gcc_checking_assert (GET_CODE (operands[funop + 2]) == CONST_INT);
+ gcc_checking_assert (CONST_INT_P (operands[funop + 2]));
int cookie = INTVAL (operands[funop + 2]);
if (cookie & CALL_LONG)
{
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 0695f3b6538..905d3054de2 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -433,7 +433,7 @@ rx_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
rx_print_operand (file, index, 'A');
fprintf (file, ",");
}
- else /* GET_CODE (index) == CONST_INT */
+ else /* CONST_INT_P (index) */
{
rx_print_operand (file, index, 'A');
fprintf (file, "[");
@@ -813,7 +813,7 @@ rx_print_operand (FILE * file, rtx op, int letter)
else if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (op, 0), 0)) == UNSPEC
- && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (op, 0), 1)))
{
if (print_hash)
fprintf (file, "#");
@@ -2585,7 +2585,7 @@ valid_psw_flag (rtx op, const char *which)
{
static int mvtc_inform_done = 0;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
switch (INTVAL (op))
{
case 0: case 'c': case 'C':
@@ -3476,7 +3476,7 @@ rx_adjust_insn_length (rtx_insn *insn, int current_length)
gcc_checking_assert (REG_P (XEXP (XEXP (mem, 0), 0)));
offset = XEXP (XEXP (mem, 0), 1);
- gcc_checking_assert (GET_CODE (offset) == CONST_INT);
+ gcc_checking_assert (CONST_INT_P (offset));
if (IN_RANGE (INTVAL (offset), 0, 255 * factor))
return (zero && factor == 1) ? 3 : 4;
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 9df73e6efc6..7065be69e43 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -1296,7 +1296,7 @@
operands[5] = gen_reg_rtx (SImode);
operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
operands[2] = operands[5];
@@ -1320,7 +1320,7 @@
operands[5] = gen_reg_rtx (SImode);
operands[6] = gen_rtx_SUBREG (GET_MODE (operands[0]), operands[3],
TARGET_BIG_ENDIAN_DATA ? (GET_MODE (operands[0]) == HImode ? 2 : 3) : 0);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
emit_move_insn (operands[5], gen_rtx_ZERO_EXTEND (SImode, operands[2]));
operands[2] = operands[5];
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index fa15c05bcad..15758fb731a 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -173,7 +173,7 @@
/* Allow adding *even* in-range constants. */
if (GET_CODE (op) == PLUS)
{
- if (GET_CODE (XEXP (op, 1)) != CONST_INT
+ if (!CONST_INT_P (XEXP (op, 1))
|| (INTVAL (XEXP (op, 1)) & 1) != 0)
return false;
if (INTVAL (XEXP (op, 1)) >= HOST_WIDE_INT_1 << 31
@@ -407,7 +407,7 @@
off = 0;
else if (GET_CODE (src_addr) == PLUS
&& GET_CODE (XEXP (src_addr, 0)) == REG
- && GET_CODE (XEXP (src_addr, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (src_addr, 1)))
{
off = INTVAL (XEXP (src_addr, 1));
src_addr = XEXP (src_addr, 0);
@@ -427,7 +427,7 @@
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| GET_CODE (XEXP (SET_SRC (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_SRC (elt), 0), 0), src_addr)
- || GET_CODE (XEXP (XEXP (SET_SRC (elt), 0), 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (XEXP (SET_SRC (elt), 0), 1))
|| INTVAL (XEXP (XEXP (SET_SRC (elt), 0), 1))
!= off + i * GET_MODE_SIZE (elt_mode))
return false;
@@ -510,7 +510,7 @@
off = 0;
else if (GET_CODE (dest_addr) == PLUS
&& GET_CODE (XEXP (dest_addr, 0)) == REG
- && GET_CODE (XEXP (dest_addr, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (dest_addr, 1)))
{
off = INTVAL (XEXP (dest_addr, 1));
dest_addr = XEXP (dest_addr, 0);
@@ -530,7 +530,7 @@
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| GET_CODE (XEXP (SET_DEST (elt), 0)) != PLUS
|| ! rtx_equal_p (XEXP (XEXP (SET_DEST (elt), 0), 0), dest_addr)
- || GET_CODE (XEXP (XEXP (SET_DEST (elt), 0), 1)) != CONST_INT
+ || !CONST_INT_P (XEXP (XEXP (SET_DEST (elt), 0), 1))
|| INTVAL (XEXP (XEXP (SET_DEST (elt), 0), 1))
!= off + i * GET_MODE_SIZE (elt_mode))
return false;
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 24b8a5c7a0d..c863514325a 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1457,7 +1457,7 @@ s390_tm_ccmode (rtx op1, rtx op2, bool mixed)
int bit0, bit1;
/* ??? Fixme: should work on CONST_WIDE_INT as well. */
- if (GET_CODE (op1) != CONST_INT || GET_CODE (op2) != CONST_INT)
+ if (!CONST_INT_P (op1) || !CONST_INT_P (op2))
return VOIDmode;
/* Selected bits all zero: CC0.
@@ -1499,7 +1499,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
if ((GET_CODE (op0) == NEG || GET_CODE (op0) == ABS)
&& GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT)
return CCAPmode;
- if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
+ if (GET_CODE (op0) == PLUS && CONST_INT_P (XEXP (op0, 1))
&& CONST_OK_FOR_K (INTVAL (XEXP (op0, 1))))
return CCAPmode;
if ((GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS
@@ -1521,11 +1521,11 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
}
if (register_operand (op0, HImode)
- && GET_CODE (op1) == CONST_INT
+ && CONST_INT_P (op1)
&& (INTVAL (op1) == -1 || INTVAL (op1) == 65535))
return CCT3mode;
if (register_operand (op0, QImode)
- && GET_CODE (op1) == CONST_INT
+ && CONST_INT_P (op1)
&& (INTVAL (op1) == -1 || INTVAL (op1) == 255))
return CCT3mode;
@@ -1548,7 +1548,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
constant the overflow behavior gets predictable. e.g.:
int a, b; if ((b = a + c) > 0)
with c as a constant value: c < 0 -> CCAN and c >= 0 -> CCAP */
- if (GET_CODE (op0) == PLUS && GET_CODE (XEXP (op0, 1)) == CONST_INT
+ if (GET_CODE (op0) == PLUS && CONST_INT_P (XEXP (op0, 1))
&& (CONST_OK_FOR_K (INTVAL (XEXP (op0, 1)))
|| (CONST_OK_FOR_CONSTRAINT_P (INTVAL (XEXP (op0, 1)), 'O', "Os")
/* Avoid INT32_MIN on 32 bit. */
@@ -1569,7 +1569,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
case UNGT:
case LTGT:
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
- && GET_CODE (op1) != CONST_INT)
+ && !CONST_INT_P (op1))
return CCSRmode;
return CCSmode;
@@ -1580,7 +1580,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
return CCL1mode;
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
- && GET_CODE (op1) != CONST_INT)
+ && !CONST_INT_P (op1))
return CCURmode;
return CCUmode;
@@ -1591,7 +1591,7 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1)
return CCL2mode;
if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND)
- && GET_CODE (op1) != CONST_INT)
+ && !CONST_INT_P (op1))
return CCURmode;
return CCUmode;
@@ -1614,8 +1614,8 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
if ((*code == EQ || *code == NE)
&& *op1 == const0_rtx
&& GET_CODE (*op0) == ZERO_EXTRACT
- && GET_CODE (XEXP (*op0, 1)) == CONST_INT
- && GET_CODE (XEXP (*op0, 2)) == CONST_INT
+ && CONST_INT_P (XEXP (*op0, 1))
+ && CONST_INT_P (XEXP (*op0, 2))
&& SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
{
rtx inner = XEXP (*op0, 0);
@@ -1640,7 +1640,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
if ((*code == EQ || *code == NE)
&& *op1 == const0_rtx
&& GET_CODE (*op0) == AND
- && GET_CODE (XEXP (*op0, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (*op0, 1))
&& SCALAR_INT_MODE_P (GET_MODE (XEXP (*op0, 0))))
{
rtx inner = XEXP (*op0, 0);
@@ -1673,7 +1673,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
/* Narrow comparisons against 0xffff to HImode if possible. */
if ((*code == EQ || *code == NE)
- && GET_CODE (*op1) == CONST_INT
+ && CONST_INT_P (*op1)
&& INTVAL (*op1) == 0xffff
&& SCALAR_INT_MODE_P (GET_MODE (*op0))
&& (nonzero_bits (*op0, GET_MODE (*op0))
@@ -2312,7 +2312,7 @@ s390_single_part (rtx op,
= (HOST_WIDE_INT_1U << GET_MODE_BITSIZE (part_mode)) - 1;
int i, part = -1;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return -1;
for (i = 0; i < n_parts; i++)
@@ -2607,7 +2607,7 @@ s390_overlap_p (rtx mem1, rtx mem2, HOST_WIDE_INT size)
overlapping.
That's why we return false here although this may accept operations on
overlapping memory areas. */
- if (!addr_delta || GET_CODE (addr_delta) != CONST_INT)
+ if (!addr_delta || !CONST_INT_P (addr_delta))
return false;
delta = INTVAL (addr_delta);
@@ -2798,7 +2798,7 @@ s390_short_displacement (rtx disp)
return true;
/* Integer displacement in range. */
- if (GET_CODE (disp) == CONST_INT)
+ if (CONST_INT_P (disp))
return INTVAL (disp) >= 0 && INTVAL (disp) < 4096;
/* GOT offset is not OK, the GOT can be large. */
@@ -2946,14 +2946,14 @@ s390_decompose_address (rtx addr, struct s390_address *out)
orig_disp = disp;
if (disp)
{
- if (GET_CODE (disp) == CONST_INT)
+ if (CONST_INT_P (disp))
{
offset = INTVAL (disp);
disp = NULL_RTX;
}
else if (GET_CODE (disp) == CONST
&& GET_CODE (XEXP (disp, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (disp, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (disp, 0), 1)))
{
offset = INTVAL (XEXP (XEXP (disp, 0), 1));
disp = XEXP (XEXP (disp, 0), 0);
@@ -3684,7 +3684,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
{
rtx left = XEXP (x, 0);
rtx right = XEXP (x, 1);
- if (GET_CODE (right) == CONST_INT
+ if (CONST_INT_P (right)
&& CONST_OK_FOR_K (INTVAL (right)))
*total = s390_cost->mhi;
else if (GET_CODE (left) == SIGN_EXTEND)
@@ -3699,7 +3699,7 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
rtx right = XEXP (x, 1);
if (TARGET_ZARCH)
{
- if (GET_CODE (right) == CONST_INT
+ if (CONST_INT_P (right)
&& CONST_OK_FOR_K (INTVAL (right)))
*total = s390_cost->mghi;
else if (GET_CODE (left) == SIGN_EXTEND)
@@ -3854,8 +3854,8 @@ s390_rtx_costs (rtx x, machine_mode mode, int outer_code,
}
if (GET_CODE (XEXP (x, 0)) == AND
- && GET_CODE (XEXP (x, 1)) == CONST_INT
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 1))
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1)))
{
rtx op0 = XEXP (XEXP (x, 0), 0);
rtx op1 = XEXP (XEXP (x, 0), 1);
@@ -4154,24 +4154,24 @@ bool
legitimate_reload_constant_p (rtx op)
{
/* Accept la(y) operands. */
- if (GET_CODE (op) == CONST_INT
+ if (CONST_INT_P (op)
&& DISP_IN_RANGE (INTVAL (op)))
return true;
/* Accept l(g)hi/l(g)fi operands. */
- if (GET_CODE (op) == CONST_INT
+ if (CONST_INT_P (op)
&& (CONST_OK_FOR_K (INTVAL (op)) || CONST_OK_FOR_Os (INTVAL (op))))
return true;
/* Accept lliXX operands. */
if (TARGET_ZARCH
- && GET_CODE (op) == CONST_INT
+ && CONST_INT_P (op)
&& trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
&& s390_single_part (op, word_mode, HImode, 0) >= 0)
return true;
if (TARGET_EXTIMM
- && GET_CODE (op) == CONST_INT
+ && CONST_INT_P (op)
&& trunc_int_for_mode (INTVAL (op), word_mode) == INTVAL (op)
&& s390_single_part (op, word_mode, SImode, 0) >= 0)
return true;
@@ -4188,7 +4188,7 @@ legitimate_reload_constant_p (rtx op)
/* Accept double-word operands that can be split. */
if (GET_CODE (op) == CONST_WIDE_INT
- || (GET_CODE (op) == CONST_INT
+ || (CONST_INT_P (op)
&& trunc_int_for_mode (INTVAL (op), word_mode) != INTVAL (op)))
{
machine_mode dword_mode = word_mode == SImode ? DImode : TImode;
@@ -4286,7 +4286,7 @@ s390_preferred_reload_class (rtx op, reg_class_t rclass)
inheritance (see emit_input_reload_insns). */
if (GET_CODE (XEXP (op, 0)) == PLUS
&& GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
- && GET_CODE (XEXP (XEXP(op, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP(op, 0), 1)))
{
if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
return ADDR_REGS;
@@ -4465,7 +4465,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
displacements. */
if (MEM_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& !SHORT_DISP_IN_RANGE(INTVAL (XEXP (XEXP (x, 0), 1)))
&& reg_class_subset_p (rclass, VEC_REGS)
&& (!reg_class_subset_p (rclass, FP_REGS)
@@ -4573,7 +4573,7 @@ s390_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
a scratch register. */
if (MEM_P (x)
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& !DISP_IN_RANGE (INTVAL (XEXP (XEXP (x, 0), 1))
+ GET_MODE_SIZE (mode) - 1))
{
@@ -4890,7 +4890,7 @@ legitimize_pic_address (rtx orig, rtx reg)
|| (GET_CODE (addr) == UNSPEC &&
(XINT (addr, 1) == UNSPEC_GOTENT
|| XINT (addr, 1) == UNSPEC_PLT)))
- && GET_CODE (addend) == CONST_INT)
+ && CONST_INT_P (addend))
{
/* This can be locally addressed. */
@@ -5021,7 +5021,7 @@ legitimize_pic_address (rtx orig, rtx reg)
new_rtx = reg;
}
}
- else if (GET_CODE (addr) == UNSPEC && GET_CODE (addend) == CONST_INT)
+ else if (GET_CODE (addr) == UNSPEC && CONST_INT_P (addend))
{
gcc_assert (XVECLEN (addr, 0) == 1);
switch (XINT (addr, 1))
@@ -5066,7 +5066,7 @@ legitimize_pic_address (rtx orig, rtx reg)
rtx base = legitimize_pic_address (addr, reg);
new_rtx = legitimize_pic_address (addend,
base == reg ? NULL_RTX : reg);
- if (GET_CODE (new_rtx) == CONST_INT)
+ if (CONST_INT_P (new_rtx))
new_rtx = plus_constant (Pmode, base, INTVAL (new_rtx));
else
{
@@ -5264,7 +5264,7 @@ legitimize_tls_address (rtx addr, rtx reg)
}
else if (GET_CODE (addr) == CONST && GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
{
new_rtx = XEXP (XEXP (addr, 0), 0);
if (GET_CODE (new_rtx) != SYMBOL_REF)
@@ -5352,7 +5352,7 @@ s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
pointing into the stack frame, as the offsets will
change later anyway. */
- if (GET_CODE (constant_term) == CONST_INT
+ if (CONST_INT_P (constant_term)
&& !TARGET_LONG_DISPLACEMENT
&& !DISP_IN_RANGE (INTVAL (constant_term))
&& !(REG_P (x) && REGNO_PTR_FRAME_P (REGNO (x))))
@@ -5421,7 +5421,7 @@ legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
if (GET_CODE (ad) == PLUS
&& GET_CODE (XEXP (ad, 0)) == REG
- && GET_CODE (XEXP (ad, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (ad, 1))
&& !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
{
HOST_WIDE_INT lower = INTVAL (XEXP (ad, 1)) & 0xfff;
@@ -5453,7 +5453,7 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
do the right thing. Only for constant lengths below 64k we will
generate inline code. */
if (s390_tune >= PROCESSOR_2097_Z10
- && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
+ && (!CONST_INT_P (len) || INTVAL (len) > (1<<16)))
return false;
/* Expand memcpy for constant length operands without a loop if it
@@ -5461,7 +5461,7 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
With a constant length argument a
memcpy loop (without pfd) is 36 bytes -> 6 * mvc */
- if (GET_CODE (len) == CONST_INT
+ if (CONST_INT_P (len)
&& INTVAL (len) >= 0
&& INTVAL (len) <= 256 * 6
&& (!TARGET_MVCLE || INTVAL (len) <= 256))
@@ -5524,7 +5524,7 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
emit_label (loop_start_label);
if (TARGET_Z10
- && (GET_CODE (len) != CONST_INT || INTVAL (len) > 768))
+ && (!CONST_INT_P (len) || INTVAL (len) > 768))
{
rtx prefetch;
@@ -5571,10 +5571,10 @@ s390_expand_cpymem (rtx dst, rtx src, rtx len)
void
s390_expand_setmem (rtx dst, rtx len, rtx val)
{
- if (GET_CODE (len) == CONST_INT && INTVAL (len) <= 0)
+ if (CONST_INT_P (len) && INTVAL (len) <= 0)
return;
- gcc_assert (GET_CODE (val) == CONST_INT || GET_MODE (val) == QImode);
+ gcc_assert (CONST_INT_P (val) || GET_MODE (val) == QImode);
/* Expand setmem/clrmem for a constant length operand without a
loop if it will be shorter that way.
@@ -5582,7 +5582,7 @@ s390_expand_setmem (rtx dst, rtx len, rtx val)
clrmem loop (without PFD) is 24 bytes -> 4 * xc
setmem loop (with PFD) is 38 bytes -> ~4 * (mvi/stc + mvc)
setmem loop (without PFD) is 32 bytes -> ~4 * (mvi/stc + mvc) */
- if (GET_CODE (len) == CONST_INT
+ if (CONST_INT_P (len)
&& ((val == const0_rtx
&& (INTVAL (len) <= 256 * 4
|| (INTVAL (len) <= 256 * 5 && TARGET_SETMEM_PFD(val,len))))
@@ -5762,14 +5762,14 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
do the right thing. Only for constant lengths below 64k we will
generate inline code. */
if (s390_tune >= PROCESSOR_2097_Z10
- && (GET_CODE (len) != CONST_INT || INTVAL (len) > (1<<16)))
+ && (!CONST_INT_P (len) || INTVAL (len) > (1<<16)))
return false;
/* As the result of CMPINT is inverted compared to what we need,
we have to swap the operands. */
tmp = op0; op0 = op1; op1 = tmp;
- if (GET_CODE (len) == CONST_INT && INTVAL (len) >= 0 && INTVAL (len) <= 256)
+ if (CONST_INT_P (len) && INTVAL (len) >= 0 && INTVAL (len) <= 256)
{
if (INTVAL (len) > 0)
{
@@ -5826,7 +5826,7 @@ s390_expand_cmpmem (rtx target, rtx op0, rtx op1, rtx len)
emit_label (loop_start_label);
if (TARGET_Z10
- && (GET_CODE (len) != CONST_INT || INTVAL (len) > 512))
+ && (!CONST_INT_P (len) || INTVAL (len) > 512))
{
rtx prefetch;
@@ -7417,7 +7417,7 @@ s390_delegitimize_address (rtx orig_x)
y = XEXP (XEXP (x, 1), 0);
if (GET_CODE (y) == PLUS
- && GET_CODE (XEXP (y, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (y, 1)))
{
offset = INTVAL (XEXP (y, 1));
y = XEXP (y, 0);
@@ -8146,7 +8146,7 @@ static bool
s390_assemble_integer (rtx x, unsigned int size, int aligned_p)
{
if (size == 8 && aligned_p
- && GET_CODE (x) == CONST_INT && INTVAL (x) < INT_MIN)
+ && CONST_INT_P (x) && INTVAL (x) < INT_MIN)
{
fprintf (asm_out_file, "\t.quad\t" HOST_WIDE_INT_PRINT_HEX "\n",
INTVAL (x));
@@ -8349,7 +8349,7 @@ annotate_constant_pool_refs_1 (rtx *x)
if (GET_CODE (memref) == CONST
&& GET_CODE (XEXP (memref, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (memref, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (memref, 0), 1))
&& GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
{
@@ -8382,7 +8382,7 @@ annotate_constant_pool_refs_1 (rtx *x)
if (GET_CODE (addrref) == CONST
&& GET_CODE (XEXP (addrref, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addrref, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (addrref, 0), 1))
&& GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
{
@@ -8504,7 +8504,7 @@ replace_constant_pool_ref_1 (rtx *x, rtx ref, rtx offset)
}
if (GET_CODE (*x) == PLUS
- && GET_CODE (XEXP (*x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (*x, 1))
&& GET_CODE (XEXP (*x, 0)) == UNSPEC
&& XINT (XEXP (*x, 0), 1) == UNSPEC_LTREF
&& XVECEXP (XEXP (*x, 0), 0, 0) == ref)
@@ -10076,7 +10076,7 @@ s390_optimize_nonescaping_tx (void)
cc = XEXP (XEXP (ite, 0), 0);
if (!REG_P (cc) || !CC_REGNO_P (REGNO (cc))
|| GET_MODE (cc) != CCRAWmode
- || GET_CODE (XEXP (XEXP (ite, 0), 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (XEXP (ite, 0), 1)))
return;
if (bb->succs->length () != 2)
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index e4516f6c378..a50090af0a1 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2307,7 +2307,7 @@
"GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& get_pool_mode (operands[1]) == HImode
- && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
+ && CONST_INT_P (get_pool_constant (operands[1]))"
[(set (match_dup 0) (match_dup 2))]
"operands[2] = get_pool_constant (operands[1]);")
@@ -2372,7 +2372,7 @@
"GET_CODE (operands[1]) == SYMBOL_REF
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& get_pool_mode (operands[1]) == QImode
- && GET_CODE (get_pool_constant (operands[1])) == CONST_INT"
+ && CONST_INT_P (get_pool_constant (operands[1]))"
[(set (match_dup 0) (match_dup 2))]
"operands[2] = get_pool_constant (operands[1]);")
@@ -2837,7 +2837,7 @@
/* Support only loading a constant number of fixed-point registers from
memory and only bother with this if more than two */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
|| GET_CODE (operands[1]) != MEM
@@ -2861,7 +2861,7 @@
}
else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)))
{
from = XEXP (XEXP (operands[1], 0), 0);
off = INTVAL (XEXP (XEXP (operands[1], 0), 1));
@@ -2928,7 +2928,7 @@
/* Support only storing a constant number of fixed-point registers to
memory and only bother with this if more than two. */
- if (GET_CODE (operands[2]) != CONST_INT
+ if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
|| GET_CODE (operands[0]) != MEM
@@ -2953,7 +2953,7 @@
}
else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
&& GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)))
{
to = XEXP (XEXP (operands[0], 0), 0);
off = INTVAL (XEXP (XEXP (operands[0], 0), 1));
@@ -6105,7 +6105,7 @@
(match_operand:DI 2 "nonmemory_operand" "")))]
"TARGET_64BIT"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
HOST_WIDE_INT c = INTVAL (operands[2]);
@@ -6131,7 +6131,7 @@
(use (const_int 0))])]
"!TARGET_64BIT"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
HOST_WIDE_INT c = INTVAL (operands[2]);
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index ee475800cfc..e19e8fdffb3 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -109,7 +109,7 @@
return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
|| GET_CODE (XEXP (op, 0)) == LABEL_REF)
- && GET_CODE (XEXP (op, 1)) == CONST_INT);
+ && CONST_INT_P (XEXP (op, 1)));
default:
gcc_unreachable ();
@@ -275,7 +275,7 @@
if (TARGET_ARCH64 || arith_simple_operand)
return arith_simple_operand;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return false;
m1 = trunc_int_for_mode (INTVAL (op), SImode);
@@ -397,7 +397,7 @@
/* If 32-bit mode and this is a DImode constant, allow it
so that the splits can be generated. */
- if (TARGET_ARCH32 && mode == DImode && GET_CODE (op) == CONST_INT)
+ if (TARGET_ARCH32 && mode == DImode && CONST_INT_P (op))
return true;
/* Allow FP constants to be built in integer registers. */
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 0227a53861f..dc833072f8c 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -2258,7 +2258,7 @@ sparc_expand_move (machine_mode mode, rtx *operands)
|| (GET_CODE (operands[1]) == CONST
&& GET_CODE (XEXP (operands[1], 0)) == PLUS
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1))
&& can_use_mov_pic_label_ref (XEXP (XEXP (operands[1], 0), 0))))
{
if (mode == SImode)
@@ -2373,7 +2373,7 @@ sparc_emit_set_const32 (rtx op0, rtx op1)
if (can_create_pseudo_p ())
temp = gen_reg_rtx (mode);
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
{
gcc_assert (!small_int_operand (op1, mode)
&& !const_high_operand (op1, mode));
@@ -2964,7 +2964,7 @@ sparc_emit_set_const64 (rtx op0, rtx op1)
if (! can_create_pseudo_p ())
temp = op0;
- if (GET_CODE (op1) != CONST_INT)
+ if (!CONST_INT_P (op1))
{
sparc_emit_set_symbolic_const64 (op0, op1, temp);
return;
@@ -3573,7 +3573,7 @@ emit_conditional_branch_insn (rtx operands[])
&& GET_CODE (operands[1]) == REG
&& (GET_MODE (operands[1]) == SImode
|| (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
- && (GET_CODE (operands[2]) != CONST_INT
+ && (!CONST_INT_P (operands[2])
|| SPARC_SIMM5_P (INTVAL (operands[2]))))
{
emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2], operands[3]);
@@ -4353,7 +4353,7 @@ pic_address_needs_scratch (rtx x)
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& !SMALL_INT (XEXP (XEXP (x, 0), 1)))
return 1;
@@ -4507,7 +4507,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& GET_CODE (rs2) != MEM
&& !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
&& (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
- && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2)))
+ && (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
|| ((REG_P (rs1)
|| GET_CODE (rs1) == SUBREG)
&& RTX_OK_FOR_OFFSET_P (rs2, mode)))
@@ -4575,7 +4575,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& XEXP (rs1, 0) == imm1)
return 1;
}
- else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr))
+ else if (CONST_INT_P (addr) && SMALL_INT (addr))
return 1;
else
return 0;
@@ -4827,7 +4827,7 @@ sparc_legitimize_tls_address (rtx addr)
offset = XEXP (XEXP (addr, 0), 1);
base = force_operand (base, NULL_RTX);
- if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset)))
+ if (!(CONST_INT_P (offset) && SMALL_INT (offset)))
offset = force_reg (Pmode, offset);
ret = gen_rtx_PLUS (Pmode, base, offset);
}
@@ -4933,7 +4933,7 @@ sparc_legitimize_pic_address (rtx orig, rtx reg)
offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1),
base == reg ? NULL_RTX : reg);
- if (GET_CODE (offset) == CONST_INT)
+ if (CONST_INT_P (offset))
{
if (SMALL_INT (offset))
return plus_constant (Pmode, base, INTVAL (offset));
@@ -5046,7 +5046,7 @@ sparc_delegitimize_address (rtx x)
|| (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT));
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))));
}
}
@@ -5182,7 +5182,7 @@ mem_min_alignment (rtx mem, int desired)
REG is aligned properly, the compiler will make
sure any REG based index upon it will be so
as well. */
- if (GET_CODE (XEXP (addr, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (addr, 1)))
offset = XEXP (addr, 1);
else
offset = const0_rtx;
@@ -8910,7 +8910,7 @@ epilogue_renumber (register rtx *where, int test)
case PLUS:
if (GET_CODE (XEXP (*where, 0)) == REG
&& REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
- && (GET_CODE (XEXP (*where, 1)) != CONST_INT
+ && (!CONST_INT_P (XEXP (*where, 1))
|| INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
return 1;
break;
@@ -9166,7 +9166,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
{
reg1 = REGNO (XEXP (addr1, 0));
/* The offset must be constant! */
- if (GET_CODE (XEXP (addr1, 1)) != CONST_INT)
+ if (!CONST_INT_P (XEXP (addr1, 1)))
return 0;
offset1 = INTVAL (XEXP (addr1, 1));
}
@@ -9185,7 +9185,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
return 0;
if (GET_CODE (XEXP (addr2, 0)) != REG
- || GET_CODE (XEXP (addr2, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (addr2, 1)))
return 0;
if (reg1 != REGNO (XEXP (addr2, 0)))
@@ -9341,7 +9341,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
case 'Y':
/* Adjust the operand to take into account a RESTORE operation. */
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
break;
else if (GET_CODE (x) != REG)
output_operand_lossage ("invalid %%Y operand");
@@ -9596,7 +9596,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
{
/* Print a sign-extended 32-bit value. */
HOST_WIDE_INT i;
- if (GET_CODE(x) == CONST_INT)
+ if (CONST_INT_P (x))
i = INTVAL (x);
else
{
@@ -9741,7 +9741,7 @@ sparc_assemble_integer (rtx x, unsigned int size, int aligned_p)
{
/* ??? We only output .xword's for symbols and only then in environments
where the assembler can handle them. */
- if (aligned_p && size == 8 && GET_CODE (x) != CONST_INT)
+ if (aligned_p && size == 8 && !CONST_INT_P (x))
{
if (TARGET_V9)
{
@@ -10314,7 +10314,7 @@ set_extends (rtx_insn *insn)
{
rtx op0 = XEXP (SET_SRC (pat), 0);
rtx op1 = XEXP (SET_SRC (pat), 1);
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
return INTVAL (op1) >= 0;
if (GET_CODE (op0) != REG)
return 0;
@@ -10329,7 +10329,7 @@ set_extends (rtx_insn *insn)
rtx op1 = XEXP (SET_SRC (pat), 1);
if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
return 0;
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
return INTVAL (op1) >= 0;
return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
}
@@ -10522,10 +10522,10 @@ output_v8plus_shift (rtx_insn *insn, rtx *operands, const char *opcode)
operands[3] = operands[0];
/* We can only shift by constants <= 63. */
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
- if (GET_CODE (operands[1]) == CONST_INT)
+ if (CONST_INT_P (operands[1]))
{
output_asm_insn ("mov\t%1, %3", operands);
}
@@ -10922,7 +10922,7 @@ static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX];
static int
check_constant_argument (enum insn_code icode, int opnum, rtx opval)
{
- if (GET_CODE (opval) != CONST_INT)
+ if (!CONST_INT_P (opval))
{
error ("%qs expects a constant argument", insn_data[icode].name);
return false;
@@ -12071,7 +12071,7 @@ sparc_rtx_costs (rtx x, machine_mode mode, int outer_code,
{
int nbits;
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1));
for (nbits = 0; value != 0; value &= value - 1)
@@ -13162,7 +13162,7 @@ output_v8plus_mult (rtx_insn *insn, rtx *operands, const char *opcode)
output_asm_insn ("srl\t%L1, 0, %L1", operands);
if (which_alternative == 1)
output_asm_insn ("sllx\t%H1, 32, %H1", operands);
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
if (which_alternative == 1)
{
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 7af62d599b9..14ce445d1e2 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2551,8 +2551,8 @@ visl")
rtx high_part = gen_highpart (SImode, operands[0]);
rtx low_part = gen_lowpart (SImode, operands[0]);
- gcc_assert (GET_CODE (hi) == CONST_INT);
- gcc_assert (GET_CODE (lo) == CONST_INT);
+ gcc_assert (CONST_INT_P (hi));
+ gcc_assert (CONST_INT_P (lo));
emit_move_insn_1 (high_part, hi);
@@ -3063,7 +3063,7 @@ visl")
(define_insn "*zero_extendqihi2_insn"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(zero_extend:HI (match_operand:QI 1 "input_operand" "r,m")))]
- "GET_CODE (operands[1]) != CONST_INT"
+ "!CONST_INT_P (operands[1])"
"@
and\t%1, 0xff, %0
ldub\t%1, %0"
@@ -3080,7 +3080,7 @@ visl")
(define_insn "*zero_extendqisi2_insn"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(zero_extend:SI (match_operand:QI 1 "input_operand" "r,m")))]
- "GET_CODE (operands[1]) != CONST_INT"
+ "!CONST_INT_P (operands[1])"
"@
and\t%1, 0xff, %0
ldub\t%1, %0"
@@ -3097,7 +3097,7 @@ visl")
(define_insn "*zero_extendqidi2_insn"
[(set (match_operand:DI 0 "register_operand" "=r,r")
(zero_extend:DI (match_operand:QI 1 "input_operand" "r,m")))]
- "TARGET_ARCH64 && GET_CODE (operands[1]) != CONST_INT"
+ "TARGET_ARCH64 && !CONST_INT_P (operands[1])"
"@
and\t%1, 0xff, %0
ldub\t%1, %0"
@@ -3149,7 +3149,7 @@ visl")
[(set (match_operand:DI 0 "register_operand" "=r,r,r")
(zero_extend:DI (match_operand:SI 1 "input_operand" "r,m,*f")))]
"TARGET_ARCH64
- && GET_CODE (operands[1]) != CONST_INT"
+ && !CONST_INT_P (operands[1])"
"@
srl\t%1, 0, %0
lduw\t%1, %0
@@ -6488,7 +6488,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sll\t%1, %2, %0";
}
@@ -6502,7 +6502,7 @@ visl")
{
if (TARGET_ARCH32)
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
FAIL;
emit_insn (gen_ashldi3_v8plus (operands[0], operands[1], operands[2]));
DONE;
@@ -6515,7 +6515,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "sllx\t%1, %2, %0";
}
@@ -6559,7 +6559,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sra\t%1, %2, %0";
}
@@ -6571,7 +6571,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI"))))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "sra\t%1, %2, %0";
}
@@ -6615,7 +6615,7 @@ visl")
{
if (TARGET_ARCH32)
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
FAIL; /* prefer generic code in this case */
emit_insn (gen_ashrdi3_v8plus (operands[0], operands[1], operands[2]));
DONE;
@@ -6628,7 +6628,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "srax\t%1, %2, %0";
}
@@ -6652,7 +6652,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI")))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "srl\t%1, %2, %0";
}
@@ -6665,7 +6665,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI"))))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "srl\t%1, %2, %0";
}
@@ -6681,7 +6681,7 @@ visl")
(match_operand 3 "const_int_operand" "")))]
"TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f);
return "srl\t%1, %2, %0";
}
@@ -6710,7 +6710,7 @@ visl")
{
if (TARGET_ARCH32)
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
FAIL;
emit_insn (gen_lshrdi3_v8plus (operands[0], operands[1], operands[2]));
DONE;
@@ -6723,7 +6723,7 @@ visl")
(match_operand:SI 2 "arith_operand" "rI")))]
"TARGET_ARCH64"
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
return "srlx\t%1, %2, %0";
}
@@ -6865,7 +6865,7 @@ visl")
gcc_assert (MEM_P (operands[0]) && GET_MODE (operands[0]) == FUNCTION_MODE);
- gcc_assert (GET_CODE (operands[3]) == CONST_INT);
+ gcc_assert (CONST_INT_P (operands[3]));
if (GET_CODE (XEXP (operands[0], 0)) == LABEL_REF)
{
@@ -6948,7 +6948,7 @@ visl")
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
+ "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0"
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
@@ -6964,7 +6964,7 @@ visl")
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) > 0"
+ "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) > 0"
{
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xfff);
return "call\t%a0, %1\n\t nop\n\tunimp\t%2";
@@ -6980,7 +6980,7 @@ visl")
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
+ "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0"
"call\t%a0, %1\n\t nop\n\tnop"
[(set_attr "type" "call_no_delay_slot")
(set_attr "length" "3")])
@@ -6993,7 +6993,7 @@ visl")
(match_operand 2 "immediate_operand" "")
(clobber (reg:SI O7_REG))]
;;- Do not use operand 1 for most machines.
- "TARGET_ARCH32 && GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0"
+ "TARGET_ARCH32 && CONST_INT_P (operands[2]) && INTVAL (operands[2]) < 0"
"call\t%a0, %1\n\t nop\n\tnop"
[(set_attr "type" "call_no_delay_slot")
(set_attr "length" "3")])
@@ -8780,7 +8780,7 @@ visl")
(clobber (match_scratch:SI 1 "=X,&h"))]
"TARGET_VIS && TARGET_ARCH32"
{
- if (GET_CODE (operands[0]) == CONST_INT
+ if (CONST_INT_P (operands[0])
|| sparc_check_64 (operands[0], insn))
return "wr\t%%g0, %0, %%gsr";
diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index 6c6897d0602..2a542a7101e 100644
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -161,7 +161,7 @@
(define_memory_constraint "T"
"Call operand, const_int, for absolute calls."
(and (match_code "mem")
- (match_test "GET_CODE (XEXP (op, 0)) == CONST_INT
+ (match_test "CONST_INT_P (XEXP (op, 0))
&& INTVAL (XEXP (op, 0)) >= 0
&& INTVAL (XEXP (op, 0)) <= 0x3ffff")))
diff --git a/gcc/config/spu/predicates.md b/gcc/config/spu/predicates.md
index 8d7767dad13..0d4314be398 100644
--- a/gcc/config/spu/predicates.md
+++ b/gcc/config/spu/predicates.md
@@ -65,7 +65,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_VECTOR)
+ if (CONST_INT_P (op) || GET_CODE (op) == CONST_VECTOR)
return arith_immediate_p (op, mode, -0x200, 0x1ff);
return 0;
})
@@ -75,7 +75,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+ if (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode);
return 0;
@@ -86,7 +86,7 @@
{
if (spu_reg_operand (op, mode))
return 1;
- if (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+ if (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR)
return logical_immediate_p (op, mode)
|| iohl_immediate_p (op, mode);
diff --git a/gcc/config/spu/spu-builtins.md b/gcc/config/spu/spu-builtins.md
index 524324f22ab..fd56cdda586 100644
--- a/gcc/config/spu/spu-builtins.md
+++ b/gcc/config/spu/spu-builtins.md
@@ -28,10 +28,10 @@
(const_int -16))))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) & 15) != 0)
operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx op2 = operands[2];
operands[2] = force_reg (Pmode, operands[2]);
@@ -54,7 +54,7 @@
(const_int -16))))]
""
{
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& (INTVAL (operands[1]) & 15) != 0)
operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
})
@@ -73,10 +73,10 @@
(match_operand:TI 0 "spu_reg_operand" "r,r"))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) & 15) != 0)
operands[2] = GEN_INT (INTVAL (operands[2]) & -16);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx op2 = operands[2];
operands[2] = force_reg (Pmode, operands[2]);
@@ -99,7 +99,7 @@
(match_operand:TI 0 "spu_reg_operand" "r"))]
""
{
- if (GET_CODE (operands[1]) == CONST_INT
+ if (CONST_INT_P (operands[1])
&& (INTVAL (operands[1]) & 15) != 0)
operands[1] = GEN_INT (INTVAL (operands[1]) & -16);
})
@@ -468,13 +468,13 @@
(match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convtf expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx exp2;
rtx cnv = gen_reg_rtx (V4SFmode);
@@ -501,14 +501,14 @@
""
{
rtx exp2;
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convts expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx mul = gen_reg_rtx (V4SFmode);
emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
@@ -525,13 +525,13 @@
(match_operand:SI 2 "spu_nonmem_operand")] 0 ))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convtf expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx exp2;
rtx cnv = gen_reg_rtx (V4SFmode);
@@ -558,14 +558,14 @@
""
{
rtx exp2;
- if (GET_CODE (operands[2]) == CONST_INT
+ if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < 0 || INTVAL (operands[2]) > 127))
{
error ("spu_convtu expects an integer literal in the range [0, 127].");
operands[2] = force_reg (SImode, operands[2]);
}
exp2 = spu_gen_exp2 (V4SFmode, operands[2]);
- if (GET_CODE (operands[2]) != CONST_INT)
+ if (!CONST_INT_P (operands[2]))
{
rtx mul = gen_reg_rtx (V4SFmode);
emit_insn (gen_mulv4sf3 (mul, operands[1], exp2));
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 613d30149c1..0e21e28b2e7 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -430,7 +430,7 @@ spu_expand_extv (rtx ops[], int unsignedp)
emit_move_insn (mask, GEN_INT (-1));
emit_insn (gen_rotqby_ti (s0, s0, r0));
emit_insn (gen_rotqby_ti (s1, s1, r0));
- if (GET_CODE (r0) == CONST_INT)
+ if (CONST_INT_P (r0))
r1 = GEN_INT (INTVAL (r0) & 15);
else
emit_insn (gen_andsi3 (r1, r0, GEN_INT (15)));
@@ -603,8 +603,8 @@ spu_expand_block_move (rtx ops[])
HOST_WIDE_INT bytes, align, offset;
rtx src, dst, sreg, dreg, target;
int i;
- if (GET_CODE (ops[2]) != CONST_INT
- || GET_CODE (ops[3]) != CONST_INT
+ if (!CONST_INT_P (ops[2])
+ || !CONST_INT_P (ops[3])
|| INTVAL (ops[2]) > (HOST_WIDE_INT) (MOVE_RATIO (optimize_insn_for_speed_p ()) * 8))
return 0;
@@ -690,7 +690,7 @@ spu_emit_branch_or_set (int is_set, rtx cmp, rtx operands[])
/* When op1 is a CONST_INT change (X >= C) to (X > C-1),
and so on, to keep the constant in operand 1. */
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
{
HOST_WIDE_INT val = INTVAL (op1) - 1;
if (trunc_int_for_mode (val, GET_MODE (op0)) == val)
@@ -719,7 +719,7 @@ spu_emit_branch_or_set (int is_set, rtx cmp, rtx operands[])
/* However, if we generate an integer result, performing a reverse test
would require an extra negation, so avoid that where possible. */
- if (GET_CODE (op1) == CONST_INT && is_set == 1)
+ if (CONST_INT_P (op1) && is_set == 1)
{
HOST_WIDE_INT val = INTVAL (op1) + 1;
if (trunc_int_for_mode (val, GET_MODE (op0)) == val)
@@ -1037,7 +1037,7 @@ print_operand_address (FILE * file, register rtx addr)
rtx offset;
if (GET_CODE (addr) == AND
- && GET_CODE (XEXP (addr, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (addr, 1))
&& INTVAL (XEXP (addr, 1)) == -16)
addr = XEXP (addr, 0);
@@ -1055,7 +1055,7 @@ print_operand_address (FILE * file, register rtx addr)
fprintf (file, "%s,%s", reg_names[REGNO (reg)],
reg_names[REGNO (offset)]);
}
- else if (GET_CODE (offset) == CONST_INT)
+ else if (CONST_INT_P (offset))
{
fprintf (file, HOST_WIDE_INT_PRINT_DEC "(%s)",
INTVAL (offset), reg_names[REGNO (reg)]);
@@ -1305,7 +1305,7 @@ print_operand (FILE * file, rtx x, int code)
break;
case 'M': /* print code for c*d */
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
switch (INTVAL (x))
{
case 1:
@@ -3072,7 +3072,7 @@ int
spu_constant_address_p (rtx x)
{
return (GET_CODE (x) == LABEL_REF || GET_CODE (x) == SYMBOL_REF
- || GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST
+ || CONST_INT_P (x) || GET_CODE (x) == CONST
|| GET_CODE (x) == HIGH);
}
@@ -3174,7 +3174,7 @@ classify_immediate (rtx op, machine_mode mode)
if (!flag_pic
&& mode == V4SImode
&& GET_CODE (op) == CONST_VECTOR
- && GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_INT
+ && !CONST_INT_P (CONST_VECTOR_ELT (op, 0))
&& GET_CODE (CONST_VECTOR_ELT (op, 0)) != CONST_DOUBLE)
op = unwrap_const_vec_duplicate (op);
@@ -3194,7 +3194,7 @@ classify_immediate (rtx op, machine_mode mode)
rtx cst = XEXP (XEXP (op, 0), 1);
if (GET_CODE (sym) == SYMBOL_REF
- && GET_CODE (cst) == CONST_INT
+ && CONST_INT_P (cst)
&& satisfies_constraint_K (cst))
return IC_IL1s;
}
@@ -3205,7 +3205,7 @@ classify_immediate (rtx op, machine_mode mode)
case CONST_VECTOR:
for (i = 0; i < GET_MODE_NUNITS (mode); i++)
- if (GET_CODE (CONST_VECTOR_ELT (op, i)) != CONST_INT
+ if (!CONST_INT_P (CONST_VECTOR_ELT (op, i))
&& GET_CODE (CONST_VECTOR_ELT (op, i)) != CONST_DOUBLE)
return IC_POOL;
/* Fall through. */
@@ -3289,7 +3289,7 @@ const_vector_immediate_p (rtx x)
int i;
gcc_assert (GET_CODE (x) == CONST_VECTOR);
for (i = 0; i < GET_MODE_NUNITS (GET_MODE (x)); i++)
- if (GET_CODE (CONST_VECTOR_ELT (x, i)) != CONST_INT
+ if (!CONST_INT_P (CONST_VECTOR_ELT (x, i))
&& GET_CODE (CONST_VECTOR_ELT (x, i)) != CONST_DOUBLE)
return 0;
return 1;
@@ -3302,7 +3302,7 @@ logical_immediate_p (rtx op, machine_mode mode)
unsigned char arr[16];
int i, j;
- gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3334,7 +3334,7 @@ iohl_immediate_p (rtx op, machine_mode mode)
unsigned char arr[16];
int i, j;
- gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3366,7 +3366,7 @@ arith_immediate_p (rtx op, machine_mode mode,
unsigned char arr[16];
int bytes, i, j;
- gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3407,7 +3407,7 @@ exp2_immediate_p (rtx op, machine_mode mode, int low, int high)
unsigned char arr[16];
int bytes, i, j;
- gcc_assert (GET_CODE (op) == CONST_INT || GET_CODE (op) == CONST_DOUBLE
+ gcc_assert (CONST_INT_P (op) || GET_CODE (op) == CONST_DOUBLE
|| GET_CODE (op) == CONST_VECTOR);
if (GET_CODE (op) == CONST_VECTOR
@@ -3459,7 +3459,7 @@ ea_symbol_ref_p (const_rtx x)
rtx plus = XEXP (x, 0);
rtx op0 = XEXP (plus, 0);
rtx op1 = XEXP (plus, 1);
- if (GET_CODE (op1) == CONST_INT)
+ if (CONST_INT_P (op1))
x = op0;
}
@@ -3518,7 +3518,7 @@ spu_legitimate_address_p (machine_mode mode,
int aligned = GET_MODE_SIZE (mode) >= 16;
if (aligned
&& GET_CODE (x) == AND
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& INTVAL (XEXP (x, 1)) == (HOST_WIDE_INT) - 16)
x = XEXP (x, 0);
switch (GET_CODE (x))
@@ -3557,7 +3557,7 @@ spu_legitimate_address_p (machine_mode mode,
op1 = XEXP (op1, 0);
if (GET_CODE (op0) == REG
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
- && GET_CODE (op1) == CONST_INT
+ && CONST_INT_P (op1)
&& ((INTVAL (op1) >= -0x2000 && INTVAL (op1) <= 0x1fff)
/* If virtual registers are involved, the displacement will
change later on anyway, so checking would be premature.
@@ -4493,7 +4493,7 @@ spu_expand_mov (rtx * ops, machine_mode mode)
/* Catch the SImode immediates greater than 0x7fffffff, and sign
extend them. */
- if (GET_CODE (ops[1]) == CONST_INT)
+ if (CONST_INT_P (ops[1]))
{
HOST_WIDE_INT val = trunc_int_for_mode (INTVAL (ops[1]), mode);
if (val != INTVAL (ops[1]))
@@ -4575,7 +4575,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
rot = gen_reg_rtx (SImode);
emit_insn (gen_addsi3 (rot, p0, p1));
}
- else if (GET_CODE (p1) == CONST_INT && (INTVAL (p1) & 15))
+ else if (CONST_INT_P (p1) && (INTVAL (p1) & 15))
{
if (INTVAL (p1) > 0
&& REG_POINTER (p0)
@@ -4602,7 +4602,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
}
else
{
- if (GET_CODE (p1) == CONST_INT && (INTVAL (p1) & 15))
+ if (CONST_INT_P (p1) && (INTVAL (p1) & 15))
{
rot_amt = INTVAL (p1) & 15;
if (INTVAL (p1) & -16)
@@ -4626,7 +4626,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
{
if (GET_CODE (XEXP (addr, 0)) == PLUS
&& ALIGNED_SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0))
- && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
{
rot_amt = INTVAL (XEXP (XEXP (addr, 0), 1));
if (rot_amt & -16)
@@ -4643,7 +4643,7 @@ spu_expand_load (rtx dst0, rtx dst1, rtx src, int extra_rotby)
emit_move_insn (rot, addr);
}
}
- else if (GET_CODE (addr) == CONST_INT)
+ else if (CONST_INT_P (addr))
{
rot_amt = INTVAL (addr);
addr = GEN_INT (rot_amt & -16);
@@ -4755,7 +4755,7 @@ spu_split_store (rtx * ops)
aform = 0;
p0 = XEXP (addr, 0);
p1 = p1_lo = XEXP (addr, 1);
- if (REG_P (p0) && GET_CODE (p1) == CONST_INT)
+ if (REG_P (p0) && CONST_INT_P (p1))
{
p1_lo = GEN_INT (INTVAL (p1) & 15);
if (reg_aligned_for_addr (p0))
@@ -4791,7 +4791,7 @@ spu_split_store (rtx * ops)
else if (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
&& ALIGNED_SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0))
- && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
{
HOST_WIDE_INT v = INTVAL (XEXP (XEXP (addr, 0), 1));
if ((v & -16) != 0)
@@ -4803,7 +4803,7 @@ spu_split_store (rtx * ops)
addr = XEXP (XEXP (addr, 0), 0);
p1_lo = GEN_INT (v & 15);
}
- else if (GET_CODE (addr) == CONST_INT)
+ else if (CONST_INT_P (addr))
{
p1_lo = GEN_INT (INTVAL (addr) & 15);
addr = GEN_INT (INTVAL (addr) & -16);
@@ -4991,9 +4991,9 @@ gen_cpat_const (rtx * ops)
{
unsigned char dst[16];
int i, offset, shift, isize;
- if (GET_CODE (ops[3]) != CONST_INT
- || GET_CODE (ops[2]) != CONST_INT
- || (GET_CODE (ops[1]) != CONST_INT
+ if (!CONST_INT_P (ops[3])
+ || !CONST_INT_P (ops[2])
+ || (!CONST_INT_P (ops[1])
&& GET_CODE (ops[1]) != REG))
return 0;
if (GET_CODE (ops[1]) == REG
@@ -5029,7 +5029,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
memset (arr, 0, 16);
mode = GET_MODE (x) != VOIDmode ? GET_MODE (x) : mode;
- if (GET_CODE (x) == CONST_INT
+ if (CONST_INT_P (x)
|| (GET_CODE (x) == CONST_DOUBLE
&& (mode == SFmode || mode == DFmode)))
{
@@ -5076,7 +5076,7 @@ constant_to_array (machine_mode mode, rtx x, unsigned char arr[16])
for (i = 0; i < units; i++)
{
elt = CONST_VECTOR_ELT (x, i);
- if (GET_CODE (elt) == CONST_INT || GET_CODE (elt) == CONST_DOUBLE)
+ if (CONST_INT_P (elt) || GET_CODE (elt) == CONST_DOUBLE)
{
if (GET_CODE (elt) == CONST_DOUBLE)
val = const_double_to_hwint (elt);
@@ -5309,7 +5309,7 @@ spu_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
REG ? COSTS_N_INSNS (12) : COSTS_N_INSNS (7);
if (mode == SImode && GET_CODE (XEXP (x, 0)) == REG)
{
- if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 1)))
{
HOST_WIDE_INT val = INTVAL (XEXP (x, 1));
cost = COSTS_N_INSNS (14);
@@ -5651,7 +5651,7 @@ void
spu_builtin_splats (rtx ops[])
{
machine_mode mode = GET_MODE (ops[0]);
- if (GET_CODE (ops[1]) == CONST_INT || GET_CODE (ops[1]) == CONST_DOUBLE)
+ if (CONST_INT_P (ops[1]) || GET_CODE (ops[1]) == CONST_DOUBLE)
{
unsigned char arr[16];
constant_to_array (GET_MODE_INNER (mode), ops[1], arr);
@@ -5704,7 +5704,7 @@ spu_builtin_extract (rtx ops[])
mode = GET_MODE (ops[1]);
- if (GET_CODE (ops[2]) == CONST_INT)
+ if (CONST_INT_P (ops[2]))
{
switch (mode)
{
@@ -5769,7 +5769,7 @@ spu_builtin_insert (rtx ops[])
rtx mask = gen_reg_rtx (TImode);
rtx offset;
- if (GET_CODE (ops[3]) == CONST_INT)
+ if (CONST_INT_P (ops[3]))
offset = GEN_INT (INTVAL (ops[3]) * GET_MODE_SIZE (imode));
else
{
@@ -5798,7 +5798,7 @@ spu_builtin_promote (rtx ops[])
emit_insn (gen_spu_convert (from, ops[1]));
- if (GET_CODE (ops[2]) == CONST_INT)
+ if (CONST_INT_P (ops[2]))
{
pos = -GET_MODE_SIZE (imode) * INTVAL (ops[2]);
if (GET_MODE_SIZE (imode) < 4)
@@ -6312,7 +6312,7 @@ spu_force_reg (machine_mode mode, rtx op)
rtx x, r;
if (GET_MODE (op) == VOIDmode || GET_MODE (op) == BLKmode)
{
- if ((SCALAR_INT_MODE_P (mode) && GET_CODE (op) == CONST_INT)
+ if ((SCALAR_INT_MODE_P (mode) && CONST_INT_P (op))
|| GET_MODE (op) == BLKmode)
return force_reg (mode, convert_to_mode (mode, op, 0));
abort ();
@@ -6353,10 +6353,10 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
v = INTVAL (XEXP (XEXP (op, 0), 1));
op = XEXP (XEXP (op, 0), 0);
}
- else if (GET_CODE (op) == CONST_INT)
+ else if (CONST_INT_P (op))
v = INTVAL (op);
else if (GET_CODE (op) == CONST_VECTOR
- && GET_CODE (CONST_VECTOR_ELT (op, 0)) == CONST_INT)
+ && CONST_INT_P (CONST_VECTOR_ELT (op, 0)))
v = INTVAL (CONST_VECTOR_ELT (op, 0));
/* The default for v is 0 which is valid in every range. */
@@ -6504,11 +6504,11 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
si_ai(), we sometimes need to convert the scalar argument to a
vector argument by splatting the scalar. */
if (VECTOR_MODE_P (mode)
- && (GET_CODE (ops[i]) == CONST_INT
+ && (CONST_INT_P (ops[i])
|| GET_MODE_CLASS (GET_MODE (ops[i])) == MODE_INT
|| GET_MODE_CLASS (GET_MODE (ops[i])) == MODE_FLOAT))
{
- if (GET_CODE (ops[i]) == CONST_INT)
+ if (CONST_INT_P (ops[i]))
ops[i] = spu_const (mode, INTVAL (ops[i]));
else
{
@@ -6960,8 +6960,8 @@ rtx
spu_gen_exp2 (machine_mode mode, rtx scale)
{
gcc_assert (mode == V4SFmode);
- gcc_assert (GET_MODE (scale) == SImode || GET_CODE (scale) == CONST_INT);
- if (GET_CODE (scale) != CONST_INT)
+ gcc_assert (GET_MODE (scale) == SImode || CONST_INT_P (scale));
+ if (!CONST_INT_P (scale))
{
/* unsigned int exp = (127 + scale) << 23;
__vector float m = (__vector float) spu_splats (exp); */
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index bb622981abd..ba7858a645f 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -1440,7 +1440,7 @@
rtx b = operands[4];
rtx c = operands[5];
rtx d = operands[6];
- if (GET_CODE(operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
val = INTVAL(operands[2]);
emit_move_insn(d, operands[2]);
@@ -2378,7 +2378,7 @@
(match_operand:SI 2 "spu_nonmem_operand" "")))
(clobber (match_dup:TI 3))])]
""
- "if (GET_CODE (operands[2]) == CONST_INT)
+ "if (CONST_INT_P (operands[2]))
{
emit_insn (gen_ashlti3_imm(operands[0], operands[1], operands[2]));
DONE;
@@ -2515,7 +2515,7 @@
(match_dup:SI 5)))]
{
operands[3] = gen_reg_rtx (<MODE>mode);
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
HOST_WIDE_INT val = INTVAL(operands[2]);
operands[4] = GEN_INT (val & 7);
@@ -2541,7 +2541,7 @@
(const_int -8))))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (7 - INTVAL (operands[2]));
else
{
@@ -2576,7 +2576,7 @@
(lshiftrt:DTI (match_dup:DTI 1)
(and:SI (neg:SI (match_dup:SI 3)) (const_int 7))))]
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[3] = GEN_INT (-INTVAL (operands[2]));
else
emit_insn (gen_subsi3 (operands[3], GEN_INT (0), operands[2]));
@@ -2601,7 +2601,7 @@
(const_int 8))))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT (-INTVAL (operands[2]));
else
{
@@ -2685,13 +2685,13 @@
rtx op4 = operands[4];
rtx op5 = operands[5];
- if (GET_CODE (op2) == CONST_INT && INTVAL (op2) >= 63)
+ if (CONST_INT_P (op2) && INTVAL (op2) >= 63)
{
rtx op0s = gen_rtx_REG (SImode, REGNO (op0));
emit_insn (gen_ashrsi3 (op0s, op1s, GEN_INT (32)));
emit_insn (gen_spu_fsm (op0v, op0s));
}
- else if (GET_CODE (op2) == CONST_INT && INTVAL (op2) >= 32)
+ else if (CONST_INT_P (op2) && INTVAL (op2) >= 32)
{
rtx op0d = gen_rtx_REG (V2DImode, REGNO (op0));
HOST_WIDE_INT val = INTVAL (op2);
diff --git a/gcc/config/stormy16/predicates.md b/gcc/config/stormy16/predicates.md
index c8928c706d0..e5a653ac5a7 100644
--- a/gcc/config/stormy16/predicates.md
+++ b/gcc/config/stormy16/predicates.md
@@ -73,7 +73,7 @@
op = XEXP (XEXP (op, 0), 0);
else
return 0;
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
{
HOST_WIDE_INT i = INTVAL (op);
return (i >= 0x7f00 && i < 0x7fff);
@@ -107,7 +107,7 @@
(match_code "const_int")
{
HOST_WIDE_INT i;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return 0;
i = ~ INTVAL (op);
if (mode == QImode)
@@ -123,7 +123,7 @@
(match_code "const_int")
{
HOST_WIDE_INT i;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return 0;
i = INTVAL (op);
if (mode == QImode)
@@ -147,7 +147,7 @@
(define_predicate "xstormy16_carry_plus_operand"
(match_code "plus")
{
- return (GET_CODE (XEXP (op, 1)) == CONST_INT
+ return (CONST_INT_P (XEXP (op, 1))
&& (INTVAL (XEXP (op, 1)) < -4 || INTVAL (XEXP (op, 1)) > 4));
})
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index 0de83623b5d..d662ad0308d 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -22,7 +22,7 @@
(define_predicate "reg_or_0_operand"
(match_code "reg,subreg,const_int,const_double")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return INTVAL (op) == 0;
else if (GET_CODE (op) == CONST_DOUBLE)
@@ -38,7 +38,7 @@
(define_predicate "reg_or_int5_operand"
(match_code "reg,subreg,const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return CONST_OK_FOR_J (INTVAL (op));
else
@@ -51,7 +51,7 @@
(define_predicate "reg_or_int9_operand"
(match_code "reg,subreg,const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return CONST_OK_FOR_O (INTVAL (op));
return register_operand (op, mode);
@@ -62,7 +62,7 @@
(define_predicate "reg_or_const_operand"
(match_code "reg,const_int")
{
- if (GET_CODE (op) == CONST_INT)
+ if (CONST_INT_P (op))
return TRUE;
return register_operand (op, mode);
@@ -99,7 +99,7 @@
must be done with HIGH & LO_SUM patterns. */
if (CONSTANT_P (op)
&& GET_CODE (op) != HIGH
- && !(GET_CODE (op) == CONST_INT
+ && !(CONST_INT_P (op)
&& (CONST_OK_FOR_J (INTVAL (op))
|| CONST_OK_FOR_K (INTVAL (op))
|| CONST_OK_FOR_L (INTVAL (op)))))
@@ -114,7 +114,7 @@
(define_predicate "disp23_operand"
(match_code "const_int")
{
- if (GET_CODE (op) == CONST_INT
+ if (CONST_INT_P (op)
&& ((unsigned)(INTVAL (op)) >= 0x8000)
&& ((unsigned)(INTVAL (op)) < 0x400000))
return 1;
@@ -145,7 +145,7 @@
(define_predicate "power_of_two_operand"
(match_code "const_int")
{
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return 0;
if (exact_log2 (INTVAL (op)) == -1)
@@ -209,7 +209,7 @@
|| GET_CODE (XEXP (plus, 0)) != REG
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
- || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (plus, 1)))
return 0;
/* If the register is being pushed somewhere other than the stack
@@ -296,7 +296,7 @@
|| GET_CODE (XEXP (plus, 0)) != REG
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
- || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (plus, 1)))
return 0;
}
@@ -368,7 +368,7 @@
|| GET_CODE (XEXP (plus, 0)) != REG
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
- || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (plus, 1)))
return 0;
}
@@ -433,7 +433,7 @@
|| GET_CODE (XEXP (plus, 0)) != REG
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
- || GET_CODE (XEXP (plus, 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (plus, 1)))
return 0;
/* If the register is being pushed somewhere other than the stack
@@ -464,7 +464,7 @@
else
return 0;
- if (GET_CODE (op) != CONST_INT)
+ if (!CONST_INT_P (op))
return 0;
if (exact_log2 (~INTVAL (op) & mask) == -1)
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index cca24edb3ae..bf9fbea608d 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -373,7 +373,7 @@ v850_rtx_costs (rtx x, machine_mode mode, int outer_code,
{
if (GET_CODE (XEXP (x, 1)) == REG)
*total = 4;
- else if (GET_CODE (XEXP (x, 1)) == CONST_INT)
+ else if (CONST_INT_P (XEXP (x, 1)))
{
if (CONST_OK_FOR_O (INTVAL (XEXP (x, 1))))
*total = 6;
@@ -554,7 +554,7 @@ v850_print_operand (FILE * file, rtx x, int code)
machine_mode mode = GET_MODE (x);
x = XEXP (adjust_address (x, SImode, 4), 0);
v850_print_operand_address (file, mode, x);
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, "[r0]");
}
break;
@@ -629,7 +629,7 @@ v850_print_operand (FILE * file, rtx x, int code)
switch (GET_CODE (x))
{
case MEM:
- if (GET_CODE (XEXP (x, 0)) == CONST_INT)
+ if (CONST_INT_P (XEXP (x, 0)))
output_address (GET_MODE (x),
gen_rtx_PLUS (SImode, gen_rtx_REG (SImode, 0),
XEXP (x, 0)));
@@ -823,7 +823,7 @@ output_move_single (rtx * operands)
if (REG_P (src))
return "mov %1,%0";
- else if (GET_CODE (src) == CONST_INT)
+ else if (CONST_INT_P (src))
{
HOST_WIDE_INT value = INTVAL (src);
@@ -898,7 +898,7 @@ output_move_single (rtx * operands)
if (REG_P (src))
return "%S0st%W0 %1,%0";
- else if (GET_CODE (src) == CONST_INT && INTVAL (src) == 0)
+ else if (CONST_INT_P (src) && INTVAL (src) == 0)
return "%S0st%W0 %.,%0";
else if (GET_CODE (src) == CONST_DOUBLE
@@ -1091,7 +1091,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
case PLUS:
op0 = XEXP (addr, 0);
op1 = XEXP (addr, 1);
- if (GET_CODE (op1) == CONST_INT
+ if (CONST_INT_P (op1)
&& INTVAL (op1) < max_offset
&& INTVAL (op1) >= 0
&& (INTVAL (op1) & mask) == 0)
@@ -1186,7 +1186,7 @@ Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, end
else if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG
&& REGNO (XEXP (addr, 0)) == (unsigned) regno
- && GET_CODE (XEXP (addr, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (addr, 1))
&& ((INTVAL (XEXP (addr, 1)))
< ep_memory_offset (GET_MODE (*p_mem),
unsignedp))
@@ -1349,7 +1349,7 @@ v850_reorg (void)
else if (GET_CODE (addr) == PLUS
&& GET_CODE (XEXP (addr, 0)) == REG
- && GET_CODE (XEXP (addr, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (addr, 1))
&& ((INTVAL (XEXP (addr, 1)))
< ep_memory_offset (GET_MODE (mem), unsignedp))
&& ((INTVAL (XEXP (addr, 1))) >= 0))
@@ -2217,7 +2217,7 @@ construct_restore_jr (rtx op)
registers. */
gcc_assert (GET_CODE (XVECEXP (op, 0, 1)) == SET);
gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS);
- gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)));
stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1));
@@ -2322,7 +2322,7 @@ construct_save_jarl (rtx op)
gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET);
gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS);
gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) == REG);
- gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)));
/* Work out how many bytes to push onto the stack after storing the
registers. */
@@ -2620,7 +2620,7 @@ construct_dispose_instruction (rtx op)
stack before retrieving registers. */
gcc_assert (GET_CODE (XVECEXP (op, 0, 1)) == SET);
gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 1))) == PLUS);
- gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1)));
stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 1)), 1));
@@ -2741,7 +2741,7 @@ construct_prepare_instruction (rtx op)
the stack after storing the registers. */
gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET);
gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS);
- gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)) == CONST_INT);
+ gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)));
stack_bytes = INTVAL (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1));
@@ -3024,7 +3024,7 @@ v850_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
|| !(GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
+ && CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& !CONST_OK_FOR_K (INTVAL (XEXP (XEXP (x, 0), 1)))));
}
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 112ce9b0d5f..167d87ca60b 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -255,7 +255,7 @@
&& GET_CODE (operands[1]) != HIGH
&& ! (TARGET_V850E_UP)
&& !special_symbolref_operand (operands[1], VOIDmode)
- && !(GET_CODE (operands[1]) == CONST_INT
+ && !(CONST_INT_P (operands[1])
&& (CONST_OK_FOR_J (INTVAL (operands[1]))
|| CONST_OK_FOR_K (INTVAL (operands[1]))
|| CONST_OK_FOR_L (INTVAL (operands[1])))))
@@ -590,7 +590,7 @@
(sign_extend:SI (match_operand:HI 2 "nonmemory_operand" ""))))]
""
{
- if (GET_CODE (operands[2]) == CONST_INT)
+ if (CONST_INT_P (operands[2]))
{
emit_insn (gen_mulhisi3_internal2 (operands[0], operands[1], operands[2]));
DONE;
@@ -1150,8 +1150,8 @@
&& GET_MODE (XEXP (operands[1], 0)) != SImode)
FAIL;
- if ((GET_CODE (operands[2]) == CONST_INT
- && GET_CODE (operands[3]) == CONST_INT))
+ if ((CONST_INT_P (operands[2])
+ && CONST_INT_P (operands[3])))
{
int o2 = INTVAL (operands[2]);
int o3 = INTVAL (operands[3]);
@@ -1304,7 +1304,7 @@
"(TARGET_V850E_UP)
&& ((INTVAL (operands[2]) ^ INTVAL (operands[3])) == 1)
&& ((INTVAL (operands[2]) + INTVAL (operands[3])) != 1)
- && (GET_CODE (operands[5]) == CONST_INT
+ && (CONST_INT_P (operands[5])
|| REGNO (operands[0]) != REGNO (operands[5]))
&& REGNO (operands[0]) != REGNO (operands[4])"
[(set (match_dup 0) (match_dup 6))
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 431f64cfcad..48e02e04689 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -1902,7 +1902,7 @@ visium_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
machine_mode mode)
{
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (x, 1))
&& GET_CODE (XEXP (x, 0)) == REG && mode != BLKmode)
{
int offset = INTVAL (XEXP (x, 1));
@@ -1947,7 +1947,7 @@ visium_legitimize_reload_address (rtx x, machine_mode mode, int opnum,
newrtx = tem ? tem : x;
if (GET_CODE (newrtx) == PLUS
- && GET_CODE (XEXP (newrtx, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (newrtx, 1))
&& GET_CODE (XEXP (newrtx, 0)) == REG
&& BASE_REGISTER_P (REGNO (XEXP (newrtx, 0))))
{
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 2b97fa2e270..802323c2f8e 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -534,9 +534,9 @@ smalloffset_mem_p (rtx op)
{
rtx offset = XEXP (addr, 0);
HOST_WIDE_INT val;
- if (GET_CODE (offset) != CONST_INT)
+ if (!CONST_INT_P (offset))
offset = XEXP (addr, 1);
- if (GET_CODE (offset) != CONST_INT)
+ if (!CONST_INT_P (offset))
return FALSE;
val = INTVAL (offset);
@@ -723,7 +723,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
mode = GET_MODE (cmp1);
/* Make sure we can handle any constants given to us. */
- if (GET_CODE (cmp1) == CONST_INT)
+ if (CONST_INT_P (cmp1))
{
HOST_WIDE_INT value = INTVAL (cmp1);
unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value;
@@ -748,13 +748,13 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
}
/* See if we need to invert the result. */
- *p_invert = ((GET_CODE (cmp1) == CONST_INT)
+ *p_invert = ((CONST_INT_P (cmp1))
? p_info->invert_const
: p_info->invert_reg);
/* Comparison to constants, may involve adding 1 to change a LT into LE.
Comparison between two registers, may involve switching operands. */
- if (GET_CODE (cmp1) == CONST_INT)
+ if (CONST_INT_P (cmp1))
{
if (p_info->const_add != 0)
cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add);
@@ -1047,7 +1047,7 @@ xtensa_emit_move_sequence (rtx *operands, machine_mode mode)
rtx src = operands[1];
if (CONSTANT_P (src)
- && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src))))
+ && (!CONST_INT_P (src) || ! xtensa_simm12b (INTVAL (src))))
{
rtx dst = operands[0];
@@ -1283,7 +1283,7 @@ xtensa_expand_block_move (rtx *operands)
rtx x;
/* If this is not a fixed size move, just call memcpy. */
- if (!optimize || (GET_CODE (operands[2]) != CONST_INT))
+ if (!optimize || (!CONST_INT_P (operands[2])))
return 0;
bytes = INTVAL (operands[2]);
@@ -1810,7 +1810,7 @@ xtensa_emit_call (int callop, rtx *operands)
static char result[64];
rtx tgt = operands[callop];
- if (GET_CODE (tgt) == CONST_INT)
+ if (CONST_INT_P (tgt))
sprintf (result, "call%d\t" HOST_WIDE_INT_PRINT_HEX,
WINDOW_SIZE, INTVAL (tgt));
else if (register_operand (tgt, VOIDmode))
@@ -1977,7 +1977,7 @@ xtensa_legitimize_address (rtx x,
/* Try to split up the offset to use an ADDMI instruction. */
if (GET_CODE (plus0) == REG
- && GET_CODE (plus1) == CONST_INT
+ && CONST_INT_P (plus1)
&& !xtensa_mem_offset (INTVAL (plus1), mode)
&& !xtensa_simm8 (INTVAL (plus1))
&& xtensa_mem_offset (INTVAL (plus1) & 0xff, mode)
@@ -2400,7 +2400,7 @@ print_operand (FILE *file, rtx x, int letter)
break;
case 'K':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
{
int num_bits = 0;
unsigned val = INTVAL (x);
@@ -2419,28 +2419,28 @@ print_operand (FILE *file, rtx x, int letter)
break;
case 'L':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 0x1f);
else
output_operand_lossage ("invalid %%L value");
break;
case 'R':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x1f);
else
output_operand_lossage ("invalid %%R value");
break;
case 'x':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
printx (file, INTVAL (x));
else
output_operand_lossage ("invalid %%x value");
break;
case 'd':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
else
output_operand_lossage ("invalid %%d value");
@@ -2448,7 +2448,7 @@ print_operand (FILE *file, rtx x, int letter)
case 't':
case 'b':
- if (GET_CODE (x) == CONST_INT)
+ if (CONST_INT_P (x))
{
printx (file, INTVAL (x));
fputs (letter == 't' ? "@h" : "@l", file);
@@ -2471,7 +2471,7 @@ print_operand (FILE *file, rtx x, int letter)
if (GET_CODE (XEXP (x, 0)) != PLUS
|| (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
&& GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF)
- || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT)
+ || !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
output_operand_lossage ("invalid %%t/%%b value");
print_operand (file, XEXP (XEXP (x, 0), 0), 0);
fputs (letter == 't' ? "@h" : "@l", file);
@@ -2505,7 +2505,7 @@ print_operand (FILE *file, rtx x, int letter)
fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
- else if (GET_CODE (x) == CONST_INT)
+ else if (CONST_INT_P (x))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x));
else
output_addr_const (file, x);
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 70d948720e9..a9e6e7ded5d 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -625,7 +625,7 @@ typedef struct xtensa_args
but rejecting CONST_DOUBLE. */
#define CONSTANT_ADDRESS_P(X) \
((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
- || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \
+ || CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
/* A C expression that is nonzero if X is a legitimate immediate
diff --git a/gcc/cse.c b/gcc/cse.c
index 35840a6d5ca..5a6fcf8cbb7 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -1289,7 +1289,7 @@ find_reg_offset_for_const (struct table_elt *anchor_elt, HOST_WIDE_INT offs,
if (REG_P (elt->exp)
|| (GET_CODE (elt->exp) == PLUS
&& REG_P (XEXP (elt->exp, 0))
- && GET_CODE (XEXP (elt->exp, 1)) == CONST_INT))
+ && CONST_INT_P (XEXP (elt->exp, 1))))
{
rtx x;
@@ -5029,7 +5029,7 @@ cse_insn (rtx_insn *insn)
if (targetm.const_anchor
&& !src_related
&& src_const
- && GET_CODE (src_const) == CONST_INT)
+ && CONST_INT_P (src_const))
{
src_related = try_const_anchors (src_const, mode);
src_related_is_const_anchor = src_related != NULL_RTX;
@@ -5998,7 +5998,7 @@ cse_insn (rtx_insn *insn)
if (targetm.const_anchor
&& REG_P (dest)
&& SCALAR_INT_MODE_P (GET_MODE (dest))
- && GET_CODE (sets[i].src_elt->exp) == CONST_INT)
+ && CONST_INT_P (sets[i].src_elt->exp))
insert_const_anchors (dest, sets[i].src_elt->exp, GET_MODE (dest));
elt->in_memory = (MEM_P (sets[i].inner_dest)
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index aa7fd7eb465..63cb01c8198 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -15129,7 +15129,7 @@ clz_loc_descriptor (rtx rtl, scalar_int_mode mode,
msb = immed_wide_int_const
(wi::set_bit_in_zero (GET_MODE_PRECISION (mode) - 1,
GET_MODE_PRECISION (mode)), mode);
- if (GET_CODE (msb) == CONST_INT && INTVAL (msb) < 0)
+ if (CONST_INT_P (msb) && INTVAL (msb) < 0)
tmp = new_loc_descr (HOST_BITS_PER_WIDE_INT == 32
? DW_OP_const4u : HOST_BITS_PER_WIDE_INT == 64
? DW_OP_const8u : DW_OP_constu, INTVAL (msb), 0);
diff --git a/gcc/explow.c b/gcc/explow.c
index 7eb854bca4a..c74c689aead 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -2178,7 +2178,7 @@ anti_adjust_stack_and_probe (rtx size, bool adjust_back)
if (temp != const0_rtx)
{
/* Manual CSE if the difference is not known at compile-time. */
- if (GET_CODE (temp) != CONST_INT)
+ if (!CONST_INT_P (temp))
temp = gen_rtx_MINUS (Pmode, size, rounded_size_op);
anti_adjust_stack (temp);
emit_stack_probe (stack_pointer_rtx);
diff --git a/gcc/expr.c b/gcc/expr.c
index 20e3f9ce337..d020627203b 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -1659,7 +1659,7 @@ rtx
emit_block_move (rtx x, rtx y, rtx size, enum block_op_methods method)
{
unsigned HOST_WIDE_INT max, min = 0;
- if (GET_CODE (size) == CONST_INT)
+ if (CONST_INT_P (size))
min = max = UINTVAL (size);
else
max = GET_MODE_MASK (GET_MODE (size));
@@ -3052,7 +3052,7 @@ rtx
clear_storage (rtx object, rtx size, enum block_op_methods method)
{
unsigned HOST_WIDE_INT max, min = 0;
- if (GET_CODE (size) == CONST_INT)
+ if (CONST_INT_P (size))
min = max = UINTVAL (size);
else
max = GET_MODE_MASK (GET_MODE (size));
diff --git a/gcc/genrecog.c b/gcc/genrecog.c
index f20089eeee8..82b00fde9ed 100644
--- a/gcc/genrecog.c
+++ b/gcc/genrecog.c
@@ -1687,7 +1687,7 @@ simplify_tests (state *s)
for (decision *d = s->first; d; d = d->next)
{
uint64_t label;
- /* Convert checks for GET_CODE (x) == CONST_INT and XWINT (x, 0) == N
+ /* Convert checks for CONST_INT_P (x) and XWINT (x, 0) == N
into checks for const_int_rtx[N'], if N is suitably small. */
if (d->test.kind == rtx_test::CODE
&& d->if_statement_p (&label)
diff --git a/gcc/ree.c b/gcc/ree.c
index c63e1591ae3..03d610137f9 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -268,7 +268,7 @@ update_reg_equal_equiv_notes (rtx_insn *insn, machine_mode new_mode,
rtx orig_src = XEXP (*loc, 0);
/* Update equivalency constants. Recall that RTL constants are
sign-extended. */
- if (GET_CODE (orig_src) == CONST_INT
+ if (CONST_INT_P (orig_src)
&& HWI_COMPUTABLE_MODE_P (new_mode))
{
if (INTVAL (orig_src) >= 0 || code == SIGN_EXTEND)
@@ -336,7 +336,7 @@ combine_set_extension (ext_cand *cand, rtx_insn *curr_insn, rtx *orig_set)
/* Merge constants by directly moving the constant into the register under
some conditions. Recall that RTL constants are sign-extended. */
- if (GET_CODE (orig_src) == CONST_INT
+ if (CONST_INT_P (orig_src)
&& HWI_COMPUTABLE_MODE_P (cand->mode))
{
if (INTVAL (orig_src) >= 0 || cand->code == SIGN_EXTEND)
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 38ee356a791..2747f0b2e53 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -5994,7 +5994,7 @@ function_invariant_p (const_rtx x)
return 1;
if (GET_CODE (x) == PLUS
&& (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
- && GET_CODE (XEXP (x, 1)) == CONST_INT)
+ && CONST_INT_P (XEXP (x, 1)))
return 1;
return 0;
}
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 8004951d2e8..1d85e03ee2e 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -264,13 +264,13 @@ addr_for_mem_ref (struct mem_address *addr, addr_space_t as,
into OFF and clear BSE. Otherwise we may later try to pull a mode from
BSE to generate a REG, which won't work with constants because they
are modeless. */
- if (bse && GET_CODE (bse) == CONST_INT)
+ if (bse && CONST_INT_P (bse))
{
if (off)
off = simplify_gen_binary (PLUS, pointer_mode, bse, off);
else
off = bse;
- gcc_assert (GET_CODE (off) == CONST_INT);
+ gcc_assert (CONST_INT_P (off));
bse = NULL_RTX;
}
gen_addr_rtx (pointer_mode, sym, bse, idx, st, off, &address, NULL, NULL);
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 67f25c1c795..599c6bd7f33 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -2043,7 +2043,7 @@ vt_get_canonicalize_base (rtx loc)
{
while ((GET_CODE (loc) == PLUS
|| GET_CODE (loc) == AND)
- && GET_CODE (XEXP (loc, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (loc, 1))
&& (GET_CODE (loc) != AND
|| negative_power_of_two_p (INTVAL (XEXP (loc, 1)))))
loc = XEXP (loc, 0);
@@ -2195,7 +2195,7 @@ vt_canonicalize_addr (dataflow_set *set, rtx oloc)
canonicalize the base and we're done. We'll normally have
only one stack alignment anyway. */
if (GET_CODE (loc) == AND
- && GET_CODE (XEXP (loc, 1)) == CONST_INT
+ && CONST_INT_P (XEXP (loc, 1))
&& negative_power_of_two_p (INTVAL (XEXP (loc, 1))))
{
x = vt_canonicalize_addr (set, XEXP (loc, 0));
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 15/18] Use LABEL_REF_P macro.
2019-08-06 3:11 ` Arvind Sankar
` (2 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 14/18] Use LABEL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh LABEL_REF Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 06/18] Use CONST_DOUBLE_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_DOUBLE Arvind Sankar
` (13 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* rtlanal.c: Convert GET_CODE (..) == LABEL_REF to
LABEL_REF_P (..).
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index cb6c8902353..a8becc85047 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -3347,8 +3347,7 @@ computed_jump_p (const rtx_insn *insn)
for (i = len - 1; i >= 0; i--)
if (GET_CODE (XVECEXP (pat, 0, i)) == USE
- && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0))
- == LABEL_REF))
+ && LABEL_REF_P (XEXP (XVECEXP (pat, 0, i), 0)))
{
has_use_labelref = 1;
break;
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 05/18] Use CONST_FIXED_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_FIXED
2019-08-06 3:11 ` Arvind Sankar
` (11 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 02/18] Use CONST_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_INT Arvind Sankar
@ 2019-08-06 3:12 ` Arvind Sankar
2019-08-06 3:13 ` [PATCH v2 16/18] Use SYMBOL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SYMBOL_REF Arvind Sankar
` (4 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:12 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* cfgexpand.c: Convert GET_CODE (..) == CONST_FIXED
to CONST_FIXED_P.
* config/spu/spu.c: Likewise.
* varasm.c: Likewise.
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index 33af991573f..b141a57d3af 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -5481,7 +5481,7 @@ expand_debug_locations (void)
gcc_assert (mode == GET_MODE (val)
|| (GET_MODE (val) == VOIDmode
&& (CONST_SCALAR_INT_P (val)
- || GET_CODE (val) == CONST_FIXED
+ || CONST_FIXED_P (val)
|| GET_CODE (val) == LABEL_REF)));
}
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 0e21e28b2e7..e6b25ab3b98 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -5985,7 +5985,7 @@ spu_expand_vector_init (rtx target, rtx vals)
x = XVECEXP (vals, 0, i);
if (!(CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE
- || GET_CODE (x) == CONST_FIXED))
+ || CONST_FIXED_P (x)))
++n_var;
else
{
@@ -6026,7 +6026,7 @@ spu_expand_vector_init (rtx target, rtx vals)
x = XVECEXP (constant_parts_rtx, 0, i);
if (!(CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE
- || GET_CODE (x) == CONST_FIXED))
+ || CONST_FIXED_P (x)))
XVECEXP (constant_parts_rtx, 0, i) = first_constant;
}
@@ -6046,7 +6046,7 @@ spu_expand_vector_init (rtx target, rtx vals)
x = XVECEXP (vals, 0, i);
if (!(CONST_INT_P (x)
|| GET_CODE (x) == CONST_DOUBLE
- || GET_CODE (x) == CONST_FIXED))
+ || CONST_FIXED_P (x)))
{
if (!register_operand (x, GET_MODE (x)))
x = force_reg (GET_MODE (x), x);
diff --git a/gcc/varasm.c b/gcc/varasm.c
index e886cdc71b8..0e833b9bc58 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -2813,7 +2813,7 @@ assemble_integer (rtx x, unsigned int size, unsigned int align, int force)
subsize = size > UNITS_PER_WORD? UNITS_PER_WORD : 1;
subalign = MIN (align, subsize * BITS_PER_UNIT);
- if (GET_CODE (x) == CONST_FIXED)
+ if (CONST_FIXED_P (x))
mclass = GET_MODE_CLASS (GET_MODE (x));
else
mclass = MODE_INT;
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 18/18] Use DEBUG_INSN_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh DEBUG_INSN_P
2019-08-06 3:11 ` Arvind Sankar
` (13 preceding siblings ...)
2019-08-06 3:13 ` [PATCH v2 16/18] Use SYMBOL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SYMBOL_REF Arvind Sankar
@ 2019-08-06 3:13 ` Arvind Sankar
2019-08-06 3:13 ` [PATCH v2 11/18] Use REG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh REG Arvind Sankar
` (2 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:13 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* reload1.c: Convert GET_CODE (..) == DEBUG_INSN to
DEBUG_INSN_P (..).
* reorg.c: Likewise.
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/gcc/reload1.c b/gcc/reload1.c
index 1a68d0567fc..d30badc0c4f 100644
--- a/gcc/reload1.c
+++ b/gcc/reload1.c
@@ -2850,7 +2850,7 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn,
|| known_eq (x_size, new_size))
)
return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
- else if (insn && GET_CODE (insn) == DEBUG_INSN)
+ else if (insn && DEBUG_INSN_P (insn))
return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
else
return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
diff --git a/gcc/reorg.c b/gcc/reorg.c
index 79684952595..4ec3d7efea6 100644
--- a/gcc/reorg.c
+++ b/gcc/reorg.c
@@ -1510,7 +1510,7 @@ redundant_insn (rtx insn, rtx_insn *target, const vec<rtx_insn *> &delay_list)
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (pat))
@@ -1609,7 +1609,7 @@ redundant_insn (rtx insn, rtx_insn *target, const vec<rtx_insn *> &delay_list)
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (pat))
@@ -2047,7 +2047,7 @@ fill_simple_delay_slots (int non_jumps_p)
continue;
/* And DEBUG_INSNs never go into delay slots. */
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* Check for resource conflict first, to avoid unnecessary
@@ -2174,7 +2174,7 @@ fill_simple_delay_slots (int non_jumps_p)
continue;
/* And DEBUG_INSNs do not go in delay slots. */
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* If this already has filled delay slots, get the insn needing
@@ -2442,7 +2442,7 @@ fill_slots_from_thread (rtx_jump_insn *insn, rtx condition,
|| GET_CODE (pat) == CLOBBER_HIGH)
continue;
- if (GET_CODE (trial) == DEBUG_INSN)
+ if (DEBUG_INSN_P (trial))
continue;
/* If TRIAL conflicts with the insns ahead of it, we lose. Also,
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 11/18] Use REG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh REG
2019-08-06 3:11 ` Arvind Sankar
` (14 preceding siblings ...)
2019-08-06 3:13 ` [PATCH v2 18/18] Use DEBUG_INSN_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh DEBUG_INSN_P Arvind Sankar
@ 2019-08-06 3:13 ` Arvind Sankar
2019-08-06 3:19 ` [PATCH v2 09/18] Add CONST_STRING_P rtx_code predicate Arvind Sankar
2019-08-06 6:56 ` [PATCH v2 17/18] Use SYMBOL_REF_P macro Arvind Sankar
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:13 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* config/aarch64/aarch64-simd.md: Convert GET_CODE (..) == REG
to REG_P (..).
* config/aarch64/predicates.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/arc.md: Likewise.
* config/arc/predicates.md: Likewise.
* config/arm/arm.c: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/bfin.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/c6x.md: Likewise.
* config/c6x/predicates.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cr16/cr16.h: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.md: Likewise.
* config/csky/predicates.md: Likewise.
* config/darwin.c: Likewise.
* config/epiphany/epiphany.c: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/fr30/fr30.c: Likewise.
* config/fr30/fr30.h: Likewise.
* config/fr30/fr30.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/frv.md: Likewise.
* config/frv/predicates.md: Likewise.
* config/ft32/constraints.md: Likewise.
* config/ft32/ft32.c: Likewise.
* config/ft32/ft32.md: Likewise.
* config/ft32/predicates.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/i386/i386-expand.c: Likewise.
* config/i386/i386-features.c: Likewise.
* config/i386/predicates.md: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/ia64.md: Likewise.
* config/ia64/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/iq2000/iq2000.md: Likewise.
* config/iq2000/predicates.md: Likewise.
* config/lm32/lm32.c: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32c/predicates.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/mcore/mcore.md: Likewise.
* config/mcore/predicates.md: Likewise.
* config/microblaze/constraints.md: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/microblaze/microblaze.h: Likewise.
* config/microblaze/microblaze.md: Likewise.
* config/microblaze/predicates.md: Likewise.
* config/mips/mips.c: Likewise.
* config/mn10300/predicates.md: Likewise.
* config/moxie/moxie.md: Likewise.
* config/moxie/predicates.md: Likewise.
* config/msp430/msp430.c: Likewise.
* config/nds32/nds32-fp-as-gp.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-multiple.md: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/nds32-relax-opt.c: Likewise.
* config/nds32/nds32.c: Likewise.
* config/nios2/predicates.md: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.md: Likewise.
* config/pdp11/pdp11.c: Likewise.
* config/pdp11/pdp11.md: Likewise.
* config/pru/predicates.md: Likewise.
* config/pru/pru.c: Likewise.
* config/pru/pru.md: Likewise.
* config/riscv/constraints.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rx/rx.c: Likewise.
* config/rx/rx.md: Likewise.
* config/s390/predicates.md: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/sparc/sparc.md: Likewise.
* config/spu/constraints.md: Likewise.
* config/spu/spu.c: Likewise.
* config/spu/spu.md: Likewise.
* config/v850/predicates.md: Likewise.
* config/v850/v850.c: Likewise.
* config/v850/v850.md: Likewise.
* config/visium/predicates.md: Likewise.
* config/visium/visium.c: Likewise.
* config/visium/visium.md: Likewise.
* config/xtensa/predicates.md: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.md: Likewise.
* cse.c: Likewise.
* dse.c: Likewise.
* ira-costs.c: Likewise.
* ira.c: Likewise.
* lra-constraints.c: Likewise.
* mode-switching.c: Likewise.
* read-rtl-function.c: Likewise.
* ree.c: Likewise.
* regrename.c: Likewise.
* valtrack.c: Likewise.
* var-tracking.c: Likewise.
108 files changed, 798 insertions(+), 798 deletions(-)
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md
index c6ccc99a2aa..0fe7ef60d33 100644
--- a/gcc/config/aarch64/aarch64-simd.md
+++ b/gcc/config/aarch64/aarch64-simd.md
@@ -5257,7 +5257,7 @@
{
if (can_create_pseudo_p ())
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
}
})
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index 9f2e139899f..ef01faed19c 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -471,14 +471,14 @@
(and (match_operand 0 "general_operand")
(match_test "!MEM_P (op)
|| GET_CODE (XEXP (op, 0)) == POST_INC
- || GET_CODE (XEXP (op, 0)) == REG")))
+ || REG_P (XEXP (op, 0))")))
;; Like nonimmediate_operand but allow only valid SIMD addressing modes.
(define_predicate "aarch64_simd_nonimmediate_operand"
(and (match_operand 0 "nonimmediate_operand")
(match_test "!MEM_P (op)
|| GET_CODE (XEXP (op, 0)) == POST_INC
- || GET_CODE (XEXP (op, 0)) == REG")))
+ || REG_P (XEXP (op, 0))")))
;; Predicates used by the various SIMD shift operations. These
;; fall in to 3 categories.
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index d9225440c3f..e417756a9f4 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -830,7 +830,7 @@ arc_sched_adjust_priority (rtx_insn *insn, int priority)
rtx set = single_set (insn);
if (set
&& GET_MODE (SET_SRC(set)) == DFmode
- && GET_CODE (SET_SRC(set)) == REG)
+ && REG_P (SET_SRC(set)))
{
/* Incrementing priority by 20 (empirically derived). */
return priority + 20;
@@ -2483,7 +2483,7 @@ arc_address_cost (rtx addr, machine_mode, addr_space_t, bool speed)
register rtx plus0 = XEXP (addr, 0);
register rtx plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) != REG
+ if (!REG_P (plus0)
&& (GET_CODE (plus0) != MULT
|| !CONST_INT_P (XEXP (plus0, 1))
|| (INTVAL (XEXP (plus0, 1)) != 2
@@ -4593,7 +4593,7 @@ arc_print_operand (FILE *file, rtx x, int code)
case 'R' :
/* Write second word of DImode or DFmode reference,
register or memory. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[REGNO (x)+1], file);
else if (GET_CODE (x) == MEM)
{
@@ -4683,7 +4683,7 @@ arc_print_operand (FILE *file, rtx x, int code)
break;
case 'H' :
case 'L' :
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* L = least significant word, H = most significant word. */
if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L'))
@@ -10953,17 +10953,17 @@ compact_memory_operand_p (rtx op, machine_mode mode,
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus0)))
- && ((GET_CODE (plus1) == REG)
+ && ((REG_P (plus1))
&& ((REGNO (plus1) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus1)))))
{
return !av2short;
}
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| (COMPACT_GP_REG_P (REGNO (plus0)) && !av2short)
|| (IN_RANGE (REGNO (plus0), 0, 31) && av2short))
@@ -11033,10 +11033,10 @@ compact_memory_operand_p (rtx op, machine_mode mode,
}
if ((GET_CODE (plus0) == MULT)
- && (GET_CODE (XEXP (plus0, 0)) == REG)
+ && (REG_P (XEXP (plus0, 0)))
&& ((REGNO (XEXP (plus0, 0)) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (XEXP (plus0, 0))))
- && (GET_CODE (plus1) == REG)
+ && (REG_P (plus1))
&& ((REGNO (plus1) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus1))))
return scaled;
diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index 63b65d533a4..96d6ffbcb11 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -4163,7 +4163,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
32 bit address of the callee into a register before performing the
branch and link - this exposes cse opportunities.
Also, in weird cases like compile/20010107-1.c, we may get a PLUS. */
- if (GET_CODE (callee) != REG
+ if (!REG_P (callee)
&& (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
}
@@ -4209,7 +4209,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
gcc_assert (MEM_P (operands[1]));
callee = XEXP (operands[1], 0);
/* See the comment in define_expand \"call\". */
- if (GET_CODE (callee) != REG
+ if (!REG_P (callee)
&& (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
}")
@@ -4711,7 +4711,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
if (operands[2] == NULL_RTX)
operands[2] = const0_rtx;
- if (GET_CODE (callee) != REG
+ if (!REG_P (callee)
&& (GET_CODE (callee) == PLUS || arc_is_longcall_p (callee)))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
}"
@@ -4730,7 +4730,7 @@ core_3, archs4x, archs4xd, archs4xd_slow"
if (operands[3] == NULL_RTX)
operands[3] = const0_rtx;
- if (GET_CODE (callee) != REG && arc_is_longcall_p (callee))
+ if (!REG_P (callee) && arc_is_longcall_p (callee))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
}"
)
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index 0c2926dc5e1..01bfc1b9547 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -162,7 +162,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG)
+ return (REG_P (op))
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| COMPACT_GP_REG_P (REGNO (op))) ;
}
@@ -174,7 +174,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG)
+ return (REG_P (op))
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30)
|| !TARGET_V2);
@@ -219,7 +219,7 @@
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| COMPACT_GP_REG_P (REGNO (plus0)))
&& (CONST_INT_P (plus1)))
@@ -241,7 +241,7 @@
}
}
- if ((GET_CODE (plus0) == REG)
+ if ((REG_P (plus0))
&& ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER)
|| SP_REG_P (REGNO (plus0)))
&& (CONST_INT_P (plus1)))
@@ -483,7 +483,7 @@
return FALSE;
}
- if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG)
+ if (mode == GET_MODE (op) && REG_P (op) && REGNO (op) == CC_REG)
return TRUE;
return FALSE;
@@ -622,7 +622,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS));
})
@@ -640,7 +640,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS));
})
@@ -654,10 +654,10 @@
if ((GET_CODE (op) == MEM)
&& (mode == V8HImode)
- && GET_CODE (XEXP (op,0)) == REG)
+ && REG_P (XEXP (op,0)))
return 1;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS));
})
@@ -672,7 +672,7 @@
if ((GET_MODE (op) != mode) && (mode != VOIDmode))
return 0;
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS));
})
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index a6b493f2973..c67b7c97dcc 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -31168,7 +31168,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
if (GET_CODE (addr) == CONST)
addr = XEXP (addr, 0);
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
*base = addr;
*offset = const0_rtx;
@@ -31176,7 +31176,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
}
if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1)))
{
*base = XEXP (addr, 0);
@@ -31207,12 +31207,12 @@ fusion_load_store (rtx_insn *insn, rtx *base, rtx *offset, bool *is_load)
src = SET_SRC (x);
dest = SET_DEST (x);
- if (GET_CODE (src) == REG && GET_CODE (dest) == MEM)
+ if (REG_P (src) && GET_CODE (dest) == MEM)
{
*is_load = false;
extract_base_offset_in_addr (dest, base, offset);
}
- else if (GET_CODE (src) == MEM && GET_CODE (dest) == REG)
+ else if (GET_CODE (src) == MEM && REG_P (dest))
{
*is_load = true;
extract_base_offset_in_addr (src, base, offset);
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index dea2ee7cde5..7f8424b5f5d 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -1224,7 +1224,7 @@ bfin_delegitimize_address (rtx orig_x)
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == UNSPEC
&& XINT (XEXP (x, 1), 1) == UNSPEC_MOVE_PIC
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
return XVECEXP (XEXP (x, 1), 0, 0);
@@ -1958,7 +1958,7 @@ expand_move (rtx *operands, machine_mode mode)
register */
else if ((reload_in_progress | reload_completed) == 0
&& GET_CODE (operands[0]) == MEM
- && GET_CODE (operands[1]) != REG)
+ && !REG_P (operands[1]))
operands[1] = force_reg (mode, operands[1]);
return false;
}
@@ -2874,8 +2874,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
}
*total = cost2;
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += set_src_cost (op0, mode, speed);
#if 0 /* We'd like to do this for accuracy, but it biases the loop optimizer
towards creating too many induction variables. */
@@ -2889,8 +2889,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
if (!CONST_INT_P (op1)
|| !satisfies_constraint_Ks7 (op1))
*total += rtx_cost (op1, mode, PLUS, 1, speed);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, PLUS, 0, speed);
}
return true;
@@ -2912,8 +2912,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
op0 = XEXP (x, 0);
op1 = XEXP (x, 1);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
return true;
@@ -2937,8 +2937,8 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
}
}
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, code, 0, speed);
if (mode == DImode)
@@ -2996,11 +2996,11 @@ bfin_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno,
else
*total = COSTS_N_INSNS (3);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
- if (GET_CODE (op1) != REG
- && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG))
+ if (!REG_P (op1)
+ && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
}
return true;
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 517ee4baa39..2c70db8b39b 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -505,7 +505,7 @@
(define_insn_and_split "movdi_insn"
[(set (match_operand:DI 0 "nonimmediate_operand" "=x,mx,r")
(match_operand:DI 1 "general_operand" "iFx,r,mx"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"#"
"reload_completed"
[(set (match_dup 2) (match_dup 3))
@@ -607,7 +607,7 @@
(define_insn "*movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=da,x,da,y,da,x,x,x,da,mr")
(match_operand:SI 1 "general_operand" "da,x,y,da,xKs7,xKsh,xKuh,ix,mr,da"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%0 = %1;
%0 = %1;
@@ -647,7 +647,7 @@
[(set (match_operand:V2HI 0 "nonimmediate_operand" "=da,da,d,dm")
(match_operand:V2HI 1 "general_operand" "i,di,md,d"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
#
%0 = %1;
@@ -669,7 +669,7 @@
(define_insn "*movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=x,da,x,d,mr")
(match_operand:HI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
{
static const char *templates[] = {
"%0 = %1;",
@@ -693,7 +693,7 @@
(define_insn "*movqi_insn"
[(set (match_operand:QI 0 "nonimmediate_operand" "=x,da,x,d,mr")
(match_operand:QI 1 "general_operand" "x,xKs7,xKsh,mr,d"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%0 = %1;
%0 = %1 (X);
@@ -706,7 +706,7 @@
(define_insn "*movsf_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=x,x,da,mr")
(match_operand:SF 1 "general_operand" "x,Fx,mr,da"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%0 = %1;
#
@@ -717,7 +717,7 @@
(define_insn_and_split "movdf_insn"
[(set (match_operand:DF 0 "nonimmediate_operand" "=x,mx,r")
(match_operand:DF 1 "general_operand" "iFx,r,mx"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"#"
"reload_completed"
[(set (match_dup 2) (match_dup 3))
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index 62fab8376be..fe78ed0dfce 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1375,7 +1375,7 @@ expand_move (rtx *operands, machine_mode mode)
rtx op = operands[1];
if ((reload_in_progress | reload_completed) == 0
- && GET_CODE (dest) == MEM && GET_CODE (op) != REG)
+ && GET_CODE (dest) == MEM && !REG_P (op))
operands[1] = force_reg (mode, op);
else if (mode == SImode && symbolic_operand (op, SImode))
{
@@ -2219,7 +2219,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
case 'p':
case 'P':
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
v = REGNO (x);
if (code == 'P')
v++;
@@ -6174,11 +6174,11 @@ c6x_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno, int *total,
else if (mode == HImode)
*total = COSTS_N_INSNS (speed ? 2 : 1);
- if (GET_CODE (op0) != REG
- && (GET_CODE (op0) != SUBREG || GET_CODE (SUBREG_REG (op0)) != REG))
+ if (!REG_P (op0)
+ && (GET_CODE (op0) != SUBREG || !REG_P (SUBREG_REG (op0))))
*total += rtx_cost (op0, mode, MULT, 0, speed);
- if (op1 && GET_CODE (op1) != REG
- && (GET_CODE (op1) != SUBREG || GET_CODE (SUBREG_REG (op1)) != REG))
+ if (op1 && !REG_P (op1)
+ && (GET_CODE (op1) != SUBREG || !REG_P (SUBREG_REG (op1))))
*total += rtx_cost (op1, mode, MULT, 1, speed);
return true;
diff --git a/gcc/config/c6x/c6x.md b/gcc/config/c6x/c6x.md
index 3707e80697c..2b35d6717cb 100644
--- a/gcc/config/c6x/c6x.md
+++ b/gcc/config/c6x/c6x.md
@@ -602,7 +602,7 @@
"=a,b, a, b, ab, ab,a,?a, b,?b, Q, R, R, Q")
(match_operand:QIHIM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,Q, R, R, Q, a,?a, b,?b"))]
- "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG"
+ "GET_CODE (operands[0]) != MEM || REG_P (operands[1])"
"@
%|%.\\tmv\\t%$\\t%1, %0
%|%.\\tmv\\t%$\\t%1, %0
@@ -631,7 +631,7 @@
"=a,b, a, b, ab, ab,a,b,ab,a,?a, b,?b, Q, R, R, Q")
(match_operand:SISFVM 1 "general_operand"
"a,b,?b,?a,Is5,IsB,S0,S0,Si,Q, R, R, Q, a,?a, b,?b"))]
- "(GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) == REG
+ "(GET_CODE (operands[0]) != MEM || REG_P (operands[1])
|| (GET_CODE (operands[1]) == SUBREG && REG_P (SUBREG_REG (operands[1]))))"
"@
%|%.\\tmv\\t%$\\t%1, %0
diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md
index ea360f95543..b933de8b9dc 100644
--- a/gcc/config/c6x/predicates.md
+++ b/gcc/config/c6x/predicates.md
@@ -69,7 +69,7 @@
(define_predicate "c6x_call_operand"
(ior (match_code "symbol_ref,reg")
(and (match_code "subreg")
- (match_test "GET_CODE (XEXP (op, 0)) == REG")))
+ (match_test "REG_P (XEXP (op, 0))")))
{
/* The linker transforms jumps to undefined weak symbols in a way that
is incompatible with our code generation. */
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 9c9c4779eb2..4cdb58b06bb 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -1483,7 +1483,7 @@ cr16_print_operand (FILE * file, rtx x, int code)
return;
case 'p':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* For Push instructions, we should not print register pairs. */
fprintf (file, "%s", reg_names[REGNO (x)]);
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index 91e96ba67b3..227b536d1c9 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -341,9 +341,9 @@ enum reg_class
/* This check is for sbit/cbit instruction. */
#define OK_FOR_Z(OP) \
((GET_CODE (OP) == MEM && CONST_INT_P (XEXP (OP, 0))) \
- || (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == REG) \
+ || (GET_CODE (OP) == MEM && REG_P (XEXP (OP, 0))) \
|| (GET_CODE (OP) == MEM && GET_CODE (XEXP (OP, 0)) == PLUS \
- && GET_CODE (XEXP ((XEXP (OP, 0)), 0)) == REG \
+ && REG_P (XEXP ((XEXP (OP, 0)), 0)) \
&& CONST_INT_P (XEXP ((XEXP (OP, 0)), 1))))
/* Stack layout and calling conventions. */
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index 85850c8be1f..6d2192a5096 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -2321,11 +2321,11 @@ csky_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
x = SUBREG_REG (x);
}
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
regno = REGNO (x) + off;
}
}
- else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ else if (REG_P (x) || GET_CODE (x) == SUBREG)
regno = true_regnum (x);
/* We always require a general register when copying anything to
@@ -4260,13 +4260,13 @@ csky_output_movedouble (rtx operands[],
&& GET_CODE (XEXP (memexp, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (memexp, 0), 0)) == LABEL_REF))
return "lrw\t%0, [%1]\n\tlrw\t%R0, [%R1]";
- else if (GET_CODE (memexp) == REG)
+ else if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -4318,7 +4318,7 @@ csky_output_movedouble (rtx operands[],
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
+ else if (GET_CODE (dst) == MEM && REG_P (src))
{
rtx memexp = XEXP (dst, 0);
int srcreg = REGNO (src);
@@ -4327,13 +4327,13 @@ csky_output_movedouble (rtx operands[],
decompose_csky_address (XEXP (dst, 0), &op0);
- if (GET_CODE (memexp) == REG)
+ if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -4395,13 +4395,13 @@ csky_output_ck801_movedouble (rtx operands[],
&& GET_CODE (XEXP (memexp, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (memexp, 0), 0)) == LABEL_REF))
return "lrw\t%0, [%1]\n\tlrw\t%R0, [%R1]";
- else if (GET_CODE (memexp) == REG)
+ else if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -4440,7 +4440,7 @@ csky_output_ck801_movedouble (rtx operands[],
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
+ else if (GET_CODE (dst) == MEM && REG_P (src))
{
rtx memexp = XEXP (dst, 0);
int srcreg = REGNO (src);
@@ -4449,13 +4449,13 @@ csky_output_ck801_movedouble (rtx operands[],
decompose_csky_address (XEXP (dst, 0), &op0);
- if (GET_CODE (memexp) == REG)
+ if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -6530,7 +6530,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
if (REG_P (base))
reg = base;
if (GET_CODE (base) == PLUS
- && GET_CODE (XEXP (base, 0)) == REG)
+ && REG_P (XEXP (base, 0)))
reg = XEXP (base, 0);
if ((reg != NULL_RTX) && reg_set_p (reg, PATTERN (dep)))
return 2;
@@ -6561,7 +6561,7 @@ csky_sched_adjust_cost (rtx_insn *insn,
if (REG_P (base))
reg = base;
if (GET_CODE (base) == PLUS
- && GET_CODE (XEXP (base, 0)) == REG)
+ && REG_P (XEXP (base, 0)))
reg = XEXP (base, 0);
if ((reg != NULL_RTX) && reg_set_p (reg, PATTERN (dep))
&& get_attr_type (dep) != TYPE_LOAD)
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 7a8b382c1d8..2dd1452eb3b 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -909,7 +909,7 @@
(clobber (reg:CC CSKY_CC_REGNUM))])]
""
"
- if (CSKY_ISA_FEATURE (E1) && (GET_CODE (operands[2]) != REG))
+ if (CSKY_ISA_FEATURE (E1) && (!REG_P (operands[2])))
operands[2] = force_reg (DImode, operands[2]);
"
)
@@ -2060,7 +2060,7 @@
|| GET_CODE (operands[1]) != MEM
|| !REG_P (XEXP (operands[1], 0))
|| XEXP (operands[1], 0) != stack_pointer_rtx
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| (REGNO (XEXP (operands[1], 0)) > REGNO (operands[0])
&& (REGNO (XEXP (operands[1], 0))
< REGNO (operands[0]) + INTVAL (operands[2]))))
@@ -2098,7 +2098,7 @@
|| GET_CODE (operands[0]) != MEM
|| !REG_P (XEXP (operands[0], 0))
|| XEXP (operands[0], 0) != stack_pointer_rtx
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| (REGNO (XEXP (operands[0], 0)) >= REGNO (operands[1])
&& (REGNO (XEXP (operands[0], 0))
< REGNO (operands[1]) + INTVAL (operands[2]))))
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index 0c67e4e9cbf..93725f15209 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -31,9 +31,9 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) != REG
+ || !REG_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0))
|| XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx)
return 0;
@@ -45,7 +45,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -73,9 +73,9 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0)) != REG
+ || !REG_P (XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0))
|| XEXP (SET_DEST (XVECEXP (op, 0, 0)), 0) != stack_pointer_rtx
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return 0;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -86,7 +86,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
|| GET_CODE (SET_DEST (elt)) != MEM
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 8ccbad46310..9089c4673dc 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -743,7 +743,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
compiler's ignorance on how to move the PIC base register to
other registers. (The reload phase sometimes introduces such
insns.) */
- if (GET_CODE (XEXP (orig, 0)) == REG
+ if (REG_P (XEXP (orig, 0))
&& REGNO (XEXP (orig, 0)) == PIC_OFFSET_TABLE_REGNUM
/* Prevent the same register from being erroneously used
as both the base and index registers. */
@@ -829,7 +829,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
orig = machopic_indirect_data_reference (orig, reg);
if (GET_CODE (orig) == PLUS
- && GET_CODE (XEXP (orig, 0)) == REG)
+ && REG_P (XEXP (orig, 0)))
{
if (reg == 0)
return force_reg (mode, orig);
@@ -917,7 +917,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#endif /* HAVE_lo_sum */
{
rtx pic = pic_offset_table_rtx;
- if (GET_CODE (pic) != REG)
+ if (!REG_P (pic))
{
emit_move_insn (reg, pic);
pic = reg;
@@ -988,7 +988,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
else
{
rtx pic = pic_offset_table_rtx;
- if (GET_CODE (pic) != REG)
+ if (!REG_P (pic))
{
emit_move_insn (reg, pic);
pic = reg;
@@ -1005,7 +1005,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
}
}
- if (GET_CODE (pic_ref) != REG)
+ if (!REG_P (pic_ref))
{
if (reg != 0)
{
@@ -1027,7 +1027,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
|| GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
|| GET_CODE (XEXP (orig, 0)) == LABEL_REF)
&& XEXP (orig, 0) != pic_offset_table_rtx
- && GET_CODE (XEXP (orig, 1)) != REG)
+ && !REG_P (XEXP (orig, 1)))
{
rtx base;
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index 11f188f13e0..ea1c137a881 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -1417,7 +1417,7 @@ epiphany_print_operand_address (FILE *file, machine_mode /*mode*/, rtx addr)
offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0);
else
base = XEXP (addr, 0), index = XEXP (addr, 1);
- gcc_assert (GET_CODE (base) == REG);
+ gcc_assert (REG_P (base));
fputs (reg_names[REGNO (base)], file);
if (index == 0)
{
@@ -2674,7 +2674,7 @@ epiphany_expand_set_fp_mode (rtx *operands)
emit_insn (gen_gid ());
emit_move_insn (scratch, ctrl);
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* FP_MODE_CALLER */
emit_insn (gen_xorsi3 (scratch, scratch, src));
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index dc039ffbf6f..6804a75a290 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -96,7 +96,7 @@
(define_predicate "add_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || GET_CODE (op) == SUBREG)
return add_reg_operand (op, mode);
return satisfies_constraint_L (op) || satisfies_constraint_CnL (op);
})
@@ -105,7 +105,7 @@
(define_predicate "arith_operand"
(match_code "reg,subreg,const_int,symbol_ref,label_ref,const")
{
- if (GET_CODE (op) == REG || GET_CODE (op) == SUBREG)
+ if (REG_P (op) || GET_CODE (op) == SUBREG)
return register_operand (op, mode);
return satisfies_constraint_L (op);
})
diff --git a/gcc/config/fr30/fr30.c b/gcc/config/fr30/fr30.c
index e31d4f1266d..59aee75bbf4 100644
--- a/gcc/config/fr30/fr30.c
+++ b/gcc/config/fr30/fr30.c
@@ -530,7 +530,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
case 'p':
/* Compute the register name of the second register in a hi/lo
register pair. */
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
output_operand_lossage ("fr30_print_operand: unrecognized %%p code");
else
fprintf (file, "r%d", REGNO (x) + 1);
@@ -642,7 +642,7 @@ fr30_print_operand (FILE *file, rtx x, int code)
break;
case PLUS:
- if (GET_CODE (XEXP (x0, 0)) != REG
+ if (!REG_P (XEXP (x0, 0))
|| REGNO (XEXP (x0, 0)) < FRAME_POINTER_REGNUM
|| REGNO (XEXP (x0, 0)) > STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (x0, 1)))
@@ -848,7 +848,7 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending)
while (num_operands --)
{
- if (GET_CODE (operands [num_operands]) != REG)
+ if (!REG_P (operands [num_operands]))
return 0;
if (REGNO (operands [num_operands]) < prev_regno)
@@ -863,7 +863,7 @@ fr30_check_multiple_regs (rtx *operands, int num_operands, int descending)
while (num_operands --)
{
- if (GET_CODE (operands [num_operands]) != REG)
+ if (!REG_P (operands [num_operands]))
return 0;
if (REGNO (operands [num_operands]) > prev_regno)
@@ -930,7 +930,7 @@ fr30_move_double (rtx * operands)
rtx dest1 = operand_subword (dest, 1, TRUE, mode);
rtx new_mem;
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
/* Copy the address before clobbering it. See PR 34174. */
emit_insn (gen_rtx_SET (dest1, addr));
@@ -960,7 +960,7 @@ fr30_move_double (rtx * operands)
rtx src0;
rtx src1;
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
src0 = operand_subword (src, 0, TRUE, mode);
src1 = operand_subword (src, 1, TRUE, mode);
diff --git a/gcc/config/fr30/fr30.h b/gcc/config/fr30/fr30.h
index 85cd49a2ed1..74451237c94 100644
--- a/gcc/config/fr30/fr30.h
+++ b/gcc/config/fr30/fr30.h
@@ -552,18 +552,18 @@ enum reg_class
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
do \
{ \
- if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
&& CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 << 6) - 4)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
&& CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), -(1 << 9), (1 << 9) - 4)) \
@@ -574,18 +574,18 @@ enum reg_class
#define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \
do \
{ \
- if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
+ if (REG_P (X) && REG_OK_FOR_BASE_P (X)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& REGNO (XEXP (X, 0)) == STACK_POINTER_REGNUM \
&& CONST_INT_P (XEXP (X, 1)) \
&& IN_RANGE (INTVAL (XEXP (X, 1)), 0, (1 << 6) - 4)) \
goto LABEL; \
if (GET_CODE (X) == PLUS \
&& ((MODE) == SImode || (MODE) == SFmode) \
- && GET_CODE (XEXP (X, 0)) == REG \
+ && REG_P (XEXP (X, 0)) \
&& (REGNO (XEXP (X, 0)) == FRAME_POINTER_REGNUM \
|| REGNO (XEXP (X, 0)) == ARG_POINTER_REGNUM) \
&& CONST_INT_P (XEXP (X, 1)) \
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md
index 5a369cfa249..b8670bbdb14 100644
--- a/gcc/config/fr30/fr30.md
+++ b/gcc/config/fr30/fr30.md
@@ -653,7 +653,7 @@
(match_operand:SI 2 "nonmemory_operand" "")))]
""
"{
- if ( GET_CODE (operands[2]) == REG
+ if ( REG_P (operands[2])
|| GET_CODE (operands[2]) == SUBREG)
emit_insn (gen_addsi_regs (operands[0], operands[1], operands[2]));
else if (!CONST_INT_P (operands[2]))
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 20873856906..f8b9b781e28 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -36,7 +36,7 @@
(match_code "reg")
{
return
- (GET_CODE (op) == REG
+ (REG_P (op)
&& REGNO (op) <= 15
&& REGNO (op) >= 8);
})
@@ -47,7 +47,7 @@
(match_code "reg")
{
return
- (GET_CODE (op) == REG
+ (REG_P (op)
&& REGNO (op) <= 7);
})
@@ -58,7 +58,7 @@
{
return (GET_CODE (op) == MEM
&& (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
- || GET_CODE (XEXP (op, 0)) == REG));
+ || REG_P (XEXP (op, 0))));
})
;; Returns TRUE if OP is a valid operand of a DImode operation.
@@ -116,7 +116,7 @@
(match_code "reg,const_int")
{
return
- (GET_CODE (op) == REG
+ (REG_P (op)
|| (CONST_INT_P (op)
&& INTVAL (op) >= -16
&& INTVAL (op) <= 15));
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index c3d9408f21b..72f867d3306 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -1448,7 +1448,7 @@ frv_function_prologue (FILE *file)
&& GET_CODE (XVECEXP (pattern, 0, 1)) == USE)
{
rtx address = XEXP (XVECEXP (pattern, 0, 1), 0);
- if (GET_CODE (address) == REG && REGNO (address) == LR_REGNO)
+ if (REG_P (address) && REGNO (address) == LR_REGNO)
SET_REGNO (address, GPR_FIRST + 3);
}
}
@@ -1611,8 +1611,8 @@ frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
/* We cannot use reg+reg addressing for DImode access. */
if (mode == DImode
&& GET_CODE (XEXP (mem, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
+ && REG_P (XEXP (XEXP (mem, 0), 0))
+ && REG_P (XEXP (XEXP (mem, 0), 1)))
{
rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
@@ -1645,8 +1645,8 @@ frv_frame_access (frv_frame_accessor_t *accessor, rtx reg, int stack_offset)
/* Also we cannot use reg+reg addressing. */
if (GET_CODE (XEXP (mem, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (mem, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (mem, 0), 1)) == REG)
+ && REG_P (XEXP (XEXP (mem, 0), 0))
+ && REG_P (XEXP (XEXP (mem, 0), 1)))
{
rtx temp = gen_rtx_REG (SImode, TEMP_REGNO);
emit_move_insn (temp,
@@ -2564,7 +2564,7 @@ frv_print_operand_memory_reference (FILE * stream, rtx x, int addr_offset)
fputs ("@(", stream);
if (!x0)
fputs (reg_names[GPR_R0], stream);
- else if (GET_CODE (x0) == REG || GET_CODE (x0) == SUBREG)
+ else if (REG_P (x0) || GET_CODE (x0) == SUBREG)
frv_print_operand_memory_reference_reg (stream, x0);
else
fatal_insn ("bad insn to frv_print_operand_memory_reference:", x);
@@ -2896,7 +2896,7 @@ frv_print_operand (FILE * file, rtx x, int code)
case 'L':
/* Print the lower register of a double word register pair */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[ REGNO (x)+1 ], file);
else
fatal_insn ("bad insn to frv_print_operand, 'L' modifier:", x);
@@ -2967,7 +2967,7 @@ frv_print_operand (FILE * file, rtx x, int code)
if (CONST_INT_P (x) && INTVAL (x) == 0)
fputs (reg_names[GPR_R0], file);
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
fputs (reg_names [REGNO (x)], file);
else
@@ -2985,7 +2985,7 @@ frv_print_operand (FILE * file, rtx x, int code)
/* Fall through. */
case '\0':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names [REGNO (x)], file);
else if (CONST_INT_P (x)
@@ -3325,7 +3325,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
case SUBREG:
x = SUBREG_REG (x);
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
break;
/* Fall through. */
@@ -3337,11 +3337,11 @@ frv_legitimate_address_p_1 (machine_mode mode,
case PRE_MODIFY:
x0 = XEXP (x, 0);
x1 = XEXP (x, 1);
- if (GET_CODE (x0) != REG
+ if (!REG_P (x0)
|| ! frv_regno_ok_for_base_p (REGNO (x0), strict_p)
|| GET_CODE (x1) != PLUS
|| ! rtx_equal_p (x0, XEXP (x1, 0))
- || GET_CODE (XEXP (x1, 1)) != REG
+ || !REG_P (XEXP (x1, 1))
|| ! frv_regno_ok_for_base_p (REGNO (XEXP (x1, 1)), strict_p))
break;
@@ -3371,7 +3371,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
if (GET_CODE (x0) == SUBREG)
x0 = SUBREG_REG (x0);
- if (GET_CODE (x0) != REG)
+ if (!REG_P (x0))
break;
regno0 = REGNO (x0);
@@ -3385,7 +3385,7 @@ frv_legitimate_address_p_1 (machine_mode mode,
case SUBREG:
x1 = SUBREG_REG (x1);
- if (GET_CODE (x1) != REG)
+ if (!REG_P (x1))
break;
/* Fall through. */
@@ -3969,7 +3969,7 @@ frv_emit_movsi (rtx dest, rtx src)
/* Virtual registers will almost always be replaced by an
add instruction, so expose this to CSE by copying to
an intermediate register. */
- || (GET_CODE (src) == REG
+ || (REG_P (src)
&& IN_RANGE (REGNO (src),
FIRST_VIRTUAL_REGISTER,
LAST_VIRTUAL_POINTER_REGISTER))))
@@ -4210,14 +4210,14 @@ output_move_single (rtx operands[], rtx insn)
rtx dest = operands[0];
rtx src = operands[1];
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dest_regno = REGNO (dest);
machine_mode mode = GET_MODE (dest);
if (GPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* gpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4289,7 +4289,7 @@ output_move_single (rtx operands[], rtx insn)
else if (FPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* fpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4332,7 +4332,7 @@ output_move_single (rtx operands[], rtx insn)
else if (SPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* spr <- some sort of register */
int src_regno = REGNO (src);
@@ -4347,7 +4347,7 @@ output_move_single (rtx operands[], rtx insn)
else if (GET_CODE (dest) == MEM)
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int src_regno = REGNO (src);
machine_mode mode = GET_MODE (dest);
@@ -4425,13 +4425,13 @@ output_move_double (rtx operands[], rtx insn)
rtx src = operands[1];
machine_mode mode = GET_MODE (dest);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dest_regno = REGNO (dest);
if (GPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* gpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4465,7 +4465,7 @@ output_move_double (rtx operands[], rtx insn)
else if (FPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* fpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4506,7 +4506,7 @@ output_move_double (rtx operands[], rtx insn)
else if (GET_CODE (dest) == MEM)
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int src_regno = REGNO (src);
@@ -4555,14 +4555,14 @@ output_condmove_single (rtx operands[], rtx insn)
rtx dest = operands[2];
rtx src = operands[3];
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dest_regno = REGNO (dest);
machine_mode mode = GET_MODE (dest);
if (GPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* gpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4600,7 +4600,7 @@ output_condmove_single (rtx operands[], rtx insn)
else if (FPR_P (dest_regno))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
/* fpr <- some sort of register */
int src_regno = REGNO (src);
@@ -4631,7 +4631,7 @@ output_condmove_single (rtx operands[], rtx insn)
else if (GET_CODE (dest) == MEM)
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int src_regno = REGNO (src);
machine_mode mode = GET_MODE (dest);
@@ -4695,7 +4695,7 @@ frv_emit_comparison (enum rtx_code test, rtx op0, rtx op1)
rtx cc_reg;
/* Floating point doesn't have comparison against a constant. */
- if (GET_MODE (op0) == CC_FPmode && GET_CODE (op1) != REG)
+ if (GET_MODE (op0) == CC_FPmode && !REG_P (op1))
op1 = force_reg (GET_MODE (op0), op1);
/* Possibly disable using anything but a fixed register in order to work
@@ -5362,7 +5362,7 @@ frv_ifcvt_modify_tests (ce_if_block *ce_info, rtx *p_true, rtx *p_false)
rtx dest = SET_DEST (set);
rtx src = SET_SRC (set);
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int regno = REGNO (dest);
enum rtx_code src_code = GET_CODE (src);
@@ -5590,7 +5590,7 @@ frv_ifcvt_modify_multiple_tests (ce_if_block *ce_info,
if (!TARGET_MULTI_CE)
goto fail;
- if (GET_CODE (cr) != REG)
+ if (!REG_P (cr))
goto fail;
if (mode == CCmode || mode == CC_UNSmode || mode == CC_NZmode)
@@ -5698,7 +5698,7 @@ frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
/* First search all registers currently loaded to see if we have an
applicable constant. */
if (CONSTANT_P (value)
- || (GET_CODE (value) == REG && REGNO (value) == LR_REGNO))
+ || (REG_P (value) && REGNO (value) == LR_REGNO))
{
for (i = 0; i < num_alloc; i++)
{
@@ -5735,7 +5735,7 @@ frv_ifcvt_load_value (rtx value, rtx insn ATTRIBUTE_UNUSED)
fprintf (dump_file, "Register %s will hold %ld\n",
reg_names[ REGNO (reg)], (long)INTVAL (value));
- else if (GET_CODE (value) == REG && REGNO (value) == LR_REGNO)
+ else if (REG_P (value) && REGNO (value) == LR_REGNO)
fprintf (dump_file, "Register %s will hold LR\n",
reg_names[ REGNO (reg)]);
@@ -5766,7 +5766,7 @@ frv_ifcvt_rewrite_mem (rtx mem, machine_mode mode, rtx insn)
rtx addr_op0 = XEXP (addr, 0);
rtx addr_op1 = XEXP (addr, 1);
- if (GET_CODE (addr_op0) == REG && CONSTANT_P (addr_op1))
+ if (REG_P (addr_op0) && CONSTANT_P (addr_op1))
{
rtx reg = frv_ifcvt_load_value (addr_op1, insn);
if (!reg)
@@ -5871,7 +5871,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
op1 = XEXP (test, 1);
test_reg = XEXP (op1, 0);
- if (GET_CODE (test_reg) != REG)
+ if (!REG_P (test_reg))
goto fail;
/* Is this the first nested if block in this sequence? If so, generate
@@ -6060,7 +6060,7 @@ frv_ifcvt_modify_insn (ce_if_block *ce_info,
/* Remap a nested compare instruction to use the paired CC/CR reg. */
else if (ce_info->pass > 1
- && GET_CODE (dest) == REG
+ && REG_P (dest)
&& CC_P (REGNO (dest))
&& REGNO (dest) != REGNO (frv_ifcvt.nested_cc_reg)
&& TEST_HARD_REG_BIT (frv_ifcvt.nested_cc_ok_rewrite,
@@ -6310,7 +6310,7 @@ frv_secondary_reload_class (enum reg_class rclass,
case QUAD_REGS:
case GPR_REGS:
ret = NO_REGS;
- if (x && GET_CODE (x) == REG)
+ if (x && REG_P (x))
{
int regno = REGNO (x);
@@ -7027,7 +7027,7 @@ static int
frv_cond_flags (rtx cond)
{
gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
- && GET_CODE (XEXP (cond, 0)) == REG
+ && REG_P (XEXP (cond, 0))
&& CR_P (REGNO (XEXP (cond, 0)))
&& XEXP (cond, 1) == const0_rtx);
return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
@@ -7073,7 +7073,7 @@ frv_registers_conflict_p_1 (rtx pat, regstate_t cond)
FOR_EACH_SUBRTX_VAR (iter, array, pat, NONCONST)
{
rtx x = *iter;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
unsigned int regno;
FOR_EACH_REGNO (regno, x)
@@ -7137,7 +7137,7 @@ frv_registers_update_1 (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data)
{
unsigned int regno;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
FOR_EACH_REGNO (regno, x)
frv_packet.regstate[regno] |= *(regstate_t *) data;
@@ -7813,7 +7813,7 @@ frv_optimize_membar_local (basic_block bb, struct frv_io *next_io,
&& next_io->var_address != 0
&& next_membar != 0
&& GET_CODE (set) == SET
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& TEST_HARD_REG_BIT (used_regs, REGNO (SET_DEST (set))))
{
rtx src;
diff --git a/gcc/config/frv/frv.md b/gcc/config/frv/frv.md
index b33c272075a..d365476ef0a 100644
--- a/gcc/config/frv/frv.md
+++ b/gcc/config/frv/frv.md
@@ -6838,7 +6838,7 @@
"TARGET_MEDIA"
"
{
- if (GET_CODE (operands[0]) != REG || !ACC_P (REGNO (operands[0])))
+ if (!REG_P (operands[0]) || !ACC_P (REGNO (operands[0])))
FAIL;
operands[1] = frv_matching_accg_for_acc (operands[0]);
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index 02e5ce97789..c3724de35e6 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -27,13 +27,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_AP_OR_PSEUDO_P (REGNO (op));
@@ -53,7 +53,7 @@
rtx tmp = op;
if (GET_CODE (tmp) == SUBREG)
tmp = SUBREG_REG (tmp);
- if (GET_CODE (tmp) == REG
+ if (REG_P (tmp)
&& REGNO (tmp) >= FIRST_PSEUDO_REGISTER)
op = reg_equiv_memory_loc (REGNO (tmp));
}
@@ -70,7 +70,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -88,13 +88,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -120,13 +120,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -148,13 +148,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -177,13 +177,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -202,13 +202,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return GPR_OR_PSEUDO_P (REGNO (op));
@@ -422,7 +422,7 @@
(define_predicate "lr_operand"
(match_code "reg")
{
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -562,7 +562,7 @@
if (!TARGET_FDPIC)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
if (GET_MODE (op) != mode && mode != VOIDmode)
@@ -581,7 +581,7 @@
{
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
if (REGNO (op) != FDPIC_FPTR_REGNO && REGNO (op) < FIRST_PSEUDO_REGISTER)
return FALSE;
@@ -641,7 +641,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -658,7 +658,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -675,7 +675,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -695,7 +695,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -712,7 +712,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -729,7 +729,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode)
return FALSE;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -749,13 +749,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return FPR_OR_PSEUDO_P (REGNO (op));
@@ -773,13 +773,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -807,13 +807,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -842,13 +842,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -873,13 +873,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -905,13 +905,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -936,13 +936,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -967,13 +967,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
regno = REGNO (op);
@@ -1011,7 +1011,7 @@
return FALSE;
addr = XEXP (op, 0);
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
addr_reg = addr;
else if (GET_CODE (addr) == PLUS)
@@ -1019,7 +1019,7 @@
rtx addr0 = XEXP (addr, 0);
rtx addr1 = XEXP (addr, 1);
- if (GET_CODE (addr0) != REG)
+ if (!REG_P (addr0))
return FALSE;
if (got12_operand (addr1, VOIDmode))
@@ -1237,7 +1237,7 @@
return FALSE;
op0 = XEXP (op, 0);
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
return FALSE;
regno = REGNO (op0);
@@ -1449,13 +1449,13 @@
if (GET_CODE (op) == SUBREG)
{
- if (GET_CODE (SUBREG_REG (op)) != REG)
+ if (!REG_P (SUBREG_REG (op)))
return register_operand (op, mode);
op = SUBREG_REG (op);
}
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return FALSE;
return FPR_OR_PSEUDO_P (REGNO (op));
diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md
index 6f2d49b3d4d..09a687e309a 100644
--- a/gcc/config/ft32/constraints.md
+++ b/gcc/config/ft32/constraints.md
@@ -65,7 +65,7 @@
(and (match_code "mem")
(match_test "ft32_is_mem_pm(op) && (
((GET_CODE (XEXP (op, 0)) == PLUS)) ||
- (GET_CODE (XEXP (op, 0)) == REG))"
+ (REG_P (XEXP (op, 0))))"
)))
(define_constraint "O"
diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c
index 64b3172834f..d0f2ce262db 100644
--- a/gcc/config/ft32/ft32.c
+++ b/gcc/config/ft32/ft32.c
@@ -177,7 +177,7 @@ ft32_print_operand (FILE * file, rtx x, int code)
break;
case 'h':
- if (GET_CODE (operand) != REG)
+ if (!REG_P (operand))
internal_error ("%<h%> applied to non-register operand");
fprintf (file, "%s", reg_names[REGNO (operand) + 1]);
return;
@@ -878,7 +878,7 @@ ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
rtx op1, op2;
op1 = XEXP (x, 0);
op2 = XEXP (x, 1);
- if (GET_CODE (op1) == REG
+ if (REG_P (op1)
&& CONST_INT_P (op2)
&& (-max_offset <= INTVAL (op2))
&& (INTVAL (op2) < max_offset)
diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md
index 9e31f2ca7cb..174ef8d0bf7 100644
--- a/gcc/config/ft32/ft32.md
+++ b/gcc/config/ft32/ft32.md
@@ -747,7 +747,7 @@
""
"
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = force_reg (SImode, operands[0]);
if (operands[1] != const0_rtx)
diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md
index 89cf0b587b9..a77301f0b37 100644
--- a/gcc/config/ft32/predicates.md
+++ b/gcc/config/ft32/predicates.md
@@ -38,7 +38,7 @@
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return 1;
@@ -50,7 +50,7 @@
{
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return 1;
if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == SYMBOL_REF)
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index b4c5f228373..0006583b11e 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -1247,7 +1247,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
return gcn_address_register_p (x, SImode, strict);
else if (AS_FLAT_P (as) || AS_FLAT_SCRATCH_P (as))
{
- if (TARGET_GCN3 || GET_CODE (x) == REG)
+ if (TARGET_GCN3 || REG_P (x))
return ((GET_MODE_CLASS (mode) == MODE_VECTOR_INT
|| GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT)
? gcn_address_register_p (x, DImode, strict)
@@ -1281,7 +1281,7 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
{
gcc_assert (TARGET_GCN5_PLUS);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
return (gcn_address_register_p (x, DImode, strict)
|| (!VECTOR_MODE_P (mode)
&& gcn_vec_address_register_p (x, DImode, strict)));
@@ -1345,9 +1345,9 @@ gcn_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
rtx x1 = XEXP (x, 1);
if (!gcn_vec_address_register_p (x0, DImode, strict))
return false;
- if (GET_CODE (x1) == REG)
+ if (REG_P (x1))
{
- if (GET_CODE (x1) != REG
+ if (!REG_P (x1)
|| (REGNO (x1) <= FIRST_PSEUDO_REGISTER
&& !gcn_ssrc_register_operand (x1, DImode)))
return false;
@@ -5257,7 +5257,7 @@ print_operand_address (FILE *file, rtx mem)
}
else if (AS_ANY_FLAT_P (as))
{
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
print_reg (file, addr);
else
{
@@ -5352,7 +5352,7 @@ print_operand_address (FILE *file, rtx mem)
offset = XEXP (addr, 1);
print_reg (file, reg);
fprintf (file, ", ");
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
print_reg (file, reg);
else if (CONST_INT_P (offset))
fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (offset));
@@ -5668,7 +5668,7 @@ print_operand (FILE *file, rtx x, int code)
return;
}
- if (GET_CODE (x0) == REG)
+ if (REG_P (x0))
return;
if (GET_CODE (x0) != PLUS)
{
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index d64eda8a5e0..44a4352f36a 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -755,7 +755,7 @@ h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs)
memindex = 0, regindex = 1, offset = (index + 1) * -4;
if (GET_CODE (x) == SET
- && GET_CODE (XEXP (x, regindex)) == REG
+ && REG_P (XEXP (x, regindex))
&& GET_CODE (XEXP (x, memindex)) == MEM
&& h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset))
return REGNO (XEXP (x, regindex));
@@ -1506,13 +1506,13 @@ h8300_print_operand (FILE *file, rtx x, int code)
fprintf (file, "#%ld", 0xff & (-INTVAL (x)));
break;
case 'S':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s", names_extended[REGNO (x)]);
else
goto def;
break;
case 'T':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s", names_big[REGNO (x)]);
else
goto def;
@@ -1537,14 +1537,14 @@ h8300_print_operand (FILE *file, rtx x, int code)
break;
case 'R':
case 'X':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s", byte_reg (x, 0));
else
goto def;
break;
case 'Y':
gcc_assert (bitint >= 0);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l');
else
h8300_print_operand (file, x, 'R');
@@ -1827,7 +1827,7 @@ h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr)
fprintf (file, "(");
index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size);
- if (GET_CODE (index) == REG)
+ if (REG_P (index))
{
/* reg,foo */
h8300_print_operand_address (file, mode, XEXP (addr, 1));
@@ -2433,9 +2433,9 @@ h8300_bitfield_length (rtx op, rtx op2)
enum h8300_operand_class opclass;
unsigned int size, operand_length;
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
op = op2;
- gcc_assert (GET_CODE (op) != REG);
+ gcc_assert (!REG_P (op));
size = GET_MODE_SIZE (GET_MODE (op));
operand_length = h8300_classify_operand (op, size, &opclass);
@@ -2494,7 +2494,7 @@ h8300_short_move_mem_p (rtx op, enum rtx_code inc_code)
return (GET_CODE (addr) == inc_code
|| (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& h8300_displacement_length (addr, size) == 2));
}
@@ -2905,7 +2905,7 @@ compute_mov_length (rtx *operands)
in SImode and SFmode, the second mov.w involves an address
with displacement, namely @(2,Rs) or @(2,Rd), so we subtract
only 2 bytes. */
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
return base_length - 2;
return base_length;
@@ -3013,13 +3013,13 @@ compute_mov_length (rtx *operands)
return base_length - 6;
/* @ERs and @ERd are 6 bytes shorter than the longest. */
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
return base_length - 6;
/* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the
longest. */
if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1))
&& INTVAL (XEXP (addr, 1)) > -32768
&& INTVAL (XEXP (addr, 1)) < 32767)
@@ -3048,7 +3048,7 @@ output_plussi (rtx *operands)
if (TARGET_H8300)
{
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
return "add.w\t%f2,%f0\n\taddx\t%y2,%y0\n\taddx\t%z2,%z0";
if (CONST_INT_P (operands[2]))
@@ -3132,7 +3132,7 @@ compute_plussi_length (rtx *operands)
if (TARGET_H8300)
{
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
return 6;
if (CONST_INT_P (operands[2]))
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 5f3b98da929..1b495be4582 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -1832,7 +1832,7 @@
{
/* Force operand1 into a register if we're compiling
for the H8/300. */
- if ((GET_CODE (operands[2]) != REG && operands[2] != const0_rtx)
+ if ((!REG_P (operands[2]) && operands[2] != const0_rtx)
&& TARGET_H8300)
operands[2] = force_reg (HImode, operands[2]);
h8300_expand_branch (operands);
@@ -2994,7 +2994,7 @@
|| GET_CODE (operands[3]) == MEM)
FAIL;
- if (GET_CODE (operands[3]) != REG)
+ if (!REG_P (operands[3]))
operands[3] = force_reg (HImode, operands[3]);
})
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index 14b0604ed64..5f30de3c80a 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -264,7 +264,7 @@
(define_predicate "jump_address_operand"
(match_code "reg,mem")
{
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return GET_MODE (op) == Pmode;
if (GET_CODE (op) == MEM)
@@ -345,7 +345,7 @@
generation. This means that any named pattern which uses this predicate
must force its operands to match 'U' before emitting RTL. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return 1;
if (GET_CODE (op) == SUBREG)
return 1;
@@ -369,7 +369,7 @@
(match_code "mem")
{
return (GET_CODE (op) == MEM
- && (GET_CODE (XEXP (op, 0)) == REG
+ && (REG_P (XEXP (op, 0))
|| CONST_INT_P (XEXP (op, 0))));
})
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 0741c47bdb6..f6ab07de01b 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -269,7 +269,7 @@ ix86_expand_move (machine_mode mode, rtx operands[])
else
{
rtx temp = op0;
- if (GET_CODE (temp) != REG)
+ if (!REG_P (temp))
temp = gen_reg_rtx (Pmode);
temp = legitimize_pic_address (op1, temp);
if (temp == op0)
diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c
index 6ccd42a1874..fcac684f7b5 100644
--- a/gcc/config/i386/i386-features.c
+++ b/gcc/config/i386/i386-features.c
@@ -1200,7 +1200,7 @@ convertible_comparison_p (rtx_insn *insn)
gcc_assert (GET_CODE (src) == COMPARE);
- if (GET_CODE (dst) != REG
+ if (!REG_P (dst)
|| REGNO (dst) != FLAGS_REG
|| GET_MODE (dst) != CCZmode)
return false;
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index d36ded363c2..8a241915ee8 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -1424,7 +1424,7 @@
rtx elt = XVECEXP (op, 0, i+1);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != V8SImode
|| REGNO (SET_DEST (elt)) != GET_SSE_REGNO (i)
|| SET_SRC (elt) != CONST0_RTX (V8SImode))
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 6896b299ba1..a266f2a6fa8 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -914,7 +914,7 @@ ia64_load_pair_ok (rtx dst, rtx src)
/* ??? There is a thinko in the implementation of the "x" constraint and the
FP_REGS class. The constraint will also reject (reg f30:TI) so we must
also return false for it. */
- if (GET_CODE (dst) != REG
+ if (!REG_P (dst)
|| !(FP_REGNO_P (REGNO (dst)) && FP_REGNO_P (REGNO (dst) + 1)))
return 0;
if (GET_CODE (src) != MEM || MEM_VOLATILE_P (src))
@@ -1116,7 +1116,7 @@ ia64_cannot_force_const_mem (machine_mode mode, rtx x)
bool
ia64_expand_load_address (rtx dest, rtx src)
{
- gcc_assert (GET_CODE (dest) == REG);
+ gcc_assert (REG_P (dest));
/* ILP32 mode still loads 64-bits of data from the GOT. This avoids
having to pointer-extend the value afterward. Other forms of address
@@ -1522,7 +1522,7 @@ ia64_split_tmode (rtx out[2], rtx in, bool reversed, bool dead)
out[0] = adjust_automodify_address
(in, DImode, gen_rtx_POST_INC (Pmode, base), 0);
- if (GET_CODE (XEXP (offset, 1)) == REG)
+ if (REG_P (XEXP (offset, 1)))
{
/* Can't adjust the postmodify to match. Emit the
original, then a separate addition insn. */
@@ -1590,7 +1590,7 @@ ia64_split_tmode_move (rtx operands[])
&& reg_overlap_mentioned_p (operands[0], operands[1]))
{
rtx base = XEXP (operands[1], 0);
- while (GET_CODE (base) != REG)
+ while (!REG_P (base))
base = XEXP (base, 0);
if (REGNO (base) == REGNO (operands[0]))
@@ -1604,7 +1604,7 @@ ia64_split_tmode_move (rtx operands[])
/* Another reason to do the moves in reversed order is if the first
element of the target register pair is also the second element of
the source register pair. */
- if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG
+ if (REG_P (operands[0]) && REG_P (operands[1])
&& REGNO (operands[0]) == REGNO (operands[1]) + 1)
reversed = true;
@@ -1649,13 +1649,13 @@ spill_xfmode_rfmode_operand (rtx in, int force, machine_mode mode)
{
if (GET_CODE (in) == SUBREG
&& GET_MODE (SUBREG_REG (in)) == TImode
- && GET_CODE (SUBREG_REG (in)) == REG)
+ && REG_P (SUBREG_REG (in)))
{
rtx memt = assign_stack_temp (TImode, 16);
emit_move_insn (memt, SUBREG_REG (in));
return adjust_address (memt, mode, 0);
}
- else if (force && GET_CODE (in) == REG)
+ else if (force && REG_P (in))
{
rtx memx = assign_stack_temp (mode, 16);
emit_move_insn (memx, in);
@@ -1684,7 +1684,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
for the last case. This case does not happen for stdarg/vararg routines,
because we do a block store to memory of unnamed arguments. */
- if (GET_CODE (op0) == REG && GR_REGNO_P (REGNO (op0)))
+ if (REG_P (op0) && GR_REGNO_P (REGNO (op0)))
{
rtx out[2];
@@ -1695,7 +1695,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
/* Struct to register can just use TImode instead. */
if ((GET_CODE (operands[1]) == SUBREG
&& GET_MODE (SUBREG_REG (operands[1])) == TImode)
- || (GET_CODE (operands[1]) == REG
+ || (REG_P (operands[1])
&& GR_REGNO_P (REGNO (operands[1]))))
{
rtx op1 = operands[1];
@@ -1736,7 +1736,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
return true;
}
- if (GET_CODE (operands[1]) == REG && GR_REGNO_P (REGNO (operands[1])))
+ if (REG_P (operands[1]) && GR_REGNO_P (REGNO (operands[1])))
{
/* We're hoping to transform everything that deals with XFmode
quantities and GR registers early in the compiler. */
@@ -1773,7 +1773,7 @@ ia64_expand_movxf_movrf (machine_mode mode, rtx operands[])
{
operands[1] = spill_xfmode_rfmode_operand (operands[1], 0, mode);
- if (GET_MODE (op0) == TImode && GET_CODE (op0) == REG)
+ if (GET_MODE (op0) == TImode && REG_P (op0))
{
rtx memt, memx, in = operands[1];
if (CONSTANT_P (in))
@@ -5441,7 +5441,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
str = reg_names [FR_REG (1)];
else
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
str = reg_names [REGNO (x)];
}
fputs (str, file);
@@ -5499,7 +5499,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
value = INTVAL (x);
else
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
fprintf (file, ", %s", reg_names[REGNO (x)]);
return;
}
@@ -5570,7 +5570,7 @@ ia64_print_operand (FILE * file, rtx x, int code)
case 'r':
/* If this operand is the constant zero, write it as register zero.
Any register, zero, or CONST_INT value is OK here. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[REGNO (x)], file);
else if (x == CONST0_RTX (GET_MODE (x)))
fputs ("r0", file);
@@ -5898,7 +5898,7 @@ ia64_secondary_reload_class (enum reg_class rclass,
{
int regno = -1;
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || GET_CODE (x) == SUBREG)
regno = true_regnum (x);
switch (rclass)
@@ -6602,7 +6602,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
if (GET_CODE (cond) == EQ)
is_complemented = 1;
cond = XEXP (cond, 0);
- gcc_assert (GET_CODE (cond) == REG
+ gcc_assert (REG_P (cond)
&& REGNO_REG_CLASS (REGNO (cond)) == PR_REGS);
pred = REGNO (cond);
if (is_complemented)
@@ -6722,7 +6722,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
/* Operators with side-effects. */
case POST_INC: case POST_DEC:
- gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
+ gcc_assert (REG_P (XEXP (x, 0)));
new_flags.is_write = 0;
need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
@@ -6731,7 +6731,7 @@ rtx_needs_barrier (rtx x, struct reg_flags flags, int pred)
break;
case POST_MODIFY:
- gcc_assert (GET_CODE (XEXP (x, 0)) == REG);
+ gcc_assert (REG_P (XEXP (x, 0)));
new_flags.is_write = 0;
need_barrier = rws_access_reg (XEXP (x, 0), new_flags, pred);
@@ -9628,7 +9628,7 @@ ia64_st_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (reg);
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- gcc_assert (GET_CODE (reg) == REG);
+ gcc_assert (REG_P (reg));
dest = ia64_single_set (consumer);
gcc_assert (dest);
@@ -9652,7 +9652,7 @@ ia64_ld_address_bypass_p (rtx_insn *producer, rtx_insn *consumer)
gcc_assert (reg);
if (GET_CODE (reg) == SUBREG)
reg = SUBREG_REG (reg);
- gcc_assert (GET_CODE (reg) == REG);
+ gcc_assert (REG_P (reg));
src = ia64_single_set (consumer);
gcc_assert (src);
@@ -10171,7 +10171,7 @@ process_cfa_offset (FILE *asm_out_file, rtx pat, bool unwind)
rtx base;
gcc_assert (MEM_P (dest));
- if (GET_CODE (XEXP (dest, 0)) == REG)
+ if (REG_P (XEXP (dest, 0)))
{
base = XEXP (dest, 0);
off = 0;
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md
index 5d55b190334..5322e66e1be 100644
--- a/gcc/config/ia64/ia64.md
+++ b/gcc/config/ia64/ia64.md
@@ -250,8 +250,8 @@
[(set (match_operand:CCI 0 "register_operand" "")
(match_operand:CCI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && GR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 2) (const_int 0))
(cond_exec (ne (match_dup 3) (const_int 0))
(set (match_dup 2) (const_int 1)))]
@@ -280,8 +280,8 @@
[(set (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && GR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(cond_exec (ne (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 1)))
(cond_exec (eq (match_dup 1) (const_int 0))
@@ -292,8 +292,8 @@
[(set (match_operand:BI 0 "register_operand" "")
(match_operand:BI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(set (match_dup 2) (match_dup 4))
(set (match_dup 3) (match_dup 5))
(set (match_dup 0) (unspec:BI [(match_dup 0)] UNSPEC_PRED_REL_MUTEX))]
@@ -1570,8 +1570,8 @@
tbit.nz.and.orcm %0, %I0 = %2, 0
and %0 = %2, %1"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[2]) && PR_REGNO_P (REGNO (operands[2]))"
[(cond_exec (eq (match_dup 2) (const_int 0))
(set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1588,8 +1588,8 @@
tbit.z.and.orcm %0, %I0 = %1, 0
andcm %0 = %2, %1"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(cond_exec (ne (match_dup 1) (const_int 0))
(set (match_dup 0) (and:BI (ne:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1606,8 +1606,8 @@
tbit.nz.or.andcm %0, %I0 = %2, 0
or %0 = %2, %1"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[2]) == REG && PR_REGNO_P (REGNO (operands[2]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[2]) && PR_REGNO_P (REGNO (operands[2]))"
[(cond_exec (ne (match_dup 2) (const_int 0))
(set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1623,8 +1623,8 @@
#
tbit.z.or.andcm %0, %I0 = %1, 0"
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))"
[(cond_exec (eq (match_dup 1) (const_int 0))
(set (match_dup 0) (ior:BI (eq:BI (const_int 0) (const_int 0))
(match_dup 0))))]
@@ -1648,7 +1648,7 @@
(not:BI (match_operand:BI 1 "register_operand" "")))
(clobber (match_scratch:BI 2 ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
&& rtx_equal_p (operands[0], operands[1])"
[(set (match_dup 4) (match_dup 3))
(set (match_dup 0) (const_int 1))
@@ -1663,8 +1663,8 @@
(not:BI (match_operand:BI 1 "register_operand" "")))
(clobber (match_scratch:BI 2 ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && PR_REGNO_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && PR_REGNO_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && PR_REGNO_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && PR_REGNO_P (REGNO (operands[1]))
&& ! rtx_equal_p (operands[0], operands[1])"
[(cond_exec (ne (match_dup 1) (const_int 0))
(set (match_dup 0) (const_int 0)))
@@ -5108,12 +5108,12 @@
rtx bsp = gen_rtx_REG (Pmode, 10);
rtx sp = gen_rtx_REG (Pmode, 9);
- if (GET_CODE (operands[0]) != REG || REGNO (operands[0]) != 10)
+ if (!REG_P (operands[0]) || REGNO (operands[0]) != 10)
{
emit_move_insn (bsp, operands[0]);
operands[0] = bsp;
}
- if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 9)
+ if (!REG_P (operands[2]) || REGNO (operands[2]) != 9)
{
emit_move_insn (sp, operands[2]);
operands[2] = sp;
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index f3a34865055..4a539cdf423 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -310,7 +310,7 @@
(and (match_operand 0 "nonimmediate_operand")
(match_test "GET_CODE (op) != MEM
|| GET_CODE (XEXP (op, 0)) != POST_MODIFY
- || GET_CODE (XEXP (XEXP (XEXP (op, 0), 1), 1)) != REG")))
+ || !REG_P (XEXP (XEXP (XEXP (op, 0), 1), 1))")))
;; Like destination_operand, but don't allow any post-increments.
(define_predicate "not_postinc_destination_operand"
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index fd290d096ae..b5e2754dc3e 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -334,7 +334,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
while (GET_CODE (xinsn) == SUBREG)
xinsn = SUBREG_REG (xinsn);
- if (GET_CODE (xinsn) == REG
+ if (REG_P (xinsn)
&& iq2000_reg_mode_ok_for_base_p (xinsn, mode, strict))
return 1;
@@ -345,7 +345,7 @@ iq2000_legitimate_address_p (machine_mode mode, rtx xinsn, bool strict)
while (GET_CODE (xlow0) == SUBREG)
xlow0 = SUBREG_REG (xlow0);
- if (GET_CODE (xlow0) == REG
+ if (REG_P (xlow0)
&& iq2000_reg_mode_ok_for_base_p (xlow0, mode, strict)
&& iq2000_check_split (xlow1, mode))
return 1;
@@ -728,7 +728,7 @@ iq2000_move_1word (rtx operands[], rtx_insn *insn, int unsignedp)
rtx add_op0 = XEXP (op1, 0);
rtx add_op1 = XEXP (op1, 1);
- if (GET_CODE (XEXP (op1, 1)) == REG
+ if (REG_P (XEXP (op1, 1))
&& CONST_INT_P (XEXP (op1, 0)))
add_op0 = XEXP (op1, 1), add_op1 = XEXP (op1, 0);
@@ -842,10 +842,10 @@ iq2000_address_cost (rtx addr, machine_mode mode, addr_space_t as,
rtx plus0 = XEXP (addr, 0);
rtx plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
+ if (!REG_P (plus0) && REG_P (plus1))
plus0 = XEXP (addr, 1), plus1 = XEXP (addr, 0);
- if (GET_CODE (plus0) != REG)
+ if (!REG_P (plus0))
break;
switch (GET_CODE (plus1))
@@ -956,7 +956,7 @@ gen_int_relational (enum rtx_code test_code, rtx result, rtx cmp0, rtx cmp1,
branch_p = (result == 0);
if (branch_p)
{
- if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
+ if (REG_P (cmp0) || GET_CODE (cmp0) == SUBREG)
{
/* Comparisons against zero are simple branches. */
if (CONST_INT_P (cmp1) && INTVAL (cmp1) == 0)
@@ -1991,7 +1991,7 @@ iq2000_expand_prologue (void)
{
int words;
- gcc_assert (GET_CODE (entry_parm) == REG);
+ gcc_assert (REG_P (entry_parm));
/* Passed in a register, so will get homed automatically. */
if (GET_MODE (entry_parm) == BLKmode)
@@ -2961,7 +2961,7 @@ iq2000_print_operand_address (FILE * file, machine_mode mode, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) != REG)
+ if (!REG_P (arg0))
abort_with_insn (addr,
"PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
@@ -2978,15 +2978,15 @@ iq2000_print_operand_address (FILE * file, machine_mode mode, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) == REG)
+ if (REG_P (arg0))
{
reg = arg0;
offset = arg1;
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
}
- else if (GET_CODE (arg1) == REG)
+ else if (REG_P (arg1))
reg = arg1, offset = arg0;
else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
{
@@ -3255,7 +3255,7 @@ iq2000_print_operand (FILE *file, rtx op, int letter)
else if (letter == 't')
fputs (code == EQ ? "t" : "f", file);
- else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
+ else if (code == CONST && REG_P (XEXP (op, 0)))
{
iq2000_print_operand (file, XEXP (op, 0), letter);
}
diff --git a/gcc/config/iq2000/iq2000.md b/gcc/config/iq2000/iq2000.md
index fac0f65159d..0ff9d01998a 100644
--- a/gcc/config/iq2000/iq2000.md
+++ b/gcc/config/iq2000/iq2000.md
@@ -1306,7 +1306,7 @@
""
"*
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
return \"j\\t%0\";
return \"j\\t%l0\";
/* return \"b\\t%l0\";*/
@@ -1324,7 +1324,7 @@
if (operands[0]) /* eliminate unused code warnings */
{
dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+ if (!REG_P (dest) || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
if (!(Pmode == DImode))
@@ -1511,7 +1511,7 @@
if (operands[0]) /* eliminate unused code warnings */
{
addr = XEXP (operands[0], 0);
- if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
+ if ((!REG_P (addr) && (!CONSTANT_ADDRESS_P (addr)))
|| ! call_insn_operand (addr, VOIDmode))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
@@ -1581,7 +1581,7 @@
if (operands[0]) /* eliminate unused code warning */
{
addr = XEXP (operands[1], 0);
- if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr)))
+ if ((!REG_P (addr) && (!CONSTANT_ADDRESS_P (addr)))
|| ! call_insn_operand (addr, VOIDmode))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
diff --git a/gcc/config/iq2000/predicates.md b/gcc/config/iq2000/predicates.md
index 93fa4737648..c8f4ef37fc8 100644
--- a/gcc/config/iq2000/predicates.md
+++ b/gcc/config/iq2000/predicates.md
@@ -139,12 +139,12 @@
case PLUS:
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) == REG
+ if (REG_P (plus0)
&& CONST_INT_P (plus1) && SMALL_INT (plus1)
&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
return 1;
- else if (GET_CODE (plus1) == REG
+ else if (REG_P (plus1)
&& CONST_INT_P (plus0) && SMALL_INT (plus0)
&& SMALL_INT_UNSIGNED (plus1) /* No negative offsets. */)
return 1;
@@ -205,7 +205,7 @@
(match_code "const_int,const,symbol_ref,reg")
{
return (CONSTANT_ADDRESS_P (op)
- || (GET_CODE (op) == REG && op != arg_pointer_rtx
+ || (REG_P (op) && op != arg_pointer_rtx
&& ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
&& REGNO (op) <= LAST_VIRTUAL_REGISTER)));
})
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 294f0f46439..13ad0bf65d7 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -579,7 +579,7 @@ lm32_print_operand_address (FILE * file, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) == REG && CONSTANT_P (arg1))
+ if (REG_P (arg0) && CONSTANT_P (arg1))
{
if (CONST_INT_P (arg1))
fprintf (file, "(%s+%ld)", reg_names[REGNO (arg0)],
@@ -1055,7 +1055,7 @@ lm32_rtx_costs (rtx x, machine_mode mode, int outer_code,
*total = COSTS_N_INSNS (2 + 1 + cycles);
return true;
}
- else if (GET_CODE (XEXP (x, 1)) == REG)
+ else if (REG_P (XEXP (x, 1)))
{
*total = COSTS_N_INSNS (1 + GET_MODE_SIZE (mode) / 2);
return true;
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 9c8a72e2a17..095a9a6818f 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -318,7 +318,7 @@
(define_insn "*extendqihi2"
[(set (match_operand:HI 0 "register_operand" "=r,r")
(sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
+ "TARGET_SIGN_EXTEND_ENABLED || (!REG_P (operands[1]))"
"@
lb %0, %1
sextb %0, %1"
@@ -338,7 +338,7 @@
(define_insn "*extendqisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
+ "TARGET_SIGN_EXTEND_ENABLED || (!REG_P (operands[1]))"
"@
lb %0, %1
sextb %0, %1"
@@ -358,7 +358,7 @@
(define_insn "*extendhisi2"
[(set (match_operand:SI 0 "register_operand" "=r,r")
(sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
- "TARGET_SIGN_EXTEND_ENABLED || (GET_CODE (operands[1]) != REG)"
+ "TARGET_SIGN_EXTEND_ENABLED || (!REG_P (operands[1]))"
"@
lh %0, %1
sexth %0, %1"
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 08e0542bd2b..1ff54b41363 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -123,10 +123,10 @@ static GTY(()) rtx patternr[30];
/* Some macros to simplify the logic throughout this file. */
#define IS_MEM_REGNO(regno) ((regno) >= MEM0_REGNO && (regno) <= MEM7_REGNO)
-#define IS_MEM_REG(rtx) (GET_CODE (rtx) == REG && IS_MEM_REGNO (REGNO (rtx)))
+#define IS_MEM_REG(rtx) (REG_P (rtx) && IS_MEM_REGNO (REGNO (rtx)))
#define IS_CR_REGNO(regno) ((regno) >= SB_REGNO && (regno) <= PC_REGNO)
-#define IS_CR_REG(rtx) (GET_CODE (rtx) == REG && IS_CR_REGNO (REGNO (rtx)))
+#define IS_CR_REG(rtx) (REG_P (rtx) && IS_CR_REGNO (REGNO (rtx)))
static int
far_addr_space_p (rtx x)
@@ -176,7 +176,7 @@ encode_pattern_1 (rtx x)
GET_MODE_SIZE (GET_MODE (XEXP (x, 0))))
*patternp++ = 'S';
if (GET_MODE (x) == PSImode
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
*patternp++ = 'S';
encode_pattern_1 (XEXP (x, 0));
break;
@@ -757,7 +757,7 @@ m32c_secondary_reload_class (int rclass, machine_mode mode, rtx x)
&& GET_CODE (x) == MEM && (cc & ~class_contents[R23_REGS][0]) == 0)
return QI_REGS;
if (reg_classes_intersect_p (rclass, CR_REGS)
- && GET_CODE (x) == REG
+ && REG_P (x)
&& REGNO (x) >= SB_REGNO && REGNO (x) <= SP_REGNO)
return (TARGET_A16 || mode == HImode) ? HI_REGS : A_REGS;
return NO_REGS;
@@ -836,12 +836,12 @@ m32c_can_change_mode_class (machine_mode from,
/* Helpers for the rest of the file. */
/* TRUE if the rtx is a REG rtx for the given register. */
-#define IS_REG(rtx,regno) (GET_CODE (rtx) == REG \
+#define IS_REG(rtx,regno) (REG_P (rtx) \
&& REGNO (rtx) == regno)
/* TRUE if the rtx is a pseudo - specifically, one we can use as a
base register in address calculations (hence the "strict"
argument). */
-#define IS_PSEUDO(rtx,strict) (!strict && GET_CODE (rtx) == REG \
+#define IS_PSEUDO(rtx,strict) (!strict && REG_P (rtx) \
&& (REGNO (rtx) == AP_REGNO \
|| REGNO (rtx) >= FIRST_PSEUDO_REGISTER))
@@ -1672,7 +1672,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (GET_CODE (x) == PRE_DEC
|| GET_CODE (x) == POST_INC || GET_CODE (x) == PRE_MODIFY)
{
- return (GET_CODE (XEXP (x, 0)) == REG
+ return (REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == SP_REGNO);
}
@@ -1784,7 +1784,7 @@ m32c_legitimate_address_p (machine_mode mode, rtx x, bool strict)
int
m32c_reg_ok_for_base_p (rtx x, int strict)
{
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return 0;
switch (REGNO (x))
{
@@ -1844,7 +1844,7 @@ m32c_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
#endif
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == FB_REGNO
&& CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) < -128
@@ -1883,7 +1883,7 @@ m32c_legitimize_reload_address (rtx * x,
The code below is a second attempt at the above. */
if (GET_CODE (*x) == PLUS
- && GET_CODE (XEXP (*x, 0)) == REG
+ && REG_P (XEXP (*x, 0))
&& REGNO (XEXP (*x, 0)) == FB_REGNO
&& CONST_INT_P (XEXP (*x, 1))
&& (INTVAL (XEXP (*x, 1)) < -128
@@ -1906,7 +1906,7 @@ m32c_legitimize_reload_address (rtx * x,
if (GET_CODE (*x) == PLUS
&& GET_CODE (XEXP (*x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (*x, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (*x, 0), 0))
&& REGNO (XEXP (XEXP (*x, 0), 0)) == FB_REGNO
&& CONST_INT_P (XEXP (XEXP (*x, 0), 1))
&& CONST_INT_P (XEXP (*x, 1))
@@ -2070,7 +2070,7 @@ m32c_addr_space_legitimize_address (rtx x, rtx oldx, machine_mode mode,
fprintf (stderr, "\n");
#endif
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
{
x = force_reg (SImode, x);
}
@@ -2572,7 +2572,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
if (code == 'H' && GET_MODE (x) == HImode)
{
/* We can't actually represent this as an rtx. Do it here. */
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
switch (REGNO (x))
{
@@ -2593,7 +2593,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
/* This is for BMcond, which always wants word register names. */
if (code == 'h' && GET_MODE (x) == QImode)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
x = gen_rtx_REG (HImode, REGNO (x));
code = 0;
}
@@ -2678,7 +2678,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
entire address range. */
rtx base =
patternr[conversions[i].format[j + 2] - '0'];
- if (GET_CODE (base) == REG)
+ if (REG_P (base))
switch (REGNO (base))
{
case A0_REGNO:
@@ -2751,7 +2751,7 @@ m32c_print_operand (FILE * file, rtx x, int code)
if (ISDIGIT (conversions[i].format[k]))
{
rtx reg = patternr[conversions[i].format[k] - '0'];
- if (GET_CODE (reg) == REG
+ if (REG_P (reg)
&& (REGNO (reg) == SB_REGNO
|| REGNO (reg) == FB_REGNO
|| REGNO (reg) == SP_REGNO))
@@ -2813,7 +2813,7 @@ m32c_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx address)
address = XEXP (address, 0);
else
/* cf: gcc.dg/asm-4.c. */
- gcc_assert (GET_CODE (address) == REG);
+ gcc_assert (REG_P (address));
m32c_print_operand (stream, address, 0);
}
@@ -3148,7 +3148,7 @@ m32c_illegal_subreg_p (rtx op)
if (GET_MODE_SIZE (dest_mode) == GET_MODE_SIZE (src_mode))
return false;
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return false;
if (REGNO (op) >= MEM0_REGNO)
return false;
@@ -3266,7 +3266,7 @@ m32c_subreg (machine_mode outer,
|| GET_CODE (XEXP (XEXP (x, 0), 0)) == POST_INC))
return gen_rtx_MEM (outer, XEXP (XEXP (x, 0), 0));
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
{
rtx r = simplify_gen_subreg (outer, x, inner, byte);
if (GET_CODE (r) == SUBREG
@@ -3545,7 +3545,7 @@ m32c_expand_setmemhi(rtx *operands)
desto = gen_reg_rtx (Pmode);
counto = gen_reg_rtx (HImode);
- if (GET_CODE (desta) != REG
+ if (!REG_P (desta)
|| REGNO (desta) < FIRST_PSEUDO_REGISTER)
desta = copy_to_mode_reg (Pmode, desta);
@@ -3571,11 +3571,11 @@ m32c_expand_setmemhi(rtx *operands)
}
/* This is the generalized memset() case. */
- if (GET_CODE (val) != REG
+ if (!REG_P (val)
|| REGNO (val) < FIRST_PSEUDO_REGISTER)
val = copy_to_mode_reg (QImode, val);
- if (GET_CODE (count) != REG
+ if (!REG_P (count)
|| REGNO (count) < FIRST_PSEUDO_REGISTER)
count = copy_to_mode_reg (HImode, count);
@@ -3605,11 +3605,11 @@ m32c_expand_cpymemhi(rtx *operands)
srco = gen_reg_rtx (Pmode);
counto = gen_reg_rtx (HImode);
- if (GET_CODE (desta) != REG
+ if (!REG_P (desta)
|| REGNO (desta) < FIRST_PSEUDO_REGISTER)
desta = copy_to_mode_reg (Pmode, desta);
- if (GET_CODE (srca) != REG
+ if (!REG_P (srca)
|| REGNO (srca) < FIRST_PSEUDO_REGISTER)
srca = copy_to_mode_reg (Pmode, srca);
@@ -3627,7 +3627,7 @@ m32c_expand_cpymemhi(rtx *operands)
}
/* This is the generalized memset() case. */
- if (GET_CODE (count) != REG
+ if (!REG_P (count)
|| REGNO (count) < FIRST_PSEUDO_REGISTER)
count = copy_to_mode_reg (HImode, count);
@@ -3656,11 +3656,11 @@ m32c_expand_movstr(rtx *operands)
desto = gen_reg_rtx (Pmode);
srco = gen_reg_rtx (Pmode);
- if (GET_CODE (desta) != REG
+ if (!REG_P (desta)
|| REGNO (desta) < FIRST_PSEUDO_REGISTER)
desta = copy_to_mode_reg (Pmode, desta);
- if (GET_CODE (srca) != REG
+ if (!REG_P (srca)
|| REGNO (srca) < FIRST_PSEUDO_REGISTER)
srca = copy_to_mode_reg (Pmode, srca);
@@ -3683,11 +3683,11 @@ m32c_expand_cmpstr(rtx *operands)
src1a = XEXP (operands[1], 0);
src2a = XEXP (operands[2], 0);
- if (GET_CODE (src1a) != REG
+ if (!REG_P (src1a)
|| REGNO (src1a) < FIRST_PSEUDO_REGISTER)
src1a = copy_to_mode_reg (Pmode, src1a);
- if (GET_CODE (src2a) != REG
+ if (!REG_P (src2a)
|| REGNO (src2a) < FIRST_PSEUDO_REGISTER)
src2a = copy_to_mode_reg (Pmode, src2a);
@@ -3980,7 +3980,7 @@ const char *
m32c_scc_pattern(rtx *operands, RTX_CODE code)
{
static char buf[30];
- if (GET_CODE (operands[0]) == REG
+ if (REG_P (operands[0])
&& REGNO (operands[0]) == R0_REGNO)
{
if (code == EQ)
@@ -4376,7 +4376,7 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
/* Check for PREV changing a register that's used to compute a
value in CMP, even if it doesn't otherwise change flags. */
- if (GET_CODE (operands[0]) == REG
+ if (REG_P (operands[0])
&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[0]))
{
#if DEBUG_CMP
@@ -4385,7 +4385,7 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
#endif
return false;
}
- if (GET_CODE (operands[1]) == REG
+ if (REG_P (operands[1])
&& rtx_referenced_p (SET_DEST (PATTERN (prev)), operands[1]))
{
#if DEBUG_CMP
@@ -4403,7 +4403,7 @@ m32c_compare_redundant (rtx_insn *cmp, rtx *operands)
#endif
if (GET_CODE (pp) == SET
- && GET_CODE (XEXP (pp, 0)) == REG
+ && REG_P (XEXP (pp, 0))
&& REGNO (XEXP (pp, 0)) == FLG_REGNO
&& GET_CODE (XEXP (pp, 1)) == COMPARE)
{
diff --git a/gcc/config/m32c/predicates.md b/gcc/config/m32c/predicates.md
index 93cd9173f75..2c66da5f284 100644
--- a/gcc/config/m32c/predicates.md
+++ b/gcc/config/m32c/predicates.md
@@ -46,7 +46,7 @@
(ior (and (match_code "reg")
(match_test "REGNO(op) >= FIRST_PSEUDO_REGISTER"))
(and (match_code "subreg")
- (and (match_test "GET_CODE (XEXP (op, 0)) == REG")
+ (and (match_test "REG_P (XEXP (op, 0))")
(match_test "REGNO(XEXP (op,0)) >= FIRST_PSEUDO_REGISTER")))))
@@ -197,7 +197,7 @@
rtx reg = XEXP (op, 0);
rtx size = XEXP (op, 1);
rtx pos = XEXP (op, 2);
- return (GET_CODE (reg) == REG
+ return (REG_P (reg)
&& REGNO (reg) == R1_REGNO
&& CONST_INT_P (size)
&& INTVAL (size) == 8
@@ -229,7 +229,7 @@
(ior (match_test "REGNO(op) == R2_REGNO")
(match_test "REGNO(op) == R3_REGNO")))
(and (match_code "subreg")
- (match_test "GET_CODE (XEXP (op, 0)) == REG && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
+ (match_test "REG_P (XEXP (op, 0)) && (REGNO (XEXP (op, 0)) == R2_REGNO || REGNO (XEXP (op, 0)) == R3_REGNO)"))))
; Likewise, plus TRUE for a0..a1.
(define_predicate "m32c_r2r3a_operand"
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 4f757403f7e..5c02c6eb3df 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1541,8 +1541,8 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
}
if (ch)
{
- if (GET_CODE (XEXP (x, 1)) == REG
- && GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 1))
+ && REG_P (XEXP (x, 0)))
{
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT)
{
@@ -1554,9 +1554,9 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
if (memory_address_p (mode, x))
return x;
}
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
|| (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (x, 0), 0))
&& GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode))
{
rtx temp = gen_reg_rtx (Pmode);
@@ -1565,12 +1565,12 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
COPY_ONCE (x);
XEXP (x, 1) = temp;
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
x = force_operand (x, 0);
}
- else if (GET_CODE (XEXP (x, 1)) == REG
+ else if (REG_P (XEXP (x, 1))
|| (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND
- && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG
+ && REG_P (XEXP (XEXP (x, 1), 0))
&& GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode))
{
rtx temp = gen_reg_rtx (Pmode);
@@ -1579,7 +1579,7 @@ m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode)
COPY_ONCE (x);
XEXP (x, 0) = temp;
if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT
- && GET_CODE (XEXP (x, 1)) == REG)
+ && REG_P (XEXP (x, 1)))
x = force_operand (x, 0);
}
}
@@ -1671,7 +1671,7 @@ output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
/* The m68k cmp.l instruction requires operand1 to be a reg as used
below. Swap the operands and change the op if these requirements
are not fulfilled. */
- if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG)
+ if (REG_P (operand2) && !REG_P (operand1))
{
rtx tmp = operand1;
@@ -1680,14 +1680,14 @@ output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest)
op_code = swap_condition (op_code);
}
loperands[0] = operand1;
- if (GET_CODE (operand1) == REG)
+ if (REG_P (operand1))
loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1);
else
loperands[1] = adjust_address (operand1, SImode, 4);
if (operand2 != const0_rtx)
{
loperands[2] = operand2;
- if (GET_CODE (operand2) == REG)
+ if (REG_P (operand2))
loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1);
else
loperands[3] = adjust_address (operand2, SImode, 4);
@@ -2883,9 +2883,9 @@ m68k_rtx_costs (rtx x, machine_mode mode, int outer_code,
case PLUS:
/* An lea costs about three times as much as a simple add. */
if (mode == SImode
- && GET_CODE (XEXP (x, 1)) == REG
+ && REG_P (XEXP (x, 1))
&& GET_CODE (XEXP (x, 0)) == MULT
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& (INTVAL (XEXP (XEXP (x, 0), 1)) == 2
|| INTVAL (XEXP (XEXP (x, 0), 1)) == 4
@@ -3681,12 +3681,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
register rtx tem;
if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == REG
+ && reload_in_progress && REG_P (operand0)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand0) == SUBREG
- && GET_CODE (SUBREG_REG (operand0)) == REG
+ && REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -3698,12 +3698,12 @@ emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
}
if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == REG
+ && reload_in_progress && REG_P (operand1)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand1) == SUBREG
- && GET_CODE (SUBREG_REG (operand1)) == REG
+ && REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -4062,9 +4062,9 @@ find_addr_reg (rtx addr)
{
while (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
addr = XEXP (addr, 0);
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
addr = XEXP (addr, 1);
else if (CONSTANT_P (XEXP (addr, 0)))
addr = XEXP (addr, 1);
@@ -4073,7 +4073,7 @@ find_addr_reg (rtx addr)
else
gcc_unreachable ();
}
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
return addr;
}
@@ -4097,7 +4097,7 @@ output_addsi3 (rtx *operands)
if (CONST_INT_P (operands[2])
&& (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767))
return "move%.l %2,%0\n\tadd%.l %1,%0";
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0";
return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0";
}
@@ -4183,7 +4183,7 @@ notice_update_cc (rtx exp, rtx insn)
else if (!FP_REG_P (SET_DEST (exp))
&& !FP_REG_P (SET_SRC (exp))
&& GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4
- && (GET_CODE (SET_SRC (exp)) == REG
+ && (REG_P (SET_SRC (exp))
|| GET_CODE (SET_SRC (exp)) == MEM
|| CONST_DOUBLE_P (SET_SRC (exp))))
CC_STATUS_INIT;
@@ -4240,7 +4240,7 @@ notice_update_cc (rtx exp, rtx insn)
default:
break;
}
- if (cc_status.value1 && GET_CODE (cc_status.value1) == REG
+ if (cc_status.value1 && REG_P (cc_status.value1)
&& cc_status.value2
&& reg_overlap_mentioned_p (cc_status.value1, cc_status.value2))
cc_status.value2 = 0;
@@ -4489,7 +4489,7 @@ print_operand (FILE *file, rtx op, int letter)
if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
fprintf (file, "@PLTPC");
}
- else if (GET_CODE (op) == REG)
+ else if (REG_P (op))
{
if (letter == 'R')
/* Print out the second register name of a register pair.
@@ -4862,7 +4862,7 @@ strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn,
&& SET_SRC (set) == const0_rtx)
return true;
else if (GET_CODE (dest) == STRICT_LOW_PART
- && GET_CODE (XEXP (dest, 0)) == REG
+ && REG_P (XEXP (dest, 0))
&& REGNO (XEXP (dest, 0)) == REGNO (target)
&& (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0)))
<= GET_MODE_SIZE (mode)))
@@ -4944,7 +4944,7 @@ output_andsi3 (rtx *operands)
|| offsettable_memref_p (operands[0]))
&& !TARGET_COLDFIRE)
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = adjust_address (operands[0], HImode, 2);
operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
@@ -4982,7 +4982,7 @@ output_iorsi3 (rtx *operands)
|| offsettable_memref_p (operands[0]))
&& !TARGET_COLDFIRE)
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = adjust_address (operands[0], HImode, 2);
/* Do not delete a following tstl %0 insn; that would be incorrect. */
CC_STATUS_INIT;
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 4ed3111c439..ce4f39c953b 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -1581,7 +1581,7 @@
(match_operand:SI 1 "general_src_operand" "doJS,i")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
@@ -1599,7 +1599,7 @@
(match_operand:HI 1 "general_src_operand" "doJS,i")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == REG
+ if (REG_P (operands[0])
&& (GET_CODE (operands[1]) == MEM
|| CONST_INT_P (operands[1])))
{
@@ -1608,7 +1608,7 @@
CC_STATUS_INIT;
return "move%.w %1,%0";
}
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
@@ -1626,7 +1626,7 @@
(match_operand:SI 1 "general_src_operand" "roJS,i")))]
"!TARGET_COLDFIRE"
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
{
/* Must clear condition codes, since the move.l bases them on
the entire 32 bits, not just the desired 8 bits. */
@@ -1893,7 +1893,7 @@
operands[1] = operands[2];
operands[2] = tmp;
}
- if (GET_CODE (operands[1]) == REG
+ if (REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[3]))
output_asm_insn ("add%.l %2,%3", operands);
else
@@ -2271,7 +2271,7 @@
if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
return
"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0";
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
|| GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
@@ -2318,7 +2318,7 @@
"!TARGET_COLDFIRE"
{
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[2] = adjust_address (operands[0], SImode, 4);
@@ -2347,7 +2347,7 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[1] = adjust_address (operands[1], SImode, 4);
@@ -2374,7 +2374,7 @@
rtx high, low;
rtx xoperands[2];
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
high = operands[2];
@@ -2844,7 +2844,7 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
else
operands[1] = adjust_address (operands[1], SImode, 4);
@@ -2873,7 +2873,7 @@
rtx high, low;
rtx xoperands[2];
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
high = operands[2];
@@ -3717,7 +3717,7 @@
int byte_mode;
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[0] = adjust_address (operands[0], SImode, 4);
@@ -3811,9 +3811,9 @@
""
{
CC_STATUS_INIT;
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = adjust_address (operands[2], HImode, 2);
- if (GET_CODE (operands[2]) != REG
+ if (!REG_P (operands[2])
|| REGNO (operands[2]) != REGNO (operands[0]))
output_asm_insn ("move%.w %2,%0", operands);
return "swap %0\;mov%.w %1,%0";
@@ -3929,7 +3929,7 @@
{
if (which_alternative == 0)
return "neg%.l %0\;negx%.l %0";
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[1] = adjust_address (operands[0], SImode, 4);
@@ -4672,7 +4672,7 @@
(const_int 32)) 6))]
""
{
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = adjust_address (operands[1], HImode, 2);
return "move%.w %1,%0";
}
@@ -4912,7 +4912,7 @@
;; (const_int 32)))]
;; ""
;;{
-;; if (GET_CODE (operands[1]) == REG)
+;; if (REG_P (operands[1]))
;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
;; else
;; operands[2] = adjust_address (operands[1], SImode, 4);
@@ -5746,7 +5746,7 @@
if (operands[1] == const1_rtx
&& CONST_INT_P (operands[2]))
{
- int width = GET_CODE (operands[0]) == REG ? 31 : 7;
+ int width = REG_P (operands[0]) ? 31 : 7;
return output_btst (operands,
GEN_INT (width - INTVAL (operands[2])),
operands[0], insn, 1000);
@@ -5773,7 +5773,7 @@
if (operands[1] == const1_rtx
&& CONST_INT_P (operands[2]))
{
- int width = GET_CODE (operands[0]) == REG ? 31 : 7;
+ int width = REG_P (operands[0]) ? 31 : 7;
return output_btst (operands, GEN_INT (width - INTVAL (operands[2])),
operands[0], insn, 1000);
/* Pass 1000 as SIGNPOS argument so that btst will
@@ -6049,7 +6049,7 @@
cc_status = cc_prev_status;
return "jeq %l1";
}
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[3] = adjust_address (operands[0], SImode, 4);
@@ -6092,7 +6092,7 @@
return "jne %l1";
}
CC_STATUS_INIT;
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
else
operands[3] = adjust_address (operands[0], SImode, 4);
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index 21d15e0a6bb..d4f417a16e9 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -343,7 +343,7 @@ mcore_print_operand_address (FILE * stream, machine_mode /*mode*/, rtx x)
rtx base = XEXP (x, 0);
rtx index = XEXP (x, 1);
- if (GET_CODE (base) != REG)
+ if (!REG_P (base))
{
/* Ensure that BASE is a register (one of them must be). */
rtx temp = base;
@@ -1282,9 +1282,9 @@ mcore_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
rtx dst = operands[0];
rtx src = operands[1];
- if (GET_CODE (dst) == REG)
+ if (REG_P (dst))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
if (REGNO (src) == CC_REG) /* r-c */
return "mvc\t%0";
@@ -1352,9 +1352,9 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
rtx dst = operands[0];
rtx src = operands[1];
- if (GET_CODE (dst) == REG)
+ if (REG_P (dst))
{
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int dstreg = REGNO (dst);
int srcreg = REGNO (src);
@@ -1373,13 +1373,13 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
if (GET_CODE (memexp) == LABEL_REF)
return "lrw\t%0,[%1]\n\tlrw\t%R0,[%R1]";
- else if (GET_CODE (memexp) == REG)
+ else if (REG_P (memexp))
basereg = REGNO (memexp);
else if (GET_CODE (memexp) == PLUS)
{
- if (GET_CODE (XEXP (memexp, 0)) == REG)
+ if (REG_P (XEXP (memexp, 0)))
basereg = REGNO (XEXP (memexp, 0));
- else if (GET_CODE (XEXP (memexp, 1)) == REG)
+ else if (REG_P (XEXP (memexp, 1)))
basereg = REGNO (XEXP (memexp, 1));
else
gcc_unreachable ();
@@ -1437,7 +1437,7 @@ mcore_output_movedouble (rtx operands[], machine_mode mode ATTRIBUTE_UNUSED)
else
gcc_unreachable ();
}
- else if (GET_CODE (dst) == MEM && GET_CODE (src) == REG)
+ else if (GET_CODE (dst) == MEM && REG_P (src))
return "stw\t%1,%0\n\tstw\t%R1,%R0";
else
gcc_unreachable ();
@@ -2291,25 +2291,25 @@ is_cond_candidate (rtx insn)
dst = XEXP (pat, 0);
- if ((GET_CODE (dst) != REG &&
+ if ((!REG_P (dst) &&
GET_CODE (dst) != SUBREG) ||
GET_MODE (dst) != SImode)
return COND_NO;
src = XEXP (pat, 1);
- if ((GET_CODE (src) == REG ||
+ if ((REG_P (src) ||
(GET_CODE (src) == SUBREG &&
- GET_CODE (SUBREG_REG (src)) == REG)) &&
+ REG_P (SUBREG_REG (src)))) &&
GET_MODE (src) == SImode)
return COND_MOV_INSN;
else if (CONST_INT_P (src) &&
INTVAL (src) == 0)
return COND_CLR_INSN;
else if (GET_CODE (src) == PLUS &&
- (GET_CODE (XEXP (src, 0)) == REG ||
+ (REG_P (XEXP (src, 0)) ||
(GET_CODE (XEXP (src, 0)) == SUBREG &&
- GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
+ REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode &&
CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == 1)
@@ -2320,9 +2320,9 @@ is_cond_candidate (rtx insn)
(GET_CODE (src) == PLUS &&
CONST_INT_P (XEXP (src, 1)) &&
INTVAL (XEXP (src, 1)) == -1)) &&
- (GET_CODE (XEXP (src, 0)) == REG ||
+ (REG_P (XEXP (src, 0)) ||
(GET_CODE (XEXP (src, 0)) == SUBREG &&
- GET_CODE (SUBREG_REG (XEXP (src, 0))) == REG)) &&
+ REG_P (SUBREG_REG (XEXP (src, 0))))) &&
GET_MODE (XEXP (src, 0)) == SImode)
return COND_DEC_INSN;
@@ -2690,7 +2690,7 @@ mcore_is_same_reg (rtx x, rtx y)
while (GET_CODE (y) == SUBREG)
y = SUBREG_REG (y);
- if (GET_CODE(x) == REG && GET_CODE(y) == REG && REGNO(x) == REGNO(y))
+ if (REG_P (x) && REG_P (y) && REGNO(x) == REGNO(y))
return 1;
return 0;
diff --git a/gcc/config/mcore/mcore.md b/gcc/config/mcore/mcore.md
index 71f0bc0b17c..755a322139c 100644
--- a/gcc/config/mcore/mcore.md
+++ b/gcc/config/mcore/mcore.md
@@ -674,7 +674,7 @@
that we can later fold in the fp/sp offset from frame pointer
elimination. */
if (flag_omit_frame_pointer
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& (REGNO (operands[1]) == VIRTUAL_STACK_VARS_REGNUM
|| REGNO (operands[1]) == FRAME_POINTER_REGNUM))
{
@@ -1367,7 +1367,7 @@
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM
|| XEXP (operands[1], 0) != stack_pointer_rtx
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| REGNO (operands[0]) + INTVAL (operands[2]) != 16)
FAIL;
@@ -1387,7 +1387,7 @@
[(match_parallel 0 "mcore_load_multiple_operation"
[(set (match_operand:SI 1 "mcore_arith_reg_operand" "=r")
(mem:SI (match_operand:SI 2 "register_operand" "r")))])]
- "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
+ "REG_P (operands[2]) && REGNO (operands[2]) == STACK_POINTER_REGNUM"
"ldm %1-r15,(%2)")
(define_expand "store_multiple"
@@ -1405,7 +1405,7 @@
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
|| XEXP (operands[0], 0) != stack_pointer_rtx
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| REGNO (operands[1]) + INTVAL (operands[2]) != 16)
FAIL;
@@ -1426,7 +1426,7 @@
[(match_parallel 0 "mcore_store_multiple_operation"
[(set (mem:SI (match_operand:SI 2 "register_operand" "r"))
(match_operand:SI 1 "mcore_arith_reg_operand" "r"))])]
- "GET_CODE (operands[2]) == REG && REGNO (operands[2]) == STACK_POINTER_REGNUM"
+ "REG_P (operands[2]) && REGNO (operands[2]) == STACK_POINTER_REGNUM"
"stm %1-r15,(%2)")
;; ------------------------------------------------------------------------
@@ -2764,7 +2764,7 @@
(mcore_byte_offset (INTVAL (operands[3])) > -1 ||
mcore_halfword_offset (INTVAL (operands[3])) > -1) &&
! MEM_VOLATILE_P (operands[4]) &&
- GET_CODE (XEXP (operands[4], 0)) == REG"
+ REG_P (XEXP (operands[4], 0))"
"*
{
int ofs;
@@ -2839,12 +2839,12 @@
{
unsigned int op0 = REGNO (operands[0]);
- if (GET_CODE (operands[3]) == REG)
+ if (REG_P (operands[3]))
{
if (REGNO (operands[3]) == op0 && CONST_INT_P (operands[4])
&& INTVAL (operands[4]) == 0)
return \"btsti %1,%2\\n\\tclrf %0\";
- else if (GET_CODE (operands[4]) == REG)
+ else if (REG_P (operands[4]))
{
if (REGNO (operands[4]) == op0)
return \"btsti %1,%2\\n\\tmovf %0,%3\";
@@ -2856,7 +2856,7 @@
}
else if (CONST_INT_P (operands[3])
&& INTVAL (operands[3]) == 0
- && GET_CODE (operands[4]) == REG)
+ && REG_P (operands[4]))
return \"btsti %1,%2\\n\\tclrt %0\";
gcc_unreachable ();
diff --git a/gcc/config/mcore/predicates.md b/gcc/config/mcore/predicates.md
index 344a1e0b14e..c29792cc520 100644
--- a/gcc/config/mcore/predicates.md
+++ b/gcc/config/mcore/predicates.md
@@ -28,7 +28,7 @@
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
return REGNO (op) != CC_REG;
return 1;
@@ -51,7 +51,7 @@
(define_predicate "mcore_general_movdst_operand"
(match_code "mem,reg,subreg")
{
- if (GET_CODE (op) == REG && REGNO (op) == CC_REG)
+ if (REG_P (op) && REGNO (op) == CC_REG)
return 0;
return general_operand (op, mode);
@@ -262,7 +262,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return 0;
@@ -274,7 +274,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != SImode
|| REGNO (SET_DEST (elt)) != (unsigned) (dest_regno + i)
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -303,7 +303,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return 0;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -314,7 +314,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != SImode
|| REGNO (SET_SRC (elt)) != (unsigned) (src_regno + i)
|| GET_CODE (SET_DEST (elt)) != MEM
diff --git a/gcc/config/microblaze/constraints.md b/gcc/config/microblaze/constraints.md
index 5e1d79a2444..831e888a180 100644
--- a/gcc/config/microblaze/constraints.md
+++ b/gcc/config/microblaze/constraints.md
@@ -74,4 +74,4 @@
(define_memory_constraint "Q"
"Memory operand which is a single register."
(and (match_code "mem")
- (match_test "GET_CODE ( XEXP (op, 0)) == REG")))
+ (match_test "REG_P ( XEXP (op, 0))")))
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index 529d54cefc4..f9c2adf9ab7 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -311,19 +311,19 @@ simple_memory_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
plus0 = XEXP (addr, 0);
plus1 = XEXP (addr, 1);
- if (GET_CODE (plus0) != REG)
+ if (!REG_P (plus0))
return 0;
- if (GET_CODE (plus0) == REG && CONST_INT_P (plus1)
+ if (REG_P (plus0) && CONST_INT_P (plus1)
&& SMALL_INT (plus1))
{
return 1;
}
- else if (GET_CODE (plus1) == REG && CONST_INT_P (plus0))
+ else if (REG_P (plus1) && CONST_INT_P (plus0))
{
return 1;
}
- else if (GET_CODE (plus0) == REG && GET_CODE (plus1) == REG)
+ else if (REG_P (plus0) && REG_P (plus1))
{
return 1;
}
@@ -356,7 +356,7 @@ double_memory_operand (rtx op, machine_mode mode)
register from memory, when we could just reload directly from
memory. */
if (reload_in_progress
- && GET_CODE (op) == REG
+ && REG_P (op)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER
&& reg_renumber[REGNO (op)] < 0
&& reg_equiv_mem (REGNO (op)) != 0
@@ -409,7 +409,7 @@ microblaze_valid_base_register_p (rtx x,
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
- return (GET_CODE (x) == REG
+ return (REG_P (x)
&& microblaze_regno_ok_for_base_p (REGNO (x), strict));
}
@@ -674,7 +674,7 @@ microblaze_valid_index_register_p (rtx x,
if (!strict && GET_CODE (x) == SUBREG)
x = SUBREG_REG (x);
- return (GET_CODE (x) == REG
+ return (REG_P (x)
/* A base register is good enough to be an index register on MicroBlaze. */
&& microblaze_regno_ok_for_base_p (REGNO (x), strict));
}
@@ -841,7 +841,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
return false;
}
- else if (GET_CODE (xplus1) == REG
+ else if (REG_P (xplus1)
&& microblaze_valid_index_register_p (xplus1, mode,
strict)
&& (GET_MODE_SIZE (mode) <= UNITS_PER_WORD))
@@ -2437,7 +2437,7 @@ print_operand (FILE * file, rtx op, int letter)
else if (letter == 'y')
{
rtx mem_reg = XEXP (op, 0);
- if (GET_CODE (mem_reg) == REG)
+ if (REG_P (mem_reg))
{
register int regnum = REGNO (mem_reg);
fprintf (file, "%s", reg_names[regnum]);
@@ -2522,14 +2522,14 @@ print_operand (FILE * file, rtx op, int letter)
fputs (code == EQ ? "t" : "f", file);
else if (code == CONST
- && ((GET_CODE (XEXP (op, 0)) == REG)
+ && ((REG_P (XEXP (op, 0)))
|| (GET_CODE (XEXP (op, 0)) == UNSPEC)))
{
print_operand (file, XEXP (op, 0), letter);
}
else if (code == CONST
&& (GET_CODE (XEXP (op, 0)) == PLUS)
- && (GET_CODE (XEXP (XEXP (op, 0), 0)) == REG)
+ && (REG_P (XEXP (XEXP (op, 0), 0)))
&& (GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST))
{
print_operand_address (file, XEXP (op, 0));
@@ -3411,7 +3411,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
df_set_regs_ever_live (PIC_OFFSET_TABLE_REGNUM, true);
result = expand_pic_symbol_ref (mode, op1);
- if (TARGET_PIC_DATA_TEXT_REL && GET_CODE (op0) == REG
+ if (TARGET_PIC_DATA_TEXT_REL && REG_P (op0)
&& REGNO (op0) >= FIRST_PSEUDO_REGISTER)
result = force_reg (SImode, result);
@@ -3472,7 +3472,7 @@ int
microblaze_expand_shift (rtx operands[])
{
gcc_assert ((CONST_INT_P (operands[2]))
- || (GET_CODE (operands[2]) == REG)
+ || (REG_P (operands[2]))
|| (GET_CODE (operands[2]) == SUBREG));
/* Shift by one -- generate pattern. */
@@ -3483,9 +3483,9 @@ microblaze_expand_shift (rtx operands[])
if (TARGET_BARREL_SHIFT)
return 0;
- gcc_assert ((GET_CODE (operands[0]) == REG)
+ gcc_assert ((REG_P (operands[0]))
|| (GET_CODE (operands[0]) == SUBREG)
- || (GET_CODE (operands[1]) == REG)
+ || (REG_P (operands[1]))
|| (GET_CODE (operands[1]) == SUBREG));
/* Shift by zero -- copy regs if necessary. */
@@ -3594,7 +3594,7 @@ microblaze_expand_conditional_branch (machine_mode mode, rtx operands[])
rtx comp_reg = gen_reg_rtx (SImode);
rtx condition;
- gcc_assert ((GET_CODE (cmp_op0) == REG) || (GET_CODE (cmp_op0) == SUBREG));
+ gcc_assert ((REG_P (cmp_op0)) || (GET_CODE (cmp_op0) == SUBREG));
/* If comparing against zero, just test source reg. */
if (cmp_op1 == const0_rtx)
@@ -3630,7 +3630,7 @@ microblaze_expand_conditional_branch_reg (machine_mode mode, rtx operands[])
rtx comp_reg = gen_reg_rtx (SImode);
rtx condition;
- gcc_assert ((GET_CODE (cmp_op0) == REG)
+ gcc_assert ((REG_P (cmp_op0))
|| (GET_CODE (cmp_op0) == SUBREG));
/* If comparing against zero, just test source reg. */
diff --git a/gcc/config/microblaze/microblaze.h b/gcc/config/microblaze/microblaze.h
index fa0806e0fd9..5dea2d6f201 100644
--- a/gcc/config/microblaze/microblaze.h
+++ b/gcc/config/microblaze/microblaze.h
@@ -372,7 +372,7 @@ extern enum reg_class microblaze_regno_to_class[];
since they may change into reg + const, which the patterns
can't handle yet. */
#define CALL_INSN_OP(X) (CONSTANT_ADDRESS_P (X) \
- || (GET_CODE (X) == REG && X != arg_pointer_rtx\
+ || (REG_P (X) && X != arg_pointer_rtx\
&& ! (REGNO (X) >= FIRST_PSEUDO_REGISTER \
&& REGNO (X) <= LAST_VIRTUAL_REGISTER)))
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index 39e447ba58f..a4ffb50797f 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -751,8 +751,8 @@
[(set (match_operand:DI 0 "register_operand" "")
(not:DI (match_operand:DI 1 "register_operand" "")))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))"
[(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
(set (subreg:SI (match_dup 0) 4) (not:SI (subreg:SI (match_dup 1) 4)))]
@@ -966,8 +966,8 @@
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO(operands[0]) == (REGNO(operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
@@ -978,8 +978,8 @@
[(set (match_operand:DI 0 "register_operand" "")
(match_operand:DI 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
@@ -1277,8 +1277,8 @@
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO (operands[0]) == (REGNO (operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))
(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))]
@@ -1288,8 +1288,8 @@
[(set (match_operand:DF 0 "register_operand" "")
(match_operand:DF 1 "register_operand" ""))]
"reload_completed
- && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
- && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
+ && REG_P (operands[0]) && GP_REG_P (REGNO (operands[0]))
+ && REG_P (operands[1]) && GP_REG_P (REGNO (operands[1]))
&& (REGNO (operands[0]) != (REGNO (operands[1]) + 1))"
[(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
(set (subreg:SI (match_dup 0) 4) (subreg:SI (match_dup 1) 4))]
@@ -1810,7 +1810,7 @@
(label_ref (match_operand 0 "" "")))]
""
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
return "br%?\t%0";
else
return "bri%?\t%l0";
@@ -1824,7 +1824,7 @@
""
{
rtx dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+ if (!REG_P (dest) || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
@@ -2063,7 +2063,7 @@
XEXP (operands[0], 0) = temp;
}
- if ((GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
+ if ((!REG_P (addr) && !CONSTANT_ADDRESS_P (addr))
|| !call_insn_operand (addr, VOIDmode))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
@@ -2136,7 +2136,7 @@
}
} else if (CONST_INT_P (target))
return "la\t%@,r0,%0\;brald\tr15,%@\;%#";
- else if (GET_CODE (target) == REG)
+ else if (REG_P (target))
return "brald\tr15,%0\;%#";
else {
fprintf (stderr,"Unsupported call insn\n");
@@ -2167,7 +2167,7 @@
XEXP (operands[1], 0) = temp;
}
- if ((GET_CODE (addr) != REG && !CONSTANT_ADDRESS_P (addr))
+ if ((!REG_P (addr) && !CONSTANT_ADDRESS_P (addr))
|| !call_insn_operand (addr, VOIDmode))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
@@ -2251,7 +2251,7 @@
}
else if (CONST_INT_P (target))
return "la\t%@,r0,%1\;brald\tr15,%@\;%#";
- else if (GET_CODE (target) == REG)
+ else if (REG_P (target))
return "brald\tr15,%1\;%#";
else
return "Unsupported call insn\n";
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index 7ee237c556b..10ec60ca70c 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -101,14 +101,14 @@
(define_predicate "call_insn_simple_operand"
(and (match_test "CALL_INSN_OP (op)")
- (match_test "GET_CODE (op) == REG || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
+ (match_test "REG_P (op) || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
;; Return if OPERAND is valid as a source operand for a move instruction.
(define_predicate "move_src_operand"
(and (
not (
and (match_code "plus")
- (not (match_test "(GET_CODE (XEXP (op, 0)) == REG) ^ (GET_CODE (XEXP (op,1)) == REG)"))
+ (not (match_test "(REG_P (XEXP (op, 0))) ^ (REG_P (XEXP (op,1)))"))
)
)
(match_operand 0 "general_operand"))
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 96dff88c77d..e72e0d57a97 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -17087,7 +17087,7 @@ mips_expand_builtin_msa_test_branch (enum insn_code icode, tree exp)
create_fixed_operand (&ops[2], const0_rtx);
/* Make sure that the operand 1 is a REG. */
- if (GET_CODE (ops[1].value) != REG)
+ if (!REG_P (ops[1].value))
ops[1].value = force_reg (ops[1].mode, ops[1].value);
if ((cbranch = maybe_gen_insn (icode, 3, ops)) == NULL_RTX)
diff --git a/gcc/config/mn10300/predicates.md b/gcc/config/mn10300/predicates.md
index 6078d3cf11e..210d7140111 100644
--- a/gcc/config/mn10300/predicates.md
+++ b/gcc/config/mn10300/predicates.md
@@ -31,9 +31,9 @@
(match_code "symbol_ref,reg,unspec")
{
if (flag_pic)
- return (satisfies_constraint_S (op) || GET_CODE (op) == REG);
+ return (satisfies_constraint_S (op) || REG_P (op));
- return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op));
})
(define_predicate "impossible_plus_operand"
diff --git a/gcc/config/moxie/moxie.md b/gcc/config/moxie/moxie.md
index fa750d45401..eb2250fc260 100644
--- a/gcc/config/moxie/moxie.md
+++ b/gcc/config/moxie/moxie.md
@@ -382,9 +382,9 @@
""
"
/* Force the compare operands into registers. */
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
operands[1] = force_reg (SImode, operands[1]);
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = force_reg (SImode, operands[2]);
")
diff --git a/gcc/config/moxie/predicates.md b/gcc/config/moxie/predicates.md
index b7deba669ca..c61ce12ac28 100644
--- a/gcc/config/moxie/predicates.md
+++ b/gcc/config/moxie/predicates.md
@@ -33,7 +33,7 @@
if (MEM_P (op)
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))
&& IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)), -32768, 32767))
return 1;
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index c7f04a0bfa5..d28023b339f 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3167,7 +3167,7 @@ msp430_fixup_compare_operands (machine_mode my_mode, rtx * operands)
if (msp430_reversible_cmp_operator (operands[0], VOIDmode))
const_op_idx = 2;
- if (GET_CODE (operands[const_op_idx]) != REG
+ if (!REG_P (operands[const_op_idx])
&& GET_CODE (operands[const_op_idx]) != MEM)
operands[const_op_idx] = copy_to_mode_reg (my_mode, operands[const_op_idx]);
}
diff --git a/gcc/config/nds32/nds32-fp-as-gp.c b/gcc/config/nds32/nds32-fp-as-gp.c
index 278df99bc74..b8b038aaa7a 100644
--- a/gcc/config/nds32/nds32-fp-as-gp.c
+++ b/gcc/config/nds32/nds32-fp-as-gp.c
@@ -75,7 +75,7 @@ nds32_get_symbol_count (void)
rtx pattern = PATTERN (insn);
rtx mem;
gcc_assert (GET_CODE (pattern) == SET);
- if (GET_CODE (SET_SRC (pattern)) == REG )
+ if (REG_P (SET_SRC (pattern)) )
mem = SET_DEST (pattern);
else
mem = SET_SRC (pattern);
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index 3e6371730d0..1bc365f11ba 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -1486,12 +1486,12 @@ nds32_mem_format (rtx op)
op = XEXP (op, 0);
/* 45 format. */
- if (GET_CODE (op) == REG
+ if (REG_P (op)
&& ((mode_test == SImode) || (mode_test == SFmode)))
return ADDRESS_REG;
/* 333 format for QI/HImode. */
- if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
+ if (REG_P (op) && (REGNO (op) < R8_REGNUM))
return ADDRESS_LO_REG_IMM3U;
/* post_inc 333 format. */
@@ -1517,7 +1517,7 @@ nds32_mem_format (rtx op)
}
if ((GET_CODE (op) == PLUS)
- && (GET_CODE (XEXP (op, 0)) == REG)
+ && (REG_P (XEXP (op, 0)))
&& (CONST_INT_P (XEXP (op, 1))))
{
val = INTVAL (XEXP (op, 1));
diff --git a/gcc/config/nds32/nds32-multiple.md b/gcc/config/nds32/nds32-multiple.md
index 96810fabecd..7a767e7e426 100644
--- a/gcc/config/nds32/nds32-multiple.md
+++ b/gcc/config/nds32/nds32-multiple.md
@@ -59,7 +59,7 @@
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| GET_CODE (operands[1]) != MEM
|| MEM_VOLATILE_P (operands[1])
|| REGNO (operands[0]) + INTVAL (operands[2]) > TA_REGNUM)
@@ -1909,7 +1909,7 @@
|| INTVAL (operands[2]) > maximum
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| MEM_VOLATILE_P (operands[0])
|| REGNO (operands[1]) + INTVAL (operands[2]) > TA_REGNUM)
FAIL;
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index d99a70a2b62..649b34d3c5b 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -73,7 +73,7 @@ nds32_consecutive_registers_load_store_p (rtx op,
elt_mem = load_p ? SET_SRC (elt) : SET_DEST (elt);
/* If elt_reg is not a expected reg rtx, return false. */
- if (GET_CODE (elt_reg) != REG || GET_MODE (elt_reg) != SImode)
+ if (!REG_P (elt_reg) || GET_MODE (elt_reg) != SImode)
return false;
/* If elt_mem is not a expected mem rtx, return false. */
if (GET_CODE (elt_mem) != MEM || GET_MODE (elt_mem) != SImode)
@@ -135,7 +135,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
Note that the form is different between load and store operation. */
if (load_p)
{
- if (GET_CODE (SET_DEST (elt)) != REG
+ if (!REG_P (SET_DEST (elt))
|| GET_CODE (SET_SRC (elt)) != MEM)
return false;
@@ -143,7 +143,7 @@ nds32_valid_multiple_load_store_p (rtx op, bool load_p, bool bim_p)
}
else
{
- if (GET_CODE (SET_SRC (elt)) != REG
+ if (!REG_P (SET_SRC (elt))
|| GET_CODE (SET_DEST (elt)) != MEM)
return false;
@@ -303,7 +303,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
- || GET_CODE (elt_reg) != REG
+ || !REG_P (elt_reg)
|| REGNO (elt_reg) != FP_REGNUM)
return false;
}
@@ -315,7 +315,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
- || GET_CODE (elt_reg) != REG
+ || !REG_P (elt_reg)
|| REGNO (elt_reg) != GP_REGNUM)
return false;
}
@@ -327,7 +327,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
index++;
if (GET_CODE (elt_mem) != MEM
- || GET_CODE (elt_reg) != REG
+ || !REG_P (elt_reg)
|| REGNO (elt_reg) != LP_REGNUM)
return false;
}
@@ -346,7 +346,7 @@ nds32_valid_stack_push_pop_p (rtx op, bool push_p)
elt_plus = SET_SRC (elt);
/* Check this is (set (stack_reg) (plus stack_reg const)) pattern. */
- if (GET_CODE (elt_reg) != REG
+ if (!REG_P (elt_reg)
|| GET_CODE (elt_plus) != PLUS
|| REGNO (elt_reg) != SP_REGNUM)
return false;
diff --git a/gcc/config/nds32/nds32-relax-opt.c b/gcc/config/nds32/nds32-relax-opt.c
index 5da27530cd6..873dc5260ec 100644
--- a/gcc/config/nds32/nds32-relax-opt.c
+++ b/gcc/config/nds32/nds32-relax-opt.c
@@ -110,7 +110,7 @@ nds32_reg_base_load_store_p (rtx_insn *insn)
|| (GET_CODE (mem_src) == SIGN_EXTEND))
mem_src = XEXP (mem_src, 0);
- if (GET_CODE (XEXP (mem_src, 0)) == REG)
+ if (REG_P (XEXP (mem_src, 0)))
return true;
}
@@ -185,7 +185,7 @@ nds32_plus_reg_load_store_p (rtx_insn *insn)
else
return false;
- if (GET_CODE (XEXP (mem_src, 0)) == REG)
+ if (REG_P (XEXP (mem_src, 0)))
return true;
}
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index 5b1dfedf30d..44d2ad83e9f 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -1440,7 +1440,7 @@ nds32_address_register_rtx_p (rtx x, bool strict)
{
int regno;
- if (GET_CODE (x) != REG)
+ if (!REG_P (x))
return false;
regno = REGNO (x);
@@ -2575,7 +2575,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (GET_CODE (x) == POST_MODIFY
&& mode == DFmode)
{
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == PLUS)
{
rtx plus_op = XEXP (x, 1);
@@ -2629,7 +2629,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
}
/* Now check [reg], [symbol_ref], and [const]. */
- if (GET_CODE (x) != REG
+ if (!REG_P (x)
&& GET_CODE (x) != SYMBOL_REF
&& GET_CODE (x) != CONST)
return false;
@@ -2719,7 +2719,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
=> [Ra], Rb */
/* (mem (post_modify (reg) (plus (reg) (const_int))))
=> [Ra], const_int */
- if (GET_CODE (XEXP (x, 0)) == REG
+ if (REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == PLUS)
{
rtx plus_op = XEXP (x, 1);
diff --git a/gcc/config/nios2/predicates.md b/gcc/config/nios2/predicates.md
index a1c4ca795d7..4ad337ddde3 100644
--- a/gcc/config/nios2/predicates.md
+++ b/gcc/config/nios2/predicates.md
@@ -157,5 +157,5 @@
(match_code "mem")
{
/* ldex/ldsex/stex/stsex cannot handle memory addresses with offsets. */
- return GET_CODE (XEXP (op, 0)) == REG;
+ return REG_P (XEXP (op, 0));
})
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index ff5bfedd06d..6795fc393fd 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -1101,7 +1101,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* Special case. Get the SYMBOL_REF into a register and use indexing.
That should always be safe. */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
{
rtx reg = force_reg (Pmode, XEXP (x, 1));
@@ -1114,7 +1114,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
&& CONST_INT_P (XEXP (x, 1))
&& ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
&& !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
- || GET_CODE (XEXP (x, 0)) == REG))
+ || REG_P (XEXP (x, 0))))
{
rtx int_part, ptr_reg;
int newoffset;
@@ -1180,11 +1180,11 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
rtx reg1, reg2;
reg1 = XEXP (x, 1);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
reg2 = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
return force_reg (Pmode,
@@ -1221,15 +1221,15 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* Make sure they're both regs. If one was a SYMBOL_REF [+ const],
then pa_emit_move_sequence will turn on REG_POINTER so we'll know
it's a base register below. */
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
/* Figure out what the base and index are. */
- if (GET_CODE (reg1) == REG
+ if (REG_P (reg1)
&& REG_POINTER (reg1))
{
base = reg1;
@@ -1239,7 +1239,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
GEN_INT (shift_val)),
XEXP (x, 1));
}
- else if (GET_CODE (reg2) == REG
+ else if (REG_P (reg2)
&& REG_POINTER (reg2))
{
base = reg2;
@@ -1261,7 +1261,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
val /= (1 << shift_val);
reg1 = XEXP (XEXP (idx, 0), 0);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
reg1 = force_reg (Pmode, gen_rtx_PLUS (Pmode, reg1, GEN_INT (val)));
@@ -1300,12 +1300,12 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
/* First get A into a register. */
reg1 = XEXP (XEXP (idx, 0), 0);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
/* And get B into a register. */
reg2 = XEXP (idx, 1);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
reg1 = force_reg (Pmode,
@@ -1371,11 +1371,11 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
rtx reg1, reg2;
reg1 = XEXP (x, 1);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
reg1 = force_reg (Pmode, force_operand (reg1, 0));
reg2 = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
reg2 = force_reg (Pmode, force_operand (reg2, 0));
return
@@ -1403,7 +1403,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
= force_reg (Pmode, GEN_INT (INTVAL (XEXP (y, 1))
/ INTVAL (XEXP (XEXP (x, 0), 1))));
regx2 = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (regx2) != REG)
+ if (!REG_P (regx2))
regx2 = force_reg (Pmode, force_operand (regx2, 0));
regx2 = force_reg (Pmode, gen_rtx_fmt_ee (GET_CODE (y), Pmode,
regx2, regx1));
@@ -1666,12 +1666,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
copy_to_mode_reg (Pmode, XEXP (operand1, 0)));
if (scratch_reg
- && reload_in_progress && GET_CODE (operand0) == REG
+ && reload_in_progress && REG_P (operand0)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
operand0 = reg_equiv_mem (REGNO (operand0));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand0) == SUBREG
- && GET_CODE (SUBREG_REG (operand0)) == REG
+ && REG_P (SUBREG_REG (operand0))
&& REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -1683,12 +1683,12 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
}
if (scratch_reg
- && reload_in_progress && GET_CODE (operand1) == REG
+ && reload_in_progress && REG_P (operand1)
&& REGNO (operand1) >= FIRST_PSEUDO_REGISTER)
operand1 = reg_equiv_mem (REGNO (operand1));
else if (scratch_reg
&& reload_in_progress && GET_CODE (operand1) == SUBREG
- && GET_CODE (SUBREG_REG (operand1)) == REG
+ && REG_P (SUBREG_REG (operand1))
&& REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER)
{
/* We must not alter SUBREG_BYTE (operand0) since that would confuse
@@ -1852,7 +1852,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
/* Handle secondary reloads for SAR. These occur when trying to load
the SAR from memory or a constant. */
else if (scratch_reg
- && GET_CODE (operand0) == REG
+ && REG_P (operand0)
&& REGNO (operand0) < FIRST_PSEUDO_REGISTER
&& REGNO_REG_CLASS (REGNO (operand0)) == SHIFT_REGS
&& (GET_CODE (operand1) == MEM || CONST_INT_P (operand1)))
@@ -2137,7 +2137,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
safe to be used as the base in an indexed address.
Don't mark hard registers though. That loses. */
- if (GET_CODE (operand0) == REG
+ if (REG_P (operand0)
&& REGNO (operand0) >= FIRST_PSEUDO_REGISTER)
mark_reg_pointer (operand0, BITS_PER_UNIT);
if (REGNO (temp) >= FIRST_PSEUDO_REGISTER)
@@ -2568,8 +2568,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
operands[0] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[1])
+ && REG_P (operands[0]));
gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
@@ -2585,8 +2585,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[1], 0);
operands[0] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[1])
+ && REG_P (operands[0]));
gcc_assert (!reg_overlap_mentioned_p (high_reg, addr));
/* No overlap between high target register and address
@@ -2608,8 +2608,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
operands[1] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[0]) == REG
- && GET_CODE (operands[1]) == REG);
+ gcc_assert (REG_P (operands[0])
+ && REG_P (operands[1]));
if (!reg_overlap_mentioned_p (high_reg, addr))
{
@@ -2635,8 +2635,8 @@ pa_output_move_double (rtx *operands)
rtx high_reg = gen_rtx_SUBREG (SImode, operands[0], 0);
operands[1] = XEXP (addr, 0);
- gcc_assert (GET_CODE (operands[0]) == REG
- && GET_CODE (operands[1]) == REG);
+ gcc_assert (REG_P (operands[0])
+ && REG_P (operands[1]));
if (!reg_overlap_mentioned_p (high_reg, addr))
{
@@ -2815,7 +2815,7 @@ pa_output_fp_move_double (rtx *operands)
arbitrary address here including pre/post increment/decrement.
so avoid this in the MD. */
- gcc_assert (GET_CODE (operands[0]) == REG);
+ gcc_assert (REG_P (operands[0]));
xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
xoperands[0] = operands[0];
@@ -2832,9 +2832,9 @@ find_addr_reg (rtx addr)
{
while (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
addr = XEXP (addr, 0);
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
addr = XEXP (addr, 1);
else if (CONSTANT_P (XEXP (addr, 0)))
addr = XEXP (addr, 1);
@@ -2843,7 +2843,7 @@ find_addr_reg (rtx addr)
else
gcc_unreachable ();
}
- gcc_assert (GET_CODE (addr) == REG);
+ gcc_assert (REG_P (addr));
return addr;
}
@@ -3458,7 +3458,7 @@ remove_useless_addtr_insns (int check_notes)
/* If the destination is CCFP, then we've found an fcmp insn. */
tmp = SET_DEST (tmp);
- if (GET_CODE (tmp) == REG && REGNO (tmp) == 0)
+ if (REG_P (tmp) && REGNO (tmp) == 0)
{
fcmp_count++;
continue;
@@ -3470,7 +3470,7 @@ remove_useless_addtr_insns (int check_notes)
&& SET_DEST (tmp) == pc_rtx
&& GET_CODE (SET_SRC (tmp)) == IF_THEN_ELSE
&& GET_CODE (XEXP (SET_SRC (tmp), 0)) == NE
- && GET_CODE (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == REG
+ && REG_P (XEXP (XEXP (SET_SRC (tmp), 0), 0))
&& REGNO (XEXP (XEXP (SET_SRC (tmp), 0), 0)) == 0)
{
fbranch_count++;
@@ -3498,7 +3498,7 @@ remove_useless_addtr_insns (int check_notes)
/* The destination must be CCFP, which is register zero. */
tmp = SET_DEST (tmp);
- if (GET_CODE (tmp) != REG || REGNO (tmp) != 0)
+ if (!REG_P (tmp) || REGNO (tmp) != 0)
continue;
/* INSN should be a set of CCFP.
@@ -3516,7 +3516,7 @@ remove_useless_addtr_insns (int check_notes)
/* As does another fcmp insn. */
if (NONJUMP_INSN_P (next)
&& GET_CODE (PATTERN (next)) == SET
- && GET_CODE (SET_DEST (PATTERN (next))) == REG
+ && REG_P (SET_DEST (PATTERN (next)))
&& REGNO (SET_DEST (PATTERN (next))) == 0)
break;
@@ -3535,7 +3535,7 @@ remove_useless_addtr_insns (int check_notes)
&& SET_DEST (pattern) == pc_rtx
&& GET_CODE (SET_SRC (pattern)) == IF_THEN_ELSE
&& GET_CODE (XEXP (SET_SRC (pattern), 0)) == NE
- && GET_CODE (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == REG
+ && REG_P (XEXP (XEXP (SET_SRC (pattern), 0), 0))
&& REGNO (XEXP (XEXP (SET_SRC (pattern), 0), 0)) == 0
&& GET_CODE (XEXP (SET_SRC (pattern), 1)) == PC
&& (fcmp_count == fbranch_count
@@ -5087,7 +5087,7 @@ pa_adjust_insn_length (rtx_insn *insn, int length)
general register register. */
else if (GET_CODE (pat) == PARALLEL
&& GET_CODE (XVECEXP (pat, 0, 1)) == SET
- && GET_CODE (XEXP (XVECEXP (pat, 0, 1), 0)) == REG
+ && REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
&& ! FP_REG_P (XEXP (XVECEXP (pat, 0, 1), 0))
&& length == 4
&& ! forward_branch_p (insn))
@@ -5371,8 +5371,8 @@ pa_print_operand (FILE *file, rtx x, int code)
fputs (",ma", file);
break;
case PLUS:
- if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
+ if (REG_P (XEXP (XEXP (x, 0), 0))
+ && REG_P (XEXP (XEXP (x, 0), 1)))
{
if (ASSEMBLER_DIALECT == 0)
fputs ("x", file);
@@ -5424,7 +5424,7 @@ pa_print_operand (FILE *file, rtx x, int code)
default:
gcc_unreachable ();
}
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
fputs (reg_names [REGNO (x)], file);
if (TARGET_64BIT && FP_REG_P (x) && GET_MODE_SIZE (GET_MODE (x)) <= 4)
@@ -5462,8 +5462,8 @@ pa_print_operand (FILE *file, rtx x, int code)
fprintf (file, "%s(%s)",
reg_names [REGNO (XEXP (XEXP (XEXP (x, 0), 1), 0))],
reg_names [REGNO (XEXP (XEXP (x, 0), 0))]);
- else if (GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
- && GET_CODE (XEXP (XEXP (x, 0), 1)) == REG)
+ else if (REG_P (XEXP (XEXP (x, 0), 0))
+ && REG_P (XEXP (XEXP (x, 0), 1)))
{
/* Because the REG_POINTER flag can get lost during reload,
pa_legitimate_address_p canonicalizes the order of the
@@ -5978,7 +5978,7 @@ pa_output_arg_descriptor (rtx_insn *call_insn)
rtx use = XEXP (link, 0);
if (! (GET_CODE (use) == USE
- && GET_CODE (XEXP (use, 0)) == REG
+ && REG_P (XEXP (use, 0))
&& FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
continue;
@@ -7612,7 +7612,7 @@ copy_fp_args (rtx_insn *insn)
rtx use = XEXP (link, 0);
if (! (GET_CODE (use) == USE
- && GET_CODE (XEXP (use, 0)) == REG
+ && REG_P (XEXP (use, 0))
&& FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
continue;
@@ -7655,7 +7655,7 @@ length_fp_args (rtx_insn *insn)
rtx use = XEXP (link, 0);
if (! (GET_CODE (use) == USE
- && GET_CODE (XEXP (use, 0)) == REG
+ && REG_P (XEXP (use, 0))
&& FUNCTION_ARG_REGNO_P (REGNO (XEXP (use, 0)))))
continue;
@@ -8674,11 +8674,11 @@ pa_fmpyaddoperands (rtx *operands)
return 0;
/* All operands must be registers. */
- if (! (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[2]) == REG
- && GET_CODE (operands[3]) == REG
- && GET_CODE (operands[4]) == REG
- && GET_CODE (operands[5]) == REG))
+ if (! (REG_P (operands[1])
+ && REG_P (operands[2])
+ && REG_P (operands[3])
+ && REG_P (operands[4])
+ && REG_P (operands[5])))
return 0;
/* Only 2 real operands to the addition. One of the input operands must
@@ -8852,11 +8852,11 @@ pa_fmpysuboperands (rtx *operands)
return 0;
/* All operands must be registers. */
- if (! (GET_CODE (operands[1]) == REG
- && GET_CODE (operands[2]) == REG
- && GET_CODE (operands[3]) == REG
- && GET_CODE (operands[4]) == REG
- && GET_CODE (operands[5]) == REG))
+ if (! (REG_P (operands[1])
+ && REG_P (operands[2])
+ && REG_P (operands[3])
+ && REG_P (operands[4])
+ && REG_P (operands[5])))
return 0;
/* Only 2 real operands to the subtraction. Subtraction is not a commutative
@@ -10616,7 +10616,7 @@ pa_legitimize_reload_address (rtx ad, machine_mode mode,
if (optimize
&& GET_CODE (new_rtx) == PLUS
- && GET_CODE (XEXP (new_rtx, 0)) == REG
+ && REG_P (XEXP (new_rtx, 0))
&& CONST_INT_P (XEXP (new_rtx, 1)))
{
offset = INTVAL (XEXP ((new_rtx), 1));
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 0ce8b635411..01c778368cd 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -6953,7 +6953,7 @@
""
"
{
- if (GET_CODE (operands[0]) != REG)
+ if (!REG_P (operands[0]))
operands[0] = force_reg (SImode, operands[0]);
if (operands[1] != const0_rtx)
@@ -9668,7 +9668,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
}
operands[2] = gen_reg_rtx (SImode);
- if (GET_CODE (operands[1]) != REG)
+ if (!REG_P (operands[1]))
{
rtx tmp = gen_reg_rtx (Pmode);
emit_move_insn (tmp, operands[1]);
diff --git a/gcc/config/pdp11/pdp11.c b/gcc/config/pdp11/pdp11.c
index 4fcd9ed33d5..7a3e24a1b1f 100644
--- a/gcc/config/pdp11/pdp11.c
+++ b/gcc/config/pdp11/pdp11.c
@@ -797,7 +797,7 @@ pdp11_asm_print_operand (FILE *file, rtx x, int code)
else
fprintf (file, "@");
}
- else if (GET_CODE (x) == REG)
+ else if (REG_P (x))
fprintf (file, "%s", reg_names[REGNO (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
@@ -879,17 +879,17 @@ print_operand_address (FILE *file, register rtx addr)
}
if (GET_CODE (addr) != PLUS)
;
- else if (GET_CODE (XEXP (addr, 0)) == REG)
+ else if (REG_P (XEXP (addr, 0)))
{
breg = XEXP (addr, 0);
addr = XEXP (addr, 1);
}
- else if (GET_CODE (XEXP (addr, 1)) == REG)
+ else if (REG_P (XEXP (addr, 1)))
{
breg = XEXP (addr, 1);
addr = XEXP (addr, 0);
}
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
gcc_assert (breg == 0);
breg = addr;
@@ -904,7 +904,7 @@ print_operand_address (FILE *file, register rtx addr)
output_addr_const_pdp11 (file, addr);
if (breg != 0)
{
- gcc_assert (GET_CODE (breg) == REG);
+ gcc_assert (REG_P (breg));
fprintf (file, "(%s)", reg_names[REGNO (breg)]);
}
break;
@@ -1143,7 +1143,7 @@ pdp11_addr_cost (rtx addr, machine_mode mode, addr_space_t as ATTRIBUTE_UNUSED,
{
int cost = 0;
- if (GET_CODE (addr) != REG)
+ if (!REG_P (addr))
{
if (!simple_memory_operand (addr, mode))
cost = 2;
@@ -1376,7 +1376,7 @@ simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
-- except for @(R0), which has to be @0(R0) !!! */
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
return 0;
op=addr;
@@ -1433,7 +1433,7 @@ no_side_effect_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED)
-- except for @(R0), which has to be @0(R0) !!! */
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
return 0;
op=addr;
@@ -1587,7 +1587,7 @@ pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED,
machine_mode reload_mode ATTRIBUTE_UNUSED,
secondary_reload_info *sri ATTRIBUTE_UNUSED)
{
- if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG ||
+ if (reload_class != NO_LOAD_FPU_REGS || !REG_P (x) ||
REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS)
return NO_REGS;
@@ -1634,36 +1634,36 @@ pdp11_legitimate_address_p (machine_mode mode,
case PLUS:
/* accept X(R0) */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))))
&& CONSTANT_ADDRESS_P (XEXP (operand, 1));
case PRE_DEC:
/* accept -(R0) */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
case POST_INC:
/* accept (R0)+ */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0))));
case PRE_MODIFY:
/* accept -(SP) -- which uses PRE_MODIFY for byte mode */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
&& GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
- && GET_CODE (XEXP (xfoob, 0)) == REG
+ && REG_P (XEXP (xfoob, 0))
&& REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
&& CONST_INT_P (XEXP (xfoob, 1))
&& INTVAL (XEXP (xfoob,1)) == -2;
case POST_MODIFY:
/* accept (SP)+ -- which uses POST_MODIFY for byte mode */
- return GET_CODE (XEXP (operand, 0)) == REG
+ return REG_P (XEXP (operand, 0))
&& REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM
&& GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS
- && GET_CODE (XEXP (xfoob, 0)) == REG
+ && REG_P (XEXP (xfoob, 0))
&& REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM
&& CONST_INT_P (XEXP (xfoob, 1))
&& INTVAL (XEXP (xfoob,1)) == 2;
@@ -1694,18 +1694,18 @@ pdp11_legitimate_address_p (machine_mode mode,
case PLUS:
/* accept @X(R0) */
- return GET_CODE (XEXP (xfoob, 0)) == REG
+ return REG_P (XEXP (xfoob, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))))
&& CONSTANT_ADDRESS_P (XEXP (xfoob, 1));
case PRE_DEC:
/* accept @-(R0) */
- return GET_CODE (XEXP (xfoob, 0)) == REG
+ return REG_P (XEXP (xfoob, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
case POST_INC:
/* accept @(R0)+ */
- return GET_CODE (XEXP (xfoob, 0)) == REG
+ return REG_P (XEXP (xfoob, 0))
&& (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0))));
default:
diff --git a/gcc/config/pdp11/pdp11.md b/gcc/config/pdp11/pdp11.md
index 3b3815d19aa..e60e9f7d580 100644
--- a/gcc/config/pdp11/pdp11.md
+++ b/gcc/config/pdp11/pdp11.md
@@ -611,7 +611,7 @@
(match_dup 1))
(clobber (reg:CC FCC_REGNUM))])]
"{
- if (GET_CODE (operands[1]) == REG &&
+ if (REG_P (operands[1]) &&
REGNO_REG_CLASS (REGNO (operands[1])) == LOAD_FPU_REGS)
FAIL;
}"
@@ -777,8 +777,8 @@
[(parallel [(set (match_dup 0) (float_truncate:SF (match_dup 1)))
(clobber (reg:CC FCC_REGNUM))])]
"{
- if (GET_CODE (operands[0]) == REG &&
- GET_CODE (operands[1]) == REG &&
+ if (REG_P (operands[0]) &&
+ REG_P (operands[1]) &&
REGNO (operands[0]) == REGNO (operands[1]))
FAIL;
}"
@@ -852,8 +852,8 @@
[(parallel [(set (match_dup 0) (float_extend:DF (match_dup 1)))
(clobber (reg:CC FCC_REGNUM))])]
"{
- if (GET_CODE (operands[0]) == REG &&
- GET_CODE (operands[1]) == REG &&
+ if (REG_P (operands[0]) &&
+ REG_P (operands[1]) &&
REGNO (operands[0]) == REGNO (operands[1]))
FAIL;
}"
diff --git a/gcc/config/pru/predicates.md b/gcc/config/pru/predicates.md
index 568d6f3fa91..a14c77373fc 100644
--- a/gcc/config/pru/predicates.md
+++ b/gcc/config/pru/predicates.md
@@ -198,7 +198,7 @@
/* Perform a quick check so we don't blow up below. */
if (GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return false;
@@ -207,7 +207,7 @@
elt_mode = GET_MODE (SET_DEST (XVECEXP (op, 0, 0)));
base_reg = strip_offset (src_addr, &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
return false;
for (i = 1; i < count; i++)
@@ -217,7 +217,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| REGNO (SET_DEST (elt)) != dest_regno + i * GET_MODE_SIZE (elt_mode)
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -226,7 +226,7 @@
elt_reg = strip_offset (XEXP (SET_SRC (elt), 0), &elt_offs);
- if (GET_CODE (elt_reg) != REG
+ if (!REG_P (elt_reg)
|| ! rtx_equal_p (elt_reg, base_reg)
|| elt_offs != base_offs + i * GET_MODE_SIZE (elt_mode))
return false;
@@ -251,7 +251,7 @@
/* Perform a quick check so we don't blow up below. */
if (GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -259,7 +259,7 @@
elt_mode = GET_MODE (SET_SRC (XVECEXP (op, 0, 0)));
base_reg = strip_offset (dest_addr, &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
return false;
for (i = 1; i < count; i++)
@@ -269,7 +269,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| REGNO (SET_SRC (elt)) != src_regno + i * GET_MODE_SIZE (elt_mode)
|| GET_CODE (SET_DEST (elt)) != MEM
@@ -278,7 +278,7 @@
elt_reg = strip_offset (XEXP (SET_DEST (elt), 0), &elt_offs);
- if (GET_CODE (elt_reg) != REG
+ if (!REG_P (elt_reg)
|| ! rtx_equal_p (elt_reg, base_reg)
|| elt_offs != base_offs + i * GET_MODE_SIZE (elt_mode))
return false;
diff --git a/gcc/config/pru/pru.c b/gcc/config/pru/pru.c
index 0cae5c5cfb7..971428e65bc 100644
--- a/gcc/config/pru/pru.c
+++ b/gcc/config/pru/pru.c
@@ -1090,7 +1090,7 @@ pru_output_ltle_signed_cbranch (rtx *operands, bool is_near)
op1 = operands[1];
op2 = operands[2];
- gcc_assert (GET_CODE (op1) == REG && GET_CODE (op2) == REG);
+ gcc_assert (REG_P (op1) && REG_P (op2));
/* Determine the comparison operators for positive and negative operands. */
if (code == LT)
@@ -1147,7 +1147,7 @@ pru_output_gtge_signed_cbranch (rtx *operands, bool is_near)
op1 = operands[1];
op2 = operands[2];
- gcc_assert (GET_CODE (op1) == REG && GET_CODE (op2) == REG);
+ gcc_assert (REG_P (op1) && REG_P (op2));
/* Determine the comparison operators for positive and negative operands. */
if (code == GT)
diff --git a/gcc/config/pru/pru.md b/gcc/config/pru/pru.md
index 03527d7def8..c1cb98f5001 100644
--- a/gcc/config/pru/pru.md
+++ b/gcc/config/pru/pru.md
@@ -232,7 +232,7 @@
memory. */
if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[1]) != MEM
- || GET_CODE (operands[0]) != REG)
+ || !REG_P (operands[0]))
FAIL;
count = INTVAL (operands[2]);
@@ -246,7 +246,7 @@
gcc_assert (!can_create_pseudo_p ());
base_reg = strip_offset (XEXP (operands[1], 0), &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
FAIL;
for (i = 0; i < count; i++)
@@ -290,7 +290,7 @@
memory. */
if (!CONST_INT_P (operands[2])
|| GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG)
+ || !REG_P (operands[1]))
FAIL;
count = INTVAL (operands[2]);
@@ -304,7 +304,7 @@
gcc_assert (!can_create_pseudo_p ());
base_reg = strip_offset (XEXP (operands[0], 0), &base_offs);
- if (GET_CODE (base_reg) != REG)
+ if (!REG_P (base_reg))
FAIL;
for (i = 0; i < count; i++)
@@ -945,7 +945,7 @@
(use (label_ref (match_operand 1 "")))]
"TARGET_OPT_LOOP"
{
- if (GET_CODE (operands[0]) == REG && GET_MODE (operands[0]) == QImode)
+ if (REG_P (operands[0]) && GET_MODE (operands[0]) == QImode)
FAIL;
pru_emit_doloop (operands, 1);
DONE;
diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 40faf0e0380..6cc134df900 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -64,7 +64,7 @@
(define_memory_constraint "A"
"An address that is held in a general-purpose register."
(and (match_code "mem")
- (match_test "GET_CODE(XEXP(op,0)) == REG")))
+ (match_test "REG_P (XEXP(op,0))")))
(define_constraint "S"
"@internal
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index ada45f5bf54..f3f7ecb4b22 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -931,7 +931,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
&& XINT (x, 1) == UNS_ES_ADDR)
x = XVECEXP (x, 0, 1);
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
*base = x;
return true;
@@ -955,7 +955,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
{
if (GET_MODE (*base) == HImode
&& GET_MODE (XEXP (*base, 0)) == SImode
- && GET_CODE (XEXP (*base, 0)) == REG)
+ && REG_P (XEXP (*base, 0)))
{
/* This is a throw-away rtx just to tell everyone
else what effective register we're using. */
@@ -963,19 +963,19 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
}
}
- if (GET_CODE (*base) != REG
- && GET_CODE (x) == REG)
+ if (!REG_P (*base)
+ && REG_P (x))
{
rtx tmp = *base;
*base = x;
x = tmp;
}
- if (GET_CODE (*base) != REG)
+ if (!REG_P (*base))
return false;
if (GET_CODE (x) == ZERO_EXTEND
- && GET_CODE (XEXP (x, 0)) == REG)
+ && REG_P (XEXP (x, 0)))
{
*index = XEXP (x, 0);
return false;
@@ -1038,12 +1038,12 @@ rl78_hl_b_c_addr_p (rtx op)
hl = bc;
bc = tmp;
}
- if (GET_CODE (hl) != REG)
+ if (!REG_P (hl))
return false;
if (GET_CODE (bc) != ZERO_EXTEND)
return false;
bc = XEXP (bc, 0);
- if (GET_CODE (bc) != REG)
+ if (!REG_P (bc))
return false;
if (REGNO (hl) != HL_REG)
return false;
@@ -1182,10 +1182,10 @@ rl78_as_legitimate_address (machine_mode mode ATTRIBUTE_UNUSED, rtx x,
return false;
}
- if (strict && base && GET_CODE (base) == REG && REGNO (base) >= FIRST_PSEUDO_REGISTER)
+ if (strict && base && REG_P (base) && REGNO (base) >= FIRST_PSEUDO_REGISTER)
return false;
- if (! cfun->machine->virt_insns_ok && base && GET_CODE (base) == REG
+ if (! cfun->machine->virt_insns_ok && base && REG_P (base)
&& REGNO (base) >= 8 && REGNO (base) <= 31)
return false;
@@ -1233,7 +1233,7 @@ rl78_addr_space_convert (rtx op, tree from_type, tree to_type)
warning (OPT_Waddress, "converting far pointer to near pointer");
result = gen_reg_rtx (HImode);
if (GET_CODE (op) == SYMBOL_REF
- || (GET_CODE (op) == REG && REGNO (op) >= FIRST_PSEUDO_REGISTER))
+ || (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
tmp = gen_rtx_raw_SUBREG (HImode, op, 0);
else
tmp = simplify_subreg (HImode, op, SImode, 0);
@@ -1873,13 +1873,13 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
rl78_print_operand_1 (file, XEXP (op, 0), letter);
}
else if (GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == REG
+ && REG_P (XEXP (XEXP (op, 0), 0))
&& REGNO (XEXP (XEXP (op, 0), 0)) == 2)
{
rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 1), 'u');
fprintf (file, "[");
rl78_print_operand_1 (file, XEXP (XEXP (op, 0), 0), 0);
- if (letter == 'p' && GET_CODE (XEXP (op, 0)) == REG)
+ if (letter == 'p' && REG_P (XEXP (op, 0)))
fprintf (file, "+0");
fprintf (file, "]");
}
@@ -1979,7 +1979,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
break;
case ZERO_EXTEND:
- if (GET_CODE (XEXP (op, 0)) == REG)
+ if (REG_P (XEXP (op, 0)))
fprintf (file, "%s", reg_names [REGNO (XEXP (op, 0))]);
else
print_rtl (file, op);
@@ -2269,7 +2269,7 @@ rl78_peep_movhi_p (rtx *operands)
/* You can move a constant to memory as QImode, but not HImode. */
if (GET_CODE (operands[0]) == MEM
- && GET_CODE (operands[1]) != REG)
+ && !REG_P (operands[1]))
{
#if DEBUG_PEEP
fprintf (stderr, "no peep: move constant to memory\n");
@@ -2812,7 +2812,7 @@ insn_ok_now (rtx_insn * insn)
static inline bool
is_virtual_register (rtx r)
{
- return (GET_CODE (r) == REG
+ return (REG_P (r)
&& REGNO (r) >= 8
&& REGNO (r) < 32);
}
@@ -3643,7 +3643,7 @@ rl78_alloc_address_registers_macax (rtx_insn * insn)
OP (op) = transcode_memory_rtx (OP (op), HL, insn);
if (op == 2
&& MEM_P (OP (op))
- && ((GET_CODE (XEXP (OP (op), 0)) == REG
+ && ((REG_P (XEXP (OP (op), 0))
&& REGNO (XEXP (OP (op), 0)) == SP_REG)
|| (GET_CODE (XEXP (OP (op), 0)) == PLUS
&& REGNO (XEXP (XEXP (OP (op), 0), 0)) == SP_REG)))
@@ -3904,7 +3904,7 @@ rl78_note_reg_set (char *dead, rtx d, rtx insn)
if (GET_CODE (d) == MEM)
rl78_note_reg_uses (dead, XEXP (d, 0), insn);
- if (GET_CODE (d) != REG)
+ if (!REG_P (d))
return;
/* Do not mark the reg unused unless all QImode parts of it are dead. */
@@ -4030,11 +4030,11 @@ set_origin (rtx pat, rtx_insn * insn, int * origins, int * age)
int mb = GET_MODE_SIZE (GET_MODE (dest));
int i;
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int dr = REGNO (dest);
- if (GET_CODE (src) == REG)
+ if (REG_P (src))
{
int sr = REGNO (src);
bool same = true;
@@ -4173,7 +4173,7 @@ set_origin (rtx pat, rtx_insn * insn, int * origins, int * age)
{
rtx count = XEXP (src, 1);
- if (GET_CODE (count) == REG)
+ if (REG_P (count))
{
/* Special case - our pattern clobbers the count register. */
int r = REGNO (count);
@@ -4245,7 +4245,7 @@ rl78_propogate_register_origins (void)
rtx clobber = XVECEXP (pat, 0, 1);
pat = XVECEXP (pat, 0, 0);
if (GET_CODE (clobber) == CLOBBER
- && GET_CODE (XEXP (clobber, 0)) == REG)
+ && REG_P (XEXP (clobber, 0)))
{
int cr = REGNO (XEXP (clobber, 0));
int mb = GET_MODE_SIZE (GET_MODE (XEXP (clobber, 0)));
@@ -4271,7 +4271,7 @@ rl78_propogate_register_origins (void)
set_origin (pat, insn, origins, age);
}
else if (GET_CODE (pat) == CLOBBER
- && GET_CODE (XEXP (pat, 0)) == REG)
+ && REG_P (XEXP (pat, 0)))
{
if (REG_P (XEXP (pat, 0)))
{
@@ -4302,7 +4302,7 @@ rl78_remove_unused_sets (void)
dest = SET_DEST (set);
- if (GET_CODE (dest) != REG || REGNO (dest) > 23)
+ if (!REG_P (dest) || REGNO (dest) > 23)
continue;
if (find_regno_note (insn, REG_UNUSED, REGNO (dest)))
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index 905d3054de2..ea04eb6b836 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -120,7 +120,7 @@ rx_pid_data_operand (rtx op)
return PID_NOT_PID;
if (GET_CODE (op) == PLUS
- && GET_CODE (XEXP (op, 0)) == REG
+ && REG_P (XEXP (op, 0))
&& GET_CODE (XEXP (op, 1)) == CONST
&& GET_CODE (XEXP (XEXP (op, 1), 0)) == UNSPEC)
return PID_ENCODED;
diff --git a/gcc/config/rx/rx.md b/gcc/config/rx/rx.md
index 7065be69e43..3060e59cbc6 100644
--- a/gcc/config/rx/rx.md
+++ b/gcc/config/rx/rx.md
@@ -578,7 +578,7 @@
operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
operands[0] = rx_maybe_pidify_operand (operands[0], 0);
operands[1] = rx_maybe_pidify_operand (operands[1], 0);
- if (GET_CODE (operands[0]) != REG
+ if (!REG_P (operands[0])
&& GET_CODE (operands[1]) == PLUS)
operands[1] = copy_to_mode_reg (<register_modes:MODE>mode, operands[1]);
if (GET_CODE (operands[1]) == PLUS && GET_MODE (operands[1]) == SImode)
diff --git a/gcc/config/s390/predicates.md b/gcc/config/s390/predicates.md
index 15758fb731a..aec2de30219 100644
--- a/gcc/config/s390/predicates.md
+++ b/gcc/config/s390/predicates.md
@@ -244,7 +244,7 @@
uneq, unlt, ungt, unle, unge, ltgt,
unordered, ordered")
{
- if (GET_CODE (XEXP (op, 0)) != REG
+ if (!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM
|| (XEXP (op, 1) != const0_rtx
&& !(CONST_INT_P (XEXP (op, 1))
@@ -296,7 +296,7 @@
if (!COMPARISON_P (op))
return false;
- if (GET_CODE (XEXP (op, 0)) != REG
+ if (!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM
|| (XEXP (op, 1) != const0_rtx
&& !(CONST_INT_P (XEXP (op, 1))
@@ -345,7 +345,7 @@
if (!COMPARISON_P (op))
return false;
- if (GET_CODE (XEXP (op, 0)) != REG
+ if (!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM
|| XEXP (op, 1) != const0_rtx)
return false;
@@ -393,7 +393,7 @@
/* Perform a quick check so we don't blow up below. */
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
- || GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != REG
+ || !REG_P (SET_DEST (XVECEXP (op, 0, 0)))
|| GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != MEM)
return false;
@@ -403,10 +403,10 @@
/* Check, is base, or base + displacement. */
- if (GET_CODE (src_addr) == REG)
+ if (REG_P (src_addr))
off = 0;
else if (GET_CODE (src_addr) == PLUS
- && GET_CODE (XEXP (src_addr, 0)) == REG
+ && REG_P (XEXP (src_addr, 0))
&& CONST_INT_P (XEXP (src_addr, 1)))
{
off = INTVAL (XEXP (src_addr, 1));
@@ -420,7 +420,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_DEST (elt)) != REG
+ || !REG_P (SET_DEST (elt))
|| GET_MODE (SET_DEST (elt)) != elt_mode
|| REGNO (SET_DEST (elt)) != dest_regno + i
|| GET_CODE (SET_SRC (elt)) != MEM
@@ -497,7 +497,7 @@
if (count <= 1
|| GET_CODE (XVECEXP (op, 0, 0)) != SET
|| GET_CODE (SET_DEST (XVECEXP (op, 0, 0))) != MEM
- || GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) != REG)
+ || !REG_P (SET_SRC (XVECEXP (op, 0, 0))))
return false;
src_regno = REGNO (SET_SRC (XVECEXP (op, 0, 0)));
@@ -506,10 +506,10 @@
/* Check, is base, or base + displacement. */
- if (GET_CODE (dest_addr) == REG)
+ if (REG_P (dest_addr))
off = 0;
else if (GET_CODE (dest_addr) == PLUS
- && GET_CODE (XEXP (dest_addr, 0)) == REG
+ && REG_P (XEXP (dest_addr, 0))
&& CONST_INT_P (XEXP (dest_addr, 1)))
{
off = INTVAL (XEXP (dest_addr, 1));
@@ -523,7 +523,7 @@
rtx elt = XVECEXP (op, 0, i);
if (GET_CODE (elt) != SET
- || GET_CODE (SET_SRC (elt)) != REG
+ || !REG_P (SET_SRC (elt))
|| GET_MODE (SET_SRC (elt)) != elt_mode
|| REGNO (SET_SRC (elt)) != src_regno + i
|| GET_CODE (SET_DEST (elt)) != MEM
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 31fc179645d..a61c7d5ed79 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -1367,7 +1367,7 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode)
gcc_assert (req_mode != CCVIALLmode && req_mode != CCVIANYmode
&& req_mode != CCVFALLmode && req_mode != CCVFANYmode);
- if (GET_CODE (SET_DEST (set)) != REG || !CC_REGNO_P (REGNO (SET_DEST (set))))
+ if (!REG_P (SET_DEST (set)) || !CC_REGNO_P (REGNO (SET_DEST (set))))
return 1;
set_mode = GET_MODE (SET_DEST (set));
@@ -1688,7 +1688,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
&& XINT (*op0, 1) == UNSPEC_STRCMPCC_TO_INT
&& XVECLEN (*op0, 0) == 1
&& GET_MODE (XVECEXP (*op0, 0, 0)) == CCUmode
- && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
+ && REG_P (XVECEXP (*op0, 0, 0))
&& REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
&& *op1 == const0_rtx)
{
@@ -1715,7 +1715,7 @@ s390_canonicalize_comparison (int *code, rtx *op0, rtx *op1,
if (GET_CODE (*op0) == UNSPEC
&& XINT (*op0, 1) == UNSPEC_CC_TO_INT
&& XVECLEN (*op0, 0) == 1
- && GET_CODE (XVECEXP (*op0, 0, 0)) == REG
+ && REG_P (XVECEXP (*op0, 0, 0))
&& REGNO (XVECEXP (*op0, 0, 0)) == CC_REGNUM
&& CONST_INT_P (*op1))
{
@@ -1935,7 +1935,7 @@ s390_branch_condition_mask (rtx code)
const int CC2 = 1 << 1;
const int CC3 = 1 << 0;
- gcc_assert (GET_CODE (XEXP (code, 0)) == REG);
+ gcc_assert (REG_P (XEXP (code, 0)));
gcc_assert (REGNO (XEXP (code, 0)) == CC_REGNUM);
gcc_assert (XEXP (code, 1) == const0_rtx
|| (GET_MODE (XEXP (code, 0)) == CCRAWmode
@@ -2249,7 +2249,7 @@ s390_branch_condition_mnemonic (rtx code, int inv)
"le", "nh", "no", NULL
};
- if (GET_CODE (XEXP (code, 0)) == REG
+ if (REG_P (XEXP (code, 0))
&& REGNO (XEXP (code, 0)) == CC_REGNUM
&& (XEXP (code, 1) == const0_rtx
|| (GET_MODE (XEXP (code, 0)) == CCRAWmode
@@ -2901,7 +2901,7 @@ s390_decompose_address (rtx addr, struct s390_address *out)
/* Decompose address into base + index + displacement. */
- if (GET_CODE (addr) == REG || GET_CODE (addr) == UNSPEC)
+ if (REG_P (addr) || GET_CODE (addr) == UNSPEC)
base = addr;
else if (GET_CODE (addr) == PLUS)
@@ -3119,7 +3119,7 @@ s390_decompose_addrstyle_without_index (rtx op, rtx *base,
while (op && GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
- if (op && GET_CODE (op) != REG)
+ if (op && !REG_P (op))
return false;
if (offset)
@@ -5371,7 +5371,7 @@ s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (x) == PLUS)
{
- if (GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 0)))
{
rtx temp = gen_reg_rtx (Pmode);
rtx val = force_operand (XEXP (x, 1), temp);
@@ -5381,7 +5381,7 @@ s390_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
x = gen_rtx_PLUS (Pmode, XEXP (x, 0), temp);
}
- else if (GET_CODE (XEXP (x, 1)) == REG)
+ else if (REG_P (XEXP (x, 1)))
{
rtx temp = gen_reg_rtx (Pmode);
rtx val = force_operand (XEXP (x, 0), temp);
@@ -5420,7 +5420,7 @@ legitimize_reload_address (rtx ad, machine_mode mode ATTRIBUTE_UNUSED,
}
if (GET_CODE (ad) == PLUS
- && GET_CODE (XEXP (ad, 0)) == REG
+ && REG_P (XEXP (ad, 0))
&& CONST_INT_P (XEXP (ad, 1))
&& !DISP_IN_RANGE (INTVAL (XEXP (ad, 1))))
{
@@ -7435,7 +7435,7 @@ s390_delegitimize_address (rtx orig_x)
x = XEXP (x, 0);
if (GET_CODE (x) == PLUS
&& GET_CODE (XEXP (x, 1)) == CONST
- && GET_CODE (XEXP (x, 0)) == REG
+ && REG_P (XEXP (x, 0))
&& REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM)
{
y = XEXP (XEXP (x, 1), 0);
@@ -7490,7 +7490,7 @@ print_addrstyle_operand (FILE *file, rtx op)
/* Sanity check. */
if (base)
{
- gcc_assert (GET_CODE (base) == REG);
+ gcc_assert (REG_P (base));
gcc_assert (REGNO (base) < FIRST_PSEUDO_REGISTER);
gcc_assert (REGNO_REG_CLASS (REGNO (base)) == ADDR_REGS);
}
@@ -7964,7 +7964,7 @@ print_operand (FILE *file, rtx x, int code)
return;
case 'N':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
else if (GET_CODE (x) == MEM)
x = change_address (x, VOIDmode,
@@ -7975,7 +7975,7 @@ print_operand (FILE *file, rtx x, int code)
break;
case 'M':
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
x = gen_rtx_REG (GET_MODE (x), REGNO (x) + 1);
else if (GET_CODE (x) == MEM)
x = change_address (x, VOIDmode,
@@ -8211,7 +8211,7 @@ addr_generation_dependency_p (rtx dep_rtx, rtx_insn *insn)
while (GET_CODE (target) == SUBREG)
target = SUBREG_REG (target);
- if (GET_CODE (target) == REG)
+ if (REG_P (target))
{
int regno = REGNO (target);
@@ -13712,7 +13712,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (cfun_frame_layout.first_save_gpr != -1
&& (cfun_frame_layout.first_save_gpr < first
@@ -13750,7 +13750,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (REGNO (base) != STACK_POINTER_REGNUM
&& REGNO (base) != HARD_FRAME_POINTER_REGNUM)
@@ -13770,7 +13770,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (cfun_frame_layout.first_restore_gpr != -1
@@ -13821,7 +13821,7 @@ s390_optimize_prologue (void)
base = eliminate_constant_term (XEXP (SET_SRC (set), 0), &offset);
off = INTVAL (offset);
- if (GET_CODE (base) != REG || off < 0)
+ if (!REG_P (base) || off < 0)
continue;
if (REGNO (base) != STACK_POINTER_REGNUM
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index a50090af0a1..0f2cc5a7752 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2841,7 +2841,7 @@
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
|| GET_CODE (operands[1]) != MEM
- || GET_CODE (operands[0]) != REG
+ || !REG_P (operands[0])
|| REGNO (operands[0]) >= 16)
FAIL;
@@ -2854,13 +2854,13 @@
operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count));
if (!can_create_pseudo_p ())
{
- if (GET_CODE (XEXP (operands[1], 0)) == REG)
+ if (REG_P (XEXP (operands[1], 0)))
{
from = XEXP (operands[1], 0);
off = 0;
}
else if (GET_CODE (XEXP (operands[1], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
+ && REG_P (XEXP (XEXP (operands[1], 0), 0))
&& CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)))
{
from = XEXP (XEXP (operands[1], 0), 0);
@@ -2932,7 +2932,7 @@
|| INTVAL (operands[2]) < 2
|| INTVAL (operands[2]) > 16
|| GET_CODE (operands[0]) != MEM
- || GET_CODE (operands[1]) != REG
+ || !REG_P (operands[1])
|| REGNO (operands[1]) >= 16)
FAIL;
@@ -2946,13 +2946,13 @@
if (!can_create_pseudo_p ())
{
- if (GET_CODE (XEXP (operands[0], 0)) == REG)
+ if (REG_P (XEXP (operands[0], 0)))
{
to = XEXP (operands[0], 0);
off = 0;
}
else if (GET_CODE (XEXP (operands[0], 0)) == PLUS
- && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG
+ && REG_P (XEXP (XEXP (operands[0], 0), 0))
&& CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)))
{
to = XEXP (XEXP (operands[0], 0), 0);
@@ -10092,7 +10092,7 @@
if (Pmode != SImode)
index = convert_to_mode (Pmode, index, 1);
- if (GET_CODE (index) != REG)
+ if (!REG_P (index))
index = copy_to_mode_reg (Pmode, index);
if (TARGET_64BIT)
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index 7326d83a96f..df371584f9e 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -3490,8 +3490,8 @@ emit_scc_insn (rtx operands[])
back to the easy case. */
if (code == GTU || code == LEU)
{
- if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
- && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG))
+ if ((REG_P (x) || GET_CODE (x) == SUBREG)
+ && (REG_P (y) || GET_CODE (y) == SUBREG))
{
tem = x;
x = y;
@@ -3570,7 +3570,7 @@ emit_conditional_branch_insn (rtx operands[])
that won't fit in the 5-bit signed immediate field of a cbcond,
use one of the other v9 conditional branch sequences. */
if (TARGET_CBCOND
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& (GET_MODE (operands[1]) == SImode
|| (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode))
&& (!CONST_INT_P (operands[2])
@@ -3581,7 +3581,7 @@ emit_conditional_branch_insn (rtx operands[])
}
if (TARGET_ARCH64 && operands[2] == const0_rtx
- && GET_CODE (operands[1]) == REG
+ && REG_P (operands[1])
&& GET_MODE (operands[1]) == DImode)
{
emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]);
@@ -4018,7 +4018,7 @@ eligible_for_restore_insn (rtx trial, bool return_p)
src_reg = src;
if (GET_CODE (src_reg) == SUBREG)
src_reg = SUBREG_REG (src_reg);
- if (GET_CODE (src_reg) == REG
+ if (REG_P (src_reg)
&& SPARC_FP_REG_P (REGNO (src_reg)))
src_is_freg = true;
@@ -4119,7 +4119,7 @@ eligible_for_return_delay (rtx_insn *trial)
rtx expr = XVECEXP (pat, 0, i);
if (GET_CODE (expr) != SET)
return 0;
- if (GET_CODE (SET_DEST (expr)) != REG)
+ if (!REG_P (SET_DEST (expr)))
return 0;
regno = REGNO (SET_DEST (expr));
if (regno >= 8 && regno < 24)
@@ -4131,7 +4131,7 @@ eligible_for_return_delay (rtx_insn *trial)
if (GET_CODE (pat) != SET)
return 0;
- if (GET_CODE (SET_DEST (pat)) != REG)
+ if (!REG_P (SET_DEST (pat)))
return 0;
regno = REGNO (SET_DEST (pat));
@@ -4184,7 +4184,7 @@ eligible_for_sibcall_delay (rtx_insn *trial)
/* Otherwise, only operations which can be done in tandem with
a `restore' insn can go into the delay slot. */
- if (GET_CODE (SET_DEST (pat)) != REG
+ if (!REG_P (SET_DEST (pat))
|| (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24)
|| ! SPARC_INT_REG_P (REGNO (SET_DEST (pat))))
return 0;
@@ -5174,7 +5174,7 @@ mem_min_alignment (rtx mem, int desired)
base = offset = NULL_RTX;
if (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
{
base = XEXP (addr, 0);
@@ -5188,7 +5188,7 @@ mem_min_alignment (rtx mem, int desired)
offset = const0_rtx;
}
}
- else if (GET_CODE (addr) == REG)
+ else if (REG_P (addr))
{
base = addr;
offset = const0_rtx;
@@ -8908,7 +8908,7 @@ epilogue_renumber (register rtx *where, int test)
are in the return delayed slot. */
case PLUS:
- if (GET_CODE (XEXP (*where, 0)) == REG
+ if (REG_P (XEXP (*where, 0))
&& REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM
&& (!CONST_INT_P (XEXP (*where, 1))
|| INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS))
@@ -8917,7 +8917,7 @@ epilogue_renumber (register rtx *where, int test)
case MEM:
if (SPARC_STACK_BIAS
- && GET_CODE (XEXP (*where, 0)) == REG
+ && REG_P (XEXP (*where, 0))
&& REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM)
return 1;
break;
@@ -9038,13 +9038,13 @@ sparc_split_reg_reg_legitimate (rtx reg1, rtx reg2)
if (GET_CODE (reg1) == SUBREG)
reg1 = SUBREG_REG (reg1);
- if (GET_CODE (reg1) != REG)
+ if (!REG_P (reg1))
return 0;
const int regno1 = REGNO (reg1);
if (GET_CODE (reg2) == SUBREG)
reg2 = SUBREG_REG (reg2);
- if (GET_CODE (reg2) != REG)
+ if (!REG_P (reg2))
return 0;
const int regno2 = REGNO (reg2);
@@ -9094,7 +9094,7 @@ int
registers_ok_for_ldd_peep (rtx reg1, rtx reg2)
{
/* We might have been passed a SUBREG. */
- if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG)
+ if (!REG_P (reg1) || !REG_P (reg2))
return 0;
if (REGNO (reg1) % 2 != 0)
@@ -9160,7 +9160,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
if (GET_CODE (addr1) == PLUS)
{
/* If not a REG, return zero. */
- if (GET_CODE (XEXP (addr1, 0)) != REG)
+ if (!REG_P (XEXP (addr1, 0)))
return 0;
else
{
@@ -9171,7 +9171,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
offset1 = INTVAL (XEXP (addr1, 1));
}
}
- else if (GET_CODE (addr1) != REG)
+ else if (!REG_P (addr1))
return 0;
else
{
@@ -9184,7 +9184,7 @@ mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx)
if (GET_CODE (addr2) != PLUS)
return 0;
- if (GET_CODE (XEXP (addr2, 0)) != REG
+ if (!REG_P (XEXP (addr2, 0))
|| !CONST_INT_P (XEXP (addr2, 1)))
return 0;
@@ -9343,7 +9343,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
/* Adjust the operand to take into account a RESTORE operation. */
if (CONST_INT_P (x))
break;
- else if (GET_CODE (x) != REG)
+ else if (!REG_P (x))
output_operand_lossage ("invalid %%Y operand");
else if (REGNO (x) < 8)
fputs (reg_names[REGNO (x)], file);
@@ -9617,7 +9617,7 @@ sparc_print_operand (FILE *file, rtx x, int code)
output_operand_lossage ("invalid operand output code");
}
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
fputs (reg_names[REGNO (x)], file);
else if (GET_CODE (x) == MEM)
{
@@ -10316,22 +10316,22 @@ set_extends (rtx_insn *insn)
rtx op1 = XEXP (SET_SRC (pat), 1);
if (CONST_INT_P (op1))
return INTVAL (op1) >= 0;
- if (GET_CODE (op0) != REG)
+ if (!REG_P (op0))
return 0;
if (sparc_check_64 (op0, insn) == 1)
return 1;
- return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
+ return (REG_P (op1) && sparc_check_64 (op1, insn) == 1);
}
case IOR:
case XOR:
{
rtx op0 = XEXP (SET_SRC (pat), 0);
rtx op1 = XEXP (SET_SRC (pat), 1);
- if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0)
+ if (!REG_P (op0) || sparc_check_64 (op0, insn) <= 0)
return 0;
if (CONST_INT_P (op1))
return INTVAL (op1) >= 0;
- return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
+ return (REG_P (op1) && sparc_check_64 (op1, insn) == 1);
}
case LSHIFTRT:
return GET_MODE (SET_SRC (pat)) == SImode;
@@ -10461,7 +10461,7 @@ sparc_check_64 (rtx x, rtx_insn *insn)
int set_once = 0;
rtx y = x;
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
if (GET_MODE (x) == DImode)
y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN);
@@ -13403,7 +13403,7 @@ sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i,
if (FP_REG_CLASS_P (rclass)
&& (mode == HImode || mode == QImode)
&& (GET_CODE (x) == MEM
- || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ || ((REG_P (x) || GET_CODE (x) == SUBREG)
&& true_regnum (x) == -1)))
return GENERAL_REGS;
@@ -13530,7 +13530,7 @@ sparc_expand_conditional_move (machine_mode mode, rtx *operands)
}
if (XEXP (cmp, 1) == const0_rtx
- && GET_CODE (XEXP (cmp, 0)) == REG
+ && REG_P (XEXP (cmp, 0))
&& cmp_mode == DImode
&& v9_regcmp_p (rc))
cc_reg = XEXP (cmp, 0);
diff --git a/gcc/config/sparc/sparc.md b/gcc/config/sparc/sparc.md
index 60220904346..26b7f808e82 100644
--- a/gcc/config/sparc/sparc.md
+++ b/gcc/config/sparc/sparc.md
@@ -2131,10 +2131,10 @@ visl")
(match_operand:DI 1 "const_int_operand" ""))]
"reload_completed
&& TARGET_ARCH32
- && ((GET_CODE (operands[0]) == REG
+ && ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
|| (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
+ && REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
{
@@ -2577,10 +2577,10 @@ visl")
(match_operand:DF 1 "const_zero_operand" ""))]
"reload_completed
&& TARGET_ARCH32
- && ((GET_CODE (operands[0]) == REG
+ && ((REG_P (operands[0])
&& SPARC_INT_REG_P (REGNO (operands[0])))
|| (GET_CODE (operands[0]) == SUBREG
- && GET_CODE (SUBREG_REG (operands[0])) == REG
+ && REG_P (SUBREG_REG (operands[0]))
&& SPARC_INT_REG_P (REGNO (SUBREG_REG (operands[0])))))"
[(clobber (const_int 0))]
{
diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index 2a542a7101e..0206d15d9a8 100644
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -149,7 +149,7 @@
(define_memory_constraint "R"
"Call operand, reg, for indirect calls"
(and (match_code "mem")
- (match_test "GET_CODE(XEXP(op, 0)) == REG")))
+ (match_test "REG_P (XEXP(op, 0))")))
(define_memory_constraint "S"
"Call operand, symbol, for relative calls."
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index fe893b62a9e..e850c9ba40e 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -1050,7 +1050,7 @@ print_operand_address (FILE * file, register rtx addr)
case PLUS:
reg = XEXP (addr, 0);
offset = XEXP (addr, 1);
- if (GET_CODE (offset) == REG)
+ if (REG_P (offset))
{
fprintf (file, "%s,%s", reg_names[REGNO (reg)],
reg_names[REGNO (offset)]);
@@ -1350,7 +1350,7 @@ print_operand (FILE * file, rtx x, int code)
case 'i': /* indirect call */
if (xcode == MEM)
{
- if (GET_CODE (XEXP (x, 0)) == REG)
+ if (REG_P (XEXP (x, 0)))
/* Used in indirect function calls. */
fprintf (file, "%s", reg_names[REGNO (XEXP (x, 0))]);
else
@@ -1377,7 +1377,7 @@ print_operand (FILE * file, rtx x, int code)
fprintf (file, "r");
else if (xcode == PLUS || xcode == LO_SUM)
{
- if (GET_CODE (XEXP (x, 1)) == REG)
+ if (REG_P (XEXP (x, 1)))
fprintf (file, "x");
else
fprintf (file, "d");
@@ -2253,7 +2253,7 @@ insn_clobbers_hbr (rtx_insn *insn)
{
clobber = XVECEXP (parallel, 0, j);
if (GET_CODE (clobber) == CLOBBER
- && GET_CODE (XEXP (clobber, 0)) == REG
+ && REG_P (XEXP (clobber, 0))
&& REGNO (XEXP (clobber, 0)) == HBR_REGNUM)
return 1;
}
@@ -2508,7 +2508,7 @@ spu_machine_dependent_reorg (void)
{
insn_addr = INSN_ADDRESSES (INSN_UID (insn));
if (branch
- && ((GET_CODE (branch_target) == REG
+ && ((REG_P (branch_target)
&& set_of (branch_target, insn) != NULL_RTX)
|| insn_clobbers_hbr (insn)
|| branch_addr - insn_addr > 600))
@@ -2589,7 +2589,7 @@ spu_machine_dependent_reorg (void)
&& EDGE_COUNT (prev->preds) == 1
&& EDGE_PRED (prev, 0)->src == prev2
&& prev2->loop_father == bb->loop_father
- && GET_CODE (branch_target) != REG)
+ && !REG_P (branch_target))
prop = prev;
/* Don't propagate when:
@@ -3030,7 +3030,7 @@ spu_sched_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
if (CALL_P (insn))
{
rtx target = get_branch_target (insn);
- if (GET_CODE (target) != REG || !set_of (target, insn))
+ if (!REG_P (target) || !set_of (target, insn))
return cost - 2;
return cost;
}
@@ -3045,7 +3045,7 @@ spu_sched_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn,
issued. */
if (INSN_CODE (insn) == CODE_FOR__return
&& (set = single_set (dep_insn))
- && GET_CODE (SET_DEST (set)) == REG
+ && REG_P (SET_DEST (set))
&& REGNO (SET_DEST (set)) == LINK_REGISTER_REGNUM)
return 20;
@@ -3555,7 +3555,7 @@ spu_legitimate_address_p (machine_mode mode,
op0 = XEXP (op0, 0);
if (GET_CODE (op1) == SUBREG)
op1 = XEXP (op1, 0);
- if (GET_CODE (op0) == REG
+ if (REG_P (op0)
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
&& CONST_INT_P (op1)
&& ((INTVAL (op1) >= -0x2000 && INTVAL (op1) <= 0x1fff)
@@ -3568,9 +3568,9 @@ spu_legitimate_address_p (machine_mode mode,
|| op0 == virtual_stack_vars_rtx)
&& (!aligned || (INTVAL (op1) & 15) == 0))
return TRUE;
- if (GET_CODE (op0) == REG
+ if (REG_P (op0)
&& INT_REG_OK_FOR_BASE_P (op0, reg_ok_strict)
- && GET_CODE (op1) == REG
+ && REG_P (op1)
&& INT_REG_OK_FOR_INDEX_P (op1, reg_ok_strict))
return TRUE;
}
@@ -3613,14 +3613,14 @@ spu_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
op0 = force_reg (Pmode, op0);
mark_reg_pointer (op0, 128);
}
- else if (GET_CODE (op0) != REG)
+ else if (!REG_P (op0))
op0 = force_reg (Pmode, op0);
if (ALIGNED_SYMBOL_REF_P (op1))
{
op1 = force_reg (Pmode, op1);
mark_reg_pointer (op1, 128);
}
- else if (GET_CODE (op1) != REG)
+ else if (!REG_P (op1))
op1 = force_reg (Pmode, op1);
x = gen_rtx_PLUS (Pmode, op0, op1);
}
@@ -4841,7 +4841,7 @@ spu_split_store (rtx * ops)
}
else
{
- if (GET_CODE (ops[1]) == REG)
+ if (REG_P (ops[1]))
emit_insn (gen_spu_convert (reg, ops[1]));
else if (GET_CODE (ops[1]) == SUBREG)
emit_insn (gen_spu_convert (reg, SUBREG_REG (ops[1])));
@@ -4994,9 +4994,9 @@ gen_cpat_const (rtx * ops)
if (!CONST_INT_P (ops[3])
|| !CONST_INT_P (ops[2])
|| (!CONST_INT_P (ops[1])
- && GET_CODE (ops[1]) != REG))
+ && !REG_P (ops[1])))
return 0;
- if (GET_CODE (ops[1]) == REG
+ if (REG_P (ops[1])
&& (!REG_POINTER (ops[1])
|| REGNO_POINTER_ALIGN (ORIGINAL_REGNO (ops[1])) < 128))
return 0;
@@ -5307,7 +5307,7 @@ spu_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
cost =
GET_CODE (XEXP (x, 0)) ==
REG ? COSTS_N_INSNS (12) : COSTS_N_INSNS (7);
- if (mode == SImode && GET_CODE (XEXP (x, 0)) == REG)
+ if (mode == SImode && REG_P (XEXP (x, 0)))
{
if (CONST_INT_P (XEXP (x, 1)))
{
@@ -5661,7 +5661,7 @@ spu_builtin_splats (rtx ops[])
{
rtx reg = gen_reg_rtx (TImode);
rtx shuf;
- if (GET_CODE (ops[1]) != REG
+ if (!REG_P (ops[1])
&& GET_CODE (ops[1]) != SUBREG)
ops[1] = force_reg (GET_MODE_INNER (mode), ops[1]);
switch (mode)
@@ -6450,7 +6450,7 @@ spu_expand_builtin_1 (struct spu_builtin_description *d,
/* Try to use target because not using it can lead to extra copies
and when we are using all of the registers extra copies leads
to extra spills. */
- if (target && GET_CODE (target) == REG && GET_MODE (target) == tmode)
+ if (target && REG_P (target) && GET_MODE (target) == tmode)
ops[0] = target;
else
target = ops[0] = gen_reg_rtx (tmode);
diff --git a/gcc/config/spu/spu.md b/gcc/config/spu/spu.md
index ba7858a645f..47705c65067 100644
--- a/gcc/config/spu/spu.md
+++ b/gcc/config/spu/spu.md
@@ -2354,7 +2354,7 @@
rtx op2 = operands[2];
rtx op3 = operands[3];
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
emit_insn (gen_addsi3 (op3, op2, GEN_INT (64)));
emit_insn (gen_rotlti3 (op0, op1, GEN_INT (64)));
@@ -2470,7 +2470,7 @@
"@
#
rot<bh>mi\t%0,%1,-%<umask>2"
- "reload_completed && GET_CODE (operands[2]) == REG"
+ "reload_completed && REG_P (operands[2])"
[(set (match_dup:VHSI 3)
(neg:VHSI (match_dup:VHSI 2)))
(set (match_dup:VHSI 0)
@@ -2634,7 +2634,7 @@
"@
#
rotma<bh>i\t%0,%1,-%<umask>2"
- "reload_completed && GET_CODE (operands[2]) == REG"
+ "reload_completed && REG_P (operands[2])"
[(set (match_dup:VHSI 3)
(neg:VHSI (match_dup:VHSI 2)))
(set (match_dup:VHSI 0)
@@ -2714,7 +2714,7 @@
emit_move_insn (op4, array_to_constant (TImode, arr));
emit_insn (gen_spu_fsm (op3v, op5));
- if (GET_CODE (operands[2]) == REG)
+ if (REG_P (operands[2]))
{
emit_insn (gen_selb (op4, op3, op1, op4));
emit_insn (gen_negsi2 (op5, op2));
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index 66edd7cbe09..a1821a3bc29 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -73,7 +73,7 @@
(define_predicate "even_reg_operand"
(match_code "reg")
{
- return (GET_CODE (op) == REG
+ return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| ((REGNO (op) > 0) && (REGNO (op) < 32)
&& ((REGNO (op) & 1)==0))));
@@ -86,8 +86,8 @@
{
/* Only registers are valid call operands if TARGET_LONG_CALLS. */
if (TARGET_LONG_CALLS)
- return GET_CODE (op) == REG;
- return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
+ return REG_P (op);
+ return (GET_CODE (op) == SYMBOL_REF || REG_P (op));
})
;; Return true if OP is a valid source operand for SImode move.
@@ -198,7 +198,7 @@
if (GET_CODE (dest) != MEM
|| GET_MODE (dest) != SImode
- || GET_CODE (src) != REG
+ || !REG_P (src)
|| GET_MODE (src) != SImode
|| ! register_is_ok_for_epilogue (src, SImode))
return 0;
@@ -206,7 +206,7 @@
plus = XEXP (dest, 0);
if ( GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -226,7 +226,7 @@
vector_element = XVECEXP (op, 0, i++);
if (GET_CODE (vector_element) != CLOBBER
- || GET_CODE (XEXP (vector_element, 0)) != REG
+ || !REG_P (XEXP (vector_element, 0))
|| REGNO (XEXP (vector_element, 0)) != 10)
return 0;
@@ -235,7 +235,7 @@
vector_element = XVECEXP (op, 0, i++);
if (GET_CODE (vector_element) != CLOBBER
- || GET_CODE (XEXP (vector_element, 0)) != REG
+ || !REG_P (XEXP (vector_element, 0))
|| REGNO (XEXP (vector_element, 0)) != 11)
return 0;
}
@@ -283,7 +283,7 @@
dest = SET_DEST (vector_element);
src = SET_SRC (vector_element);
- if (GET_CODE (dest) != REG
+ if (!REG_P (dest)
|| GET_MODE (dest) != SImode
|| ! register_is_ok_for_epilogue (dest, SImode)
|| GET_CODE (src) != MEM
@@ -293,7 +293,7 @@
plus = XEXP (src, 0);
if (GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -310,7 +310,7 @@
(match_code "reg")
{
/* The save/restore routines can only cope with registers 20 - 31. */
- return ((GET_CODE (op) == REG)
+ return ((REG_P (op))
&& (((REGNO (op) >= 20) && REGNO (op) <= 31)));
})
@@ -355,7 +355,7 @@
dest = SET_DEST (vector_element);
src = SET_SRC (vector_element);
- if ( GET_CODE (dest) != REG
+ if ( !REG_P (dest)
|| GET_MODE (dest) != SImode
|| ! register_is_ok_for_epilogue (dest, SImode)
|| GET_CODE (src) != MEM
@@ -365,7 +365,7 @@
plus = XEXP (src, 0);
if ( GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -421,7 +421,7 @@
if ( GET_CODE (dest) != MEM
|| GET_MODE (dest) != SImode
- || GET_CODE (src) != REG
+ || !REG_P (src)
|| GET_MODE (src) != SImode
|| ! register_is_ok_for_epilogue (src, SImode)
)
@@ -430,7 +430,7 @@
plus = XEXP (dest, 0);
if ( GET_CODE (plus) != PLUS
- || GET_CODE (XEXP (plus, 0)) != REG
+ || !REG_P (XEXP (plus, 0))
|| GET_MODE (XEXP (plus, 0)) != SImode
|| REGNO (XEXP (plus, 0)) != STACK_POINTER_REGNUM
|| !CONST_INT_P (XEXP (plus, 1)))
@@ -519,7 +519,7 @@
if (mode != GET_MODE (op) && mode != VOIDmode)
return 0;
- if ((GET_CODE (XEXP (op, 0)) != REG
+ if ((!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM)
|| XEXP (op, 1) != const0_rtx)
return 0;
@@ -559,7 +559,7 @@
if (mode != GET_MODE (op) && mode != VOIDmode)
return 0;
- if ((GET_CODE (XEXP (op, 0)) != REG
+ if ((!REG_P (XEXP (op, 0))
|| REGNO (XEXP (op, 0)) != CC_REGNUM)
|| XEXP (op, 1) != const0_rtx)
return 0;
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index ea2222cca1d..201bed4bcdb 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -371,7 +371,7 @@ v850_rtx_costs (rtx x, machine_mode mode, int outer_code,
if (TARGET_V850E
&& (mode == SImode || mode == HImode || mode == QImode))
{
- if (GET_CODE (XEXP (x, 1)) == REG)
+ if (REG_P (XEXP (x, 1)))
*total = 4;
else if (CONST_INT_P (XEXP (x, 1)))
{
@@ -676,7 +676,7 @@ v850_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
fprintf (file, "]");
break;
case LO_SUM:
- if (GET_CODE (XEXP (addr, 0)) == REG)
+ if (REG_P (XEXP (addr, 0)))
{
/* reg,foo */
fprintf (file, "lo(");
@@ -687,7 +687,7 @@ v850_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
}
break;
case PLUS:
- if (GET_CODE (XEXP (addr, 0)) == REG
+ if (REG_P (XEXP (addr, 0))
|| GET_CODE (XEXP (addr, 0)) == SUBREG)
{
/* reg,foo */
@@ -1096,7 +1096,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
&& INTVAL (op1) >= 0
&& (INTVAL (op1) & mask) == 0)
{
- if (GET_CODE (op0) == REG && REGNO (op0) == EP_REGNUM)
+ if (REG_P (op0) && REGNO (op0) == EP_REGNUM)
return TRUE;
if (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_TDA_P (op0))
@@ -1180,11 +1180,11 @@ Saved %d bytes (%d uses of register %s) in function %s, starting as insn %d, end
{
rtx addr = XEXP (*p_mem, 0);
- if (GET_CODE (addr) == REG && REGNO (addr) == (unsigned) regno)
+ if (REG_P (addr) && REGNO (addr) == (unsigned) regno)
*p_mem = change_address (*p_mem, VOIDmode, *p_ep);
else if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& REGNO (XEXP (addr, 0)) == (unsigned) regno
&& CONST_INT_P (XEXP (addr, 1))
&& ((INTVAL (XEXP (addr, 1)))
@@ -1302,11 +1302,11 @@ v850_reorg (void)
subregs to make this code simpler. */
if (GET_CODE (dest) == SUBREG
&& (GET_CODE (SUBREG_REG (dest)) == MEM
- || GET_CODE (SUBREG_REG (dest)) == REG))
+ || REG_P (SUBREG_REG (dest))))
alter_subreg (&dest, false);
if (GET_CODE (src) == SUBREG
&& (GET_CODE (SUBREG_REG (src)) == MEM
- || GET_CODE (SUBREG_REG (src)) == REG))
+ || REG_P (SUBREG_REG (src))))
alter_subreg (&src, false);
if (GET_CODE (dest) == MEM && GET_CODE (src) == MEM)
@@ -1341,14 +1341,14 @@ v850_reorg (void)
int regno = -1;
int short_p;
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
{
short_p = TRUE;
regno = REGNO (addr);
}
else if (GET_CODE (addr) == PLUS
- && GET_CODE (XEXP (addr, 0)) == REG
+ && REG_P (XEXP (addr, 0))
&& CONST_INT_P (XEXP (addr, 1))
&& ((INTVAL (XEXP (addr, 1)))
< ep_memory_offset (GET_MODE (mem), unsignedp))
@@ -1372,7 +1372,7 @@ v850_reorg (void)
/* Loading up a register in the basic block zaps any savings
for the register */
- if (GET_CODE (dest) == REG)
+ if (REG_P (dest))
{
int regno;
int endregno;
@@ -2238,7 +2238,7 @@ construct_restore_jr (rtx op)
rtx vector_element = XVECEXP (op, 0, i);
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_DEST (vector_element)) == REG);
+ gcc_assert (REG_P (SET_DEST (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_DEST (vector_element),
SImode));
@@ -2321,7 +2321,7 @@ construct_save_jarl (rtx op)
/* Paranoia. */
gcc_assert (GET_CODE (XVECEXP (op, 0, 0)) == SET);
gcc_assert (GET_CODE (SET_SRC (XVECEXP (op, 0, 0))) == PLUS);
- gcc_assert (GET_CODE (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)) == REG);
+ gcc_assert (REG_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 0)));
gcc_assert (CONST_INT_P (XEXP (SET_SRC (XVECEXP (op, 0, 0)), 1)));
/* Work out how many bytes to push onto the stack after storing the
@@ -2345,7 +2345,7 @@ construct_save_jarl (rtx op)
rtx vector_element = XVECEXP (op, 0, i);
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_SRC (vector_element)) == REG);
+ gcc_assert (REG_P (SET_SRC (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_SRC (vector_element),
SImode));
@@ -2643,7 +2643,7 @@ construct_dispose_instruction (rtx op)
rtx vector_element = XVECEXP (op, 0, i);
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_DEST (vector_element)) == REG);
+ gcc_assert (REG_P (SET_DEST (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_DEST (vector_element),
SImode));
@@ -2765,7 +2765,7 @@ construct_prepare_instruction (rtx op)
continue;
gcc_assert (GET_CODE (vector_element) == SET);
- gcc_assert (GET_CODE (SET_SRC (vector_element)) == REG);
+ gcc_assert (REG_P (SET_SRC (vector_element)));
gcc_assert (register_is_ok_for_epilogue (SET_SRC (vector_element),
SImode));
diff --git a/gcc/config/v850/v850.md b/gcc/config/v850/v850.md
index 167d87ca60b..06c87e4e7d2 100644
--- a/gcc/config/v850/v850.md
+++ b/gcc/config/v850/v850.md
@@ -1171,9 +1171,9 @@
}
else
{
- if (GET_CODE (operands[2]) != REG)
+ if (!REG_P (operands[2]))
operands[2] = copy_to_mode_reg (SImode,operands[2]);
- if (GET_CODE (operands[3]) != REG)
+ if (!REG_P (operands[3]))
operands[3] = copy_to_mode_reg (SImode, operands[3]);
}
})
@@ -1710,7 +1710,7 @@
{
if (which_alternative == 0)
{
- if (GET_CODE (operands[0]) == REG)
+ if (REG_P (operands[0]))
return "jarl %0,r31";
if (TARGET_V850E3V5_UP)
@@ -1779,7 +1779,7 @@
{
if (which_alternative == 0)
{
- if (GET_CODE (operands[1]) == REG)
+ if (REG_P (operands[1]))
return "jarl %1, r31";
/* Reload can generate this pattern.... */
@@ -2728,8 +2728,8 @@
"reload_completed
&& TARGET_USE_FPU
&& GET_MODE(operands[0]) == GET_MODE(operands[1])
- && GET_CODE(operands[0]) == REG && REGNO (operands[0]) == CC_REGNUM
- && GET_CODE(operands[1]) == REG && REGNO (operands[1]) == FCC_REGNUM
+ && REG_P (operands[0]) && REGNO (operands[0]) == CC_REGNUM
+ && REG_P (operands[1]) && REGNO (operands[1]) == FCC_REGNUM
&& (GET_MODE(operands[0]) == CC_FPU_LEmode
|| GET_MODE(operands[0]) == CC_FPU_GEmode
|| GET_MODE(operands[0]) == CC_FPU_LTmode
diff --git a/gcc/config/visium/predicates.md b/gcc/config/visium/predicates.md
index 45c976ac7c1..1515abd968c 100644
--- a/gcc/config/visium/predicates.md
+++ b/gcc/config/visium/predicates.md
@@ -50,7 +50,7 @@
if (GET_CODE (op) == SUBREG)
{
op = SUBREG_REG (op);
- if (GET_CODE (op) != REG)
+ if (!REG_P (op))
return 1;
}
diff --git a/gcc/config/visium/visium.c b/gcc/config/visium/visium.c
index 3362843f488..b2bc847b971 100644
--- a/gcc/config/visium/visium.c
+++ b/gcc/config/visium/visium.c
@@ -1193,7 +1193,7 @@ gr5_avoid_hazard (rtx_insn *insn, unsigned int *last_reg, bool *last_insn_call)
dest = XEXP (dest, 0);
dest_reg = REGNO (dest);
- if (GET_CODE (SET_SRC (set)) == REG)
+ if (REG_P (SET_SRC (set)))
{
unsigned int srcreg = REGNO (SET_SRC (set));
@@ -1903,7 +1903,7 @@ visium_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
{
if (GET_CODE (x) == PLUS
&& CONST_INT_P (XEXP (x, 1))
- && GET_CODE (XEXP (x, 0)) == REG && mode != BLKmode)
+ && REG_P (XEXP (x, 0)) && mode != BLKmode)
{
int offset = INTVAL (XEXP (x, 1));
int size = GET_MODE_SIZE (mode);
@@ -1948,7 +1948,7 @@ visium_legitimize_reload_address (rtx x, machine_mode mode, int opnum,
newrtx = tem ? tem : x;
if (GET_CODE (newrtx) == PLUS
&& CONST_INT_P (XEXP (newrtx, 1))
- && GET_CODE (XEXP (newrtx, 0)) == REG
+ && REG_P (XEXP (newrtx, 0))
&& BASE_REGISTER_P (REGNO (XEXP (newrtx, 0))))
{
int offset = INTVAL (XEXP (newrtx, 1));
@@ -2114,20 +2114,20 @@ visium_split_double_move (rtx *operands, machine_mode mode)
bool swap = false;
/* Check register to register with overlap. */
- if (GET_CODE (operands[0]) == REG
- && GET_CODE (operands[1]) == REG
+ if (REG_P (operands[0])
+ && REG_P (operands[1])
&& REGNO (operands[0]) == REGNO (operands[1]) + 1)
swap = true;
/* Check memory to register where the base reg overlaps the destination. */
- if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == MEM)
+ if (REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
{
rtx op = XEXP (operands[1], 0);
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
- if (GET_CODE (op) == REG && REGNO (op) == REGNO (operands[0]))
+ if (REG_P (op) && REGNO (op) == REGNO (operands[0]))
swap = true;
if (GET_CODE (op) == PLUS)
@@ -2135,10 +2135,10 @@ visium_split_double_move (rtx *operands, machine_mode mode)
rtx x = XEXP (op, 0);
rtx y = XEXP (op, 1);
- if (GET_CODE (x) == REG && REGNO (x) == REGNO (operands[0]))
+ if (REG_P (x) && REGNO (x) == REGNO (operands[0]))
swap = true;
- if (GET_CODE (y) == REG && REGNO (y) == REGNO (operands[0]))
+ if (REG_P (y) && REGNO (y) == REGNO (operands[0]))
swap = true;
}
}
@@ -3323,7 +3323,7 @@ visium_print_operand (FILE *file, rtx op, int letter)
case 'r':
/* It's either a register or zero. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
fputs (reg_names[REGNO (op)], file);
else
fputs (reg_names[0], file);
@@ -3331,7 +3331,7 @@ visium_print_operand (FILE *file, rtx op, int letter)
case 'f':
/* It's either a FP register or zero. */
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
fputs (reg_names[REGNO (op)], file);
else
fputs (reg_names[FP_FIRST_REGNUM], file);
@@ -4303,9 +4303,9 @@ reg_or_subreg_regno (rtx op)
{
unsigned int regno;
- if (GET_CODE (op) == REG)
+ if (REG_P (op))
regno = REGNO (op);
- else if (GET_CODE (op) == SUBREG && GET_CODE (SUBREG_REG (op)) == REG)
+ else if (GET_CODE (op) == SUBREG && REG_P (SUBREG_REG (op)))
{
if (REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER)
regno = subreg_regno (op);
diff --git a/gcc/config/visium/visium.md b/gcc/config/visium/visium.md
index e146b89d1da..6f5d3ce3a0b 100644
--- a/gcc/config/visium/visium.md
+++ b/gcc/config/visium/visium.md
@@ -2562,7 +2562,7 @@
(clobber (match_dup 3))])]
""
{
- if (GET_CODE (XEXP (operands[0], 0)) != REG)
+ if (!REG_P (XEXP (operands[0], 0)))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
if (!operands[2])
@@ -2593,7 +2593,7 @@
(clobber (match_dup 4))])]
""
{
- if (GET_CODE (XEXP (operands[1], 0)) != REG)
+ if (!REG_P (XEXP (operands[1], 0)))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
if (!operands[3])
@@ -2624,7 +2624,7 @@
(clobber (match_dup 3))])]
""
{
- if (GET_CODE (XEXP (operands[0], 0)) != REG)
+ if (!REG_P (XEXP (operands[0], 0)))
XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, XEXP (operands[0], 0));
if (!operands[2])
@@ -2650,7 +2650,7 @@
(clobber (match_dup 4))])]
""
{
- if (GET_CODE (XEXP (operands[1], 0)) != REG)
+ if (!REG_P (XEXP (operands[1], 0)))
XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, XEXP (operands[1], 0));
if (!operands[3])
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index d35c90f4f88..4d62033d810 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -86,7 +86,7 @@
(define_predicate "call_insn_operand"
(match_code "const_int,const,symbol_ref,reg")
{
- if ((GET_CODE (op) == REG)
+ if ((REG_P (op))
&& (op != arg_pointer_rtx)
&& ((REGNO (op) < FRAME_POINTER_REGNUM)
|| (REGNO (op) > LAST_VIRTUAL_REGISTER)))
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index ba983ad3ac9..d5aad718e41 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -469,7 +469,7 @@ xtensa_mask_immediate (HOST_WIDE_INT v)
int
xt_true_regnum (rtx x)
{
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
if (reg_renumber
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
@@ -528,7 +528,7 @@ smalloffset_mem_p (rtx op)
if (GET_CODE (op) == MEM)
{
rtx addr = XEXP (op, 0);
- if (GET_CODE (addr) == REG)
+ if (REG_P (addr))
return BASE_REG_P (addr, 0);
if (GET_CODE (addr) == PLUS)
{
@@ -742,7 +742,7 @@ gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */
cmp1 = force_reg (mode, cmp1);
}
}
- else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG))
+ else if ((!REG_P (cmp1)) && (GET_CODE (cmp1) != SUBREG))
{
cmp1 = force_reg (mode, cmp1);
}
@@ -1119,7 +1119,7 @@ static rtx
fixup_subreg_mem (rtx x)
{
if (GET_CODE (x) == SUBREG
- && GET_CODE (SUBREG_REG (x)) == REG
+ && REG_P (SUBREG_REG (x))
&& REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER)
{
rtx temp =
@@ -1173,7 +1173,7 @@ xtensa_copy_incoming_a7 (rtx opnd)
gcc_assert (SUBREG_BYTE (reg) == 0);
reg = SUBREG_REG (reg);
}
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) > A7_REG
|| REGNO (reg) + hard_regno_nregs (A7_REG, mode) <= A7_REG)
return opnd;
@@ -1369,7 +1369,7 @@ xtensa_expand_nonlocal_goto (rtx *operands)
/* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code
is too big to generate in-line. */
- if (GET_CODE (containing_fp) != REG)
+ if (!REG_P (containing_fp))
containing_fp = force_reg (Pmode, containing_fp);
emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"),
@@ -1835,7 +1835,7 @@ xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
addr = SUBREG_REG (addr);
/* Allow base registers. */
- if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict))
+ if (REG_P (addr) && BASE_REG_P (addr, strict))
return true;
/* Check for "register + offset" addressing. */
@@ -1969,14 +1969,14 @@ xtensa_legitimize_address (rtx x,
rtx plus0 = XEXP (x, 0);
rtx plus1 = XEXP (x, 1);
- if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
+ if (!REG_P (plus0) && REG_P (plus1))
{
plus0 = XEXP (x, 1);
plus1 = XEXP (x, 0);
}
/* Try to split up the offset to use an ADDMI instruction. */
- if (GET_CODE (plus0) == REG
+ if (REG_P (plus0)
&& CONST_INT_P (plus1)
&& !xtensa_mem_offset (INTVAL (plus1), mode)
&& !xtensa_simm8 (INTVAL (plus1))
@@ -2369,7 +2369,7 @@ print_operand (FILE *file, rtx x, int letter)
switch (letter)
{
case 'D':
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || GET_CODE (x) == SUBREG)
fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]);
else
output_operand_lossage ("invalid %%D value");
@@ -2501,7 +2501,7 @@ print_operand (FILE *file, rtx x, int letter)
/* fall through */
default:
- if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
+ if (REG_P (x) || GET_CODE (x) == SUBREG)
fprintf (file, "%s", reg_names[xt_true_regnum (x)]);
else if (GET_CODE (x) == MEM)
output_address (GET_MODE (x), XEXP (x, 0));
@@ -2540,12 +2540,12 @@ print_operand_address (FILE *file, rtx addr)
rtx arg0 = XEXP (addr, 0);
rtx arg1 = XEXP (addr, 1);
- if (GET_CODE (arg0) == REG)
+ if (REG_P (arg0))
{
reg = arg0;
offset = arg1;
}
- else if (GET_CODE (arg1) == REG)
+ else if (REG_P (arg1))
{
reg = arg1;
offset = arg0;
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index d1448a02f20..40af6056024 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1549,7 +1549,7 @@
""
{
rtx dest = operands[0];
- if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
+ if (!REG_P (dest) || GET_MODE (dest) != Pmode)
operands[0] = copy_to_mode_reg (Pmode, dest);
emit_jump_insn (gen_indirect_jump_internal (dest));
diff --git a/gcc/cse.c b/gcc/cse.c
index 5a6fcf8cbb7..7747986d637 100644
--- a/gcc/cse.c
+++ b/gcc/cse.c
@@ -1828,7 +1828,7 @@ check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr)
static void
invalidate_reg (rtx x, bool clobber_high)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
/* If X is a register, dependencies on its contents are recorded
through the qty number mechanism. Just change the qty number of
diff --git a/gcc/dse.c b/gcc/dse.c
index 8d7358d02b4..40ef3fb74e3 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -1056,7 +1056,7 @@ const_or_frame_p (rtx x)
if (CONSTANT_P (x))
return true;
- if (GET_CODE (x) == REG)
+ if (REG_P (x))
{
/* Note that we have to test for the actual rtx used for the frame
and arg pointers and not just the register number in case we have
diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c
index c7feaba3718..c49f84d621f 100644
--- a/gcc/ira-costs.c
+++ b/gcc/ira-costs.c
@@ -1475,7 +1475,7 @@ scan_one_insn (rtx_insn *insn)
if (pat_code == USE || pat_code == CLOBBER)
{
rtx x = XEXP (PATTERN (insn), 0);
- if (GET_CODE (x) == REG
+ if (REG_P (x)
&& REGNO (x) >= FIRST_PSEUDO_REGISTER
&& have_regs_of_mode[GET_MODE (x)])
ira_init_register_move_cost_if_necessary (GET_MODE (x));
diff --git a/gcc/ira.c b/gcc/ira.c
index c58daba6e79..ac3493f202f 100644
--- a/gcc/ira.c
+++ b/gcc/ira.c
@@ -2206,7 +2206,7 @@ ira_bad_reload_regno_1 (int regno, rtx x)
enum reg_class pref;
/* We only deal with pseudo regs. */
- if (! x || GET_CODE (x) != REG)
+ if (! x || !REG_P (x))
return false;
x_regno = REGNO (x);
diff --git a/gcc/lra-constraints.c b/gcc/lra-constraints.c
index f2584075937..e2a0c0afe3d 100644
--- a/gcc/lra-constraints.c
+++ b/gcc/lra-constraints.c
@@ -720,7 +720,7 @@ operands_match_p (rtx x, rtx y, int y_hard_regno)
if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))
&& x == SUBREG_REG (y))
return true;
- if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x))
+ if (REG_P (y) && code == SUBREG && REG_P (SUBREG_REG (x))
&& SUBREG_REG (x) == y)
return true;
diff --git a/gcc/mode-switching.c b/gcc/mode-switching.c
index 2ff21a40081..d706e02faf7 100644
--- a/gcc/mode-switching.c
+++ b/gcc/mode-switching.c
@@ -266,7 +266,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
&& EDGE_COUNT (EXIT_BLOCK_PTR_FOR_FN (cfun)->preds) == 1
&& NONJUMP_INSN_P ((last_insn = BB_END (src_bb)))
&& GET_CODE (PATTERN (last_insn)) == USE
- && GET_CODE ((ret_reg = XEXP (PATTERN (last_insn), 0))) == REG)
+ && REG_P ((ret_reg = XEXP (PATTERN (last_insn), 0))))
{
int ret_start = REGNO (ret_reg);
int nregs = REG_NREGS (ret_reg);
@@ -302,7 +302,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
case USE:
/* Skip USEs of multiple return registers.
__builtin_apply pattern is also handled here. */
- if (GET_CODE (XEXP (return_copy_pat, 0)) == REG
+ if (REG_P (XEXP (return_copy_pat, 0))
&& (targetm.calls.function_value_regno_p
(REGNO (XEXP (return_copy_pat, 0)))))
{
@@ -344,7 +344,7 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
the previous insn is the clobber for
the return register. */
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG
+ if (REG_P (copy_reg)
&& !HARD_REGISTER_NUM_P (REGNO (copy_reg)))
{
if (INSN_P (PREV_INSN (return_copy)))
@@ -358,10 +358,10 @@ create_pre_exit (int n_entities, int *entity_map, const int *num_modes)
}
}
copy_reg = SET_DEST (return_copy_pat);
- if (GET_CODE (copy_reg) == REG)
+ if (REG_P (copy_reg))
copy_start = REGNO (copy_reg);
else if (GET_CODE (copy_reg) == SUBREG
- && GET_CODE (SUBREG_REG (copy_reg)) == REG)
+ && REG_P (SUBREG_REG (copy_reg)))
copy_start = REGNO (SUBREG_REG (copy_reg));
else
{
diff --git a/gcc/read-rtl-function.c b/gcc/read-rtl-function.c
index f41f54a0d4a..25d9f674612 100644
--- a/gcc/read-rtl-function.c
+++ b/gcc/read-rtl-function.c
@@ -1446,7 +1446,7 @@ ensure_regno (int regno)
static rtx
consolidate_reg (rtx x)
{
- gcc_assert (GET_CODE (x) == REG);
+ gcc_assert (REG_P (x));
unsigned int regno = REGNO (x);
@@ -1463,7 +1463,7 @@ consolidate_reg (rtx x)
if (regno_reg_rtx[regno] == NULL)
regno_reg_rtx[regno] = x;
/* Use it. */
- gcc_assert (GET_CODE (regno_reg_rtx[regno]) == REG);
+ gcc_assert (REG_P (regno_reg_rtx[regno]));
gcc_assert (REGNO (regno_reg_rtx[regno]) == regno);
if (GET_MODE (x) == GET_MODE (regno_reg_rtx[regno]))
return regno_reg_rtx[regno];
diff --git a/gcc/ree.c b/gcc/ree.c
index 03d610137f9..e4de9743e4c 100644
--- a/gcc/ree.c
+++ b/gcc/ree.c
@@ -541,10 +541,10 @@ is_cond_copy_insn (rtx_insn *insn, rtx *reg1, rtx *reg2)
if (expr != NULL_RTX
&& GET_CODE (expr) == SET
- && GET_CODE (SET_DEST (expr)) == REG
+ && REG_P (SET_DEST (expr))
&& GET_CODE (SET_SRC (expr)) == IF_THEN_ELSE
- && GET_CODE (XEXP (SET_SRC (expr), 1)) == REG
- && GET_CODE (XEXP (SET_SRC (expr), 2)) == REG)
+ && REG_P (XEXP (SET_SRC (expr), 1))
+ && REG_P (XEXP (SET_SRC (expr), 2)))
{
*reg1 = XEXP (SET_SRC (expr), 1);
*reg2 = XEXP (SET_SRC (expr), 2);
diff --git a/gcc/regrename.c b/gcc/regrename.c
index 73c0ceda341..3b144f5e38b 100644
--- a/gcc/regrename.c
+++ b/gcc/regrename.c
@@ -1088,8 +1088,8 @@ scan_rtx_reg (rtx_insn *insn, rtx *loc, enum reg_class cl, enum scan_actions act
a single output. */
if (recog_data.n_operands == 2
&& GET_CODE (pat) == SET
- && GET_CODE (SET_DEST (pat)) == REG
- && GET_CODE (SET_SRC (pat)) == REG
+ && REG_P (SET_DEST (pat))
+ && REG_P (SET_SRC (pat))
&& terminated_this_insn
&& terminated_this_insn->nregs
== REG_NREGS (recog_data.operand[1]))
diff --git a/gcc/valtrack.c b/gcc/valtrack.c
index 1f67378a867..87879b5f0f9 100644
--- a/gcc/valtrack.c
+++ b/gcc/valtrack.c
@@ -320,7 +320,7 @@ dead_debug_global_replace_temp (struct dead_debug_global *global,
dead_debug_global_entry *entry
= dead_debug_global_find (global, *DF_REF_REAL_LOC (use));
- gcc_checking_assert (GET_CODE (entry->reg) == REG
+ gcc_checking_assert (REG_P (entry->reg)
&& REGNO (entry->reg) == uregno);
if (!entry->dtemp)
@@ -420,7 +420,7 @@ dead_debug_promote_uses (struct dead_debug_local *debug)
df_ref ref;
dead_debug_global_entry *entry;
- if (GET_CODE (reg) != REG
+ if (!REG_P (reg)
|| REGNO (reg) < FIRST_PSEUDO_REGISTER)
{
headp = &head->next;
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index 599c6bd7f33..353df6b6618 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -2609,7 +2609,7 @@ val_reset (dataflow_set *set, decl_or_value dv)
{
if (node->loc == cval)
continue;
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
var_reg_decl_set (set, node->loc, node->init, cdv, 0,
node->set_src, NO_INSERT);
else if (GET_CODE (node->loc) == MEM)
@@ -3814,7 +3814,7 @@ canonicalize_values_star (variable **slot, dataflow_set *set)
parent. */
clobber_variable_part (set, cval, ndv, 0, NULL);
}
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *list = set->regs[REGNO (node->loc)], **listp;
@@ -4072,7 +4072,7 @@ variable_merge_over_cur (variable *s1var, struct dfset_merge *dsm)
{
location_chain **nextp = &node->next;
- if (GET_CODE (node->loc) == REG)
+ if (REG_P (node->loc))
{
attrs *list;
@@ -4444,7 +4444,7 @@ variable_post_merge_new_vals (variable **slot, dfset_post_merge *dfpm)
{
if (GET_CODE (node->loc) == VALUE)
gcc_assert (!VALUE_RECURSED_INTO (node->loc));
- else if (GET_CODE (node->loc) == REG)
+ else if (REG_P (node->loc))
{
attrs *att, **attp, **curp = NULL;
@@ -6832,7 +6832,7 @@ compute_bb_dataflow (basic_block bb)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (out, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
else if (GET_CODE (uloc) == MEM)
@@ -6885,7 +6885,7 @@ compute_bb_dataflow (basic_block bb)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (out, val, SET_SRC (uloc), insn);
}
@@ -9330,7 +9330,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
if (VAL_HOLDS_TRACK_EXPR (loc))
{
- if (GET_CODE (uloc) == REG)
+ if (REG_P (uloc))
var_reg_set (set, uloc, VAR_INIT_STATUS_UNINITIALIZED,
NULL);
else if (GET_CODE (uloc) == MEM)
@@ -9385,7 +9385,7 @@ emit_notes_in_bb (basic_block bb, dataflow_set *set)
else if (VAL_NEEDS_RESOLUTION (loc))
{
gcc_assert (GET_CODE (uloc) == SET
- && GET_CODE (SET_SRC (uloc)) == REG);
+ && REG_P (SET_SRC (uloc)));
val_resolve (set, val, SET_SRC (uloc), insn);
}
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 16/18] Use SYMBOL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SYMBOL_REF
2019-08-06 3:11 ` Arvind Sankar
` (12 preceding siblings ...)
2019-08-06 3:12 ` [PATCH v2 05/18] Use CONST_FIXED_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_FIXED Arvind Sankar
@ 2019-08-06 3:13 ` Arvind Sankar
2019-08-06 3:13 ` [PATCH v2 18/18] Use DEBUG_INSN_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh DEBUG_INSN_P Arvind Sankar
` (3 subsequent siblings)
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:13 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* alias.c: Convert GET_CODE (..) == SYMBOL_REF to
SYMBOL_REF_P (..).
* asan.c: Likewise.
* builtins.c: Likewise.
* calls.c: Likewise.
* cfgcleanup.c: Likewise.
* cfgexpand.c: Likewise.
* combine.c: Likewise.
* config/aarch64/aarch64.c: Likewise.
* config/aarch64/predicates.md: Likewise.
* config/alpha/alpha.c: Likewise.
* config/alpha/alpha.md: Likewise.
* config/alpha/predicates.md: Likewise.
* config/arc/arc.c: Likewise.
* config/arc/arc.h: Likewise.
* config/arc/predicates.md: Likewise.
* config/arm/arm.c: Likewise.
* config/arm/arm.h: Likewise.
* config/arm/arm.md: Likewise.
* config/arm/thumb1.md: Likewise.
* config/bfin/bfin.c: Likewise.
* config/bfin/bfin.h: Likewise.
* config/bfin/bfin.md: Likewise.
* config/bfin/predicates.md: Likewise.
* config/c6x/c6x.c: Likewise.
* config/c6x/predicates.md: Likewise.
* config/cr16/cr16.c: Likewise.
* config/cr16/cr16.h: Likewise.
* config/cris/cris.c: Likewise.
* config/cris/cris.md: Likewise.
* config/csky/csky.c: Likewise.
* config/csky/csky.h: Likewise.
* config/csky/csky.md: Likewise.
* config/csky/predicates.md: Likewise.
* config/darwin.c: Likewise.
* config/darwin.h: Likewise.
* config/epiphany/epiphany.c: Likewise.
* config/epiphany/epiphany.h: Likewise.
* config/epiphany/predicates.md: Likewise.
* config/fr30/predicates.md: Likewise.
* config/frv/frv.c: Likewise.
* config/frv/predicates.md: Likewise.
* config/ft32/constraints.md: Likewise.
* config/ft32/ft32.c: Likewise.
* config/ft32/ft32.md: Likewise.
* config/ft32/predicates.md: Likewise.
* config/gcn/gcn.c: Likewise.
* config/gcn/gcn.md: Likewise.
* config/h8300/h8300.c: Likewise.
* config/h8300/h8300.h: Likewise.
* config/h8300/h8300.md: Likewise.
* config/h8300/predicates.md: Likewise.
* config/i386/i386-expand.c: Likewise.
* config/i386/i386-features.c: Likewise.
* config/i386/i386.c: Likewise.
* config/i386/i386.h: Likewise.
* config/i386/i386.md: Likewise.
* config/i386/predicates.md: Likewise.
* config/i386/winnt.c: Likewise.
* config/ia64/ia64.c: Likewise.
* config/ia64/predicates.md: Likewise.
* config/iq2000/iq2000.c: Likewise.
* config/iq2000/iq2000.h: Likewise.
* config/lm32/lm32.c: Likewise.
* config/lm32/lm32.h: Likewise.
* config/lm32/lm32.md: Likewise.
* config/m32c/addsub.md: Likewise.
* config/m32c/m32c.c: Likewise.
* config/m32r/m32r.c: Likewise.
* config/m32r/m32r.h: Likewise.
* config/m32r/predicates.md: Likewise.
* config/m68k/constraints.md: Likewise.
* config/m68k/m68k.c: Likewise.
* config/m68k/m68k.h: Likewise.
* config/m68k/m68k.md: Likewise.
* config/m68k/predicates.md: Likewise.
* config/mcore/mcore.c: Likewise.
* config/microblaze/microblaze.c: Likewise.
* config/microblaze/microblaze.md: Likewise.
* config/microblaze/predicates.md: Likewise.
* config/mips/mips.c: Likewise.
* config/mips/predicates.md: Likewise.
* config/mmix/mmix.c: Likewise.
* config/mmix/predicates.md: Likewise.
* config/mn10300/constraints.md: Likewise.
* config/mn10300/mn10300.c: Likewise.
* config/mn10300/mn10300.h: Likewise.
* config/mn10300/mn10300.md: Likewise.
* config/mn10300/predicates.md: Likewise.
* config/moxie/constraints.md: Likewise.
* config/moxie/moxie.c: Likewise.
* config/msp430/msp430.c: Likewise.
* config/nds32/nds32-md-auxiliary.c: Likewise.
* config/nds32/nds32-predicates.c: Likewise.
* config/nds32/nds32-utils.c: Likewise.
* config/nds32/nds32.c: Likewise.
* config/nds32/nds32.h: Likewise.
* config/nios2/nios2.c: Likewise.
* config/nvptx/nvptx.c: Likewise.
* config/or1k/or1k.c: Likewise.
* config/pa/pa.c: Likewise.
* config/pa/pa.h: Likewise.
* config/pa/pa.md: Likewise.
* config/pa/predicates.md: Likewise.
* config/riscv/riscv.c: Likewise.
* config/rl78/constraints.md: Likewise.
* config/rl78/rl78-expand.md: Likewise.
* config/rl78/rl78.c: Likewise.
* config/rs6000/rs6000.c: Likewise.
* config/rx/constraints.md: Likewise.
* config/rx/rx.c: Likewise.
* config/s390/s390.c: Likewise.
* config/s390/s390.h: Likewise.
* config/s390/s390.md: Likewise.
* config/sh/sh.c: Likewise.
* config/sh/sh.h: Likewise.
* config/sh/sh.md: Likewise.
* config/sparc/predicates.md: Likewise.
* config/sparc/sparc.c: Likewise.
* config/spu/constraints.md: Likewise.
* config/spu/spu.c: Likewise.
* config/spu/spu.h: Likewise.
* config/stormy16/stormy16.c: Likewise.
* config/tilegx/predicates.md: Likewise.
* config/tilegx/tilegx.c: Likewise.
* config/tilegx/tilegx.md: Likewise.
* config/tilepro/predicates.md: Likewise.
* config/tilepro/tilepro.c: Likewise.
* config/v850/constraints.md: Likewise.
* config/v850/predicates.md: Likewise.
* config/v850/v850.c: Likewise.
* config/vax/predicates.md: Likewise.
* config/vax/vax.c: Likewise.
* config/vax/vax.md: Likewise.
* config/xtensa/predicates.md: Likewise.
* config/xtensa/xtensa.c: Likewise.
* config/xtensa/xtensa.h: Likewise.
* config/xtensa/xtensa.md: Likewise.
* cselib.c: Likewise.
* dbxout.c: Likewise.
* dse.c: Likewise.
* dwarf2asm.c: Likewise.
* dwarf2out.c: Likewise.
* explow.c: Likewise.
* expr.c: Likewise.
* final.c: Likewise.
* gcse.c: Likewise.
* genattrtab.c: Likewise.
* ifcvt.c: Likewise.
* lower-subreg.c: Likewise.
* optabs.c: Likewise.
* postreload.c: Likewise.
* print-rtl.c: Likewise.
* reginfo.c: Likewise.
* reload.c: Likewise.
* rtl.c: Likewise.
* rtlanal.c: Likewise.
* sched-deps.c: Likewise.
* simplify-rtx.c: Likewise.
* symtab.c: Likewise.
* tree-ssa-address.c: Likewise.
* var-tracking.c: Likewise.
* varasm.c: Likewise.
* xcoffout.h: Likewise.
163 files changed, 701 insertions(+), 701 deletions(-)
diff --git a/gcc/alias.c b/gcc/alias.c
index 24eaeae86f3..86ada16b6ae 100644
--- a/gcc/alias.c
+++ b/gcc/alias.c
@@ -2222,7 +2222,7 @@ base_alias_check (rtx x, rtx x_base, rtx y, rtx y_base,
return 1;
/* Differing symbols not accessed via AND never alias. */
- if (GET_CODE (x_base) == SYMBOL_REF && GET_CODE (y_base) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x_base) && SYMBOL_REF_P (y_base))
return compare_base_symbol_refs (x_base, y_base) != 0;
if (GET_CODE (x_base) != ADDRESS && GET_CODE (y_base) != ADDRESS)
@@ -2444,7 +2444,7 @@ memrefs_conflict_p (poly_int64 xsize, rtx x, poly_int64 ysize, rtx y,
else
y = addr_side_effect_eval (y, maybe_lt (ysize, 0) ? -ysize : ysize, 0);
- if (GET_CODE (x) == SYMBOL_REF && GET_CODE (y) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_P (y))
{
int cmp = compare_base_symbol_refs (x,y);
@@ -2955,7 +2955,7 @@ true_dependence_1 (const_rtx mem, machine_mode mem_mode, rtx mem_addr,
base = find_base_term (x_addr);
if (base && (LABEL_REF_P (base)
- || (GET_CODE (base) == SYMBOL_REF
+ || (SYMBOL_REF_P (base)
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
@@ -3064,7 +3064,7 @@ write_dependence_p (const_rtx mem,
if (! writep
&& base
&& (LABEL_REF_P (base)
- || (GET_CODE (base) == SYMBOL_REF
+ || (SYMBOL_REF_P (base)
&& CONSTANT_POOL_ADDRESS_P (base))))
return 0;
diff --git a/gcc/asan.c b/gcc/asan.c
index a731bd490b4..9976f709a88 100644
--- a/gcc/asan.c
+++ b/gcc/asan.c
@@ -1805,7 +1805,7 @@ asan_protect_global (tree decl, bool ignore_decl_rtl_set_p)
{
rtl = DECL_RTL (decl);
- if (!MEM_P (rtl) || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF)
+ if (!MEM_P (rtl) || !SYMBOL_REF_P (XEXP (rtl, 0)))
return false;
symbol = XEXP (rtl, 0);
diff --git a/gcc/builtins.c b/gcc/builtins.c
index 695a9d191af..c01c9d4c789 100644
--- a/gcc/builtins.c
+++ b/gcc/builtins.c
@@ -1796,7 +1796,7 @@ expand_builtin_apply (rtx function, rtx arguments, rtx argsize)
/* Ensure address is valid. SYMBOL_REF is already valid, so no need,
and we don't want to load it into a register as an optimization,
because prepare_call_address already did it if it should be done. */
- if (GET_CODE (function) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (function))
function = memory_address (FUNCTION_MODE, function);
/* Generate the actual call instruction and save the return value. */
diff --git a/gcc/calls.c b/gcc/calls.c
index 453308f1ca1..7be7d3b7211 100644
--- a/gcc/calls.c
+++ b/gcc/calls.c
@@ -217,7 +217,7 @@ prepare_call_address (tree fndecl_or_type, rtx funexp, rtx static_chain_value,
{
/* Make a valid memory address and copy constants through pseudo-regs,
but not for a constant address if -fno-function-cse. */
- if (GET_CODE (funexp) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (funexp))
{
/* If it's an indirect call by descriptor, generate code to perform
runtime identification of the pointer and load the descriptor. */
@@ -393,7 +393,7 @@ emit_call_1 (rtx funexp, tree fntree ATTRIBUTE_UNUSED, tree fndecl ATTRIBUTE_UNU
/* Ensure address is valid. SYMBOL_REF is already valid, so no need,
and we don't want to load it into a register as an optimization,
because prepare_call_address already did it if it should be done. */
- if (GET_CODE (funexp) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (funexp))
funexp = memory_address (FUNCTION_MODE, funexp);
funmem = gen_rtx_MEM (FUNCTION_MODE, funexp);
@@ -4286,7 +4286,7 @@ expand_call (tree exp, rtx target, int ignore)
{
datum = XEXP (DECL_RTL (fndecl), 0);
gcc_assert (datum != NULL_RTX
- && GET_CODE (datum) == SYMBOL_REF);
+ && SYMBOL_REF_P (datum));
}
last = last_call_insn ();
add_reg_note (last, REG_CALL_DECL, datum);
@@ -5333,7 +5333,7 @@ emit_library_call_value_1 (int retval, rtx orgfun, rtx value,
if (flag_ipa_ra)
{
rtx datum = orgfun;
- gcc_assert (GET_CODE (datum) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (datum));
rtx_call_insn *last = last_call_insn ();
add_reg_note (last, REG_CALL_DECL, datum);
}
diff --git a/gcc/cfgcleanup.c b/gcc/cfgcleanup.c
index b9307631e1c..e6d3b00364f 100644
--- a/gcc/cfgcleanup.c
+++ b/gcc/cfgcleanup.c
@@ -1209,7 +1209,7 @@ old_insns_match_p (int mode ATTRIBUTE_UNUSED, rtx_insn *i1, rtx_insn *i2)
if (flag_sanitize & SANITIZE_ADDRESS)
{
rtx call = get_call_rtx_from (i1);
- if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (call && SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol)
diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c
index f4832c6d2bb..8f573140d62 100644
--- a/gcc/cfgexpand.c
+++ b/gcc/cfgexpand.c
@@ -4411,7 +4411,7 @@ expand_debug_expr (tree exp)
op0 = make_decl_rtl_for_debug (exp);
if (!MEM_P (op0)
- || GET_CODE (XEXP (op0, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op0, 0))
|| SYMBOL_REF_DECL (XEXP (op0, 0)) != exp)
return NULL;
}
diff --git a/gcc/combine.c b/gcc/combine.c
index f1e786d5678..1f43dd02dab 100644
--- a/gcc/combine.c
+++ b/gcc/combine.c
@@ -4971,7 +4971,7 @@ find_split_point (rtx *loc, rtx_insn *insn, bool set_src)
/* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
using LO_SUM and HIGH. */
if (HAVE_lo_sum && (GET_CODE (XEXP (x, 0)) == CONST
- || GET_CODE (XEXP (x, 0)) == SYMBOL_REF))
+ || SYMBOL_REF_P (XEXP (x, 0))))
{
machine_mode address_mode = get_address_mode (x);
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4927ee9320f..dc39554a25b 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1717,7 +1717,7 @@ aarch64_simd_call_p (rtx_insn *insn)
gcc_assert (CALL_P (insn));
call = get_call_rtx_from (insn);
symbol = XEXP (XEXP (call, 0), 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return false;
fndecl = SYMBOL_REF_DECL (symbol);
if (!fndecl)
@@ -1955,10 +1955,10 @@ tls_symbolic_operand_type (rtx addr)
{
poly_int64 addend;
rtx sym = strip_offset (addr, &addend);
- if (GET_CODE (sym) == SYMBOL_REF)
+ if (SYMBOL_REF_P (sym))
tls_kind = SYMBOL_REF_TLS_MODEL (sym);
}
- else if (GET_CODE (addr) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (addr))
tls_kind = SYMBOL_REF_TLS_MODEL (addr);
return tls_kind;
@@ -3290,7 +3290,7 @@ aarch64_expand_mov_immediate (rtx dest, rtx imm,
/* Check on what type of symbol it is. */
scalar_int_mode int_mode;
- if ((GET_CODE (imm) == SYMBOL_REF
+ if ((SYMBOL_REF_P (imm)
|| LABEL_REF_P (imm)
|| GET_CODE (imm) == CONST
|| GET_CODE (imm) == CONST_POLY_INT)
@@ -6126,7 +6126,7 @@ aarch64_tls_referenced_p (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
return true;
/* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
TLS offsets, not real symbol references. */
@@ -6329,7 +6329,7 @@ aarch64_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return true;
split_const (x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF || LABEL_REF_P (base))
+ if (SYMBOL_REF_P (base) || LABEL_REF_P (base))
{
if (aarch64_classify_symbol (base, INTVAL (offset))
!= SYMBOL_FORCE_TO_MEM)
@@ -6855,7 +6855,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
split_const (x, &sym, &addend);
return ((LABEL_REF_P (sym)
- || (GET_CODE (sym) == SYMBOL_REF
+ || (SYMBOL_REF_P (sym)
&& CONSTANT_POOL_ADDRESS_P (sym)
&& aarch64_pcrelative_literal_loads)));
}
@@ -6870,7 +6870,7 @@ aarch64_classify_address (struct aarch64_address_info *info,
{
rtx sym, offs;
split_const (info->offset, &sym, &offs);
- if (GET_CODE (sym) == SYMBOL_REF
+ if (SYMBOL_REF_P (sym)
&& (aarch64_classify_symbol (sym, INTVAL (offs))
== SYMBOL_SMALL_ABSOLUTE))
{
@@ -6932,7 +6932,7 @@ aarch64_symbolic_address_p (rtx x)
rtx offset;
split_const (x, &x, &offset);
- return GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x);
+ return SYMBOL_REF_P (x) || LABEL_REF_P (x);
}
/* Classify the base of symbolic expression X. */
@@ -7654,7 +7654,7 @@ aarch64_print_operand (FILE *f, rtx x, int code)
case CONST:
if (GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0)))
{
output_addr_const (f, x);
break;
@@ -8408,7 +8408,7 @@ aarch64_secondary_reload (bool in_p ATTRIBUTE_UNUSED, rtx x,
/* If we have to disable direct literal pool loads and stores because the
function is too big, then we need a scratch register. */
- if (MEM_P (x) && GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x)
+ if (MEM_P (x) && SYMBOL_REF_P (x) && CONSTANT_POOL_ADDRESS_P (x)
&& (SCALAR_FLOAT_MODE_P (GET_MODE (x))
|| targetm.vector_mode_supported_p (GET_MODE (x)))
&& !aarch64_pcrelative_literal_loads)
@@ -9067,7 +9067,7 @@ aarch64_address_cost (rtx x,
if (!aarch64_classify_address (&info, x, mode, false))
{
- if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF)
+ if (GET_CODE (x) == CONST || SYMBOL_REF_P (x))
{
/* This is a CONST or SYMBOL ref which will be split
in a different way depending on the code model in use.
@@ -13036,7 +13036,7 @@ aarch64_tls_symbol_p (rtx x)
if (! TARGET_HAVE_TLS)
return false;
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return false;
return SYMBOL_REF_TLS_MODEL (x) != 0;
@@ -13112,7 +13112,7 @@ aarch64_classify_symbol (rtx x, HOST_WIDE_INT offset)
}
}
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (aarch64_tls_symbol_p (x))
return aarch64_classify_tls_symbol (x);
@@ -13185,10 +13185,10 @@ aarch64_constant_address_p (rtx x)
bool
aarch64_legitimate_pic_operand_p (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
|| (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))))
return false;
return true;
@@ -14764,7 +14764,7 @@ aarch64_mov_operand_p (rtx x, machine_mode mode)
if (VECTOR_MODE_P (GET_MODE (x)))
return aarch64_simd_valid_immediate (x, NULL);
- if (GET_CODE (x) == SYMBOL_REF && mode == DImode && CONSTANT_ADDRESS_P (x))
+ if (SYMBOL_REF_P (x) && mode == DImode && CONSTANT_ADDRESS_P (x))
return true;
if (aarch64_sve_cnt_immediate_p (x))
diff --git a/gcc/config/aarch64/predicates.md b/gcc/config/aarch64/predicates.md
index ef01faed19c..ca33b0fda1f 100644
--- a/gcc/config/aarch64/predicates.md
+++ b/gcc/config/aarch64/predicates.md
@@ -264,7 +264,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
@@ -286,7 +286,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
diff --git a/gcc/config/alpha/alpha.c b/gcc/config/alpha/alpha.c
index f0e4061fb00..46cd61b472a 100644
--- a/gcc/config/alpha/alpha.c
+++ b/gcc/config/alpha/alpha.c
@@ -654,7 +654,7 @@ tls_symbolic_operand_1 (rtx op, int size, int unspec)
return 0;
op = XVECEXP (op, 0, 0);
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return 0;
switch (SYMBOL_REF_TLS_MODEL (op))
@@ -738,7 +738,7 @@ tls_symbolic_operand_type (rtx symbol)
{
enum tls_model model;
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return TLS_MODEL_NONE;
model = SYMBOL_REF_TLS_MODEL (symbol);
@@ -829,11 +829,11 @@ alpha_linkage_symbol_p (const char *symname)
}
#define LINKAGE_SYMBOL_REF_P(X) \
- ((GET_CODE (X) == SYMBOL_REF \
+ ((SYMBOL_REF_P (X) \
&& alpha_linkage_symbol_p (XSTR (X, 0))) \
|| (GET_CODE (X) == CONST \
&& GET_CODE (XEXP (X, 0)) == PLUS \
- && GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF \
+ && SYMBOL_REF_P (XEXP (XEXP (X, 0), 0)) \
&& alpha_linkage_symbol_p (XSTR (XEXP (XEXP (X, 0), 0), 0))))
#endif
@@ -2143,7 +2143,7 @@ alpha_legitimate_constant_p (machine_mode mode, rtx x)
else
return true;
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return true;
/* FALLTHRU */
@@ -5455,7 +5455,7 @@ alpha_print_operand_address (FILE *file, machine_mode /*mode*/, rtx addr)
case CONST:
gcc_assert(TARGET_ABI_OPEN_VMS || this_is_asm_operands);
gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF);
+ && SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0)));
fprintf (file, "%s+" HOST_WIDE_INT_PRINT_DEC,
XSTR (XEXP (XEXP (addr, 0), 0), 0),
INTVAL (XEXP (XEXP (addr, 0), 1)));
diff --git a/gcc/config/alpha/alpha.md b/gcc/config/alpha/alpha.md
index b195eb9c698..2cd36b8cc82 100644
--- a/gcc/config/alpha/alpha.md
+++ b/gcc/config/alpha/alpha.md
@@ -3303,7 +3303,7 @@
both cases. */
emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]);
- if (GET_CODE (operands[0]) == SYMBOL_REF)
+ if (SYMBOL_REF_P (operands[0]))
{
operands[2] = const0_rtx;
}
@@ -3378,7 +3378,7 @@
both cases. */
emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]);
- if (GET_CODE (operands[1]) == SYMBOL_REF)
+ if (SYMBOL_REF_P (operands[1]))
{
operands[3] = const0_rtx;
}
diff --git a/gcc/config/alpha/predicates.md b/gcc/config/alpha/predicates.md
index f96c16b533c..3e756353600 100644
--- a/gcc/config/alpha/predicates.md
+++ b/gcc/config/alpha/predicates.md
@@ -299,7 +299,7 @@
if (LABEL_REF_P (op))
return 1;
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return 0;
return (SYMBOL_REF_LOCAL_P (op)
@@ -325,7 +325,7 @@
op = XEXP (XEXP (op, 0), 0);
}
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return false;
/* ??? There's no encode_section_info equivalent for the rtl
@@ -368,7 +368,7 @@
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return 0;
return ((!SYMBOL_REF_LOCAL_P (op) || SYMBOL_REF_WEAK (op))
diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
index 13cb4706ae5..ee10dd39a38 100644
--- a/gcc/config/arc/arc.c
+++ b/gcc/config/arc/arc.c
@@ -470,7 +470,7 @@ legitimate_small_data_address_p (rtx x)
return SYMBOL_REF_SMALL_P (x);
case PLUS:
{
- bool p0 = (GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
+ bool p0 = (SYMBOL_REF_P (XEXP (x, 0)))
&& SYMBOL_REF_SMALL_P (XEXP (x, 0));
bool p1 = CONST_INT_P (XEXP (x, 1))
&& (INTVAL (XEXP (x, 1)) <= g_switch_value);
@@ -557,7 +557,7 @@ legitimate_offset_address_p (machine_mode mode, rtx x, bool index, bool strict)
/* Check for [Rx + symbol]. */
if (!flag_pic
- && (GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ && (SYMBOL_REF_P (XEXP (x, 1)))
/* Avoid this type of address for double or larger modes. */
&& (GET_MODE_SIZE (mode) <= 4)
/* Avoid small data which ends in something like GP +
@@ -2263,7 +2263,7 @@ gen_compare_reg (rtx comparison, machine_mode omode)
else
x = copy_to_mode_reg (SImode, x);
}
- if (GET_CODE (y) == SYMBOL_REF && flag_pic)
+ if (SYMBOL_REF_P (y) && flag_pic)
y = copy_to_mode_reg (SImode, y);
}
else
@@ -4634,7 +4634,7 @@ arc_print_operand (FILE *file, rtx x, int code)
return;
case 'j':
case 'S' :
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& arc_is_jli_call_p (x))
{
if (SYMBOL_REF_DECL (x))
@@ -4659,7 +4659,7 @@ arc_print_operand (FILE *file, rtx x, int code)
arc_add_jli_section (x);
return;
}
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& arc_is_secure_call_p (x))
{
/* No special treatment for secure functions. */
@@ -4845,7 +4845,7 @@ arc_print_operand (FILE *file, rtx x, int code)
}
output_operand_lossage ("invalid operand to %%O code"); return;
case 'o':
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
assemble_name (file, XSTR (x, 0));
return;
@@ -5003,7 +5003,7 @@ arc_print_operand_address (FILE *file , rtx addr)
break;
}
gcc_assert (GET_CODE (c) == PLUS);
- gcc_assert (GET_CODE (XEXP (c, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (c, 0)));
gcc_assert (CONST_INT_P (XEXP (c, 1)));
output_address (VOIDmode, XEXP (addr, 0));
@@ -6031,7 +6031,7 @@ arc_legitimate_pic_addr_p (rtx addr)
&& XINT (addr, 1) != UNSPEC_TLS_IE)
return false;
- if (GET_CODE (XVECEXP (addr, 0, 0)) != SYMBOL_REF
+ if (!SYMBOL_REF_P (XVECEXP (addr, 0, 0))
&& !LABEL_REF_P (XVECEXP (addr, 0, 0)))
return false;
@@ -6048,7 +6048,7 @@ symbolic_reference_mentioned_p (rtx op)
register const char *fmt;
register int i;
- if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
+ if (SYMBOL_REF_P (op) || LABEL_REF_P (op))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -6084,7 +6084,7 @@ arc_raw_symbolic_reference_mentioned_p (rtx op, bool skip_local)
if (GET_CODE(op) == UNSPEC)
return false;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
{
if (SYMBOL_REF_TLS_MODEL (op))
return true;
@@ -6677,7 +6677,7 @@ arc_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (!flag_pic && optimize_size && !reload_completed
&& (GET_CODE (x) == CONST)
&& (GET_CODE (XEXP (x, 0)) == PLUS)
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
+ && (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0)))
&& SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0)) == 0
&& !SYMBOL_REF_FUNCTION_P (XEXP (XEXP (x, 0), 0)))
{
@@ -7528,7 +7528,7 @@ arc_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED,
bool
arc_is_longcall_p (rtx sym_ref)
{
- if (GET_CODE (sym_ref) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (sym_ref))
return false;
return (SYMBOL_REF_LONG_CALL_P (sym_ref)
@@ -7543,7 +7543,7 @@ arc_is_longcall_p (rtx sym_ref)
bool
arc_is_shortcall_p (rtx sym_ref)
{
- if (GET_CODE (sym_ref) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (sym_ref))
return false;
return (SYMBOL_REF_SHORT_CALL_P (sym_ref)
@@ -8231,7 +8231,7 @@ jli_call_scan (void)
pat = SET_SRC (pat);
pat = XEXP (XEXP (pat, 0), 0);
- if (GET_CODE (pat) == SYMBOL_REF
+ if (SYMBOL_REF_P (pat)
&& arc_is_jli_call_p (pat))
arc_add_jli_section (pat);
}
@@ -9168,7 +9168,7 @@ prepare_move_operands (rtx *operands, machine_mode mode)
else
{
tmp = XEXP (operands[1], 0);
- gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (tmp));
}
/* Load operation. */
gcc_assert (REG_P (operands[0]));
@@ -9180,7 +9180,7 @@ prepare_move_operands (rtx *operands, machine_mode mode)
}
}
- if (GET_CODE (operands[1]) == SYMBOL_REF)
+ if (SYMBOL_REF_P (operands[1]))
{
enum tls_model model = SYMBOL_REF_TLS_MODEL (operands[1]);
if (MEM_P (operands[0]))
@@ -9688,7 +9688,7 @@ arc_legitimize_address_0 (rtx x, rtx oldx ATTRIBUTE_UNUSED,
if (GET_CODE (addr) == PLUS
&& CONST_INT_P (XEXP (addr, 1))
- && ((GET_CODE (XEXP (addr, 0)) == SYMBOL_REF
+ && ((SYMBOL_REF_P (XEXP (addr, 0))
&& !SYMBOL_REF_FUNCTION_P (XEXP (addr, 0)))
|| (REG_P (XEXP (addr, 0))
&& (INTVAL (XEXP (addr, 1)) & 252))))
@@ -9706,7 +9706,7 @@ arc_legitimize_address_0 (rtx x, rtx oldx ATTRIBUTE_UNUSED,
addr = plus_constant (Pmode, force_reg (Pmode, inner), offs - upper);
x = addr;
}
- else if (GET_CODE (addr) == SYMBOL_REF && !SYMBOL_REF_FUNCTION_P (addr))
+ else if (SYMBOL_REF_P (addr) && !SYMBOL_REF_FUNCTION_P (addr))
x = force_reg (Pmode, x);
if (memory_address_p ((machine_mode) mode, x))
return x;
diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
index 94101cff349..e680c88f586 100644
--- a/gcc/config/arc/arc.h
+++ b/gcc/config/arc/arc.h
@@ -841,7 +841,7 @@ extern int arc_initial_elimination_offset(int from, int to);
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
(flag_pic ? (arc_legitimate_pic_addr_p (X) || LABEL_P (X)): \
- (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+ (LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == CONST))
/* Is the argument a const_int rtx, containing an exact power of 2 */
diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
index a5537ec73e4..7195ca3e6f0 100644
--- a/gcc/config/arc/predicates.md
+++ b/gcc/config/arc/predicates.md
@@ -143,7 +143,7 @@
&& (size <= 1 || size > 4
|| (INTVAL (x) & (size - 1)) != 0
|| !SMALL_INT (INTVAL (x) / size)));
- else if (GET_CODE (x) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (x))
return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x);
return 0;
}
@@ -367,7 +367,7 @@
&& (GET_CODE (XEXP (addr, 0)) == MULT
|| (!CONST_INT_P (XEXP (addr, 1))
&& (TARGET_NO_SDATA_SET
- || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (addr, 1))
|| !SYMBOL_REF_SMALL_P (XEXP (addr, 1))))))
return 0;
if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY)
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 2f8d68507ec..d3dd54c2990 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -7406,10 +7406,10 @@ arm_function_ok_for_sibcall (tree decl, tree exp)
int
legitimate_pic_operand_p (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
|| (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF))
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))))
return 0;
return 1;
@@ -7517,7 +7517,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
{
gcc_assert (compute_now == (pic_reg != NULL_RTX));
- if (GET_CODE (orig) == SYMBOL_REF
+ if (SYMBOL_REF_P (orig)
|| LABEL_REF_P (orig))
{
if (reg == 0)
@@ -7536,7 +7536,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg, rtx pic_reg,
may be overridden by a non-weak definition at link time. */
rtx_insn *insn;
if ((LABEL_REF_P (orig)
- || (GET_CODE (orig) == SYMBOL_REF
+ || (SYMBOL_REF_P (orig)
&& SYMBOL_REF_LOCAL_P (orig)
&& (SYMBOL_REF_DECL (orig)
? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1)))
@@ -7957,7 +7957,7 @@ can_avoid_literal_pool_for_label_p (rtx x)
(set (reg r0) (mem (reg r0))).
No extra register is required, and (mem (reg r0)) won't cause the use
of literal pools. */
- if (arm_disable_literal_pool && GET_CODE (x) == SYMBOL_REF
+ if (arm_disable_literal_pool && SYMBOL_REF_P (x)
&& CONSTANT_POOL_ADDRESS_P (x))
return 1;
return 0;
@@ -8330,7 +8330,7 @@ thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
/* This is PC relative data before arm_reorg runs. */
else if (GET_MODE_SIZE (mode) >= 4 && CONSTANT_P (x)
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& CONSTANT_POOL_ADDRESS_P (x) && !flag_pic)
return 1;
@@ -8397,7 +8397,7 @@ thumb1_legitimate_address_p (machine_mode mode, rtx x, int strict_p)
else if (GET_MODE_CLASS (mode) != MODE_FLOAT
&& GET_MODE_SIZE (mode) == 4
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& CONSTANT_POOL_ADDRESS_P (x)
&& ! (flag_pic
&& symbol_mentioned_p (get_pool_constant (x))
@@ -8679,7 +8679,7 @@ arm_legitimize_address (rtx x, rtx orig_x, machine_mode mode)
x = XEXP (XEXP (x, 0), 0);
}
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return x;
gcc_assert (SYMBOL_REF_TLS_MODEL (x) != 0);
@@ -8890,7 +8890,7 @@ arm_tls_referenced_p (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
{
/* ARM currently does not provide relocations to encode TLS variables
into AArch32 instructions, only data, so there is no way to
@@ -8936,7 +8936,7 @@ thumb_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return (CONST_INT_P (x)
|| CONST_DOUBLE_P (x)
|| CONSTANT_ADDRESS_P (x)
- || (TARGET_HAVE_MOVT && GET_CODE (x) == SYMBOL_REF)
+ || (TARGET_HAVE_MOVT && SYMBOL_REF_P (x))
|| flag_pic);
}
@@ -9082,7 +9082,7 @@ thumb1_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
/* Memory costs quite a lot for the first word, but subsequent words
load at the equivalent of a single insn each. */
return (10 + 4 * ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
- + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
+ + ((SYMBOL_REF_P (x) && CONSTANT_POOL_ADDRESS_P (x))
? 4 : 0));
case IF_THEN_ELSE:
@@ -9237,7 +9237,7 @@ thumb1_size_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer)
return (COSTS_N_INSNS (1)
+ COSTS_N_INSNS (1)
* ((GET_MODE_SIZE (mode) - 1) / UNITS_PER_WORD)
- + ((GET_CODE (x) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (x))
+ + ((SYMBOL_REF_P (x) && CONSTANT_POOL_ADDRESS_P (x))
? COSTS_N_INSNS (1) : 0));
case IF_THEN_ELSE:
@@ -11742,7 +11742,7 @@ arm_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep, int cost,
constant pool are cached, and that others will miss. This is a
hack. */
- if ((GET_CODE (src_mem) == SYMBOL_REF
+ if ((SYMBOL_REF_P (src_mem)
&& CONSTANT_POOL_ADDRESS_P (src_mem))
|| reg_mentioned_p (stack_pointer_rtx, src_mem)
|| reg_mentioned_p (frame_pointer_rtx, src_mem)
@@ -12825,7 +12825,7 @@ symbol_mentioned_p (rtx x)
const char * fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return 1;
/* UNSPEC_TLS entries for a symbol include the SYMBOL_REF, but they
@@ -16931,7 +16931,7 @@ note_invalid_constants (rtx_insn *insn, HOST_WIDE_INT address, int do_pushes)
recog_data.operand_mode[opno], op);
}
else if (MEM_P (op)
- && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (op, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (op, 0)))
{
if (do_pushes)
@@ -18215,7 +18215,7 @@ arm_emit_call_insn (rtx pat, rtx addr, bool sibcall)
if (TARGET_VXWORKS_RTP
&& flag_pic
&& !sibcall
- && GET_CODE (addr) == SYMBOL_REF
+ && SYMBOL_REF_P (addr)
&& (SYMBOL_REF_DECL (addr)
? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
: !SYMBOL_REF_LOCAL_P (addr)))
@@ -22298,7 +22298,7 @@ arm_print_operand (FILE *stream, rtx x, int code)
case CONST:
if (GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0)))
{
output_addr_const (stream, x);
break;
@@ -23034,7 +23034,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
/* Mark symbols as position independent. We only do this in the
.text segment, not in the .data segment. */
if (NEED_GOT_RELOC && flag_pic && making_const_table &&
- (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x)))
+ (SYMBOL_REF_P (x) || LABEL_REF_P (x)))
{
/* See legitimize_pic_address for an explanation of the
TARGET_VXWORKS_RTP check. */
@@ -23042,7 +23042,7 @@ arm_assemble_integer (rtx x, unsigned int size, int aligned_p)
they may be overridden by a non-weak definition at link
time. */
if (!arm_pic_data_is_text_relative
- || (GET_CODE (x) == SYMBOL_REF
+ || (SYMBOL_REF_P (x)
&& (!SYMBOL_REF_LOCAL_P (x)
|| (SYMBOL_REF_DECL (x)
? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0))))
@@ -29914,7 +29914,7 @@ arm_valid_symbolic_address_p (rtx addr)
if (target_word_relocations)
return false;
- if (GET_CODE (tmp) == SYMBOL_REF || LABEL_REF_P (tmp))
+ if (SYMBOL_REF_P (tmp) || LABEL_REF_P (tmp))
return true;
/* (const (plus: symbol_ref const_int)) */
@@ -29926,7 +29926,7 @@ arm_valid_symbolic_address_p (rtx addr)
xop0 = XEXP (tmp, 0);
xop1 = XEXP (tmp, 1);
- if (GET_CODE (xop0) == SYMBOL_REF && CONST_INT_P (xop1))
+ if (SYMBOL_REF_P (xop0) && CONST_INT_P (xop1))
return IN_RANGE (INTVAL (xop1), -0x8000, 0x7fff);
}
@@ -30643,11 +30643,11 @@ arm_const_not_ok_for_debug_p (rtx p)
return true;
if (GET_CODE (p) == MINUS)
{
- if (GET_CODE (XEXP (p, 1)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (p, 1)))
{
decl_op1 = SYMBOL_REF_DECL (XEXP (p, 1));
if (decl_op1
- && GET_CODE (XEXP (p, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (p, 0))
&& (decl_op0 = SYMBOL_REF_DECL (XEXP (p, 0))))
{
if ((VAR_P (decl_op1)
@@ -30675,7 +30675,7 @@ extern bool
arm_is_constant_pool_ref (rtx x)
{
return (MEM_P (x)
- && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
}
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index b2a2bc8cf39..04d04f33da4 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1682,7 +1682,7 @@ enum arm_auto_incmodes
/* XXX We can address any constant, eventually... */
/* ??? Should the TARGET_ARM here also apply to thumb2? */
#define CONSTANT_ADDRESS_P(X) \
- (GET_CODE (X) == SYMBOL_REF \
+ (SYMBOL_REF_P (X) \
&& (CONSTANT_POOL_ADDRESS_P (X) \
|| (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X))))
@@ -1954,7 +1954,7 @@ extern unsigned arm_pic_register;
#define LEGITIMATE_PIC_OPERAND_P(X) \
(!(symbol_mentioned_p (X) \
|| label_mentioned_p (X) \
- || (GET_CODE (X) == SYMBOL_REF \
+ || (SYMBOL_REF_P (X) \
&& CONSTANT_POOL_ADDRESS_P (X) \
&& (symbol_mentioned_p (get_pool_constant (X)) \
|| label_mentioned_p (get_pool_constant (X))))) \
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index 5eadcc58df6..4484ae0e51f 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -6133,7 +6133,7 @@
&& TARGET_HAVE_MOVT
&& arm_disable_literal_pool
&& reload_completed
- && GET_CODE (operands[1]) == SYMBOL_REF"
+ && SYMBOL_REF_P (operands[1])"
[(clobber (const_int 0))]
"
int offset = INTVAL (operands[2]);
@@ -6161,7 +6161,7 @@
(define_split
[(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "general_operand" ""))]
- "TARGET_USE_MOVT && GET_CODE (operands[1]) == SYMBOL_REF
+ "TARGET_USE_MOVT && SYMBOL_REF_P (operands[1])
&& !target_word_relocations
&& !arm_tls_referenced_p (operands[1])"
[(clobber (const_int 0))]
@@ -8155,7 +8155,7 @@
32-bit address of the callee into a register before performing the
branch and link. */
callee = XEXP (operands[0], 0);
- if (GET_CODE (callee) == SYMBOL_REF
+ if (SYMBOL_REF_P (callee)
? arm_is_long_call_p (SYMBOL_REF_DECL (callee))
: !REG_P (callee))
XEXP (operands[0], 0) = force_reg (Pmode, callee);
@@ -8243,7 +8243,7 @@
32-bit address of the callee into a register before performing the
branch and link. */
callee = XEXP (operands[1], 0);
- if (GET_CODE (callee) == SYMBOL_REF
+ if (SYMBOL_REF_P (callee)
? arm_is_long_call_p (SYMBOL_REF_DECL (callee))
: !REG_P (callee))
XEXP (operands[1], 0) = force_reg (Pmode, callee);
@@ -8324,7 +8324,7 @@
(clobber (reg:SI LR_REGNUM))]
"TARGET_32BIT
&& !SIBLING_CALL_P (insn)
- && (GET_CODE (operands[0]) == SYMBOL_REF)
+ && (SYMBOL_REF_P (operands[0]))
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
"*
{
@@ -8348,7 +8348,7 @@
(clobber (reg:SI LR_REGNUM))]
"TARGET_32BIT
&& !SIBLING_CALL_P (insn)
- && (GET_CODE (operands[1]) == SYMBOL_REF)
+ && (SYMBOL_REF_P (operands[1]))
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
"*
{
@@ -8382,8 +8382,8 @@
rtx pat;
if ((!REG_P (XEXP (operands[0], 0))
- && GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)
- || (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+ && !SYMBOL_REF_P (XEXP (operands[0], 0)))
+ || (SYMBOL_REF_P (XEXP (operands[0], 0))
&& arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[0], 0)))))
XEXP (operands[0], 0) = force_reg (SImode, XEXP (operands[0], 0));
@@ -8415,8 +8415,8 @@
rtx pat;
if ((!REG_P (XEXP (operands[1], 0))
- && GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF)
- || (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+ && !SYMBOL_REF_P (XEXP (operands[1], 0)))
+ || (SYMBOL_REF_P (XEXP (operands[1], 0))
&& arm_is_long_call_p (SYMBOL_REF_DECL (XEXP (operands[1], 0)))))
XEXP (operands[1], 0) = force_reg (SImode, XEXP (operands[1], 0));
diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md
index 13ac28d0d85..61c30f2567b 100644
--- a/gcc/config/arm/thumb1.md
+++ b/gcc/config/arm/thumb1.md
@@ -1816,7 +1816,7 @@
(use (match_operand 2 "" ""))
(clobber (reg:SI LR_REGNUM))]
"TARGET_THUMB1
- && GET_CODE (operands[0]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[0])
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[0]))"
"bl\\t%a0"
[(set_attr "length" "4")
@@ -1830,7 +1830,7 @@
(use (match_operand 3 "" ""))
(clobber (reg:SI LR_REGNUM))]
"TARGET_THUMB1
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& !arm_is_long_call_p (SYMBOL_REF_DECL (operands[1]))"
"bl\\t%a1"
[(set_attr "length" "4")
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index cf0986b2f13..14f63496e93 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -138,14 +138,14 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
rtx addr = orig;
rtx new_rtx = orig;
- if (GET_CODE (addr) == SYMBOL_REF || LABEL_REF_P (addr))
+ if (SYMBOL_REF_P (addr) || LABEL_REF_P (addr))
{
int unspec;
rtx tmp;
if (TARGET_ID_SHARED_LIBRARY)
unspec = UNSPEC_MOVE_PIC;
- else if (GET_CODE (addr) == SYMBOL_REF
+ else if (SYMBOL_REF_P (addr)
&& SYMBOL_REF_FUNCTION_P (addr))
unspec = UNSPEC_FUNCDESC_GOT17M4;
else
@@ -1097,7 +1097,7 @@ bfin_expand_prologue (void)
emit_move_insn (p2reg, gen_rtx_MEM (Pmode, p2reg));
lim = p2reg;
}
- if (GET_CODE (lim) == SYMBOL_REF)
+ if (SYMBOL_REF_P (lim))
{
if (TARGET_ID_SHARED_LIBRARY)
{
@@ -1791,7 +1791,7 @@ symbolic_reference_mentioned_p (rtx op)
register const char *fmt;
register int i;
- if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
+ if (SYMBOL_REF_P (op) || LABEL_REF_P (op))
return 1;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -1936,7 +1936,7 @@ expand_move (rtx *operands, machine_mode mode)
emit_pic_move (operands, mode);
else if (mode == SImode && GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& !targetm.legitimate_constant_p (mode, op))
{
rtx dest = operands[0];
@@ -1998,7 +1998,7 @@ split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[])
bool
bfin_longcall_p (rtx op, int call_cookie)
{
- gcc_assert (GET_CODE (op) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (op));
if (SYMBOL_REF_WEAK (op))
return 1;
if (call_cookie & CALL_SHORT)
@@ -2031,7 +2031,7 @@ bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
/* Static functions and indirect calls don't need the pic register. */
if (!TARGET_FDPIC && flag_pic
- && GET_CODE (callee) == SYMBOL_REF
+ && SYMBOL_REF_P (callee)
&& !SYMBOL_REF_LOCAL_P (callee))
use_reg (&use, pic_offset_table_rtx);
@@ -2049,7 +2049,7 @@ bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
DECL_ATTRIBUTES (cfun->decl)) != NULL_TREE)
caller_in_sram = 2;
- if (GET_CODE (callee) == SYMBOL_REF
+ if (SYMBOL_REF_P (callee)
&& SYMBOL_REF_DECL (callee) && DECL_P (SYMBOL_REF_DECL (callee)))
{
if (lookup_attribute
@@ -2062,14 +2062,14 @@ bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
callee_in_sram = 2;
}
- if (GET_CODE (callee) != SYMBOL_REF
+ if (!SYMBOL_REF_P (callee)
|| bfin_longcall_p (callee, INTVAL (cookie))
- || (GET_CODE (callee) == SYMBOL_REF
+ || (SYMBOL_REF_P (callee)
&& !SYMBOL_REF_LOCAL_P (callee)
&& TARGET_INLINE_PLT)
|| caller_in_sram != callee_in_sram
|| (caller_in_sram && callee_in_sram
- && (GET_CODE (callee) != SYMBOL_REF
+ && (!SYMBOL_REF_P (callee)
|| !SYMBOL_REF_LOCAL_P (callee))))
{
rtx addr = callee;
@@ -2088,8 +2088,8 @@ bfin_expand_call (rtx retval, rtx fnaddr, rtx callarg1, rtx cookie, int sibcall)
nelts++;
}
else if ((!register_no_elim_operand (callee, Pmode)
- && GET_CODE (callee) != SYMBOL_REF)
- || (GET_CODE (callee) == SYMBOL_REF
+ && !SYMBOL_REF_P (callee))
+ || (SYMBOL_REF_P (callee)
&& ((TARGET_ID_SHARED_LIBRARY && !TARGET_LEAF_ID_SHARED_LIBRARY)
|| bfin_longcall_p (callee, INTVAL (cookie)))))
{
@@ -2801,7 +2801,7 @@ bfin_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
sym = XEXP (x, 0);
x = XEXP (x, 1);
- if (GET_CODE (sym) != SYMBOL_REF
+ if (!SYMBOL_REF_P (sym)
|| !CONST_INT_P (x))
return true;
offset = INTVAL (x);
@@ -4946,7 +4946,7 @@ bfin_assemble_integer (rtx value, unsigned int size, int aligned_p)
{
if (TARGET_FDPIC && size == UNITS_PER_WORD)
{
- if (GET_CODE (value) == SYMBOL_REF
+ if (SYMBOL_REF_P (value)
&& SYMBOL_REF_FUNCTION_P (value))
{
fputs ("\t.picptr\tfuncdesc(", asm_out_file);
diff --git a/gcc/config/bfin/bfin.h b/gcc/config/bfin/bfin.h
index 2ee2abbd226..d4babb2f89d 100644
--- a/gcc/config/bfin/bfin.h
+++ b/gcc/config/bfin/bfin.h
@@ -782,7 +782,7 @@ typedef struct {
#define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X)
#define SYMBOLIC_CONST(X) \
-(GET_CODE (X) == SYMBOL_REF \
+(SYMBOL_REF_P (X) \
|| LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md
index 627b5a4b47c..d93ddc45363 100644
--- a/gcc/config/bfin/bfin.md
+++ b/gcc/config/bfin/bfin.md
@@ -2077,7 +2077,7 @@
(use (match_operand 3 "" ""))
(clobber (reg:SI REG_RETS))]
"! SIBLING_CALL_P (insn)
- && GET_CODE (operands[0]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[0])
&& !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
"call %0;"
[(set_attr "type" "call")
@@ -2090,7 +2090,7 @@
(use (match_operand 3 "" ""))
(return)]
"SIBLING_CALL_P (insn)
- && GET_CODE (operands[0]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[0])
&& !bfin_longcall_p (operands[0], INTVAL (operands[3]))"
"jump.l %0;"
[(set_attr "type" "br")
@@ -2104,7 +2104,7 @@
(use (match_operand 4 "" ""))
(clobber (reg:SI REG_RETS))]
"! SIBLING_CALL_P (insn)
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
"call %1;"
[(set_attr "type" "call")
@@ -2118,7 +2118,7 @@
(use (match_operand 4 "" ""))
(return)]
"SIBLING_CALL_P (insn)
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& !bfin_longcall_p (operands[1], INTVAL (operands[4]))"
"jump.l %1;"
[(set_attr "type" "br")
@@ -2177,7 +2177,7 @@
(clobber (reg:SI REG_RETS))]
"! SIBLING_CALL_P (insn)
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
- && GET_CODE (operands[0]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[0])
&& !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
"call %0;"
[(set_attr "type" "call")
@@ -2190,7 +2190,7 @@
(return)]
"SIBLING_CALL_P (insn)
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
- && GET_CODE (operands[0]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[0])
&& !bfin_longcall_p (operands[0], INTVAL (operands[2]))"
"jump.l %0;"
[(set_attr "type" "br")
@@ -2204,7 +2204,7 @@
(clobber (reg:SI REG_RETS))]
"! SIBLING_CALL_P (insn)
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
"call %1;"
[(set_attr "type" "call")
@@ -2218,7 +2218,7 @@
(return)]
"SIBLING_CALL_P (insn)
&& (!TARGET_ID_SHARED_LIBRARY || TARGET_LEAF_ID_SHARED_LIBRARY)
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& !bfin_longcall_p (operands[1], INTVAL (operands[3]))"
"jump.l %1;"
[(set_attr "type" "br")
diff --git a/gcc/config/bfin/predicates.md b/gcc/config/bfin/predicates.md
index 261323a41b2..c13f7cd544a 100644
--- a/gcc/config/bfin/predicates.md
+++ b/gcc/config/bfin/predicates.md
@@ -162,7 +162,7 @@
(ior (match_code "symbol_ref,label_ref")
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
- && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (op, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
diff --git a/gcc/config/c6x/c6x.c b/gcc/config/c6x/c6x.c
index 7e52de17a4b..2ebbfd8ac54 100644
--- a/gcc/config/c6x/c6x.c
+++ b/gcc/config/c6x/c6x.c
@@ -1290,7 +1290,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
rtx addr = orig;
rtx new_rtx = orig;
- if (GET_CODE (addr) == SYMBOL_REF || LABEL_REF_P (addr))
+ if (SYMBOL_REF_P (addr) || LABEL_REF_P (addr))
{
int unspec = UNSPEC_LOAD_GOT;
rtx tmp;
@@ -2237,7 +2237,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
x = XEXP (x, 0);
}
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
t = SYMBOL_REF_DECL (x);
if (DECL_P (t))
@@ -2259,7 +2259,7 @@ c6x_print_operand (FILE *file, rtx x, int code)
if (GET_CODE (x) == PLUS
|| GET_RTX_CLASS (GET_CODE (x)) == RTX_AUTOINC)
x = XEXP (x, 0);
- if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF)
+ if (GET_CODE (x) == CONST || SYMBOL_REF_P (x))
{
gcc_assert (sdata_symbolic_operand (x, Pmode));
fputs ("2", file);
@@ -2429,7 +2429,7 @@ c6x_legitimate_address_p_1 (machine_mode mode, rtx x, bool strict,
&& GET_CODE (XEXP (x, 1)) == UNSPEC
&& XINT (XEXP (x, 1), 1) == UNSPEC_LOAD_GOT
&& XEXP (x, 0) == pic_offset_table_rtx
- && (GET_CODE (XVECEXP (XEXP (x, 1), 0, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XVECEXP (XEXP (x, 1), 0, 0))
|| LABEL_REF_P (XVECEXP (XEXP (x, 1), 0, 0))))
return !no_large_offset;
if (!CONST_INT_P (XEXP (x, 1)))
diff --git a/gcc/config/c6x/predicates.md b/gcc/config/c6x/predicates.md
index 1670df870cc..c0b2c60d91d 100644
--- a/gcc/config/c6x/predicates.md
+++ b/gcc/config/c6x/predicates.md
@@ -73,7 +73,7 @@
{
/* The linker transforms jumps to undefined weak symbols in a way that
is incompatible with our code generation. */
- return (GET_CODE (op) != SYMBOL_REF
+ return (!SYMBOL_REF_P (op)
|| (!SYMBOL_REF_WEAK (op)
&& !c6x_long_call_p (op)));
})
@@ -84,7 +84,7 @@
(ior (match_code "symbol_ref,label_ref")
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
- && (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (op, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))
@@ -187,7 +187,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
offset = INTVAL (XEXP (op, 1));
diff --git a/gcc/config/cr16/cr16.c b/gcc/config/cr16/cr16.c
index 1fc95285ba5..8da6bbd1c52 100644
--- a/gcc/config/cr16/cr16.c
+++ b/gcc/config/cr16/cr16.c
@@ -1162,7 +1162,7 @@ legitimate_pic_operand_p (rtx x)
case CONST:
/* REVISIT: Use something like symbol_referenced_p. */
if (GET_CODE (XEXP (x, 0)) == PLUS
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return 0;
@@ -1191,7 +1191,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
rtx reg)
{
/* First handle a simple SYMBOL_REF or LABEL_REF. */
- if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
+ if (SYMBOL_REF_P (orig) || LABEL_REF_P (orig))
{
if (reg == 0)
reg = gen_reg_rtx (Pmode);
diff --git a/gcc/config/cr16/cr16.h b/gcc/config/cr16/cr16.h
index 9814b725aec..8df4b4cd95b 100644
--- a/gcc/config/cr16/cr16.h
+++ b/gcc/config/cr16/cr16.h
@@ -415,7 +415,7 @@ struct cumulative_args
#define CONSTANT_ADDRESS_P(X) \
(LABEL_REF_P (X) \
- || GET_CODE (X) == SYMBOL_REF \
+ || SYMBOL_REF_P (X) \
|| GET_CODE (X) == CONST \
|| CONST_INT_P (X))
diff --git a/gcc/config/cris/cris.c b/gcc/config/cris/cris.c
index 6a573dda1ab..aa8db75e2c5 100644
--- a/gcc/config/cris/cris.c
+++ b/gcc/config/cris/cris.c
@@ -3910,7 +3910,7 @@ cris_output_addr_const (FILE *file, rtx x)
void
cris_asm_output_symbol_ref (FILE *file, rtx x)
{
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
if (flag_pic && in_code > 0)
{
@@ -3956,7 +3956,7 @@ cris_output_addr_const_extra (FILE *file, rtx xconst)
case UNSPEC:
x = XVECEXP (xconst, 0, 0);
- CRIS_ASSERT (GET_CODE (x) == SYMBOL_REF
+ CRIS_ASSERT (SYMBOL_REF_P (x)
|| LABEL_REF_P (x)
|| GET_CODE (x) == CONST);
output_addr_const (file, x);
diff --git a/gcc/config/cris/cris.md b/gcc/config/cris/cris.md
index 94ebb9d8539..a0243bc0c27 100644
--- a/gcc/config/cris/cris.md
+++ b/gcc/config/cris/cris.md
@@ -1087,7 +1087,7 @@
if (TARGET_V32)
{
if (!flag_pic
- && (GET_CODE (operands[1]) == SYMBOL_REF
+ && (SYMBOL_REF_P (operands[1])
|| LABEL_REF_P (operands[1])
|| (GET_CODE (operands[1]) == CONST
&& (GET_CODE (XEXP (operands[1], 0)) != UNSPEC
diff --git a/gcc/config/csky/csky.c b/gcc/config/csky/csky.c
index a41b8ed431e..d562d9fdf09 100644
--- a/gcc/config/csky/csky.c
+++ b/gcc/config/csky/csky.c
@@ -1578,7 +1578,7 @@ csky_emit_constant_pools (void)
rtx insn_body = PATTERN (this_fix->insn);
rtx src = XEXP (insn_body, 1);
*this_fix->loc = gen_rtx_MEM (this_fix->mode, addr);
- if (GET_CODE (this_fix->value) == SYMBOL_REF)
+ if (SYMBOL_REF_P (this_fix->value))
emit_insn_after (gen_rtx_UNSPEC_VOLATILE (VOIDmode,
gen_rtvec (1, src),
VUNSPEC_SYMBOL_REF),
@@ -2649,7 +2649,7 @@ csky_tls_referenced_p (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
return true;
/* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
@@ -2716,7 +2716,7 @@ csky_tls_symbol_p (rtx x)
if (!TARGET_TLS)
return false;
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return false;
return SYMBOL_REF_TLS_MODEL (x) != 0;
@@ -4035,7 +4035,7 @@ csky_output_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "lrw\t%0, %x1\t";
}
- else if (TARGET_ANCHOR && GET_CODE (src) == SYMBOL_REF)
+ else if (TARGET_ANCHOR && SYMBOL_REF_P (src))
{
if (SYMBOL_REF_FUNCTION_P (src))
return "lrw\t%0, %1@BTEXT";
@@ -4156,7 +4156,7 @@ csky_output_ck801_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[],
else
return "lrw\t%0, %x1\t";
}
- else if (TARGET_ANCHOR && GET_CODE (src) == SYMBOL_REF)
+ else if (TARGET_ANCHOR && SYMBOL_REF_P (src))
{
if (SYMBOL_REF_FUNCTION_P (src))
return "lrw\t%0, %1@BTEXT";
@@ -4731,7 +4731,7 @@ csky_symbolic_address_p (rtx x)
return 1;
case CONST:
x = XEXP (x, 0);
- return ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ return ((SYMBOL_REF_P (XEXP (x, 0))
|| LABEL_REF_P (XEXP (x, 0)))
&& CONST_INT_P (XEXP (x, 1)));
default:
@@ -5592,7 +5592,7 @@ csky_symbol_mentioned_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (x));
@@ -5679,7 +5679,7 @@ csky_legitimize_pic_address (rtx orig, rtx reg, bool gotrel_p)
rtx pic_reg = gen_rtx_REG (SImode, PIC_OFFSET_TABLE_REGNUM);
bool optimize_p = false;
- if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
+ if (SYMBOL_REF_P (orig) || LABEL_REF_P (orig))
{
rtx pic_ref, address, rtx_tmp;
rtx insn;
@@ -5698,7 +5698,7 @@ csky_legitimize_pic_address (rtx orig, rtx reg, bool gotrel_p)
else
address = reg;
- if (GET_CODE (orig) == SYMBOL_REF && !SYMBOL_REF_LOCAL_P (orig))
+ if (SYMBOL_REF_P (orig) && !SYMBOL_REF_LOCAL_P (orig))
{
/* When gotrel_p generate sym@GOT, otherwise generate sym@PLT. */
rtx_tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, orig),
@@ -5725,7 +5725,7 @@ csky_legitimize_pic_address (rtx orig, rtx reg, bool gotrel_p)
return pic_ref;
}
/* grs rx, symbol */
- else if (flag_pic == 1 && (GET_CODE (orig) == SYMBOL_REF)
+ else if (flag_pic == 1 && (SYMBOL_REF_P (orig))
&& SYMBOL_REF_FUNCTION_P (orig))
{
pic_ref = gen_rtx_UNSPEC (Pmode,
diff --git a/gcc/config/csky/csky.h b/gcc/config/csky/csky.h
index 1c86fd10b18..56feefbd7f2 100644
--- a/gcc/config/csky/csky.h
+++ b/gcc/config/csky/csky.h
@@ -686,7 +686,7 @@ extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER];
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
- (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF)
+ (LABEL_REF_P (X) || SYMBOL_REF_P (X))
/* Maximum number of registers that can appear in a valid memory address.
Shifts in addresses can't be by a register. */
diff --git a/gcc/config/csky/csky.md b/gcc/config/csky/csky.md
index 6e680c14ac2..a2fdc9c8122 100644
--- a/gcc/config/csky/csky.md
+++ b/gcc/config/csky/csky.md
@@ -173,7 +173,7 @@
tmp = XEXP (XEXP (tmp, 0), 0);
}
- gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (tmp));
gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0);
tmp = csky_legitimize_tls_address (tmp, scratch);
diff --git a/gcc/config/csky/predicates.md b/gcc/config/csky/predicates.md
index c2dadba3d27..81d0e5bdb3b 100644
--- a/gcc/config/csky/predicates.md
+++ b/gcc/config/csky/predicates.md
@@ -161,7 +161,7 @@
(define_predicate "csky_call_address_operand"
(match_code "reg,subreg,symbol_ref")
{
- if (!flag_pic && (GET_CODE (op) == SYMBOL_REF))
+ if (!flag_pic && (SYMBOL_REF_P (op)))
return 1;
if (register_operand (op, mode))
return 1;
diff --git a/gcc/config/darwin.c b/gcc/config/darwin.c
index 4ca16520080..fc055919acc 100644
--- a/gcc/config/darwin.c
+++ b/gcc/config/darwin.c
@@ -644,7 +644,7 @@ machopic_indirect_data_reference (rtx orig, rtx reg)
if (! MACHOPIC_INDIRECT)
return orig;
- if (GET_CODE (orig) == SYMBOL_REF)
+ if (SYMBOL_REF_P (orig))
{
int defined = machopic_data_defined_p (orig);
@@ -795,7 +795,7 @@ machopic_indirect_call_target (rtx target)
return target;
if (MACHOPIC_INDIRECT
- && GET_CODE (XEXP (target, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (target, 0))
&& !(SYMBOL_REF_FLAGS (XEXP (target, 0))
& MACHO_SYMBOL_FLAG_DEFINED))
{
@@ -823,7 +823,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
/* First handle a simple SYMBOL_REF or LABEL_REF */
if (LABEL_REF_P (orig)
- || GET_CODE (orig) == SYMBOL_REF)
+ || SYMBOL_REF_P (orig))
{
/* addr(foo) = &func+(foo-func) */
orig = machopic_indirect_data_reference (orig, reg);
@@ -848,7 +848,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
#if HAVE_lo_sum
if (MACHO_DYNAMIC_NO_PIC_P
- && (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (orig, 0))
|| LABEL_REF_P (XEXP (orig, 0))))
{
#if defined (TARGET_TOC) /* ppc */
@@ -871,7 +871,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
pic_ref = reg;
}
else
- if (GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (orig, 0))
|| LABEL_REF_P (XEXP (orig, 0)))
{
rtx offset = machopic_gen_offset (XEXP (orig, 0));
@@ -941,7 +941,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
{
#if HAVE_lo_sum
- if (GET_CODE (orig) == SYMBOL_REF
+ if (SYMBOL_REF_P (orig)
|| LABEL_REF_P (orig))
{
rtx offset = machopic_gen_offset (orig);
@@ -1024,7 +1024,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
}
else if (GET_CODE (orig) == PLUS
&& (MEM_P (XEXP (orig, 0))
- || GET_CODE (XEXP (orig, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (orig, 0))
|| LABEL_REF_P (XEXP (orig, 0)))
&& XEXP (orig, 0) != pic_offset_table_rtx
&& !REG_P (XEXP (orig, 1)))
@@ -1056,7 +1056,7 @@ machopic_legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
return machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
}
else if (MEM_P (orig)
- && GET_CODE (XEXP (orig, 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (orig, 0)))
{
rtx addr = machopic_legitimize_pic_address (XEXP (orig, 0), Pmode, reg);
addr = replace_equiv_address (orig, addr);
@@ -1196,7 +1196,7 @@ int
machopic_operand_p (rtx op)
{
if (MACHOPIC_JUST_INDIRECT)
- return (GET_CODE (op) == SYMBOL_REF
+ return (SYMBOL_REF_P (op)
&& machopic_symbol_defined_p (op));
else
return (GET_CODE (op) == CONST
@@ -1768,7 +1768,7 @@ machopic_select_rtx_section (machine_mode mode, rtx x,
|| CONST_VECTOR_P (x)))
return darwin_sections[literal16_section];
else if (MACHOPIC_INDIRECT
- && (GET_CODE (x) == SYMBOL_REF
+ && (SYMBOL_REF_P (x)
|| GET_CODE (x) == CONST
|| LABEL_REF_P (x)))
return darwin_sections[const_data_section];
@@ -2164,7 +2164,7 @@ darwin_non_lazy_pcrel (FILE *file, rtx addr)
{
const char *nlp_name;
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
nlp_name = machopic_indirection_name (addr, /*stub_p=*/false);
fputs ("\t.long\t", file);
@@ -2208,7 +2208,7 @@ darwin_asm_declare_object_name (FILE *file,
&& (!DECL_COMMON (decl)
|| !TREE_PUBLIC (decl)));
- if (GET_CODE (XEXP (DECL_RTL (decl), 0)) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (XEXP (DECL_RTL (decl), 0)))
xname = IDENTIFIER_POINTER (DECL_NAME (decl));
if (local_def)
diff --git a/gcc/config/darwin.h b/gcc/config/darwin.h
index ab5ad03f175..85c5ffc03db 100644
--- a/gcc/config/darwin.h
+++ b/gcc/config/darwin.h
@@ -652,7 +652,7 @@ extern GTY(()) int darwin_ms_struct;
#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
do { \
const char *xname = NAME; \
- if (GET_CODE (XEXP (DECL_RTL (DECL), 0)) != SYMBOL_REF) \
+ if (!SYMBOL_REF_P (XEXP (DECL_RTL (DECL), 0))) \
xname = IDENTIFIER_POINTER (DECL_NAME (DECL)); \
if (! DECL_WEAK (DECL) \
&& ((TREE_STATIC (DECL) \
diff --git a/gcc/config/epiphany/epiphany.c b/gcc/config/epiphany/epiphany.c
index ea1c137a881..442cd4d02c1 100644
--- a/gcc/config/epiphany/epiphany.c
+++ b/gcc/config/epiphany/epiphany.c
@@ -2135,7 +2135,7 @@ epiphany_small16 (rtx x)
base = XEXP (XEXP (x, 0), 0);
offs = XEXP (XEXP (x, 0), 1);
}
- if (GET_CODE (base) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (base)
+ if (SYMBOL_REF_P (base) && SYMBOL_REF_FUNCTION_P (base)
&& epiphany_is_long_call_p (base))
return false;
return TARGET_SMALL16 != 0;
@@ -2197,7 +2197,7 @@ epiphany_call_uninterruptible_p (rtx mem)
rtx addr = XEXP (mem, 0);
tree t = NULL_TREE;
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
t = SYMBOL_REF_DECL (addr);
if (!t)
t = MEM_EXPR (mem);
diff --git a/gcc/config/epiphany/epiphany.h b/gcc/config/epiphany/epiphany.h
index 8d5a9c55616..8ac1100358a 100644
--- a/gcc/config/epiphany/epiphany.h
+++ b/gcc/config/epiphany/epiphany.h
@@ -602,7 +602,7 @@ typedef struct GTY (()) machine_function
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
-(LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+(LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == CONST)
#define RTX_OK_FOR_OFFSET_P(MODE, X) \
diff --git a/gcc/config/epiphany/predicates.md b/gcc/config/epiphany/predicates.md
index b59c23b9c10..33dd8847cfe 100644
--- a/gcc/config/epiphany/predicates.md
+++ b/gcc/config/epiphany/predicates.md
@@ -24,7 +24,7 @@
(define_predicate "symbolic_operand"
(match_code "symbol_ref,label_ref,const")
{
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return (!epiphany_is_long_call_p (op)
&& (!flag_pic || SYMBOL_REF_LOCAL_P (op)));
if (LABEL_REF_P (op))
diff --git a/gcc/config/fr30/predicates.md b/gcc/config/fr30/predicates.md
index 1fa5f167f27..597330ce2e1 100644
--- a/gcc/config/fr30/predicates.md
+++ b/gcc/config/fr30/predicates.md
@@ -57,7 +57,7 @@
(match_code "mem")
{
return (MEM_P (op)
- && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (op, 0))
|| REG_P (XEXP (op, 0))));
})
diff --git a/gcc/config/frv/frv.c b/gcc/config/frv/frv.c
index 13e8dafbc7d..5392082034f 100644
--- a/gcc/config/frv/frv.c
+++ b/gcc/config/frv/frv.c
@@ -534,7 +534,7 @@ static bool frv_modes_tieable_p (machine_mode, machine_mode);
struct gcc_target targetm = TARGET_INITIALIZER;
#define FRV_SYMBOL_REF_TLS_P(RTX) \
- (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0)
+ (SYMBOL_REF_P (RTX) && SYMBOL_REF_TLS_MODEL (RTX) != 0)
\f
/* Any function call that satisfies the machine-independent
@@ -553,7 +553,7 @@ frv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED,
static FRV_INLINE bool
frv_small_data_reloc_p (rtx symbol, int reloc)
{
- return (GET_CODE (symbol) == SYMBOL_REF
+ return (SYMBOL_REF_P (symbol)
&& SYMBOL_REF_SMALL_P (symbol)
&& (!TARGET_FDPIC || flag_pic == 1)
&& (reloc == R_FRV_GOTOFF12 || reloc == R_FRV_GPREL12));
@@ -3063,7 +3063,7 @@ frv_init_cumulative_args (CUMULATIVE_ARGS *cum,
get_tree_code_name (TREE_CODE (ret_type)));
}
- if (libname && GET_CODE (libname) == SYMBOL_REF)
+ if (libname && SYMBOL_REF_P (libname))
fprintf (stderr, " libname=%s", XSTR (libname, 0));
if (cfun->returns_struct)
@@ -3603,7 +3603,7 @@ frv_legitimize_address (rtx x,
rtx oldx ATTRIBUTE_UNUSED,
machine_mode mode ATTRIBUTE_UNUSED)
{
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
enum tls_model model = SYMBOL_REF_TLS_MODEL (x);
if (model != 0)
@@ -3775,7 +3775,7 @@ frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
all external functions, so one would have to also mark function
declarations available in the same module with non-default
visibility, which is advantageous in itself. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& ((!SYMBOL_REF_LOCAL_P (addr) && TARGET_INLINE_PLT)
|| sibcall))
{
@@ -3791,7 +3791,7 @@ frv_expand_fdpic_call (rtx *operands, bool ret_value, bool sibcall)
crtl->uses_pic_offset_table = TRUE;
addr = dest;
}
- else if (GET_CODE (addr) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (addr))
{
/* These are always either local, or handled through a local
PLT. */
@@ -3832,7 +3832,7 @@ frv_function_symbol_referenced_p (rtx x)
int length;
int j;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return SYMBOL_REF_FUNCTION_P (x);
length = GET_RTX_LENGTH (GET_CODE (x));
@@ -3917,7 +3917,7 @@ direct_return_p (void)
void
frv_emit_move (machine_mode mode, rtx dest, rtx src)
{
- if (GET_CODE (src) == SYMBOL_REF)
+ if (SYMBOL_REF_P (src))
{
enum tls_model model = SYMBOL_REF_TLS_MODEL (src);
if (model != 0)
@@ -4041,10 +4041,10 @@ frv_emit_movsi (rtx dest, rtx src)
{
sym = XEXP (sym, 0);
if (GET_CODE (sym) == PLUS
- && GET_CODE (XEXP (sym, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (sym, 0))
&& CONST_INT_P (XEXP (sym, 1)))
sym = XEXP (sym, 0);
- if (GET_CODE (sym) == SYMBOL_REF)
+ if (SYMBOL_REF_P (sym))
goto handle_sym;
else if (LABEL_REF_P (sym))
goto handle_label;
@@ -4140,7 +4140,7 @@ frv_emit_movsi (rtx dest, rtx src)
if (base_regno >= 0)
{
- if (GET_CODE (sym) == SYMBOL_REF && SYMBOL_REF_SMALL_P (sym))
+ if (SYMBOL_REF_P (sym) && SYMBOL_REF_SMALL_P (sym))
emit_insn (gen_symGOTOFF2reg (dest, src,
gen_rtx_REG (Pmode, base_regno),
GEN_INT (R_FRV_GPREL12)));
@@ -4279,7 +4279,7 @@ output_move_single (rtx operands[], rtx insn)
return "#";
}
- else if (GET_CODE (src) == SYMBOL_REF
+ else if (SYMBOL_REF_P (src)
|| LABEL_REF_P (src)
|| GET_CODE (src) == CONST)
{
@@ -6824,10 +6824,10 @@ frv_assemble_integer (rtx value, unsigned int size, int aligned_p)
if ((flag_pic || TARGET_FDPIC) && size == UNITS_PER_WORD)
{
if (GET_CODE (value) == CONST
- || GET_CODE (value) == SYMBOL_REF
+ || SYMBOL_REF_P (value)
|| LABEL_REF_P (value))
{
- if (TARGET_FDPIC && GET_CODE (value) == SYMBOL_REF
+ if (TARGET_FDPIC && SYMBOL_REF_P (value)
&& SYMBOL_REF_FUNCTION_P (value))
{
fputs ("\t.picptr\tfuncdesc(", asm_out_file);
diff --git a/gcc/config/frv/predicates.md b/gcc/config/frv/predicates.md
index 9fd855646c8..63e570a9056 100644
--- a/gcc/config/frv/predicates.md
+++ b/gcc/config/frv/predicates.md
@@ -524,7 +524,7 @@
op = XEXP (op, 0);
if (GET_CODE (op) == PLUS && CONST_INT_P (XEXP (op, 1)))
op = XEXP (op, 0);
- return GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op);
+ return SYMBOL_REF_P (op) || LABEL_REF_P (op);
case SYMBOL_REF:
if (TARGET_FDPIC)
@@ -1069,7 +1069,7 @@
if (GET_MODE (op) != mode && mode != VOIDmode && !CONST_INT_P (op))
return FALSE;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return !TARGET_LONG_CALLS || SYMBOL_REF_LOCAL_P (op);
/* Note this doesn't allow reg+reg or reg+imm12 addressing (which should
@@ -1130,7 +1130,7 @@
/* Allow (const:SI (plus:SI (symbol_ref) (const_int))). */
return GET_MODE (op) == SImode
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1));
}
diff --git a/gcc/config/ft32/constraints.md b/gcc/config/ft32/constraints.md
index b6f2bb1ba87..23a25dd122f 100644
--- a/gcc/config/ft32/constraints.md
+++ b/gcc/config/ft32/constraints.md
@@ -26,14 +26,14 @@
"An absolute address."
(and (match_code "mem")
(match_test "(!ft32_is_mem_pm(op))")
- (ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF")
+ (ior (match_test "SYMBOL_REF_P (XEXP (op, 0))")
(match_test "LABEL_REF_P (XEXP (op, 0))")
(match_test "CONST_INT_P (XEXP (op, 0))")
(and (match_test "(GET_CODE (XEXP (op, 0)) == PLUS)")
- (ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF")
+ (ior (match_test "SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))")
(match_test "LABEL_REF_P (XEXP (XEXP (op, 0), 0))")
(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 0))"))
- (ior (match_test "GET_CODE (XEXP (XEXP (op, 0), 1)) == SYMBOL_REF")
+ (ior (match_test "SYMBOL_REF_P (XEXP (XEXP (op, 0), 1))")
(match_test "LABEL_REF_P (XEXP (XEXP (op, 0), 1))")
(match_test "CONST_INT_P (XEXP (XEXP (op, 0), 1))"))))))
@@ -54,7 +54,7 @@
"An offset address."
(and (match_code "mem")
(match_test "ft32_is_mem_pm(op) && (
- (GET_CODE (XEXP (op, 0)) == SYMBOL_REF) ||
+ (SYMBOL_REF_P (XEXP (op, 0))) ||
(LABEL_REF_P (XEXP (op, 0))) ||
(CONST_INT_P (XEXP (op, 0))) ||
(GET_CODE (XEXP (op, 0)) == CONST))"
@@ -99,7 +99,7 @@
(and (match_code "const_int")
(match_test "ival >= -524288 && ival <= 524287"))
(match_test "LABEL_REF_P (op)")
- (match_test "GET_CODE (op) == SYMBOL_REF")
+ (match_test "SYMBOL_REF_P (op)")
(match_test "GET_CODE (op) == CONST")))
(define_constraint "b"
diff --git a/gcc/config/ft32/ft32.c b/gcc/config/ft32/ft32.c
index 87defc3824f..b9fcec1344b 100644
--- a/gcc/config/ft32/ft32.c
+++ b/gcc/config/ft32/ft32.c
@@ -135,7 +135,7 @@ ft32_print_operand_address (FILE * file, rtx x)
case CONST:
{
rtx plus = XEXP (XEXP (x, 1), 0);
- if (GET_CODE (XEXP (plus, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (plus, 0))
&& CONST_INT_P (XEXP (plus, 1)))
{
output_addr_const (file, XEXP (plus, 0));
@@ -884,12 +884,12 @@ ft32_addr_space_legitimate_address_p (machine_mode mode, rtx x, bool strict,
&& (INTVAL (op2) < max_offset)
&& reg_ok_for_base_p (op1, strict))
goto yes;
- if (GET_CODE (op1) == SYMBOL_REF && CONST_INT_P (op2))
+ if (SYMBOL_REF_P (op1) && CONST_INT_P (op2))
goto yes;
}
if (REG_P (x) && reg_ok_for_base_p (x, strict))
goto yes;
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
|| LABEL_REF_P (x) || CONST_INT_P (x))
goto yes;
}
@@ -917,7 +917,7 @@ ft32_elf_encode_section_info (tree decl, rtx rtl, int first)
if (!MEM_P (rtl))
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
default_encode_section_info (decl, rtl, first);
diff --git a/gcc/config/ft32/ft32.md b/gcc/config/ft32/ft32.md
index cf30c11848d..498a2ea62bc 100644
--- a/gcc/config/ft32/ft32.md
+++ b/gcc/config/ft32/ft32.md
@@ -300,7 +300,7 @@
rtx o = XEXP (operands[0], 0);
if (!REG_P(o) &&
!CONST_INT_P(o) &&
- GET_CODE(o) != SYMBOL_REF &&
+ !SYMBOL_REF_P (o) &&
!LABEL_REF_P (o)) {
operands[0] = gen_rtx_MEM (SImode, force_reg (SImode, XEXP (operands[0], 0)));
}
@@ -439,7 +439,7 @@
rtx o = XEXP (operands[0], 0);
if (!REG_P(o) &&
!CONST_INT_P(o) &&
- GET_CODE(o) != SYMBOL_REF &&
+ !SYMBOL_REF_P (o) &&
!LABEL_REF_P (o)) {
operands[0] = gen_rtx_MEM (HImode, force_reg (SImode, XEXP (operands[0], 0)));
}
diff --git a/gcc/config/ft32/predicates.md b/gcc/config/ft32/predicates.md
index 51bdedd60ef..9c93eff7508 100644
--- a/gcc/config/ft32/predicates.md
+++ b/gcc/config/ft32/predicates.md
@@ -53,7 +53,7 @@
&& REG_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1)))
return 1;
- if (MEM_P (op) && GET_CODE (XEXP (op, 0)) == SYMBOL_REF)
+ if (MEM_P (op) && SYMBOL_REF_P (XEXP (op, 0)))
return 1;
return REG_P(op) ||
(MEM_P(op) && REG_P(XEXP (op, 0)));
diff --git a/gcc/config/gcn/gcn.c b/gcc/config/gcn/gcn.c
index 402713135d4..9cb7285c795 100644
--- a/gcc/config/gcn/gcn.c
+++ b/gcc/config/gcn/gcn.c
@@ -2111,14 +2111,14 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src)
if (MEM_P (dest)
&& AS_FLAT_P (MEM_ADDR_SPACE (dest))
&& (gcn_flat_address_p (XEXP (dest, 0), mode)
- || GET_CODE (XEXP (dest, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (dest, 0))
|| LABEL_REF_P (XEXP (dest, 0)))
&& gcn_vgpr_register_operand (src, mode))
return true;
else if (MEM_P (src)
&& AS_FLAT_P (MEM_ADDR_SPACE (src))
&& (gcn_flat_address_p (XEXP (src, 0), mode)
- || GET_CODE (XEXP (src, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (src, 0))
|| LABEL_REF_P (XEXP (src, 0)))
&& gcn_vgpr_register_operand (dest, mode))
return true;
@@ -2126,14 +2126,14 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src)
if (MEM_P (dest)
&& AS_GLOBAL_P (MEM_ADDR_SPACE (dest))
&& (gcn_global_address_p (XEXP (dest, 0))
- || GET_CODE (XEXP (dest, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (dest, 0))
|| LABEL_REF_P (XEXP (dest, 0)))
&& gcn_vgpr_register_operand (src, mode))
return true;
else if (MEM_P (src)
&& AS_GLOBAL_P (MEM_ADDR_SPACE (src))
&& (gcn_global_address_p (XEXP (src, 0))
- || GET_CODE (XEXP (src, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (src, 0))
|| LABEL_REF_P (XEXP (src, 0)))
&& gcn_vgpr_register_operand (dest, mode))
return true;
@@ -2141,14 +2141,14 @@ gcn_valid_move_p (machine_mode mode, rtx dest, rtx src)
if (MEM_P (dest)
&& MEM_ADDR_SPACE (dest) == ADDR_SPACE_SCALAR_FLAT
&& (gcn_scalar_flat_address_p (XEXP (dest, 0))
- || GET_CODE (XEXP (dest, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (dest, 0))
|| LABEL_REF_P (XEXP (dest, 0)))
&& gcn_ssrc_register_operand (src, mode))
return true;
else if (MEM_P (src)
&& MEM_ADDR_SPACE (src) == ADDR_SPACE_SCALAR_FLAT
&& (gcn_scalar_flat_address_p (XEXP (src, 0))
- || GET_CODE (XEXP (src, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (src, 0))
|| LABEL_REF_P (XEXP (src, 0)))
&& gcn_sdst_register_operand (dest, mode))
return true;
diff --git a/gcc/config/gcn/gcn.md b/gcc/config/gcn/gcn.md
index 202805b486a..20a55628824 100644
--- a/gcc/config/gcn/gcn.md
+++ b/gcc/config/gcn/gcn.md
@@ -406,7 +406,7 @@
}
if (<MODE>mode == DImode
- && (GET_CODE (operands[1]) == SYMBOL_REF
+ && (SYMBOL_REF_P (operands[1])
|| LABEL_REF_P (operands[1])))
{
if (lra_in_progress)
@@ -564,7 +564,7 @@
"=SD,SD,SD,RS,Sm,v, v,Sg, v, v,RF,RLRG, v, v,RM")
(match_operand:DIDF 1 "general_operand"
"SSA, C,DB,Sm,RS,v,DB, v,Sv,RF, v, v,RLRG,RM, v"))]
- "GET_CODE(operands[1]) != SYMBOL_REF"
+ "!SYMBOL_REF_P (operands[1])"
"@
s_mov_b64\t%0, %1
s_mov_b64\t%0, %1
@@ -819,7 +819,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=Sg")
(match_operand:DI 1 "general_operand" "Y"))
(clobber (reg:BI SCC_REG))]
- "GET_CODE (operands[1]) == SYMBOL_REF || LABEL_REF_P (operands[1])"
+ "SYMBOL_REF_P (operands[1]) || LABEL_REF_P (operands[1])"
{
if (SYMBOL_REF_P (operands[1])
&& SYMBOL_REF_WEAK (operands[1]))
@@ -840,7 +840,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand" "=Sg")
(match_operand:DI 1 "general_operand" "Y"))
(clobber (reg:BI CC_SAVE_REG))]
- "(GET_CODE (operands[1]) == SYMBOL_REF || LABEL_REF_P (operands[1]))
+ "(SYMBOL_REF_P (operands[1]) || LABEL_REF_P (operands[1]))
&& (lra_in_progress || reload_completed)"
{
/* !!! These sequences clobber CC_SAVE_REG. */
diff --git a/gcc/config/h8300/h8300.c b/gcc/config/h8300/h8300.c
index d9d69e4791e..bfa2d349ea3 100644
--- a/gcc/config/h8300/h8300.c
+++ b/gcc/config/h8300/h8300.c
@@ -5620,12 +5620,12 @@ h8300_eightbit_constant_address_p (rtx x)
unsigned HOST_WIDE_INT addr;
/* We accept symbols declared with eightbit_data. */
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0;
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0)
return 1;
diff --git a/gcc/config/h8300/h8300.h b/gcc/config/h8300/h8300.h
index f0f95125404..5aaa26eabad 100644
--- a/gcc/config/h8300/h8300.h
+++ b/gcc/config/h8300/h8300.h
@@ -477,7 +477,7 @@ struct cum_arg
/* 1 if X is an rtx for a constant that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
- (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+ (LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| (CONST_INT_P (X) \
/* We handle signed and unsigned offsets here. */ \
&& INTVAL (X) > (TARGET_H8300 ? -0x10000 : -0x1000000) \
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index 401420c42f1..b4dbcb0b16b 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -2071,7 +2071,7 @@
""
{
if (!register_operand (XEXP (operands[0], 0), Pmode)
- && GET_CODE (XEXP (operands[0], 0)) != SYMBOL_REF)
+ && !SYMBOL_REF_P (XEXP (operands[0], 0)))
XEXP (operands[0], 0) = force_reg (Pmode, XEXP (operands[0], 0));
})
@@ -2083,7 +2083,7 @@
rtx xoperands[1];
xoperands[0] = gen_rtx_MEM (QImode, operands[0]);
gcc_assert (GET_MODE (operands[0]) == Pmode);
- if (GET_CODE (XEXP (xoperands[0], 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (xoperands[0], 0))
&& (SYMBOL_REF_FLAGS (XEXP (xoperands[0], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
output_asm_insn ("jsr\\t@%0:8", xoperands);
else
@@ -2108,7 +2108,7 @@
""
{
if (!register_operand (XEXP (operands[1], 0), Pmode)
- && GET_CODE (XEXP (operands[1], 0)) != SYMBOL_REF)
+ && !SYMBOL_REF_P (XEXP (operands[1], 0)))
XEXP (operands[1], 0) = force_reg (Pmode, XEXP (operands[1], 0));
})
@@ -2122,7 +2122,7 @@
gcc_assert (GET_MODE (operands[1]) == Pmode);
xoperands[0] = operands[0];
xoperands[1] = gen_rtx_MEM (QImode, operands[1]);
- if (GET_CODE (XEXP (xoperands[1], 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (xoperands[1], 0))
&& (SYMBOL_REF_FLAGS (XEXP (xoperands[1], 0)) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
output_asm_insn ("jsr\\t@%1:8", xoperands);
else
diff --git a/gcc/config/h8300/predicates.md b/gcc/config/h8300/predicates.md
index b71bdde6de8..dc78188bce9 100644
--- a/gcc/config/h8300/predicates.md
+++ b/gcc/config/h8300/predicates.md
@@ -251,7 +251,7 @@
return 1;
/* A call through the function vector is a small call too. */
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
&& (SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
return 1;
diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index e83ab66a598..6750c3e5d29 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -185,7 +185,7 @@ ix86_expand_move (machine_mode mode, rtx operands[])
tmp = XEXP (op1, 0);
if (GET_CODE (tmp) != PLUS
- || GET_CODE (XEXP (tmp, 0)) != SYMBOL_REF)
+ || !SYMBOL_REF_P (XEXP (tmp, 0)))
break;
op1 = XEXP (tmp, 0);
@@ -5262,7 +5262,7 @@ ix86_split_long_move (rtx operands[])
fp moves, that force all constants to memory to allow combining. */
if (MEM_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (operands[1], 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (operands[1], 0)))
operands[1] = get_pool_constant (XEXP (operands[1], 0));
if (push_operand (operands[0], VOIDmode))
@@ -7911,7 +7911,7 @@ construct_plt_address (rtx symbol)
{
rtx tmp, unspec;
- gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (symbol));
gcc_assert (ix86_cmodel == CM_LARGE_PIC && !TARGET_PECOFF);
gcc_assert (Pmode == DImode);
@@ -7944,7 +7944,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
unsigned int vec_len = 0;
tree fndecl;
- if (GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (fnaddr, 0)))
{
fndecl = SYMBOL_REF_DECL (XEXP (fnaddr, 0));
if (fndecl
@@ -7962,7 +7962,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
if (TARGET_MACHO && !TARGET_64BIT)
{
#if TARGET_MACHO
- if (flag_pic && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
+ if (flag_pic && SYMBOL_REF_P (XEXP (fnaddr, 0)))
fnaddr = machopic_indirect_call_target (fnaddr);
#endif
}
@@ -7973,7 +7973,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
it an indirect call. */
rtx addr = XEXP (fnaddr, 0);
if (flag_pic
- && GET_CODE (addr) == SYMBOL_REF
+ && SYMBOL_REF_P (addr)
&& !SYMBOL_REF_LOCAL_P (addr))
{
if (flag_plt
@@ -8037,7 +8037,7 @@ ix86_expand_call (rtx retval, rtx fnaddr, rtx callarg1,
if (ix86_cmodel == CM_LARGE_PIC
&& !TARGET_PECOFF
&& MEM_P (fnaddr)
- && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (fnaddr, 0))
&& !local_symbolic_operand (XEXP (fnaddr, 0), VOIDmode))
fnaddr = gen_rtx_MEM (QImode, construct_plt_address (XEXP (fnaddr, 0)));
/* Since x32 GOT slot is 64 bit with zero upper 32 bits, indirect
@@ -19847,7 +19847,7 @@ ix86_notrack_prefixed_insn_p (rtx insn)
/* Do not emit 'notrack' if it's not an indirect call. */
if (MEM_P (addr)
- && GET_CODE (XEXP (addr, 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (addr, 0)))
return false;
else
return find_reg_note (insn, REG_CALL_NOCF_CHECK, 0);
diff --git a/gcc/config/i386/i386-features.c b/gcc/config/i386/i386-features.c
index fcac684f7b5..c2d6e597f63 100644
--- a/gcc/config/i386/i386-features.c
+++ b/gcc/config/i386/i386-features.c
@@ -1853,7 +1853,7 @@ rest_of_insert_endbranch (void)
/* Also generate ENDBRANCH for non-tail call which
may return via indirect branch. */
- if (GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (fnaddr, 0)))
fndecl = SYMBOL_REF_DECL (XEXP (fnaddr, 0));
if (fndecl == NULL_TREE)
fndecl = MEM_EXPR (fnaddr);
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 4b74e1fe0f2..d485c4cdce8 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -4941,7 +4941,7 @@ symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
+ if (SYMBOL_REF_P (op) || LABEL_REF_P (op))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -9834,7 +9834,7 @@ ix86_force_load_from_GOT_p (rtx x)
&& !TARGET_PECOFF && !TARGET_MACHO
&& !flag_pic
&& ix86_cmodel != CM_LARGE
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& SYMBOL_REF_FUNCTION_P (x)
&& (!flag_plt
|| (SYMBOL_REF_DECL (x)
@@ -9875,11 +9875,11 @@ ix86_legitimate_constant_p (machine_mode mode, rtx x)
case UNSPEC_TPOFF:
case UNSPEC_NTPOFF:
x = XVECEXP (x, 0, 0);
- return (GET_CODE (x) == SYMBOL_REF
+ return (SYMBOL_REF_P (x)
&& SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
case UNSPEC_DTPOFF:
x = XVECEXP (x, 0, 0);
- return (GET_CODE (x) == SYMBOL_REF
+ return (SYMBOL_REF_P (x)
&& SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC);
default:
return false;
@@ -9888,7 +9888,7 @@ ix86_legitimate_constant_p (machine_mode mode, rtx x)
/* We must have drilled down to a symbol. */
if (LABEL_REF_P (x))
return true;
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return false;
/* FALLTHRU */
@@ -9970,7 +9970,7 @@ static bool
is_imported_p (rtx x)
{
if (!TARGET_DLLIMPORT_DECL_ATTRIBUTES
- || GET_CODE (x) != SYMBOL_REF)
+ || !SYMBOL_REF_P (x))
return false;
return SYMBOL_REF_DLLIMPORT_P (x) || SYMBOL_REF_STUBVAR_P (x);
@@ -10004,7 +10004,7 @@ legitimate_pic_operand_p (rtx x)
return TARGET_64BIT;
case UNSPEC_TPOFF:
x = XVECEXP (inner, 0, 0);
- return (GET_CODE (x) == SYMBOL_REF
+ return (SYMBOL_REF_P (x)
&& SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_EXEC);
case UNSPEC_MACHOPIC_OFFSET:
return legitimate_pic_address_disp_p (x);
@@ -10065,7 +10065,7 @@ legitimate_pic_address_disp_p (rtx disp)
if (GET_CODE (op0) == UNSPEC
&& XINT (op0, 1) == UNSPEC_PCREL)
return true;
- if (GET_CODE (op0) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op0))
break;
/* FALLTHRU */
@@ -10129,7 +10129,7 @@ legitimate_pic_address_disp_p (rtx disp)
&& XINT (disp, 1) != UNSPEC_PLTOFF))
return false;
- if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
+ if (!SYMBOL_REF_P (XVECEXP (disp, 0, 0))
&& !LABEL_REF_P (XVECEXP (disp, 0, 0)))
return false;
return true;
@@ -10158,13 +10158,13 @@ legitimate_pic_address_disp_p (rtx disp)
/* We need to check for both symbols and labels because VxWorks loads
text labels with @GOT rather than @GOTOFF. See gotoff_operand for
details. */
- return (GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
+ return (SYMBOL_REF_P (XVECEXP (disp, 0, 0))
|| LABEL_REF_P (XVECEXP (disp, 0, 0)));
case UNSPEC_GOTOFF:
/* Refuse GOTOFF in 64bit mode since it is always 64bit when used.
While ABI specify also 32bit relocation but we don't produce it in
small PIC model at all. */
- if ((GET_CODE (XVECEXP (disp, 0, 0)) == SYMBOL_REF
+ if ((SYMBOL_REF_P (XVECEXP (disp, 0, 0))
|| LABEL_REF_P (XVECEXP (disp, 0, 0)))
&& !TARGET_64BIT)
return !TARGET_PECOFF && gotoff_operand (XVECEXP (disp, 0, 0), Pmode);
@@ -10175,15 +10175,15 @@ legitimate_pic_address_disp_p (rtx disp)
if (saw_plus)
return false;
disp = XVECEXP (disp, 0, 0);
- return (GET_CODE (disp) == SYMBOL_REF
+ return (SYMBOL_REF_P (disp)
&& SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_INITIAL_EXEC);
case UNSPEC_NTPOFF:
disp = XVECEXP (disp, 0, 0);
- return (GET_CODE (disp) == SYMBOL_REF
+ return (SYMBOL_REF_P (disp)
&& SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_EXEC);
case UNSPEC_DTPOFF:
disp = XVECEXP (disp, 0, 0);
- return (GET_CODE (disp) == SYMBOL_REF
+ return (SYMBOL_REF_P (disp)
&& SYMBOL_REF_TLS_MODEL (disp) == TLS_MODEL_LOCAL_DYNAMIC);
}
@@ -10412,7 +10412,7 @@ ix86_legitimate_address_p (machine_mode, rtx addr, bool strict)
&& !CONST_INT_P (disp)
&& (GET_CODE (disp) != CONST
|| !ix86_legitimate_constant_p (Pmode, disp))
- && (GET_CODE (disp) != SYMBOL_REF
+ && (!SYMBOL_REF_P (disp)
|| !ix86_legitimate_constant_p (Pmode, disp)))
/* Displacement is not constant. */
return false;
@@ -10527,7 +10527,7 @@ legitimize_pic_address (rtx orig, rtx reg)
else
new_rtx = gen_rtx_PLUS (Pmode, pic_offset_table_rtx, new_rtx);
}
- else if ((GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (addr) == 0)
+ else if ((SYMBOL_REF_P (addr) && SYMBOL_REF_TLS_MODEL (addr) == 0)
/* We can't use @GOTOFF for text labels
on VxWorks, see gotoff_operand. */
|| (TARGET_VXWORKS_RTP && LABEL_REF_P (addr)))
@@ -10653,7 +10653,7 @@ legitimize_pic_address (rtx orig, rtx reg)
/* For %rip addressing, we have to use
just disp32, not base nor index. */
if (TARGET_64BIT
- && (GET_CODE (base) == SYMBOL_REF
+ && (SYMBOL_REF_P (base)
|| LABEL_REF_P (base)))
base = force_reg (mode, base);
if (GET_CODE (new_rtx) == PLUS
@@ -11189,11 +11189,11 @@ legitimize_pe_coff_symbol (rtx addr, bool inreg)
if (TARGET_DLLIMPORT_DECL_ATTRIBUTES)
{
- if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DLLIMPORT_P (addr))
+ if (SYMBOL_REF_P (addr) && SYMBOL_REF_DLLIMPORT_P (addr))
return legitimize_dllimport_symbol (addr, inreg);
if (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0))
&& SYMBOL_REF_DLLIMPORT_P (XEXP (XEXP (addr, 0), 0)))
{
rtx t = legitimize_dllimport_symbol (XEXP (XEXP (addr, 0), 0), inreg);
@@ -11203,7 +11203,7 @@ legitimize_pe_coff_symbol (rtx addr, bool inreg)
if (ix86_cmodel != CM_LARGE_PIC && ix86_cmodel != CM_MEDIUM_PIC)
return NULL_RTX;
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& !is_imported_p (addr)
&& SYMBOL_REF_EXTERNAL_P (addr)
&& SYMBOL_REF_DECL (addr))
@@ -11211,7 +11211,7 @@ legitimize_pe_coff_symbol (rtx addr, bool inreg)
if (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0))
&& !is_imported_p (XEXP (XEXP (addr, 0), 0))
&& SYMBOL_REF_EXTERNAL_P (XEXP (XEXP (addr, 0), 0))
&& SYMBOL_REF_DECL (XEXP (XEXP (addr, 0), 0)))
@@ -11246,12 +11246,12 @@ ix86_legitimize_address (rtx x, rtx, machine_mode mode)
bool changed = false;
unsigned log;
- log = GET_CODE (x) == SYMBOL_REF ? SYMBOL_REF_TLS_MODEL (x) : 0;
+ log = SYMBOL_REF_P (x) ? SYMBOL_REF_TLS_MODEL (x) : 0;
if (log)
return legitimize_tls_address (x, (enum tls_model) log, false);
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& (log = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (x, 0), 0))))
{
rtx t = legitimize_tls_address (XEXP (XEXP (x, 0), 0),
@@ -11659,7 +11659,7 @@ ix86_delegitimize_tls_address (rtx orig_x)
if (GET_CODE (unspec) != UNSPEC || XINT (unspec, 1) != UNSPEC_NTPOFF)
return orig_x;
x = XVECEXP (unspec, 0, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
if (unspec != XEXP (addr.disp, 0))
x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.disp, 0), 1));
if (addr.index)
@@ -12956,7 +12956,7 @@ ix86_print_operand (FILE *file, rtx x, int code)
if (ASSEMBLER_DIALECT == ASM_ATT)
putc ('$', file);
}
- else if (GET_CODE (x) == CONST || GET_CODE (x) == SYMBOL_REF
+ else if (GET_CODE (x) == CONST || SYMBOL_REF_P (x)
|| LABEL_REF_P (x))
{
if (ASSEMBLER_DIALECT == ASM_ATT)
@@ -13053,7 +13053,7 @@ ix86_print_operand_address_as (FILE *file, rtx addr,
symbol = XEXP (XEXP (disp, 0), 0);
if (LABEL_REF_P (symbol)
- || (GET_CODE (symbol) == SYMBOL_REF
+ || (SYMBOL_REF_P (symbol)
&& SYMBOL_REF_TLS_MODEL (symbol) == 0))
base = pc_rtx;
}
@@ -15664,7 +15664,7 @@ ix86_rip_relative_addr_p (struct ix86_address *parts)
symbol = XEXP (symbol, 0);
if (LABEL_REF_P (symbol)
- || (GET_CODE (symbol) == SYMBOL_REF
+ || (SYMBOL_REF_P (symbol)
&& SYMBOL_REF_TLS_MODEL (symbol) == 0)
|| (GET_CODE (symbol) == UNSPEC
&& (XINT (symbol, 1) == UNSPEC_GOTPCREL
@@ -22120,7 +22120,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
if (GET_CODE (addr) == CONST)
addr = XEXP (addr, 0);
- if (REG_P (addr) || GET_CODE (addr) == SYMBOL_REF)
+ if (REG_P (addr) || SYMBOL_REF_P (addr))
{
*base = addr;
*offset = const0_rtx;
@@ -22129,7 +22129,7 @@ extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset)
if (GET_CODE (addr) == PLUS
&& (REG_P (XEXP (addr, 0))
- || GET_CODE (XEXP (addr, 0)) == SYMBOL_REF)
+ || SYMBOL_REF_P (XEXP (addr, 0)))
&& CONST_INT_P (XEXP (addr, 1)))
{
*base = XEXP (addr, 0);
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 3f037a72b18..1b787f86968 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1843,7 +1843,7 @@ typedef struct ix86_args {
#define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X)
#define SYMBOLIC_CONST(X) \
- (GET_CODE (X) == SYMBOL_REF \
+ (SYMBOL_REF_P (X) \
|| LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
\f
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 785a0d11b1b..44b0822c02c 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -8476,7 +8476,7 @@
(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))
(clobber (reg:CC FLAGS_REG))])]
{
- if (GET_CODE (operands[2]) == SYMBOL_REF
+ if (SYMBOL_REF_P (operands[2])
|| LABEL_REF_P (operands[2]))
{
operands[2] = shallow_copy_rtx (operands[2]);
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md
index 9cf0473bd97..33df906ec92 100644
--- a/gcc/config/i386/predicates.md
+++ b/gcc/config/i386/predicates.md
@@ -510,7 +510,7 @@
case CONST:
op = XEXP (op, 0);
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
|| LABEL_REF_P (op)
|| (GET_CODE (op) == UNSPEC
&& (XINT (op, 1) == UNSPEC_GOT
@@ -523,7 +523,7 @@
return false;
op = XEXP (op, 0);
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
|| LABEL_REF_P (op))
return true;
/* Only @GOTOFF gets offsets. */
@@ -532,7 +532,7 @@
return false;
op = XVECEXP (op, 0, 0);
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
|| LABEL_REF_P (op))
return true;
return false;
@@ -554,7 +554,7 @@
if (LABEL_REF_P (op))
return true;
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return false;
if (SYMBOL_REF_TLS_MODEL (op))
@@ -1131,7 +1131,7 @@
}
if (TARGET_64BIT
&& flag_pic
- && (GET_CODE (disp) == SYMBOL_REF
+ && (SYMBOL_REF_P (disp)
|| LABEL_REF_P (disp)))
return false;
}
diff --git a/gcc/config/i386/winnt.c b/gcc/config/i386/winnt.c
index 1b439552f9c..cb27b101506 100644
--- a/gcc/config/i386/winnt.c
+++ b/gcc/config/i386/winnt.c
@@ -306,7 +306,7 @@ i386_pe_encode_section_info (tree decl, rtx rtl, int first)
return;
symbol = XEXP (rtl, 0);
- gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (symbol));
switch (TREE_CODE (decl))
{
@@ -651,7 +651,7 @@ i386_pe_maybe_record_exported_symbol (tree decl, const char *name, int is_data)
return;
symbol = XEXP (DECL_RTL (decl), 0);
- gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (symbol));
if (!SYMBOL_REF_DLLEXPORT_P (symbol))
return;
diff --git a/gcc/config/ia64/ia64.c b/gcc/config/ia64/ia64.c
index 86ef8bc0078..de5d47459ed 100644
--- a/gcc/config/ia64/ia64.c
+++ b/gcc/config/ia64/ia64.c
@@ -878,7 +878,7 @@ ia64_encode_section_info (tree decl, rtx rtl, int first)
/* Careful not to prod global register variables. */
if (TREE_CODE (decl) == VAR_DECL
&& MEM_P (DECL_RTL (decl))
- && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (DECL_RTL (decl), 0))
&& (TREE_STATIC (decl) || DECL_EXTERNAL (decl)))
ia64_encode_addr_area (decl, XEXP (rtl, 0));
}
@@ -974,10 +974,10 @@ tls_symbolic_operand_type (rtx addr)
if (GET_CODE (addr) == CONST)
{
if (GET_CODE (XEXP (addr, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (addr, 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (addr, 0), 0)))
tls_kind = SYMBOL_REF_TLS_MODEL (XEXP (XEXP (addr, 0), 0));
}
- else if (GET_CODE (addr) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (addr))
tls_kind = SYMBOL_REF_TLS_MODEL (addr);
return tls_kind;
@@ -1133,7 +1133,7 @@ ia64_expand_load_address (rtx dest, rtx src)
if (TARGET_AUTO_PIC)
emit_insn (gen_load_gprel64 (dest, src));
- else if (GET_CODE (src) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (src))
+ else if (SYMBOL_REF_P (src) && SYMBOL_REF_FUNCTION_P (src))
emit_insn (gen_load_fptr (dest, src));
else if (sdata_symbolic_operand (src, VOIDmode))
emit_insn (gen_load_gprel (dest, src));
@@ -4351,7 +4351,7 @@ ia64_assemble_integer (rtx x, unsigned int size, int aligned_p)
{
if (size == POINTER_SIZE / BITS_PER_UNIT
&& !(TARGET_NO_PIC || TARGET_AUTO_PIC)
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& SYMBOL_REF_FUNCTION_P (x))
{
static const char * const directive[2][2] = {
diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md
index 4b78dcf4971..9af0e4761c6 100644
--- a/gcc/config/ia64/predicates.md
+++ b/gcc/config/ia64/predicates.md
@@ -44,7 +44,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
offset = INTVAL (XEXP (op, 1));
@@ -109,7 +109,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
@@ -132,7 +132,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
@@ -183,7 +183,7 @@
/* Accept only (plus (symbol_ref) (const_int)). */
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
@@ -226,7 +226,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
@@ -266,7 +266,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1))
|| (INTVAL (XEXP (op, 1)) & 0x3fff) != 0)
return false;
@@ -290,7 +290,7 @@
case CONST:
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
op = XEXP (op, 0);
@@ -336,7 +336,7 @@
/* Accept only (plus (symbol_ref) (const_int)). */
op = XEXP (op, 0);
if (GET_CODE (op) != PLUS
- || GET_CODE (XEXP (op, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (op, 0))
|| !CONST_INT_P (XEXP (op, 1)))
return false;
diff --git a/gcc/config/iq2000/iq2000.c b/gcc/config/iq2000/iq2000.c
index 44a6fbfe122..f2916b69bcd 100644
--- a/gcc/config/iq2000/iq2000.c
+++ b/gcc/config/iq2000/iq2000.c
@@ -289,9 +289,9 @@ iq2000_check_split (rtx address, machine_mode mode)
if (GET_MODE_SIZE (mode) > (unsigned) UNITS_PER_WORD)
return 0;
- if ((GET_CODE (address) == SYMBOL_REF)
+ if ((SYMBOL_REF_P (address))
|| (GET_CODE (address) == CONST
- && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (address, 0), 0)))
|| LABEL_REF_P (address))
return 1;
@@ -825,7 +825,7 @@ iq2000_address_cost (rtx addr, machine_mode mode, addr_space_t as,
if (LABEL_REF_P (addr))
return 2;
- if (GET_CODE (addr) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (addr))
return 4;
if (! SMALL_INT (offset))
@@ -3443,7 +3443,7 @@ iq2000_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED,
if (LABEL_REF_P (symref))
* total = COSTS_N_INSNS (2);
- else if (GET_CODE (symref) != SYMBOL_REF)
+ else if (!SYMBOL_REF_P (symref))
* total = COSTS_N_INSNS (4);
/* Let's be paranoid.... */
else if (INTVAL (offset) < -32768 || INTVAL (offset) > 32767)
diff --git a/gcc/config/iq2000/iq2000.h b/gcc/config/iq2000/iq2000.h
index 5224b0a49be..d96159a54d1 100644
--- a/gcc/config/iq2000/iq2000.h
+++ b/gcc/config/iq2000/iq2000.h
@@ -345,7 +345,7 @@ typedef struct iq2000_args
/* Addressing Modes. */
#define CONSTANT_ADDRESS_P(X) \
- ( (LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+ ( (LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
diff --git a/gcc/config/lm32/lm32.c b/gcc/config/lm32/lm32.c
index 9f7c4cc54aa..0ad519e91d6 100644
--- a/gcc/config/lm32/lm32.c
+++ b/gcc/config/lm32/lm32.c
@@ -899,7 +899,7 @@ nonpic_symbol_mentioned_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x)
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x)
|| GET_CODE (x) == PC)
return 1;
@@ -1222,7 +1222,7 @@ lm32_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x, bool stric
return true;
/* gp(sym) */
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_SMALL_P (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_SMALL_P (x))
return true;
return false;
diff --git a/gcc/config/lm32/lm32.h b/gcc/config/lm32/lm32.h
index 636e13e25e7..514e47358f3 100644
--- a/gcc/config/lm32/lm32.h
+++ b/gcc/config/lm32/lm32.h
@@ -305,7 +305,7 @@ enum reg_class
/*---------------------*/
#define CONSTANT_ADDRESS_P(X) \
- ((LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+ ((LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
diff --git a/gcc/config/lm32/lm32.md b/gcc/config/lm32/lm32.md
index 31337484f13..357e0749b0b 100644
--- a/gcc/config/lm32/lm32.md
+++ b/gcc/config/lm32/lm32.md
@@ -149,7 +149,7 @@
if (flag_pic && symbolic_operand (operands[1], SImode))
{
if (LABEL_REF_P (operands[1])
- || (GET_CODE (operands[1]) == SYMBOL_REF
+ || (SYMBOL_REF_P (operands[1])
&& SYMBOL_REF_LOCAL_P (operands[1])
&& !SYMBOL_REF_WEAK (operands[1])))
{
@@ -174,7 +174,7 @@
rtx arg0 = XEXP (op, 0);
rtx arg1 = XEXP (op, 1);
if (LABEL_REF_P (arg0)
- || (GET_CODE (arg0) == SYMBOL_REF
+ || (SYMBOL_REF_P (arg0)
&& SYMBOL_REF_LOCAL_P (arg0)
&& !SYMBOL_REF_WEAK (arg0)))
{
diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md
index 90f86fd935b..ba18bfcd48a 100644
--- a/gcc/config/m32c/addsub.md
+++ b/gcc/config/m32c/addsub.md
@@ -92,7 +92,7 @@
case 1:
return \"add.w %X2,%h0\;adcf.w %H0\";
case 2:
- if (GET_CODE (operands[2]) == SYMBOL_REF)
+ if (SYMBOL_REF_P (operands[2]))
{
output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands);
return \"adc.w #%%hi(%d2),%H0\";
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 4a122a76908..b524c8eadd4 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -2353,7 +2353,7 @@ m32c_asm_integer (rtx x, unsigned int size, int aligned_p)
fputc ('\n', asm_out_file);
return true;
case 4:
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
fprintf (asm_out_file, "\t.long\t");
output_addr_const (asm_out_file, x);
@@ -2972,7 +2972,7 @@ current_function_special_page_vector (rtx x)
{
int num;
- if ((GET_CODE(x) == SYMBOL_REF)
+ if ((SYMBOL_REF_P (x))
&& (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
{
tree list;
diff --git a/gcc/config/m32r/m32r.c b/gcc/config/m32r/m32r.c
index 19533fa4323..5bb40ad2a44 100644
--- a/gcc/config/m32r/m32r.c
+++ b/gcc/config/m32r/m32r.c
@@ -549,12 +549,12 @@ small_data_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
if (! TARGET_SDATA_USE)
return 0;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return SYMBOL_REF_SMALL_P (op);
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0));
@@ -574,11 +574,11 @@ addr24_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
if (LABEL_REF_P (op))
return TARGET_ADDR24;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
sym = op;
else if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& satisfies_constraint_M (XEXP (XEXP (op, 0), 1)))
sym = XEXP (XEXP (op, 0), 0);
else
@@ -605,11 +605,11 @@ addr32_operand (rtx op, machine_mode mode)
if (LABEL_REF_P (op))
return TARGET_ADDR32;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
sym = op;
else if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& CONST_INT_P (XEXP (XEXP (op, 0), 1))
&& ! flag_pic)
sym = XEXP (XEXP (op, 0), 0);
@@ -628,7 +628,7 @@ call26_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
if (flag_pic)
return 1;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE;
return TARGET_CALL26;
@@ -1931,12 +1931,12 @@ direct_return (void)
int
m32r_legitimate_pic_operand_p (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
return 0;
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return 0;
@@ -1951,7 +1951,7 @@ m32r_legitimize_pic_address (rtx orig, rtx reg)
printf("m32r_legitimize_pic_address()\n");
#endif
- if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
+ if (SYMBOL_REF_P (orig) || LABEL_REF_P (orig))
{
rtx pic_ref, address;
int subregs = 0;
@@ -1972,7 +1972,7 @@ m32r_legitimize_pic_address (rtx orig, rtx reg)
crtl->uses_pic_offset_table = 1;
if (LABEL_REF_P (orig)
- || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
+ || (SYMBOL_REF_P (orig) && SYMBOL_REF_LOCAL_P (orig)))
{
emit_insn (gen_gotoff_load_addr (reg, orig));
emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
@@ -2343,7 +2343,7 @@ m32r_print_operand_address (FILE * file, machine_mode /*mode*/, rtx addr)
fprintf (file, "%s,%s",
reg_names[REGNO (base)], reg_names[REGNO (index)]);
/* Not sure this can happen, but leave in for now. */
- else if (GET_CODE (index) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (index))
{
output_addr_const (file, index);
fputc (',', file);
@@ -2963,7 +2963,7 @@ m32r_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
return !(GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& UINTVAL (XEXP (XEXP (x, 0), 1)) > 32767);
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h
index 99b976523a8..84fdac2d018 100644
--- a/gcc/config/m32r/m32r.h
+++ b/gcc/config/m32r/m32r.h
@@ -686,7 +686,7 @@ L2: .word STATIC
/* Recognize any constant value that is a valid address. */
#define CONSTANT_ADDRESS_P(X) \
( LABEL_REF_P (X) \
- || GET_CODE (X) == SYMBOL_REF \
+ || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) \
|| (GET_CODE (X) == CONST \
&& ! (flag_pic && ! m32r_legitimate_pic_operand_p (X))))
diff --git a/gcc/config/m32r/predicates.md b/gcc/config/m32r/predicates.md
index e180aee143e..09550362809 100644
--- a/gcc/config/m32r/predicates.md
+++ b/gcc/config/m32r/predicates.md
@@ -426,13 +426,13 @@
if (flag_pic)
return 0;
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
|| LABEL_REF_P (op))
return 1;
if (GET_CODE (op) == CONST
&& GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& satisfies_constraint_J (XEXP (XEXP (op, 0), 1)))
return 1;
diff --git a/gcc/config/m68k/constraints.md b/gcc/config/m68k/constraints.md
index c0318055286..14caa0d623d 100644
--- a/gcc/config/m68k/constraints.md
+++ b/gcc/config/m68k/constraints.md
@@ -87,7 +87,7 @@
"Used for operands that satisfy 'm' when -mpcrel is in effect."
(and (match_code "mem")
(match_test "TARGET_PCREL
- && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST)")))
diff --git a/gcc/config/m68k/m68k.c b/gcc/config/m68k/m68k.c
index 64cedf626e9..21568d51fea 100644
--- a/gcc/config/m68k/m68k.c
+++ b/gcc/config/m68k/m68k.c
@@ -1033,7 +1033,7 @@ m68k_expand_prologue (void)
/* If the stack limit is a symbol, we can check it here,
before actually allocating the space. */
if (crtl->limit_stack
- && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
+ && SYMBOL_REF_P (stack_limit_rtx))
{
limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4);
if (!m68k_legitimate_constant_p (Pmode, limit))
@@ -1132,7 +1132,7 @@ m68k_expand_prologue (void)
stack_pointer_rtx, stack_limit_rtx,
const1_rtx));
- else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF)
+ else if (!SYMBOL_REF_P (stack_limit_rtx))
warning (0, "stack limit expression is not supported");
}
@@ -1936,7 +1936,7 @@ m68k_illegitimate_symbolic_constant_p (rtx x)
if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
{
split_const (x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF
+ if (SYMBOL_REF_P (base)
&& !offset_within_block_p (base, INTVAL (offset)))
return true;
}
@@ -1971,7 +1971,7 @@ m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p)
if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1)
{
split_const (x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF
+ if (SYMBOL_REF_P (base)
&& !offset_within_block_p (base, INTVAL (offset) + reach - 1))
return false;
}
@@ -2471,7 +2471,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED,
rtx pic_ref = orig;
/* First handle a simple SYMBOL_REF or LABEL_REF */
- if (GET_CODE (orig) == SYMBOL_REF || LABEL_REF_P (orig))
+ if (SYMBOL_REF_P (orig) || LABEL_REF_P (orig))
{
gcc_assert (reg);
@@ -2704,7 +2704,7 @@ m68k_tls_symbol_p (rtx x)
if (!TARGET_HAVE_TLS)
return false;
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return false;
return SYMBOL_REF_TLS_MODEL (x) != 0;
@@ -2728,7 +2728,7 @@ m68k_tls_reference_p (rtx x, bool legitimate_p)
rtx x = *iter;
/* Note: this is not the same as m68k_tls_symbol_p. */
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
return true;
/* Don't recurse into legitimate TLS references. */
@@ -3064,11 +3064,11 @@ output_move_simode (rtx *operands)
{
if (CONST_INT_P (operands[1]))
return output_move_simode_const (operands);
- else if ((GET_CODE (operands[1]) == SYMBOL_REF
+ else if ((SYMBOL_REF_P (operands[1])
|| GET_CODE (operands[1]) == CONST)
&& push_operand (operands[0], SImode))
return "pea %a1";
- else if ((GET_CODE (operands[1]) == SYMBOL_REF
+ else if ((SYMBOL_REF_P (operands[1])
|| GET_CODE (operands[1]) == CONST)
&& ADDRESS_REG_P (operands[0]))
return "lea %a1,%0";
@@ -4486,7 +4486,7 @@ print_operand (FILE *file, rtx op, int letter)
else if (letter == 'p')
{
output_addr_const (file, op);
- if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op)))
+ if (!(SYMBOL_REF_P (op) && SYMBOL_REF_LOCAL_P (op)))
fprintf (file, "@PLTPC");
}
else if (REG_P (op))
@@ -4533,7 +4533,7 @@ print_operand (FILE *file, rtx op, int letter)
to ensure that we print relevant PIC stuff. */
asm_fprintf (file, "%I");
if (TARGET_PCREL
- && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST))
+ && (SYMBOL_REF_P (op) || GET_CODE (op) == CONST))
print_operand_address (file, op);
else
output_addr_const (file, op);
@@ -4662,7 +4662,7 @@ m68k_delegitimize_address (rtx orig_x)
&& XINT (unspec, 1) != UNSPEC_RELOC32))
return orig_x;
x = XVECEXP (unspec, 0, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x));
+ gcc_assert (SYMBOL_REF_P (x) || LABEL_REF_P (x));
if (unspec != XEXP (addr.offset, 0))
x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1));
if (addr.index)
@@ -4737,7 +4737,7 @@ print_operand_address (FILE *file, rtx addr)
/* (xxx).l. We need a special case for SYMBOL_REF if the symbol
name ends in `.<letter>', as the last 2 characters can be
mistaken as a size suffix. Put the name in parentheses. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& strlen (XSTR (addr, 0)) > 2
&& XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.')
{
diff --git a/gcc/config/m68k/m68k.h b/gcc/config/m68k/m68k.h
index cd74628fe55..7a1112378e2 100644
--- a/gcc/config/m68k/m68k.h
+++ b/gcc/config/m68k/m68k.h
@@ -630,7 +630,7 @@ __transfer_from_trampoline () \
#define MAX_REGS_PER_ADDRESS 2
#define CONSTANT_ADDRESS_P(X) \
- ((LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+ ((LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == CONST \
|| GET_CODE (X) == HIGH) \
&& m68k_legitimate_constant_p (Pmode, X))
diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index c995f4469c3..f3760031131 100644
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -900,7 +900,7 @@
tmp = XEXP (XEXP (tmp, 0), 0);
}
- gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (tmp));
gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0);
tmp = m68k_legitimize_tls_address (tmp);
@@ -944,7 +944,7 @@
if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P)
{
split_const (operands[1], &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF
+ if (SYMBOL_REF_P (base)
&& !offset_within_block_p (base, INTVAL (offset)))
{
tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode);
diff --git a/gcc/config/m68k/predicates.md b/gcc/config/m68k/predicates.md
index 6fa1df65938..37be09a47a2 100644
--- a/gcc/config/m68k/predicates.md
+++ b/gcc/config/m68k/predicates.md
@@ -26,7 +26,7 @@
{
if (TARGET_PCREL
&& MEM_P (op)
- && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
@@ -41,7 +41,7 @@
(match_code "subreg,reg,mem")
{
if (TARGET_PCREL && MEM_P (op)
- && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
@@ -55,7 +55,7 @@
(match_code "subreg,mem")
{
if (TARGET_PCREL && MEM_P (op)
- && (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0))
|| GET_CODE (XEXP (op, 0)) == CONST))
return 1;
@@ -150,7 +150,7 @@
case CONST:
op = XEXP (op, 0);
- return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ return ((SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
diff --git a/gcc/config/mcore/mcore.c b/gcc/config/mcore/mcore.c
index d7c70861426..c53298387a9 100644
--- a/gcc/config/mcore/mcore.c
+++ b/gcc/config/mcore/mcore.c
@@ -698,7 +698,7 @@ mcore_symbolic_address_p (rtx x)
return 1;
case CONST:
x = XEXP (x, 0);
- return ( (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ return ( (SYMBOL_REF_P (XEXP (x, 0))
|| LABEL_REF_P (XEXP (x, 0)))
&& CONST_INT_P (XEXP (x, 1)));
default:
@@ -731,7 +731,7 @@ mcore_output_call (rtx operands[], int index)
if (TARGET_CG_DATA)
{
gcc_assert (mcore_current_function_name);
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
ASM_OUTPUT_CG_EDGE (asm_out_file, mcore_current_function_name,
XSTR (addr, 0), 0);
@@ -1991,7 +1991,7 @@ mcore_expand_prolog (void)
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
free (mcore_current_function_name);
@@ -2913,7 +2913,7 @@ mcore_mark_dllexport (tree decl)
if (MEM_P (rtlname))
rtlname = XEXP (rtlname, 0);
- gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (rtlname));
oldname = XSTR (rtlname, 0);
if (mcore_dllexport_name_p (oldname))
@@ -2948,7 +2948,7 @@ mcore_mark_dllimport (tree decl)
if (MEM_P (rtlname))
rtlname = XEXP (rtlname, 0);
- gcc_assert (GET_CODE (rtlname) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (rtlname));
oldname = XSTR (rtlname, 0);
gcc_assert (!mcore_dllexport_name_p (oldname));
@@ -3034,7 +3034,7 @@ mcore_encode_section_info (tree decl, rtx rtl ATTRIBUTE_UNUSED, int first ATTRIB
&& DECL_RTL (decl) != NULL_RTX
&& MEM_P (DECL_RTL (decl))
&& MEM_P (XEXP (DECL_RTL (decl), 0))
- && GET_CODE (XEXP (XEXP (DECL_RTL (decl), 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (DECL_RTL (decl), 0), 0))
&& mcore_dllimport_name_p (XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0)))
{
const char * oldname = XSTR (XEXP (XEXP (DECL_RTL (decl), 0), 0), 0);
diff --git a/gcc/config/microblaze/microblaze.c b/gcc/config/microblaze/microblaze.c
index d85030c47da..cc4d3a07607 100644
--- a/gcc/config/microblaze/microblaze.c
+++ b/gcc/config/microblaze/microblaze.c
@@ -432,7 +432,7 @@ microblaze_tls_symbol_p (rtx x)
if (!TARGET_HAVE_TLS)
return false;
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return false;
return SYMBOL_REF_TLS_MODEL (x) != 0;
@@ -449,7 +449,7 @@ microblaze_tls_referenced_p (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
return true;
/* Don't recurse into UNSPEC_TLS looking for TLS symbols; these are
TLS offsets, not real symbol references. */
@@ -472,7 +472,7 @@ symbol_mentioned_p (rtx x)
const char * fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return 1;
/* UNSPEC entries for a symbol include the SYMBOL_REF, but they
@@ -693,7 +693,7 @@ get_base_reg (rtx x)
base_reg = MB_ABI_PIC_ADDR_REGNUM;
if (TARGET_XLGPOPT
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& SYMBOL_REF_SMALL_P (x) && (decl = SYMBOL_REF_DECL (x)) != NULL)
{
if (TREE_READONLY (decl))
@@ -778,7 +778,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
return microblaze_classify_unspec (info, xplus1);
}
- else if ((GET_CODE (xplus1) == SYMBOL_REF ||
+ else if ((SYMBOL_REF_P (xplus1) ||
LABEL_REF_P (xplus1)))
{
if (flag_pic == 2 || microblaze_tls_symbol_p(xplus1))
@@ -816,7 +816,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
xconst0 = XEXP (xconst0, 0);
}
- if (GET_CODE (xconst0) == SYMBOL_REF
+ if (SYMBOL_REF_P (xconst0)
|| LABEL_REF_P (xconst0))
{
if (flag_pic == 2 || microblaze_tls_symbol_p(xconst0))
@@ -883,7 +883,7 @@ microblaze_classify_address (struct microblaze_address_info *info, rtx x,
/* Avoid error in print_operand_address in case UNSPEC
is removed from SYMBOL or LABEL REFS during optimization. */
- if ((GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
+ if ((SYMBOL_REF_P (x) || LABEL_REF_P (x))
&& flag_pic && TARGET_PIC_DATA_TEXT_REL && strict == 2)
{
info->type = ADDRESS_SYMBOLIC_TXT_REL;
@@ -928,7 +928,7 @@ microblaze_legitimate_address_p (machine_mode mode, rtx x, bool strict)
bool
microblaze_constant_address_p (rtx x)
{
- return ((LABEL_REF_P (x)) || (GET_CODE (x) == SYMBOL_REF)
+ return ((LABEL_REF_P (x)) || (SYMBOL_REF_P (x))
|| CONST_INT_P (x)
|| (GET_CODE (x) == CONST
&& ! (flag_pic && pic_address_needs_scratch (x))));
@@ -1100,7 +1100,7 @@ microblaze_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
}
}
- if (GET_CODE (xinsn) == SYMBOL_REF)
+ if (SYMBOL_REF_P (xinsn))
{
rtx reg;
if (microblaze_tls_symbol_p(xinsn))
@@ -1505,7 +1505,7 @@ pic_address_needs_scratch (rtx x)
p0 = XEXP (XEXP (x, 0), 0);
p1 = XEXP (XEXP (x, 0), 1);
- if ((GET_CODE (p0) == SYMBOL_REF || LABEL_REF_P (p0))
+ if ((SYMBOL_REF_P (p0) || LABEL_REF_P (p0))
&& (CONST_INT_P (p1))
&& (flag_pic == 2 || microblaze_tls_symbol_p (p0) || !SMALL_INT (p1)))
return 1;
@@ -3291,7 +3291,7 @@ static rtx
expand_pic_symbol_ref (machine_mode mode ATTRIBUTE_UNUSED, rtx op)
{
rtx result;
- bool isFunc = (GET_CODE (op) == SYMBOL_REF
+ bool isFunc = (SYMBOL_REF_P (op)
&& (SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_FUNCTION));
result = (!TARGET_PIC_DATA_TEXT_REL)
? gen_rtx_UNSPEC (Pmode, gen_rtvec (1, op), UNSPEC_GOTOFF)
@@ -3396,7 +3396,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
}
/* If operands[1] is a constant address invalid for pic, then we need to
handle it just like LEGITIMIZE_ADDRESS does. */
- if (GET_CODE (op1) == SYMBOL_REF || LABEL_REF_P (op1))
+ if (SYMBOL_REF_P (op1) || LABEL_REF_P (op1))
{
rtx result;
if (microblaze_tls_symbol_p(op1))
@@ -3451,7 +3451,7 @@ microblaze_expand_move (machine_mode mode, rtx operands[])
if ((CONST_INT_P (p1))
&& ((GET_CODE (p0) == UNSPEC)
- || ((GET_CODE (p0) == SYMBOL_REF || LABEL_REF_P (p0))
+ || ((SYMBOL_REF_P (p0) || LABEL_REF_P (p0))
&& (flag_pic == 2 || microblaze_tls_symbol_p (p0)
|| !SMALL_INT (p1)))))
{
@@ -3787,7 +3787,7 @@ microblaze_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
if ((GET_CODE (p0) == UNSPEC))
return false;
- if ((GET_CODE (p0) == SYMBOL_REF || LABEL_REF_P (p0))
+ if ((SYMBOL_REF_P (p0) || LABEL_REF_P (p0))
&& (microblaze_tls_symbol_p (p0) || !SMALL_INT (p1)))
return false;
}
diff --git a/gcc/config/microblaze/microblaze.md b/gcc/config/microblaze/microblaze.md
index a83d7ff2d80..cf64c31634b 100644
--- a/gcc/config/microblaze/microblaze.md
+++ b/gcc/config/microblaze/microblaze.md
@@ -2056,7 +2056,7 @@
rtx addr = XEXP (operands[0], 0);
if (flag_pic == 2 && !TARGET_PIC_DATA_TEXT_REL
- && GET_CODE (addr) == SYMBOL_REF
+ && SYMBOL_REF_P (addr)
&& !SYMBOL_REF_LOCAL_P (addr))
{
rtx temp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_PLT);
@@ -2125,7 +2125,7 @@
register rtx target = operands[0];
register rtx target2 = gen_rtx_REG (Pmode,
GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
- if (GET_CODE (target) == SYMBOL_REF) {
+ if (SYMBOL_REF_P (target)) {
if (microblaze_break_function_p (SYMBOL_REF_DECL (target))) {
gen_rtx_CLOBBER (VOIDmode, target2);
return "brki\tr16,%0\;%#";
@@ -2160,7 +2160,7 @@
rtx addr = XEXP (operands[1], 0);
if (flag_pic == 2 && !TARGET_PIC_DATA_TEXT_REL
- && GET_CODE (addr) == SYMBOL_REF
+ && SYMBOL_REF_P (addr)
&& !SYMBOL_REF_LOCAL_P (addr))
{
rtx temp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), UNSPEC_PLT);
@@ -2235,7 +2235,7 @@
register rtx target = operands[1];
register rtx target2=gen_rtx_REG (Pmode,GP_REG_FIRST + MB_ABI_SUB_RETURN_ADDR_REGNUM);
- if (GET_CODE (target) == SYMBOL_REF)
+ if (SYMBOL_REF_P (target))
{
gen_rtx_CLOBBER (VOIDmode,target2);
if (microblaze_break_function_p (SYMBOL_REF_DECL (target)))
diff --git a/gcc/config/microblaze/predicates.md b/gcc/config/microblaze/predicates.md
index fae269894c4..4aaf6602146 100644
--- a/gcc/config/microblaze/predicates.md
+++ b/gcc/config/microblaze/predicates.md
@@ -63,7 +63,7 @@
p0 = XEXP (const0, 0);
p1 = XEXP (const0, 1);
- if ((GET_CODE(p0) == SYMBOL_REF
+ if ((SYMBOL_REF_P (p0)
|| LABEL_REF_P (p0))
&& CONST_INT_P (p1))
{
@@ -101,7 +101,7 @@
(define_predicate "call_insn_simple_operand"
(and (match_test "CALL_INSN_OP (op)")
- (match_test "REG_P (op) || GET_CODE (op) == SYMBOL_REF || CONST_INT_P (op)")))
+ (match_test "REG_P (op) || SYMBOL_REF_P (op) || CONST_INT_P (op)")))
;; Return if OPERAND is valid as a source operand for a move instruction.
(define_predicate "move_src_operand"
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 34287cb40e1..016f72ddce1 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -1823,7 +1823,7 @@ mips_got_symbol_type_p (enum mips_symbol_type type)
static bool
mips_tls_symbol_p (rtx x)
{
- return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
+ return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0;
}
/* Return true if SYMBOL_REF X is associated with a global symbol
@@ -1848,7 +1848,7 @@ mips_global_symbol_p (const_rtx x)
static bool
mips16_stub_function_p (const_rtx x)
{
- return (GET_CODE (x) == SYMBOL_REF
+ return (SYMBOL_REF_P (x)
&& strncmp (XSTR (x, 0), "__mips16_", 9) == 0);
}
@@ -1858,7 +1858,7 @@ mips16_stub_function_p (const_rtx x)
static bool
mips16_local_function_p (const_rtx x)
{
- return (GET_CODE (x) == SYMBOL_REF
+ return (SYMBOL_REF_P (x)
&& SYMBOL_REF_LOCAL_P (x)
&& !SYMBOL_REF_EXTERNAL_P (x)
&& (mips_get_compress_mode (SYMBOL_REF_DECL (x)) & MASK_MIPS16));
@@ -2028,7 +2028,7 @@ mips_dangerous_for_la25_p (rtx x)
{
return (!TARGET_EXPLICIT_RELOCS
&& TARGET_USE_GOT
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& mips_global_symbol_p (x));
}
@@ -2044,7 +2044,7 @@ mips_use_pic_fn_addr_reg_p (const_rtx x)
if (mips16_stub_function_p (x))
return false;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
/* If PLTs and copy relocations are available, the static linker
will make sure that $25 is valid on entry to the target function. */
@@ -2088,7 +2088,7 @@ mips_classify_symbol (const_rtx x, enum mips_symbol_context context)
return SYMBOL_ABSOLUTE;
}
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
if (SYMBOL_REF_TLS_MODEL (x))
return SYMBOL_TLS;
@@ -2185,7 +2185,7 @@ mips_symbolic_constant_p (rtx x, enum mips_symbol_context context,
*symbol_type = UNSPEC_ADDRESS_TYPE (x);
x = UNSPEC_ADDRESS (x);
}
- else if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
+ else if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
{
*symbol_type = mips_classify_symbol (x, context);
if (*symbol_type == SYMBOL_TLS)
@@ -7117,7 +7117,7 @@ static bool
mips_ok_for_lazy_binding_p (rtx x)
{
return (TARGET_USE_GOT
- && GET_CODE (x) == SYMBOL_REF
+ && SYMBOL_REF_P (x)
&& !SYMBOL_REF_BIND_NOW_P (x)
&& !mips_symbol_binds_local_p (x));
}
@@ -7509,7 +7509,7 @@ mips16_build_call_stub (rtx retval, rtx *fn_ptr, rtx args_size, int fp_code)
/* If we're calling via a function pointer, use one of the magic
libgcc.a stubs provided for each (FP_CODE, FP_RET_P) combination.
Each stub expects the function address to arrive in register $2. */
- if (GET_CODE (fn) != SYMBOL_REF
+ if (!SYMBOL_REF_P (fn)
|| !call_insn_operand (fn, VOIDmode))
{
char buf[32];
@@ -17426,7 +17426,7 @@ mips16_rewrite_pool_constant (struct mips16_constant_pool *pool, rtx *x)
rtx_code_label *label;
split_const (*x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (base))
+ if (SYMBOL_REF_P (base) && CONSTANT_POOL_ADDRESS_P (base))
{
label = mips16_add_constant (pool, copy_rtx (get_pool_constant (base)),
get_pool_mode (base));
@@ -17772,7 +17772,7 @@ r10k_needs_protection_p_call (const_rtx x)
if (MEM_P (mem))
{
const_rtx addr = XEXP (mem, 0);
- if (GET_CODE (addr) == SYMBOL_REF && SYMBOL_REF_DECL (addr))
+ if (SYMBOL_REF_P (addr) && SYMBOL_REF_DECL (addr))
iter.skip_subrtxes ();
else
return true;
@@ -17974,21 +17974,21 @@ mips_pic_call_symbol_from_set (df_ref def, rtx reg, bool recurse_p)
/* First see whether the source is a plain symbol. This is used
when calling symbols that are not lazily bound. */
src = SET_SRC (set);
- if (GET_CODE (src) == SYMBOL_REF)
+ if (SYMBOL_REF_P (src))
return src;
/* Handle %call16 references. */
symbol = mips_strip_unspec_call (src);
if (symbol)
{
- gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (symbol));
return symbol;
}
/* If we have something more complicated, look for a
REG_EQUAL or REG_EQUIV note. */
note = find_reg_equal_equiv_note (def_insn);
- if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
+ if (note && SYMBOL_REF_P (XEXP (note, 0)))
return XEXP (note, 0);
/* Follow at most one simple register copy. Such copies are
@@ -18086,7 +18086,7 @@ mips_get_pic_call_symbol (rtx *operands, int args_size_opno)
gcc_assert (XINT (args_size, 1) == UNSPEC_CALL_ATTR);
symbol = XVECEXP (args_size, 0, 1);
- gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (symbol));
operands[args_size_opno] = symbol;
return true;
diff --git a/gcc/config/mips/predicates.md b/gcc/config/mips/predicates.md
index 0b0b004b4f1..80691253a62 100644
--- a/gcc/config/mips/predicates.md
+++ b/gcc/config/mips/predicates.md
@@ -343,7 +343,7 @@
/* If -mlong-calls or if this function has an explicit long_call
attribute, we must use register addressing. The
SYMBOL_FLAG_LONG_CALL bit is set by mips_encode_section_info. */
- return !(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LONG_CALL_P (op));
+ return !(SYMBOL_REF_P (op) && SYMBOL_REF_LONG_CALL_P (op));
case SYMBOL_GOT_DISP:
/* Without explicit relocs, there is no special syntax for
diff --git a/gcc/config/mmix/mmix.c b/gcc/config/mmix/mmix.c
index 6f68981f777..d9e9a68ab4b 100644
--- a/gcc/config/mmix/mmix.c
+++ b/gcc/config/mmix/mmix.c
@@ -1061,7 +1061,7 @@ mmix_constant_address_p (rtx x)
rtx x0 = XEXP (XEXP (x, 0), 0);
rtx x1 = XEXP (XEXP (x, 0), 1);
- if ((GET_CODE (x0) == SYMBOL_REF
+ if ((SYMBOL_REF_P (x0)
|| LABEL_REF_P (x0))
&& (CONST_INT_P (x1)
|| (CONST_DOUBLE_P (x1)
@@ -1625,7 +1625,7 @@ mmix_print_operand (FILE *stream, rtx x, int code)
return;
}
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
output_addr_const (stream, x);
return;
diff --git a/gcc/config/mmix/predicates.md b/gcc/config/mmix/predicates.md
index 41e4f342826..9bdc847c96f 100644
--- a/gcc/config/mmix/predicates.md
+++ b/gcc/config/mmix/predicates.md
@@ -110,7 +110,7 @@
case CONST:
/* The reason why this body still is C. */
op = XEXP (op, 0);
- if ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ if ((SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0)))
&& (CONST_INT_P (XEXP (op, 1))
|| (CONST_DOUBLE_P (XEXP (op, 1))
diff --git a/gcc/config/mn10300/constraints.md b/gcc/config/mn10300/constraints.md
index b4c7cbed0e5..1e8abd7b296 100644
--- a/gcc/config/mn10300/constraints.md
+++ b/gcc/config/mn10300/constraints.md
@@ -59,7 +59,7 @@
(ior (match_test "XINT (op, 1) == UNSPEC_PLT")
(match_test "XINT (op, 1) == UNSPEC_PIC")
(match_test "XINT (op, 1) == UNSPEC_GOTSYM_OFF")))
- (match_test "GET_CODE (op) == SYMBOL_REF")))
+ (match_test "SYMBOL_REF_P (op)")))
;; Integer constraints
diff --git a/gcc/config/mn10300/mn10300.c b/gcc/config/mn10300/mn10300.c
index 10cce63ca3f..da4d8c3e13d 100644
--- a/gcc/config/mn10300/mn10300.c
+++ b/gcc/config/mn10300/mn10300.c
@@ -1798,7 +1798,7 @@ mn10300_symbolic_operand (rtx op,
return 1;
case CONST:
op = XEXP (op, 0);
- return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ return ((SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
default:
@@ -1867,7 +1867,7 @@ mn10300_legitimize_pic_address (rtx orig, rtx reg)
rtx_insn *insn;
if (LABEL_REF_P (orig)
- || (GET_CODE (orig) == SYMBOL_REF
+ || (SYMBOL_REF_P (orig)
&& (CONSTANT_POOL_ADDRESS_P (orig)
|| ! MN10300_GLOBAL_P (orig))))
{
@@ -1880,7 +1880,7 @@ mn10300_legitimize_pic_address (rtx orig, rtx reg)
insn = emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx));
}
- else if (GET_CODE (orig) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (orig))
{
if (reg == NULL)
reg = gen_reg_rtx (Pmode);
@@ -1908,7 +1908,7 @@ mn10300_legitimate_pic_operand_p (rtx x)
const char *fmt;
int i;
- if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
return 0;
if (GET_CODE (x) == UNSPEC
@@ -2149,7 +2149,7 @@ mn10300_delegitimize_address (rtx orig_x)
else
return orig_x;
- gcc_assert (GET_CODE (ret) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (ret));
if (need_mem != MEM_P (orig_x))
return orig_x;
if (need_mem && addend)
@@ -2515,7 +2515,7 @@ mn10300_encode_section_info (tree decl, rtx rtl, int first)
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
if (flag_pic)
diff --git a/gcc/config/mn10300/mn10300.h b/gcc/config/mn10300/mn10300.h
index 4239598aece..189d0426045 100644
--- a/gcc/config/mn10300/mn10300.h
+++ b/gcc/config/mn10300/mn10300.h
@@ -538,7 +538,7 @@ do { \
#define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_"
#define SYMBOLIC_CONST_P(X) \
-((GET_CODE (X) == SYMBOL_REF || LABEL_REF_P (X)) \
+((SYMBOL_REF_P (X) || LABEL_REF_P (X)) \
&& ! LEGITIMATE_PIC_OPERAND_P (X))
/* Non-global SYMBOL_REFs have SYMBOL_REF_FLAG enabled. */
diff --git a/gcc/config/mn10300/mn10300.md b/gcc/config/mn10300/mn10300.md
index c7c7bbf6174..45fb5cae646 100644
--- a/gcc/config/mn10300/mn10300.md
+++ b/gcc/config/mn10300/mn10300.md
@@ -1574,7 +1574,7 @@
{
rtx fn = XEXP (operands[0], 0);
- if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
+ if (flag_pic && SYMBOL_REF_P (fn))
{
if (MN10300_GLOBAL_P (fn))
{
@@ -1621,7 +1621,7 @@
{
rtx fn = XEXP (operands[1], 0);
- if (flag_pic && GET_CODE (fn) == SYMBOL_REF)
+ if (flag_pic && SYMBOL_REF_P (fn))
{
if (MN10300_GLOBAL_P (fn))
{
diff --git a/gcc/config/mn10300/predicates.md b/gcc/config/mn10300/predicates.md
index 210d7140111..6ec23f032fc 100644
--- a/gcc/config/mn10300/predicates.md
+++ b/gcc/config/mn10300/predicates.md
@@ -33,7 +33,7 @@
if (flag_pic)
return (satisfies_constraint_S (op) || REG_P (op));
- return (GET_CODE (op) == SYMBOL_REF || REG_P (op));
+ return (SYMBOL_REF_P (op) || REG_P (op));
})
(define_predicate "impossible_plus_operand"
diff --git a/gcc/config/moxie/constraints.md b/gcc/config/moxie/constraints.md
index 554b5cb5105..241815cf60b 100644
--- a/gcc/config/moxie/constraints.md
+++ b/gcc/config/moxie/constraints.md
@@ -25,7 +25,7 @@
(define_constraint "A"
"An absolute address."
(and (match_code "mem")
- (ior (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF")
+ (ior (match_test "SYMBOL_REF_P (XEXP (op, 0))")
(match_test "LABEL_REF_P (XEXP (op, 0))")
(match_test "GET_CODE (XEXP (op, 0)) == CONST"))))
diff --git a/gcc/config/moxie/moxie.c b/gcc/config/moxie/moxie.c
index ed532244357..78fe9551d93 100644
--- a/gcc/config/moxie/moxie.c
+++ b/gcc/config/moxie/moxie.c
@@ -133,7 +133,7 @@ moxie_print_operand_address (FILE *file, machine_mode, rtx x)
case CONST:
{
rtx plus = XEXP (XEXP (x, 1), 0);
- if (GET_CODE (XEXP (plus, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (plus, 0))
&& CONST_INT_P (XEXP (plus, 1)))
{
output_addr_const(file, XEXP (plus, 0));
@@ -603,7 +603,7 @@ moxie_legitimate_address_p (machine_mode mode ATTRIBUTE_UNUSED,
return true;
if (REG_P (x) && moxie_reg_ok_for_base_p (x, strict_p))
return true;
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
|| LABEL_REF_P (x)
|| GET_CODE (x) == CONST)
return true;
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c
index 0d3421a0121..7d93f15c1bc 100644
--- a/gcc/config/msp430/msp430.c
+++ b/gcc/config/msp430/msp430.c
@@ -3196,7 +3196,7 @@ msp430_subreg (machine_mode mode, rtx r, machine_mode omode, int byte)
}
else if (MEM_P (r))
rv = adjust_address (r, mode, byte);
- else if (GET_CODE (r) == SYMBOL_REF
+ else if (SYMBOL_REF_P (r)
&& (byte == 0 || byte == 2)
&& mode == HImode)
{
@@ -3222,7 +3222,7 @@ msp430_split_movsi (rtx *operands)
op02 = msp430_subreg (HImode, operands[0], SImode, 2);
if (GET_CODE (operands[1]) == CONST
- || GET_CODE (operands[1]) == SYMBOL_REF)
+ || SYMBOL_REF_P (operands[1]))
{
op10 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (0));
op10 = gen_rtx_CONST (HImode, op10);
diff --git a/gcc/config/nds32/nds32-md-auxiliary.c b/gcc/config/nds32/nds32-md-auxiliary.c
index 90f9c89643c..bc6be927790 100644
--- a/gcc/config/nds32/nds32-md-auxiliary.c
+++ b/gcc/config/nds32/nds32-md-auxiliary.c
@@ -3456,7 +3456,7 @@ symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
+ if (SYMBOL_REF_P (op) || LABEL_REF_P (op))
return true;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -3503,7 +3503,7 @@ nds32_legitimize_pic_address (rtx x)
int relax_group_id = nds32_alloc_relax_group_id ();
if (LABEL_REF_P (x)
- || (GET_CODE (x) == SYMBOL_REF
+ || (SYMBOL_REF_P (x)
&& (CONSTANT_POOL_ADDRESS_P (x)
|| SYMBOL_REF_LOCAL_P (x))))
{
@@ -3512,7 +3512,7 @@ nds32_legitimize_pic_address (rtx x)
emit_insn (gen_sym_got (reg, addr, GEN_INT (relax_group_id)));
x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx);
}
- else if (GET_CODE (x) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (x))
{
addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, x), UNSPEC_GOT);
addr = gen_rtx_CONST (SImode, addr);
@@ -3532,7 +3532,7 @@ nds32_legitimize_pic_address (rtx x)
rtx op1 = XEXP (addr, 1);
if ((LABEL_REF_P (op0)
- || (GET_CODE (op0) == SYMBOL_REF
+ || (SYMBOL_REF_P (op0)
&& (CONSTANT_POOL_ADDRESS_P (op0)
|| SYMBOL_REF_LOCAL_P (op0))))
&& CONST_INT_P (op1))
@@ -3543,7 +3543,7 @@ nds32_legitimize_pic_address (rtx x)
emit_insn (gen_sym_got (reg, pat, GEN_INT (relax_group_id)));
x = gen_rtx_PLUS (Pmode, reg, pic_offset_table_rtx);
}
- else if (GET_CODE (op0) == SYMBOL_REF
+ else if (SYMBOL_REF_P (op0)
&& CONST_INT_P (op1))
{
/* This is a constant offset from a @GOT symbol reference. */
@@ -3597,7 +3597,7 @@ nds32_legitimize_ict_address (rtx x)
rtx symbol = x;
rtx addr = x;
rtx reg = gen_reg_rtx (Pmode);
- gcc_assert (GET_CODE (x) == SYMBOL_REF
+ gcc_assert (SYMBOL_REF_P (x)
&& nds32_indirect_call_referenced_p (x));
addr = gen_rtx_UNSPEC (SImode, gen_rtvec (1, symbol), UNSPEC_ICT);
@@ -3626,7 +3626,7 @@ nds32_indirect_call_referenced_p (rtx x)
if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_ICT)
x = XVECEXP (x, 0, 0);
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
tree decl = SYMBOL_REF_DECL (x);
@@ -3659,7 +3659,7 @@ nds32_tls_referenced_p (rtx x)
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x))
return true;
return false;
@@ -3675,7 +3675,7 @@ nds32_legitimize_tls_address (rtx x)
rtx pat, insns, reg0;
int relax_group_id = nds32_alloc_relax_group_id ();
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
switch (SYMBOL_REF_TLS_MODEL (x))
{
case TLS_MODEL_GLOBAL_DYNAMIC:
diff --git a/gcc/config/nds32/nds32-predicates.c b/gcc/config/nds32/nds32-predicates.c
index 7cfa77eb5cd..c3b8237803c 100644
--- a/gcc/config/nds32/nds32-predicates.c
+++ b/gcc/config/nds32/nds32-predicates.c
@@ -444,7 +444,7 @@ nds32_symbol_load_store_p (rtx_insn *insn)
|| (GET_CODE (mem_src) == SIGN_EXTEND))
mem_src = XEXP (mem_src, 0);
- if ((GET_CODE (XEXP (mem_src, 0)) == SYMBOL_REF)
+ if ((SYMBOL_REF_P (XEXP (mem_src, 0)))
|| (GET_CODE (XEXP (mem_src, 0)) == LO_SUM))
return true;
}
@@ -460,14 +460,14 @@ nds32_float_mem_operand_p (rtx op)
rtx addr = XEXP (op, 0);
/* Not support [symbol] [const] memory */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
|| GET_CODE (addr) == CONST
|| GET_CODE (addr) == LO_SUM)
return false;
if (GET_CODE (addr) == PLUS)
{
- if (GET_CODE (XEXP (addr, 0)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (addr, 0)))
return false;
/* Restrict const range: (imm12s << 2) */
@@ -548,7 +548,7 @@ nds32_const_unspec_p (rtx x)
}
}
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& SYMBOL_REF_TLS_MODEL (x))
return false;
diff --git a/gcc/config/nds32/nds32-utils.c b/gcc/config/nds32/nds32-utils.c
index 327636bbd55..bd89824c847 100644
--- a/gcc/config/nds32/nds32-utils.c
+++ b/gcc/config/nds32/nds32-utils.c
@@ -339,7 +339,7 @@ extract_base_reg (rtx_insn *insn)
plus_rtx = XEXP (mem_rtx, 0);
- if (GET_CODE (plus_rtx) == SYMBOL_REF
+ if (SYMBOL_REF_P (plus_rtx)
|| GET_CODE (plus_rtx) == CONST)
return NULL_RTX;
diff --git a/gcc/config/nds32/nds32.c b/gcc/config/nds32/nds32.c
index 44d2ad83e9f..574c571dc7d 100644
--- a/gcc/config/nds32/nds32.c
+++ b/gcc/config/nds32/nds32.c
@@ -2567,7 +2567,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
/* When using floating-point instructions,
we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */
if ((mode == DFmode || mode == SFmode)
- && (GET_CODE (x) == SYMBOL_REF
+ && (SYMBOL_REF_P (x)
|| GET_CODE(x) == CONST))
return false;
@@ -2630,7 +2630,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
/* Now check [reg], [symbol_ref], and [const]. */
if (!REG_P (x)
- && GET_CODE (x) != SYMBOL_REF
+ && !SYMBOL_REF_P (x)
&& GET_CODE (x) != CONST)
return false;
}
@@ -2681,7 +2681,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
rtx op0 = XEXP (plus_op, 0);
rtx op1 = XEXP (plus_op, 1);
- if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
+ if (SYMBOL_REF_P (op0) && CONST_INT_P (op1))
{
/* Now we see the [ + const_addr ] pattern, but we need
some further checking. */
@@ -2781,7 +2781,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
if (!REG_P (XEXP (x, 0)))
return false;
- if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (x, 1)))
sym = XEXP (x, 1);
else if (GET_CODE (XEXP (x, 1)) == CONST)
{
@@ -2794,7 +2794,7 @@ nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict)
else
return false;
- gcc_assert (GET_CODE (sym) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (sym));
if (TARGET_ICT_MODEL_LARGE
&& nds32_indirect_call_referenced_p (sym))
@@ -3091,7 +3091,7 @@ nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p)
{
rtx addr = XEXP (rtl, 0);
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
{
/* For (mem (symbol_ref X)) case. */
SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA;
@@ -3104,7 +3104,7 @@ nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p)
rtx op0 = XEXP (plus_op, 0);
rtx op1 = XEXP (plus_op, 1);
- if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1))
+ if (SYMBOL_REF_P (op0) && CONST_INT_P (op1))
SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA;
}
}
diff --git a/gcc/config/nds32/nds32.h b/gcc/config/nds32/nds32.h
index 1a8a6675bba..0a9a69f8536 100644
--- a/gcc/config/nds32/nds32.h
+++ b/gcc/config/nds32/nds32.h
@@ -1491,7 +1491,7 @@ enum reg_class
#define PIC_OFFSET_TABLE_REGNUM GP_REGNUM
#define SYMBOLIC_CONST_P(X) \
-(GET_CODE (X) == SYMBOL_REF \
+(SYMBOL_REF_P (X) \
|| LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
diff --git a/gcc/config/nios2/nios2.c b/gcc/config/nios2/nios2.c
index d2a85d0ad6f..e19b3823b44 100644
--- a/gcc/config/nios2/nios2.c
+++ b/gcc/config/nios2/nios2.c
@@ -562,7 +562,7 @@ nios2_emit_stack_limit_check (int size)
{
rtx sum = NULL_RTX;
- if (GET_CODE (stack_limit_rtx) == SYMBOL_REF)
+ if (SYMBOL_REF_P (stack_limit_rtx))
{
/* This generates a %hiadj/%lo pair with the constant size
add handled by the relocations. */
@@ -1362,7 +1362,7 @@ nios2_option_override (void)
if (flag_pic && !TARGET_LINUX_ABI)
sorry ("position-independent code requires the Linux ABI");
if (flag_pic && stack_limit_rtx
- && GET_CODE (stack_limit_rtx) == SYMBOL_REF)
+ && SYMBOL_REF_P (stack_limit_rtx))
sorry ("PIC support for %<-fstack-limit-symbol%>");
/* Function to allocate machine-dependent function status. */
@@ -2078,7 +2078,7 @@ nios2_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
{
rtx base, offset;
split_const (x, &base, &offset);
- return GET_CODE (base) != SYMBOL_REF || !SYMBOL_REF_TLS_MODEL (base);
+ return !SYMBOL_REF_P (base) || !SYMBOL_REF_TLS_MODEL (base);
}
/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */
@@ -2395,7 +2395,7 @@ nios2_symbol_ref_in_small_data_p (rtx sym)
{
tree decl;
- gcc_assert (GET_CODE (sym) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (sym));
decl = SYMBOL_REF_DECL (sym);
/* TLS variables are not accessed through the GP. */
@@ -2469,7 +2469,7 @@ nios2_symbol_ref_in_r0rel_data_p (rtx sym)
{
tree decl;
- gcc_assert (GET_CODE (sym) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (sym));
decl = SYMBOL_REF_DECL (sym);
/* TLS variables are not accessed through r0. */
@@ -2532,7 +2532,7 @@ static rtx
nios2_load_pic_address (rtx sym, int unspec, rtx tmp)
{
if (flag_pic == 2
- && GET_CODE (sym) == SYMBOL_REF
+ && SYMBOL_REF_P (sym)
&& nios2_symbol_binds_local_p (sym))
/* Under -fPIC, generate a GOTOFF address for local symbols. */
{
@@ -2553,7 +2553,7 @@ nios2_legitimate_pic_operand_p (rtx x)
if (nios2_large_unspec_reloc_p (x))
return true;
- return ! (GET_CODE (x) == SYMBOL_REF
+ return ! (SYMBOL_REF_P (x)
|| LABEL_REF_P (x) || GET_CODE (x) == CONST);
}
@@ -2561,7 +2561,7 @@ nios2_legitimate_pic_operand_p (rtx x)
static bool
nios2_tls_symbol_p (rtx x)
{
- return (targetm.have_tls && GET_CODE (x) == SYMBOL_REF
+ return (targetm.have_tls && SYMBOL_REF_P (x)
&& SYMBOL_REF_TLS_MODEL (x) != 0);
}
@@ -3075,7 +3075,7 @@ nios2_print_operand (FILE *file, rtx op, int letter)
bool
gprel_constant_p (rtx op)
{
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
&& nios2_symbol_ref_in_small_data_p (op))
return true;
else if (GET_CODE (op) == CONST
@@ -3089,7 +3089,7 @@ gprel_constant_p (rtx op)
bool
r0rel_constant_p (rtx op)
{
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
&& nios2_symbol_ref_in_r0rel_data_p (op))
return true;
else if (GET_CODE (op) == CONST
diff --git a/gcc/config/nvptx/nvptx.c b/gcc/config/nvptx/nvptx.c
index 07180eaad07..9fd8dc3270a 100644
--- a/gcc/config/nvptx/nvptx.c
+++ b/gcc/config/nvptx/nvptx.c
@@ -1636,7 +1636,7 @@ nvptx_expand_call (rtx retval, rtx address)
address = change_address (address, QImode, callee);
}
- if (GET_CODE (callee) == SYMBOL_REF)
+ if (SYMBOL_REF_P (callee))
{
tree decl = SYMBOL_REF_DECL (callee);
if (decl != NULL_TREE)
@@ -2059,7 +2059,7 @@ nvptx_assemble_integer (rtx x, unsigned int size, int ARG_UNUSED (aligned_p))
gcc_assert (GET_CODE (x) == PLUS);
val = INTVAL (XEXP (x, 1));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
/* FALLTHROUGH */
case SYMBOL_REF:
@@ -2375,7 +2375,7 @@ nvptx_output_call_insn (rtx_insn *insn, rtx result, rtx callee)
reg_names[NVPTX_RETURN_REGNUM]);
/* Ensure we have a ptx declaration in the output if necessary. */
- if (GET_CODE (callee) == SYMBOL_REF)
+ if (SYMBOL_REF_P (callee))
{
decl = SYMBOL_REF_DECL (callee);
if (!decl
@@ -2565,7 +2565,7 @@ nvptx_print_operand (FILE *file, rtx x, int code)
if (GET_CODE (x) == PLUS)
x = XEXP (x, 0);
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
fputs (section_for_sym (x), file);
break;
@@ -2909,7 +2909,7 @@ nvptx_call_insn_is_syscall_p (rtx_insn *insn)
gcc_checking_assert (GET_CODE (pat) == CALL
&& MEM_P (XEXP (pat, 0)));
rtx addr = XEXP (XEXP (pat, 0), 0);
- if (GET_CODE (addr) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (addr))
return false;
const char *name = XSTR (addr, 0);
/* Ordinary malloc/free are redirected to __nvptx_{malloc,free), so only the
diff --git a/gcc/config/or1k/or1k.c b/gcc/config/or1k/or1k.c
index f8eed4a7797..26062c87b87 100644
--- a/gcc/config/or1k/or1k.c
+++ b/gcc/config/or1k/or1k.c
@@ -1502,7 +1502,7 @@ or1k_expand_call (rtx retval, rtx fnaddr, rtx callarg1, bool sibcall)
/* Calls via the PLT require the PIC register. */
if (flag_pic
- && GET_CODE (XEXP (fnaddr, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (fnaddr, 0))
&& !SYMBOL_REF_LOCAL_P (XEXP (fnaddr, 0)))
{
crtl->uses_pic_offset_table = 1;
diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 418dfc8c8f4..56fce41cdb6 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -830,7 +830,7 @@ legitimize_pic_address (rtx orig, machine_mode mode, rtx reg)
crtl->uses_pic_offset_table = 1;
return reg;
}
- if (GET_CODE (orig) == SYMBOL_REF)
+ if (SYMBOL_REF_P (orig))
{
rtx_insn *insn;
rtx tmp_reg;
@@ -941,7 +941,7 @@ legitimize_tls_address (rtx addr)
rtx_insn *insn;
/* Currently, we can't handle anything but a SYMBOL_REF. */
- if (GET_CODE (addr) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (addr))
return addr;
switch (SYMBOL_REF_TLS_MODEL (addr))
@@ -1102,7 +1102,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
That should always be safe. */
if (GET_CODE (x) == PLUS
&& REG_P (XEXP (x, 0))
- && GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (x, 1)))
{
rtx reg = force_reg (Pmode, XEXP (x, 1));
return force_reg (Pmode, gen_rtx_PLUS (Pmode, reg, XEXP (x, 0)));
@@ -1112,7 +1112,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
since the assembler/linker can't handle arithmetic on plabels. */
if (GET_CODE (x) == PLUS
&& CONST_INT_P (XEXP (x, 1))
- && ((GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && ((SYMBOL_REF_P (XEXP (x, 0))
&& !FUNCTION_NAME_P (XSTR (XEXP (x, 0), 0)))
|| REG_P (XEXP (x, 0))))
{
@@ -1138,7 +1138,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
handle 4->2 or 5->2 combinations, so do not create
them. */
if (! VAL_14_BITS_P (newoffset)
- && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (x, 0)))
{
rtx const_part = plus_constant (Pmode, XEXP (x, 0), newoffset);
rtx tmp_reg
@@ -1355,7 +1355,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
If const_int is big, but can be divided evenly by shadd_const
and added to (reg). This allows more scaled indexed addresses. */
- if (GET_CODE (XEXP (y, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (y, 0))
&& mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
&& CONST_INT_P (XEXP (y, 1))
&& INTVAL (XEXP (y, 1)) >= -4096
@@ -1387,7 +1387,7 @@ hppa_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
reg1));
}
else if ((mode == DFmode || mode == SFmode)
- && GET_CODE (XEXP (y, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (y, 0))
&& mem_shadd_or_shadd_rtx_p (XEXP (x, 0))
&& CONST_INT_P (XEXP (y, 1))
&& INTVAL (XEXP (y, 1)) % (1 << INTVAL (XEXP (XEXP (x, 0), 1))) == 0)
@@ -2166,7 +2166,7 @@ pa_emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg)
tmp = XEXP (XEXP (tmp, 0), 0);
}
- gcc_assert (GET_CODE (tmp) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (tmp));
tmp = legitimize_tls_address (tmp);
if (addend)
{
@@ -3327,7 +3327,7 @@ pa_assemble_integer (rtx x, unsigned int size, int aligned_p)
calling output_addr_const. Otherwise, it may call assemble_external
in the midst of outputing the assembler code for the SYMBOL_REF.
We restore the SYMBOL_REF_DECL after the output is done. */
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
decl = SYMBOL_REF_DECL (x);
if (decl)
@@ -5496,9 +5496,9 @@ pa_output_global_address (FILE *file, rtx x, int round_constant)
if (GET_CODE (x) == HIGH)
x = XEXP (x, 0);
- if (GET_CODE (x) == SYMBOL_REF && read_only_operand (x, VOIDmode))
+ if (SYMBOL_REF_P (x) && read_only_operand (x, VOIDmode))
output_addr_const (file, x);
- else if (GET_CODE (x) == SYMBOL_REF && !flag_pic)
+ else if (SYMBOL_REF_P (x) && !flag_pic)
{
output_addr_const (file, x);
fputs ("-$global$", file);
@@ -5562,7 +5562,7 @@ pa_output_global_address (FILE *file, rtx x, int round_constant)
break;
case MINUS:
- gcc_assert (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0)));
sep = "-";
break;
@@ -8320,7 +8320,7 @@ pa_encode_section_info (tree decl, rtx rtl, int first)
{
int old_referenced = 0;
- if (!first && MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF)
+ if (!first && MEM_P (rtl) && SYMBOL_REF_P (XEXP (rtl, 0)))
old_referenced
= SYMBOL_REF_FLAGS (XEXP (rtl, 0)) & SYMBOL_FLAG_REFERENCED;
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index b6b7ed17a5c..ae0b65c1e39 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -758,7 +758,7 @@ extern int may_call_alloca;
/* TLS symbolic reference. */
#define PA_SYMBOL_REF_TLS_P(X) \
- (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0)
+ (SYMBOL_REF_P (X) && SYMBOL_REF_TLS_MODEL (X) != 0)
/* Recognize any constant value that is a valid address except
for symbolic addresses. We get better CSE by rejecting them
@@ -767,7 +767,7 @@ extern int may_call_alloca;
#define CONSTANT_ADDRESS_P(X) \
((LABEL_REF_P (X) \
- || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
+ || (SYMBOL_REF_P (X) && !SYMBOL_REF_TLS_MODEL (X)) \
|| CONST_INT_P (X) \
|| (GET_CODE (X) == CONST && !tls_referenced_p (X)) \
|| GET_CODE (X) == HIGH) \
diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md
index 5f7c45053cf..8d0139120c4 100644
--- a/gcc/config/pa/pa.md
+++ b/gcc/config/pa/pa.md
@@ -7069,7 +7069,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
op = XEXP (operands[0], 0);
/* Generate indirect long calls to non-local functions. */
- if (TARGET_LONG_CALLS && GET_CODE (op) == SYMBOL_REF)
+ if (TARGET_LONG_CALLS && SYMBOL_REF_P (op))
{
tree call_decl = SYMBOL_REF_DECL (op);
if (!(call_decl && targetm.binds_local_p (call_decl)))
@@ -7133,7 +7133,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
if (TARGET_64BIT)
{
rtx r4 = gen_rtx_REG (word_mode, 4);
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
emit_call_insn (gen_call_symref_64bit (op, nb, r4));
else
{
@@ -7143,7 +7143,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
}
else
{
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
{
if (flag_pic)
{
@@ -7563,7 +7563,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
else
{
op = XEXP (operands[1], 0);
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
{
/* Handle special call to buggy powf function. */
if (TARGET_HPUX && !TARGET_DISABLE_FPREGS && !TARGET_SOFT_FLOAT
@@ -7636,7 +7636,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
if (TARGET_64BIT)
{
rtx r4 = gen_rtx_REG (word_mode, 4);
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
{
if (call_powf)
emit_call_insn (gen_call_val_powf_64bit (dst, op, nb, r4));
@@ -7651,7 +7651,7 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
}
else
{
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
{
if (flag_pic)
{
diff --git a/gcc/config/pa/predicates.md b/gcc/config/pa/predicates.md
index a633a276509..17e37b88f35 100644
--- a/gcc/config/pa/predicates.md
+++ b/gcc/config/pa/predicates.md
@@ -520,7 +520,7 @@
{
if (GET_CODE (op) == CONST)
op = XEXP (XEXP (op, 0), 0);
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
{
if (flag_pic)
return SYMBOL_REF_FLAG (op) && !CONSTANT_POOL_ADDRESS_P (op);
@@ -628,7 +628,7 @@
case CONST:
op = XEXP (op, 0);
return (GET_CODE (op) == PLUS
- && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && ((SYMBOL_REF_P (XEXP (op, 0))
&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
|| LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index c885bb5f0eb..0c9c4b1af01 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -547,7 +547,7 @@ riscv_classify_symbol (const_rtx x)
if (riscv_tls_symbol_p (x))
return SYMBOL_TLS;
- if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x))
+ if (SYMBOL_REF_P (x) && flag_pic && !riscv_symbol_binds_local_p (x))
return SYMBOL_GOT_DISP;
return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL;
@@ -581,7 +581,7 @@ riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type)
*symbol_type = UNSPEC_ADDRESS_TYPE (x);
x = UNSPEC_ADDRESS (x);
}
- else if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
+ else if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
*symbol_type = riscv_classify_symbol (x);
else
return false;
diff --git a/gcc/config/rl78/constraints.md b/gcc/config/rl78/constraints.md
index e660628df47..21be6ac775f 100644
--- a/gcc/config/rl78/constraints.md
+++ b/gcc/config/rl78/constraints.md
@@ -226,7 +226,7 @@
"[addr]"
(and (match_code "mem")
(ior (match_test "CONSTANT_P (XEXP (op, 0))")
- (match_test "GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF"))
+ (match_test "GET_CODE (XEXP (op, 0)) == PLUS && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))"))
)
)
(define_memory_constraint "Wab"
@@ -413,5 +413,5 @@
(define_constraint "Qs8"
"Integer constant computed from (SUBREG (SYMREF))."
(and (match_code "subreg")
- (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF"))
+ (match_test "SYMBOL_REF_P (XEXP (op, 0))"))
)
diff --git a/gcc/config/rl78/rl78-expand.md b/gcc/config/rl78/rl78-expand.md
index 3706a8c01f6..ea5a0b46b61 100644
--- a/gcc/config/rl78/rl78-expand.md
+++ b/gcc/config/rl78/rl78-expand.md
@@ -35,7 +35,7 @@
provided that the destination is a register. If not, then load the
source into a register first. */
if (SUBREG_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (operands[1], 0))
&& ! REG_P (operands[0]))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
@@ -44,7 +44,7 @@
if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == CONST
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (XEXP (operands[1], 0), 0), 0))
&& ! REG_P (operands[0]))
operands[1] = copy_to_mode_reg (QImode, operands[1]);
@@ -66,13 +66,13 @@
/* FIXME: Not sure how GCC can generate (SUBREG (SYMBOL_REF)),
but it does. Since this makes no sense, reject it here. */
if (SUBREG_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (operands[1], 0)))
FAIL;
/* Similarly for (SUBREG (CONST (PLUS (SYMBOL_REF)))). */
if (SUBREG_P (operands[1])
&& GET_CODE (XEXP (operands[1], 0)) == CONST
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (XEXP (operands[1], 0), 0), 0)))
FAIL;
}
)
diff --git a/gcc/config/rl78/rl78.c b/gcc/config/rl78/rl78.c
index a667ac8f543..4559c5a4780 100644
--- a/gcc/config/rl78/rl78.c
+++ b/gcc/config/rl78/rl78.c
@@ -538,7 +538,7 @@ rl78_expand_movsi (rtx *operands)
op00 = rl78_subreg (HImode, operands[0], SImode, 0);
op02 = rl78_subreg (HImode, operands[0], SImode, 2);
if (GET_CODE (operands[1]) == CONST
- || GET_CODE (operands[1]) == SYMBOL_REF)
+ || SYMBOL_REF_P (operands[1]))
{
op10 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (0));
op10 = gen_rtx_CONST (HImode, op10);
@@ -575,7 +575,7 @@ rl78_split_movsi (rtx *operands, machine_mode omode)
op02 = rl78_subreg (HImode, operands[0], omode, 2);
if (GET_CODE (operands[1]) == CONST
- || GET_CODE (operands[1]) == SYMBOL_REF)
+ || SYMBOL_REF_P (operands[1]))
{
op10 = gen_rtx_ZERO_EXTRACT (HImode, operands[1], GEN_INT (16), GEN_INT (0));
op10 = gen_rtx_CONST (HImode, op10);
@@ -939,7 +939,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
/* We sometimes get these without the CONST wrapper */
if (GET_CODE (x) == PLUS
- && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (x, 0))
&& CONST_INT_P (XEXP (x, 1)))
{
*addend = x;
@@ -985,7 +985,7 @@ characterize_address (rtx x, rtx *base, rtx *index, rtx *addend)
switch (GET_CODE (x))
{
case PLUS:
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONST_INT_P (XEXP (x, 0)))
{
*addend = x;
@@ -1232,7 +1232,7 @@ rl78_addr_space_convert (rtx op, tree from_type, tree to_type)
warning (OPT_Waddress, "converting far pointer to near pointer");
result = gen_reg_rtx (HImode);
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
|| (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER))
tmp = gen_rtx_raw_SUBREG (HImode, op, 0);
else
@@ -1866,7 +1866,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
rl78_print_operand_1 (file, XEXP (op, 0), letter);
}
else if (GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (op, 0), 0)))
{
if (!rl78_saddr_p (op))
fprintf (file, "!");
@@ -2010,7 +2010,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
if (GET_CODE (XEXP (op, 0)) == ZERO_EXTEND)
{
- if (GET_CODE (XEXP (op, 1)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (op, 1))
&& SYMBOL_REF_DECL (XEXP (op, 1))
&& TREE_CODE (SYMBOL_REF_DECL (XEXP (op, 1))) == FUNCTION_DECL)
{
@@ -2029,7 +2029,7 @@ rl78_print_operand_1 (FILE * file, rtx op, int letter)
}
else
{
- if (GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (op, 0))
&& SYMBOL_REF_DECL (XEXP (op, 0))
&& TREE_CODE (SYMBOL_REF_DECL (XEXP (op, 0))) == FUNCTION_DECL)
{
@@ -2848,7 +2848,7 @@ rl78_lo16 (rtx addr)
{
rtx r;
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
|| GET_CODE (addr) == CONST)
{
r = gen_rtx_ZERO_EXTRACT (HImode, addr, GEN_INT (16), GEN_INT (0));
@@ -2867,7 +2867,7 @@ rl78_lo16 (rtx addr)
static rtx
rl78_hi8 (rtx addr)
{
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
|| GET_CODE (addr) == CONST)
{
rtx r = gen_rtx_ZERO_EXTRACT (QImode, addr, GEN_INT (8), GEN_INT (16));
@@ -4469,7 +4469,7 @@ rl78_saddr_p (rtx x)
x = XEXP (x, 0);
if (GET_CODE (x) == PLUS)
x = XEXP (x, 0);
- if (GET_CODE (x) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (x))
return 0;
c = XSTR (x, 0);
@@ -4565,10 +4565,10 @@ rl78_encode_section_info (tree decl, rtx rtl, int first)
rtlname = XEXP (rtl, 0);
- if (GET_CODE (rtlname) == SYMBOL_REF)
+ if (SYMBOL_REF_P (rtlname))
oldname = XSTR (rtlname, 0);
else if (MEM_P (rtlname)
- && GET_CODE (XEXP (rtlname, 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (rtlname, 0)))
oldname = XSTR (XEXP (rtlname, 0), 0);
else
gcc_unreachable ();
@@ -4891,7 +4891,7 @@ rl78_addsi3_internal (rtx * operands, unsigned int alternative)
that it is invalid to access anything above 64K relative to
this address. So we can skip adding in the high bytes. */
if (TARGET_ES0
- && GET_CODE (operands[2]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[2])
&& TREE_CODE (SYMBOL_REF_DECL (operands[2])) == VAR_DECL
&& TREE_READONLY (SYMBOL_REF_DECL (operands[2]))
&& ! TREE_SIDE_EFFECTS (SYMBOL_REF_DECL (operands[2])))
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index facc468ec7c..0ce89c5878c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -24168,7 +24168,7 @@ rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
/* Handle longcall attributes. */
is_pltseq_longcall = false;
if ((INTVAL (cookie) & CALL_LONG) != 0
- && GET_CODE (func_desc) == SYMBOL_REF)
+ && SYMBOL_REF_P (func_desc))
{
func = rs6000_longcall_ref (func_desc, tlsarg);
if (TARGET_PLTSEQ)
@@ -24268,7 +24268,7 @@ rs6000_call_aix (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
originally direct, the 3rd word has not been written since no
trampoline has been built, so we ought not to load it, lest we
override a static chain value. */
- if (!(GET_CODE (func_desc) == SYMBOL_REF
+ if (!(SYMBOL_REF_P (func_desc)
&& SYMBOL_REF_FUNCTION_P (func_desc))
&& TARGET_POINTERS_TO_NESTED_FUNCTIONS
&& !chain_already_loaded (get_current_sequence ()->next->last))
@@ -24362,7 +24362,7 @@ rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
/* Handle longcall attributes. */
if ((INTVAL (cookie) & CALL_LONG) != 0
- && GET_CODE (func_desc) == SYMBOL_REF)
+ && SYMBOL_REF_P (func_desc))
{
func = rs6000_longcall_ref (func_desc, tlsarg);
/* If the longcall was implemented as an inline PLT call using
@@ -24378,7 +24378,7 @@ rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
}
/* Handle indirect calls. */
- if (GET_CODE (func) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (func))
{
func = force_reg (Pmode, func);
@@ -24411,7 +24411,7 @@ rs6000_call_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
n = 2;
if (TARGET_SECURE_PLT
&& flag_pic
- && GET_CODE (func_addr) == SYMBOL_REF
+ && SYMBOL_REF_P (func_addr)
&& !SYMBOL_REF_LOCAL_P (func_addr))
call[n++] = gen_rtx_USE (VOIDmode, pic_offset_table_rtx);
@@ -24439,7 +24439,7 @@ rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
/* Handle longcall attributes. */
if ((INTVAL (cookie) & CALL_LONG) != 0
- && GET_CODE (func_desc) == SYMBOL_REF)
+ && SYMBOL_REF_P (func_desc))
{
func = rs6000_longcall_ref (func_desc, tlsarg);
/* If the longcall was implemented as an inline PLT call using
@@ -24455,7 +24455,7 @@ rs6000_sibcall_sysv (rtx value, rtx func_desc, rtx tlsarg, rtx cookie)
}
/* Handle indirect calls. */
- if (GET_CODE (func) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (func))
{
func = force_reg (Pmode, func);
@@ -24521,7 +24521,7 @@ rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
If we're going to use this, then we need to keep the CALL_LONG bit set,
so that we can pick up the special insn form later. */
if ((cookie_val & CALL_LONG) != 0
- && GET_CODE (func_desc) == SYMBOL_REF)
+ && SYMBOL_REF_P (func_desc))
{
/* FIXME: the longcall opt should not hang off picsymbol stubs. */
if (darwin_picsymbol_stubs && TARGET_32BIT)
@@ -24536,7 +24536,7 @@ rs6000_call_darwin_1 (rtx value, rtx func_desc, rtx tlsarg,
}
/* Handle indirect calls. */
- if (GET_CODE (func) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (func))
{
func = force_reg (Pmode, func);
diff --git a/gcc/config/rx/constraints.md b/gcc/config/rx/constraints.md
index c252dc49bc4..a18031568b7 100644
--- a/gcc/config/rx/constraints.md
+++ b/gcc/config/rx/constraints.md
@@ -21,7 +21,7 @@
(define_constraint "Symbol"
"@internal Constraint on the type of rtx allowed in call insns"
- (match_test "GET_CODE (op) == SYMBOL_REF")
+ (match_test "SYMBOL_REF_P (op)")
)
diff --git a/gcc/config/rx/rx.c b/gcc/config/rx/rx.c
index b8d182e5944..02c6774ca00 100644
--- a/gcc/config/rx/rx.c
+++ b/gcc/config/rx/rx.c
@@ -86,7 +86,7 @@ rx_decl_for_addr (rtx op)
op = XEXP (op, 0);
while (GET_CODE (op) == PLUS)
op = XEXP (op, 0);
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return SYMBOL_REF_DECL (op);
return NULL_TREE;
}
@@ -135,7 +135,7 @@ rx_pid_data_operand (rtx op)
else
{
/* Sigh, some special cases. */
- if (GET_CODE (op) == SYMBOL_REF
+ if (SYMBOL_REF_P (op)
|| LABEL_REF_P (op))
return PID_UNENCODED;
}
@@ -171,7 +171,7 @@ rx_small_data_operand (rtx op)
if (rx_small_data_limit == 0)
return false;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return SYMBOL_REF_SMALL_P (op);
return false;
diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c
index 6f85090f2ce..656a6d17920 100644
--- a/gcc/config/s390/s390.c
+++ b/gcc/config/s390/s390.c
@@ -2966,7 +2966,7 @@ s390_decompose_address (rtx addr, struct s390_address *out)
/* We can convert literal pool addresses to
displacements by basing them off the base register. */
- if (disp && GET_CODE (disp) == SYMBOL_REF && CONSTANT_POOL_ADDRESS_P (disp))
+ if (disp && SYMBOL_REF_P (disp) && CONSTANT_POOL_ADDRESS_P (disp))
{
if (base || indx)
return false;
@@ -3053,7 +3053,7 @@ s390_decompose_address (rtx addr, struct s390_address *out)
zarch CPUs. In this case the literal pool contains an lt
relative offset to the _GLOBAL_OFFSET_TABLE_ label which
will most likely exceed the displacement. */
- if (GET_CODE (XVECEXP (disp, 0, 0)) != SYMBOL_REF
+ if (!SYMBOL_REF_P (XVECEXP (disp, 0, 0))
|| !CONSTANT_POOL_ADDRESS_P (XVECEXP (disp, 0, 0)))
return false;
@@ -3226,7 +3226,7 @@ s390_loadrelative_operand_p (rtx addr, rtx *symref, HOST_WIDE_INT *addend)
addr = XEXP (addr, 0);
}
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
|| (GET_CODE (addr) == UNSPEC
&& (XINT (addr, 1) == UNSPEC_GOTENT
|| XINT (addr, 1) == UNSPEC_PLT)))
@@ -3931,7 +3931,7 @@ s390_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
int
tls_symbolic_operand (rtx op)
{
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return 0;
return SYMBOL_REF_TLS_MODEL (op);
}
@@ -3961,7 +3961,7 @@ symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF || LABEL_REF_P (op))
+ if (SYMBOL_REF_P (op) || LABEL_REF_P (op))
return 1;
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -3991,7 +3991,7 @@ tls_symbolic_reference_mentioned_p (rtx op)
const char *fmt;
int i;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return tls_symbolic_operand (op);
fmt = GET_RTX_FORMAT (GET_CODE (op));
@@ -4285,7 +4285,7 @@ s390_preferred_reload_class (rtx op, reg_class_t rclass)
they are used as literal pool slot replacement in reload
inheritance (see emit_input_reload_insns). */
if (GET_CODE (XEXP (op, 0)) == PLUS
- && GET_CODE (XEXP (XEXP(op, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP(op, 0), 0))
&& CONST_INT_P (XEXP (XEXP(op, 0), 1)))
{
if (flag_pic && reg_class_subset_p (ADDR_REGS, rclass))
@@ -4335,7 +4335,7 @@ s390_check_symref_alignment (rtx addr, HOST_WIDE_INT alignment)
if (addend & (alignment - 1))
return false;
- if (GET_CODE (symref) == SYMBOL_REF)
+ if (SYMBOL_REF_P (symref))
{
/* s390_encode_section_info is not called for anchors, since they don't
have corresponding VAR_DECLs. Therefore, we cannot rely on
@@ -4955,7 +4955,7 @@ legitimize_pic_address (rtx orig, rtx reg)
}
}
}
- else if (GET_CODE (addr) == SYMBOL_REF && addend == const0_rtx)
+ else if (SYMBOL_REF_P (addr) && addend == const0_rtx)
{
/* A non-local symbol reference without addend.
@@ -5133,7 +5133,7 @@ legitimize_tls_address (rtx addr, rtx reg)
rtx new_rtx, tls_call, temp, base, r2;
rtx_insn *insn;
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
switch (tls_symbolic_operand (addr))
{
case TLS_MODEL_GLOBAL_DYNAMIC:
@@ -5267,7 +5267,7 @@ legitimize_tls_address (rtx addr, rtx reg)
&& CONST_INT_P (XEXP (XEXP (addr, 0), 1)))
{
new_rtx = XEXP (XEXP (addr, 0), 0);
- if (GET_CODE (new_rtx) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (new_rtx))
new_rtx = gen_rtx_CONST (Pmode, new_rtx);
new_rtx = legitimize_tls_address (new_rtx, reg);
@@ -7863,7 +7863,7 @@ print_operand (FILE *file, rtx x, int code)
return;
case 'J':
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
fprintf (file, "%s", ":tls_load:");
output_addr_const (file, x);
@@ -8328,7 +8328,7 @@ annotate_constant_pool_refs_1 (rtx *x)
int i, j;
const char *fmt;
- gcc_assert (GET_CODE (*x) != SYMBOL_REF
+ gcc_assert (!SYMBOL_REF_P (*x)
|| !CONSTANT_POOL_ADDRESS_P (*x));
/* Literal pool references can only occur inside a MEM ... */
@@ -8336,7 +8336,7 @@ annotate_constant_pool_refs_1 (rtx *x)
{
rtx memref = XEXP (*x, 0);
- if (GET_CODE (memref) == SYMBOL_REF
+ if (SYMBOL_REF_P (memref)
&& CONSTANT_POOL_ADDRESS_P (memref))
{
rtx base = cfun->machine->base_reg;
@@ -8350,7 +8350,7 @@ annotate_constant_pool_refs_1 (rtx *x)
if (GET_CODE (memref) == CONST
&& GET_CODE (XEXP (memref, 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (memref, 0), 1))
- && GET_CODE (XEXP (XEXP (memref, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (memref, 0), 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (memref, 0), 0)))
{
HOST_WIDE_INT off = INTVAL (XEXP (XEXP (memref, 0), 1));
@@ -8369,7 +8369,7 @@ annotate_constant_pool_refs_1 (rtx *x)
{
rtx addrref = SET_SRC (*x);
- if (GET_CODE (addrref) == SYMBOL_REF
+ if (SYMBOL_REF_P (addrref)
&& CONSTANT_POOL_ADDRESS_P (addrref))
{
rtx base = cfun->machine->base_reg;
@@ -8383,7 +8383,7 @@ annotate_constant_pool_refs_1 (rtx *x)
if (GET_CODE (addrref) == CONST
&& GET_CODE (XEXP (addrref, 0)) == PLUS
&& CONST_INT_P (XEXP (XEXP (addrref, 0), 1))
- && GET_CODE (XEXP (XEXP (addrref, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (addrref, 0), 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (XEXP (addrref, 0), 0)))
{
HOST_WIDE_INT off = INTVAL (XEXP (XEXP (addrref, 0), 1));
@@ -8436,13 +8436,13 @@ find_constant_pool_ref_1 (rtx x, rtx *ref)
&& XINT (x, 1) == UNSPECV_POOL_ENTRY)
return;
- gcc_assert (GET_CODE (x) != SYMBOL_REF
+ gcc_assert (!SYMBOL_REF_P (x)
|| !CONSTANT_POOL_ADDRESS_P (x));
if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_LTREF)
{
rtx sym = XVECEXP (x, 0, 0);
- gcc_assert (GET_CODE (sym) == SYMBOL_REF
+ gcc_assert (SYMBOL_REF_P (sym)
&& CONSTANT_POOL_ADDRESS_P (sym));
if (*ref == NULL_RTX)
@@ -12915,7 +12915,7 @@ s390_encode_section_info (tree decl, rtx rtl, int first)
differently here. We rely on the information in the MEM_ALIGN
entry to decide upon the alignment. */
if (MEM_P (rtl)
- && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (rtl, 0))
&& TREE_CONSTANT_POOL_ADDRESS_P (XEXP (rtl, 0)))
{
if (MEM_ALIGN (rtl) == 0 || MEM_ALIGN (rtl) % 16)
@@ -13456,7 +13456,7 @@ s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
int i;
/* Direct function calls need special treatment. */
- if (GET_CODE (addr_location) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr_location))
{
/* When calling a global routine in PIC mode, we must
replace the symbol itself with the PLT stub. */
@@ -13488,7 +13488,7 @@ s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
SYMBOL_REF to somewhere else make sure the address can be found in
register 1. */
if (retaddr_reg == NULL_RTX
- && GET_CODE (addr_location) != SYMBOL_REF
+ && !SYMBOL_REF_P (addr_location)
&& !plt_call)
{
emit_move_insn (gen_rtx_REG (Pmode, SIBCALL_REGNUM), addr_location);
@@ -13496,7 +13496,7 @@ s390_emit_call (rtx addr_location, rtx tls_call, rtx result_reg,
}
if (TARGET_INDIRECT_BRANCH_NOBP_CALL
- && GET_CODE (addr_location) != SYMBOL_REF
+ && !SYMBOL_REF_P (addr_location)
&& !plt_call)
{
/* Indirect branch thunks require the target to be a single GPR. */
diff --git a/gcc/config/s390/s390.h b/gcc/config/s390/s390.h
index adf64951258..4e5ec0f8305 100644
--- a/gcc/config/s390/s390.h
+++ b/gcc/config/s390/s390.h
@@ -807,12 +807,12 @@ CUMULATIVE_ARGS;
/* Helper macro for s390.c and s390.md to check for symbolic constants. */
#define SYMBOLIC_CONST(X) \
- (GET_CODE (X) == SYMBOL_REF \
+ (SYMBOL_REF_P (X) \
|| LABEL_REF_P (X) \
|| (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X)))
#define TLS_SYMBOLIC_CONST(X) \
- ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \
+ ((SYMBOL_REF_P (X) && tls_symbolic_operand (X)) \
|| (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X)))
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index 3305d9fdf73..0bc49be5428 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -1968,7 +1968,7 @@
(mem:DI (match_operand 1 "address_operand" "")))]
"TARGET_ZARCH
&& !FP_REG_P (operands[0])
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& get_pool_mode (operands[1]) == DImode
&& legitimate_reload_constant_p (get_pool_constant (operands[1]))"
@@ -2162,7 +2162,7 @@
[(set (match_operand:SI 0 "register_operand" "")
(mem:SI (match_operand 1 "address_operand" "")))]
"!FP_REG_P (operands[0])
- && GET_CODE (operands[1]) == SYMBOL_REF
+ && SYMBOL_REF_P (operands[1])
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& get_pool_mode (operands[1]) == SImode
&& legitimate_reload_constant_p (get_pool_constant (operands[1]))"
@@ -2304,7 +2304,7 @@
(define_peephole2
[(set (match_operand:HI 0 "register_operand" "")
(mem:HI (match_operand 1 "address_operand" "")))]
- "GET_CODE (operands[1]) == SYMBOL_REF
+ "SYMBOL_REF_P (operands[1])
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& get_pool_mode (operands[1]) == HImode
&& CONST_INT_P (get_pool_constant (operands[1]))"
@@ -2369,7 +2369,7 @@
(define_peephole2
[(set (match_operand:QI 0 "nonimmediate_operand" "")
(mem:QI (match_operand 1 "address_operand" "")))]
- "GET_CODE (operands[1]) == SYMBOL_REF
+ "SYMBOL_REF_P (operands[1])
&& CONSTANT_POOL_ADDRESS_P (operands[1])
&& get_pool_mode (operands[1]) == QImode
&& CONST_INT_P (get_pool_constant (operands[1]))"
diff --git a/gcc/config/sh/sh.c b/gcc/config/sh/sh.c
index 2d1bd801851..50f561f63eb 100644
--- a/gcc/config/sh/sh.c
+++ b/gcc/config/sh/sh.c
@@ -1795,7 +1795,7 @@ prepare_move_operands (rtx operands[], machine_mode mode)
rtx base, offset;
split_const (operands[1], &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF
+ if (SYMBOL_REF_P (base)
&& !offset_within_block_p (base, INTVAL (offset)))
{
rtx tmp = can_create_pseudo_p () ? gen_reg_rtx (mode) : operands[0];
@@ -2840,7 +2840,7 @@ static bool
sh_assemble_integer (rtx value, unsigned int size, int aligned_p)
{
if (TARGET_FDPIC && size == UNITS_PER_WORD
- && GET_CODE (value) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (value))
+ && SYMBOL_REF_P (value) && SYMBOL_REF_FUNCTION_P (value))
{
fputs ("\t.long\t", asm_out_file);
output_addr_const (asm_out_file, value);
@@ -5987,7 +5987,7 @@ sh_reorg (void)
being set to a symbol. In theory, we could sometimes
optimize calls to a constant location, but the assembler
and linker do not support that at present. */
- if (GET_CODE (SET_SRC (set)) != SYMBOL_REF
+ if (!SYMBOL_REF_P (SET_SRC (set))
&& !LABEL_REF_P (SET_SRC (set)))
continue;
@@ -8511,7 +8511,7 @@ sh2a_handle_function_vector_handler_attribute (tree * node, tree name,
bool
sh2a_is_function_vector_call (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
{
tree tr = SYMBOL_REF_DECL (x);
@@ -8528,7 +8528,7 @@ sh2a_is_function_vector_call (rtx x)
int
sh2a_get_function_vector_number (rtx x)
{
- if ((GET_CODE (x) == SYMBOL_REF)
+ if ((SYMBOL_REF_P (x))
&& (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_FUNCVEC_FUNCTION))
{
tree t = SYMBOL_REF_DECL (x);
@@ -8729,7 +8729,7 @@ fp_one_operand (rtx op)
enum tls_model
tls_symbolic_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED)
{
- if (GET_CODE (op) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (op))
return TLS_MODEL_NONE;
return SYMBOL_REF_TLS_MODEL (op);
}
@@ -9096,7 +9096,7 @@ sh_legitimate_address_p (machine_mode mode, rtx x, bool strict)
bool
nonpic_symbol_mentioned_p (rtx x)
{
- if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x)
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x)
|| GET_CODE (x) == PC)
return true;
@@ -9146,13 +9146,13 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
return orig;
if (LABEL_REF_P (orig)
- || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig)))
+ || (SYMBOL_REF_P (orig) && SYMBOL_REF_LOCAL_P (orig)))
{
if (reg == NULL_RTX)
reg = gen_reg_rtx (Pmode);
if (TARGET_FDPIC
- && GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (orig))
+ && SYMBOL_REF_P (orig) && SYMBOL_REF_FUNCTION_P (orig))
{
/* Weak functions may be NULL which doesn't work with
GOTOFFFUNCDESC because the runtime offset is not known. */
@@ -9163,7 +9163,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
}
else if (TARGET_FDPIC
&& (LABEL_REF_P (orig)
- || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_DECL (orig)
+ || (SYMBOL_REF_P (orig) && SYMBOL_REF_DECL (orig)
&& (TREE_READONLY (SYMBOL_REF_DECL (orig))
|| SYMBOL_REF_EXTERNAL_P (orig)
|| DECL_SECTION_NAME(SYMBOL_REF_DECL (orig))))))
@@ -9173,7 +9173,7 @@ legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, rtx reg)
emit_insn (gen_symGOTOFF2reg (reg, orig));
return reg;
}
- else if (GET_CODE (orig) == SYMBOL_REF)
+ else if (SYMBOL_REF_P (orig))
{
if (reg == NULL_RTX)
reg = gen_reg_rtx (Pmode);
@@ -11506,7 +11506,7 @@ sh_legitimate_constant_p (machine_mode mode, rtx x)
rtx base, offset;
split_const (x, &base, &offset);
- if (GET_CODE (base) == SYMBOL_REF
+ if (SYMBOL_REF_P (base)
&& !offset_within_block_p (base, INTVAL (offset)))
return false;
}
diff --git a/gcc/config/sh/sh.h b/gcc/config/sh/sh.h
index 4305398f9ff..d2515fe2dac 100644
--- a/gcc/config/sh/sh.h
+++ b/gcc/config/sh/sh.h
@@ -1406,12 +1406,12 @@ extern bool current_function_interrupt;
&& XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF)
#define NON_PIC_REFERENCE_P(OP) \
- (LABEL_REF_P (OP) || GET_CODE (OP) == SYMBOL_REF \
+ (LABEL_REF_P (OP) || SYMBOL_REF_P (OP) \
|| (GET_CODE (OP) == CONST \
&& (LABEL_REF_P (XEXP ((OP), 0)) \
- || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \
+ || SYMBOL_REF_P (XEXP ((OP), 0)))) \
|| (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \
- && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \
+ && (SYMBOL_REF_P (XEXP (XEXP ((OP), 0), 0)) \
|| LABEL_REF_P (XEXP (XEXP ((OP), 0), 0))) \
&& CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))
@@ -1590,12 +1590,12 @@ extern bool current_function_interrupt;
nor can we indirect via the constant pool. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
((! nonpic_symbol_mentioned_p (X) \
- && (GET_CODE (X) != SYMBOL_REF \
+ && (!SYMBOL_REF_P (X) \
|| ! CONSTANT_POOL_ADDRESS_P (X) \
|| ! nonpic_symbol_mentioned_p (get_pool_constant (X)))))
#define SYMBOLIC_CONST_P(X) \
-((GET_CODE (X) == SYMBOL_REF || LABEL_REF_P (X)) \
+((SYMBOL_REF_P (X) || LABEL_REF_P (X)) \
&& nonpic_symbol_mentioned_p (X))
\f
/* Compute extra cost of moving data between one register class
@@ -1880,7 +1880,7 @@ extern tree *sh_deferred_function_attributes_tail;
if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \
&& ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \
{ \
- gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \
+ gcc_assert (SYMBOL_REF_P (ADDR)); \
SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \
if (0) goto DONE; \
} \
@@ -1889,7 +1889,7 @@ extern tree *sh_deferred_function_attributes_tail;
{ \
fputs ("\t.ualong ", FILE); \
output_addr_const (FILE, ADDR); \
- if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \
+ if (SYMBOL_REF_P (ADDR) && SYMBOL_REF_FUNCTION_P (ADDR)) \
fputs ("@GOTFUNCDESC", FILE); \
else \
fputs ("@GOT", FILE); \
diff --git a/gcc/config/sh/sh.md b/gcc/config/sh/sh.md
index 86a27e24788..8b6e0594cf7 100644
--- a/gcc/config/sh/sh.md
+++ b/gcc/config/sh/sh.md
@@ -6712,7 +6712,7 @@
if (!flag_pic && TARGET_SH2A
&& MEM_P (operands[0])
- && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (operands[0], 0)))
{
if (sh2a_is_function_vector_call (XEXP (operands[0], 0)))
{
@@ -6723,7 +6723,7 @@
}
if (flag_pic && TARGET_SH2
&& MEM_P (operands[0])
- && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (operands[0], 0)))
{
emit_call_insn (gen_call_pcrel (XEXP (operands[0], 0), operands[1]));
DONE;
@@ -6761,7 +6761,7 @@
if (!flag_pic && TARGET_SH2A
&& MEM_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (operands[1], 0)))
{
if (sh2a_is_function_vector_call (XEXP (operands[1], 0)))
{
@@ -6772,7 +6772,7 @@
}
if (flag_pic && TARGET_SH2
&& MEM_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (operands[1], 0)))
{
emit_call_insn (gen_call_value_pcrel (operands[0], XEXP (operands[1], 0),
operands[2]));
@@ -6939,7 +6939,7 @@
if (flag_pic && TARGET_SH2
&& MEM_P (operands[0])
- && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (operands[0], 0))
/* The PLT needs the PIC register, but the epilogue would have
to restore it, so we can only use PC-relative PIC calls for
static functions. */
@@ -7114,7 +7114,7 @@
if (flag_pic && TARGET_SH2
&& MEM_P (operands[1])
- && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (operands[1], 0))
/* The PLT needs the PIC register, but the epilogue would have
to restore it, so we can only use PC-relative PIC calls for
static functions. */
@@ -7382,7 +7382,7 @@
&& flag_stack_protect
&& GET_CODE (operands[1]) == CONST
&& GET_CODE (XEXP (operands[1], 0)) == UNSPEC
- && GET_CODE (XVECEXP (XEXP (operands[1], 0), 0, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XVECEXP (XEXP (operands[1], 0), 0, 0))
&& strcmp (XSTR (XVECEXP (XEXP (operands[1], 0), 0, 0), 0),
"__stack_chk_guard") == 0)
stack_chk_guard_p = true;
diff --git a/gcc/config/sparc/predicates.md b/gcc/config/sparc/predicates.md
index 7d1f700d421..313cf33f8ad 100644
--- a/gcc/config/sparc/predicates.md
+++ b/gcc/config/sparc/predicates.md
@@ -106,7 +106,7 @@
case CONST:
op = XEXP (op, 0);
- return (((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ return (((SYMBOL_REF_P (XEXP (op, 0))
&& !SYMBOL_REF_TLS_MODEL (XEXP (op, 0)))
|| LABEL_REF_P (XEXP (op, 0)))
&& CONST_INT_P (XEXP (op, 1)));
@@ -147,7 +147,7 @@
(const (minus (label) (pc))))). */
op = XEXP (op, 0);
return GET_CODE (op) == MINUS
- && GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (op, 0))
&& GET_CODE (XEXP (op, 1)) == CONST
&& GET_CODE (XEXP (XEXP (op, 1), 0)) == MINUS;
})
diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c
index b5540da8d4a..3adb460147e 100644
--- a/gcc/config/sparc/sparc.c
+++ b/gcc/config/sparc/sparc.c
@@ -4331,7 +4331,7 @@ check_pic (int i)
{
case 1:
op = recog_data.operand[i];
- gcc_assert (GET_CODE (op) != SYMBOL_REF
+ gcc_assert (!SYMBOL_REF_P (op)
&& (GET_CODE (op) != CONST
|| (GET_CODE (XEXP (op, 0)) == MINUS
&& XEXP (XEXP (op, 0), 0) == sparc_got ()
@@ -4352,7 +4352,7 @@ pic_address_needs_scratch (rtx x)
/* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& !SMALL_INT (XEXP (XEXP (x, 0), 1)))
return 1;
@@ -4505,7 +4505,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
&& !SUBREG_P (rs2)
&& GET_CODE (rs2) != LO_SUM
&& !MEM_P (rs2)
- && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2))
+ && !(SYMBOL_REF_P (rs2) && SYMBOL_REF_TLS_MODEL (rs2))
&& (! symbolic_operand (rs2, VOIDmode) || mode == Pmode)
&& (!CONST_INT_P (rs2) || SMALL_INT (rs2)))
|| ((REG_P (rs1)
@@ -4550,7 +4550,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
imm1 = XEXP (rs1, 1);
rs1 = XEXP (rs1, 0);
if (!CONSTANT_P (imm1)
- || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
+ || (SYMBOL_REF_P (rs1) && SYMBOL_REF_TLS_MODEL (rs1)))
return 0;
}
}
@@ -4560,7 +4560,7 @@ sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict)
imm1 = XEXP (addr, 1);
if (!CONSTANT_P (imm1)
- || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1)))
+ || (SYMBOL_REF_P (rs1) && SYMBOL_REF_TLS_MODEL (rs1)))
return 0;
/* We can't allow TFmode in 32-bit mode, because an offset greater
@@ -4661,7 +4661,7 @@ sparc_tls_referenced_p (rtx x)
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x))
return true;
/* That's all we handle in sparc_legitimize_tls_address for now. */
@@ -4679,7 +4679,7 @@ sparc_legitimize_tls_address (rtx addr)
gcc_assert (can_create_pseudo_p ());
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
/* Although the various sethi/or sequences generate SImode values, many of
them can be transformed by the linker when relaxing and, if relaxing to
local-exec, will become a sethi/xor pair, which is signed and therefore
@@ -4846,7 +4846,7 @@ sparc_legitimize_tls_address (rtx addr)
static rtx
sparc_legitimize_pic_address (rtx orig, rtx reg)
{
- if (GET_CODE (orig) == SYMBOL_REF
+ if (SYMBOL_REF_P (orig)
/* See the comment in sparc_expand_move. */
|| (LABEL_REF_P (orig) && !can_use_mov_pic_label_ref (orig)))
{
@@ -4995,7 +4995,7 @@ sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0)))
x = gen_rtx_PLUS (Pmode, XEXP (x, 1),
copy_to_mode_reg (Pmode, XEXP (x, 0)));
- else if (GET_CODE (x) == SYMBOL_REF
+ else if (SYMBOL_REF_P (x)
|| GET_CODE (x) == CONST
|| LABEL_REF_P (x))
x = copy_to_suggested_reg (x, NULL_RTX, Pmode);
@@ -5019,11 +5019,11 @@ sparc_delegitimize_address (rtx x)
case UNSPEC_MOVE_PIC:
case UNSPEC_TLSLE:
x = XVECEXP (x, 0, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
break;
case UNSPEC_MOVE_GOTDATA:
x = XVECEXP (x, 0, 2);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
break;
default:
break;
@@ -5141,7 +5141,7 @@ sparc_emit_call_insn (rtx pat, rtx addr)
/* The PIC register is live on entry to VxWorks PIC PLT entries. */
if (TARGET_VXWORKS_RTP
&& flag_pic
- && GET_CODE (addr) == SYMBOL_REF
+ && SYMBOL_REF_P (addr)
&& (SYMBOL_REF_DECL (addr)
? !targetm.binds_local_p (SYMBOL_REF_DECL (addr))
: !SYMBOL_REF_LOCAL_P (addr)))
@@ -9686,7 +9686,7 @@ sparc_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x)
fprintf (file, "%+d", offset);
else if (REG_P (index))
fprintf (file, "+%s", reg_names[REGNO (index)]);
- else if (GET_CODE (index) == SYMBOL_REF
+ else if (SYMBOL_REF_P (index)
|| LABEL_REF_P (index)
|| GET_CODE (index) == CONST)
fputc ('+', file), output_addr_const (file, index);
diff --git a/gcc/config/spu/constraints.md b/gcc/config/spu/constraints.md
index ad028ef3686..9bf3090219a 100644
--- a/gcc/config/spu/constraints.md
+++ b/gcc/config/spu/constraints.md
@@ -155,7 +155,7 @@
"Call operand, symbol, for relative calls."
(and (match_code "mem")
(match_test "!TARGET_LARGE_MEM
- && ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
+ && ((SYMBOL_REF_P (XEXP (op, 0))
|| LABEL_REF_P (XEXP (op, 0))))")))
(define_memory_constraint "T"
diff --git a/gcc/config/spu/spu.c b/gcc/config/spu/spu.c
index 4888e90536b..475d25bd432 100644
--- a/gcc/config/spu/spu.c
+++ b/gcc/config/spu/spu.c
@@ -3071,7 +3071,7 @@ spu_float_const (const char *string, machine_mode mode)
int
spu_constant_address_p (rtx x)
{
- return (LABEL_REF_P (x) || GET_CODE (x) == SYMBOL_REF
+ return (LABEL_REF_P (x) || SYMBOL_REF_P (x)
|| CONST_INT_P (x) || GET_CODE (x) == CONST
|| GET_CODE (x) == HIGH);
}
@@ -3193,7 +3193,7 @@ classify_immediate (rtx op, machine_mode mode)
rtx sym = XEXP (XEXP (op, 0), 0);
rtx cst = XEXP (XEXP (op, 0), 1);
- if (GET_CODE (sym) == SYMBOL_REF
+ if (SYMBOL_REF_P (sym)
&& CONST_INT_P (cst)
&& satisfies_constraint_K (cst))
return IC_IL1s;
@@ -3463,7 +3463,7 @@ ea_symbol_ref_p (const_rtx x)
x = op0;
}
- return (GET_CODE (x) == SYMBOL_REF
+ return (SYMBOL_REF_P (x)
&& (decl = SYMBOL_REF_DECL (x)) != 0
&& TREE_CODE (decl) == VAR_DECL
&& TYPE_ADDR_SPACE (TREE_TYPE (decl)));
@@ -3491,7 +3491,7 @@ spu_legitimate_constant_p (machine_mode mode, rtx x)
/* V4SI with all identical symbols is valid. */
if (!flag_pic
&& mode == V4SImode
- && (GET_CODE (CONST_VECTOR_ELT (x, 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (CONST_VECTOR_ELT (x, 0))
|| LABEL_REF_P (CONST_VECTOR_ELT (x, 0))
|| GET_CODE (CONST_VECTOR_ELT (x, 0)) == CONST))
return const_vec_duplicate_p (x);
@@ -4173,7 +4173,7 @@ store_with_one_insn_p (rtx mem)
if (GET_MODE_SIZE (mode) >= 16)
return 1;
/* Only static objects. */
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
{
/* We use the associated declaration to make sure the access is
referring to the whole object.
@@ -5173,10 +5173,10 @@ reloc_diagnostic (rtx x)
if (!flag_pic || !(TARGET_WARN_RELOC || TARGET_ERROR_RELOC))
return;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
decl = SYMBOL_REF_DECL (x);
else if (GET_CODE (x) == CONST
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0)))
decl = SYMBOL_REF_DECL (XEXP (XEXP (x, 0), 0));
/* SYMBOL_REF_DECL is not necessarily a DECL. */
@@ -5219,7 +5219,7 @@ spu_assemble_integer (rtx x, unsigned int size, int aligned_p)
/* By default run-time relocations aren't supported, but we allow them
in case users support it in their own run-time loader. And we provide
a warning for those users that don't. */
- if ((GET_CODE (x) == SYMBOL_REF)
+ if ((SYMBOL_REF_P (x))
|| LABEL_REF_P (x) || GET_CODE (x) == CONST)
reloc_diagnostic (x);
@@ -6388,7 +6388,7 @@ spu_check_builtin_parm (struct spu_builtin_description *d, rtx op, int p)
}
if (LABEL_REF_P (op)
- || (GET_CODE (op) == SYMBOL_REF
+ || (SYMBOL_REF_P (op)
&& SYMBOL_REF_FUNCTION_P (op))
|| (v & ((1 << lsbits) - 1)) != 0)
warning (0, "%d least significant bits of %s are ignored", lsbits,
diff --git a/gcc/config/spu/spu.h b/gcc/config/spu/spu.h
index 4af55bd9d8d..988a68342af 100644
--- a/gcc/config/spu/spu.h
+++ b/gcc/config/spu/spu.h
@@ -104,7 +104,7 @@ extern GTY(()) int spu_tune;
/* symbol_ref's of functions are not aligned to 16 byte boundary. */
#define ALIGNED_SYMBOL_REF_P(X) \
- (GET_CODE (X) == SYMBOL_REF \
+ (SYMBOL_REF_P (X) \
&& (SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1) == 0 \
&& (! SYMBOL_REF_FUNCTION_P (X) \
|| align_functions.levels[0].get_value () >= 16))
diff --git a/gcc/config/stormy16/stormy16.c b/gcc/config/stormy16/stormy16.c
index 9a2b744426f..cc0adc218a9 100644
--- a/gcc/config/stormy16/stormy16.c
+++ b/gcc/config/stormy16/stormy16.c
@@ -515,7 +515,7 @@ xstormy16_below100_symbol (rtx x,
if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)))
x = XEXP (x, 0);
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_XSTORMY16_BELOW100) != 0;
if (CONST_INT_P (x))
@@ -1547,7 +1547,7 @@ xstormy16_asm_output_aligned_common (FILE *stream,
if (mem != NULL_RTX
&& MEM_P (mem)
- && GET_CODE (symbol = XEXP (mem, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (symbol = XEXP (mem, 0))
&& SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_XSTORMY16_BELOW100)
{
const char *name2;
@@ -1608,7 +1608,7 @@ xstormy16_encode_section_info (tree decl, rtx r, int first)
{
rtx symbol = XEXP (r, 0);
- gcc_assert (GET_CODE (symbol) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (symbol));
SYMBOL_REF_FLAGS (symbol) |= SYMBOL_FLAG_XSTORMY16_BELOW100;
}
}
@@ -1773,7 +1773,7 @@ xstormy16_print_operand (FILE *file, rtx x, int code)
case 'C':
/* Print the symbol without a surrounding @fptr(). */
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
assemble_name (file, XSTR (x, 0));
else if (LABEL_P (x))
output_asm_label (x);
diff --git a/gcc/config/tilegx/predicates.md b/gcc/config/tilegx/predicates.md
index 412a7ed24f4..bac0f483687 100644
--- a/gcc/config/tilegx/predicates.md
+++ b/gcc/config/tilegx/predicates.md
@@ -259,7 +259,7 @@
(ior (match_code "symbol_ref,label_ref")
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
- && (GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (op,0), 0))
|| LABEL_REF_P (XEXP (XEXP (op,0), 0)))
&& CONST_INT_P (XEXP (XEXP (op,0), 1))"))))
diff --git a/gcc/config/tilegx/tilegx.c b/gcc/config/tilegx/tilegx.c
index b96994c5997..afc9555bb5e 100644
--- a/gcc/config/tilegx/tilegx.c
+++ b/gcc/config/tilegx/tilegx.c
@@ -810,7 +810,7 @@ tilegx_tls_referenced_p (rtx x)
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x))
return true;
/* That's all we handle in tilegx_legitimize_tls_address for
@@ -826,7 +826,7 @@ tilegx_pic_address_needs_scratch (rtx x)
{
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& (CONST_INT_P (XEXP (XEXP (x, 0), 1))))
return true;
@@ -985,7 +985,7 @@ tilegx_legitimize_tls_address (rtx addr)
gcc_assert (can_create_pseudo_p ());
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
switch (SYMBOL_REF_TLS_MODEL (addr))
{
case TLS_MODEL_GLOBAL_DYNAMIC:
@@ -1209,7 +1209,7 @@ tilegx_legitimize_pic_address (rtx orig,
machine_mode mode ATTRIBUTE_UNUSED,
rtx reg)
{
- if (GET_CODE (orig) == SYMBOL_REF)
+ if (SYMBOL_REF_P (orig))
{
rtx address, pic_ref;
@@ -4571,7 +4571,7 @@ replace_mov_pcrel_step1 (rtx_insn *insn)
opnds[1] = XVECEXP (unspec, 0, 0);
/* We only need to replace SYMBOL_REFs, not LABEL_REFs. */
- if (GET_CODE (opnds[1]) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (opnds[1]))
return;
start_sequence ();
@@ -4648,7 +4648,7 @@ replace_mov_pcrel_step2 (rtx_insn *insn)
opnds[2] = XVECEXP (unspec, 0, 0);
/* We only need to replace SYMBOL_REFs, not LABEL_REFs. */
- if (GET_CODE (opnds[2]) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (opnds[2]))
return;
start_sequence ();
@@ -4707,7 +4707,7 @@ replace_mov_pcrel_step3 (rtx_insn *insn)
opnds[3] = XVECEXP (unspec, 0, 2);
/* We only need to replace SYMBOL_REFs, not LABEL_REFs. */
- if (GET_CODE (opnds[3]) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (opnds[3]))
return;
start_sequence ();
@@ -5371,7 +5371,7 @@ tilegx_print_operand (FILE *file, rtx x, int code)
}
case 'p':
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (flag_pic && !SYMBOL_REF_LOCAL_P (x))
fprintf (file, "plt(");
diff --git a/gcc/config/tilegx/tilegx.md b/gcc/config/tilegx/tilegx.md
index dce43eca074..7353bf71105 100644
--- a/gcc/config/tilegx/tilegx.md
+++ b/gcc/config/tilegx/tilegx.md
@@ -2535,7 +2535,7 @@
{
rtx orig_addr = XEXP (operands[0], 0);
rtx addr;
- if (GET_CODE (orig_addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (orig_addr))
{
if (tilegx_cmodel == CM_LARGE)
{
@@ -2577,7 +2577,7 @@
{
rtx orig_addr = XEXP (operands[1], 0);
rtx addr;
- if (GET_CODE (orig_addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (orig_addr))
{
if (tilegx_cmodel == CM_LARGE)
{
diff --git a/gcc/config/tilepro/predicates.md b/gcc/config/tilepro/predicates.md
index 4f8ec509bf3..e4c025593da 100644
--- a/gcc/config/tilepro/predicates.md
+++ b/gcc/config/tilepro/predicates.md
@@ -218,7 +218,7 @@
(ior (match_code "symbol_ref,label_ref")
(and (match_code "const")
(match_test "GET_CODE (XEXP (op,0)) == PLUS
- && (GET_CODE (XEXP (XEXP (op,0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (op,0), 0))
|| LABEL_REF_P (XEXP (XEXP (op,0), 0)))
&& CONST_INT_P (XEXP (XEXP (op,0), 1))"))))
diff --git a/gcc/config/tilepro/tilepro.c b/gcc/config/tilepro/tilepro.c
index 31b6d5af513..4ea38853fda 100644
--- a/gcc/config/tilepro/tilepro.c
+++ b/gcc/config/tilepro/tilepro.c
@@ -710,7 +710,7 @@ tilepro_tls_referenced_p (rtx x)
if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS)
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x))
return true;
/* That's all we handle in tilepro_legitimize_tls_address for
@@ -726,7 +726,7 @@ tilepro_pic_address_needs_scratch (rtx x)
{
if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
|| LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))
return true;
@@ -885,7 +885,7 @@ tilepro_legitimize_tls_address (rtx addr)
gcc_assert (can_create_pseudo_p ());
- if (GET_CODE (addr) == SYMBOL_REF)
+ if (SYMBOL_REF_P (addr))
switch (SYMBOL_REF_TLS_MODEL (addr))
{
case TLS_MODEL_GLOBAL_DYNAMIC:
@@ -980,7 +980,7 @@ tilepro_legitimize_pic_address (rtx orig,
machine_mode mode ATTRIBUTE_UNUSED,
rtx reg)
{
- if (GET_CODE (orig) == SYMBOL_REF)
+ if (SYMBOL_REF_P (orig))
{
rtx address, pic_ref;
@@ -4115,7 +4115,7 @@ replace_addli_pcrel (rtx_insn *insn)
opnds[3] = XVECEXP (unspec, 0, 1);
/* We only need to replace SYMBOL_REFs, not LABEL_REFs. */
- if (GET_CODE (opnds[2]) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (opnds[2]))
return;
first_insn_p = (opnds[1] == tilepro_text_label_rtx ());
@@ -4180,7 +4180,7 @@ replace_auli_pcrel (rtx_insn *insn)
opnds[3] = XVECEXP (unspec, 0, 1);
/* We only need to replace SYMBOL_REFs, not LABEL_REFs. */
- if (GET_CODE (opnds[2]) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (opnds[2]))
return;
first_insn_p = (opnds[1] == tilepro_text_label_rtx ());
@@ -4688,7 +4688,7 @@ tilepro_print_operand (FILE *file, rtx x, int code)
}
case 'p':
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (flag_pic && !SYMBOL_REF_LOCAL_P (x))
fprintf (file, "plt(");
diff --git a/gcc/config/v850/constraints.md b/gcc/config/v850/constraints.md
index 0513207136b..a901bc0d69e 100644
--- a/gcc/config/v850/constraints.md
+++ b/gcc/config/v850/constraints.md
@@ -100,7 +100,7 @@
(match_test "SYMBOL_REF_ZDA_P (op)"))
(and (match_code "const")
(match_test "GET_CODE (XEXP (op, 0)) == PLUS")
- (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF")
+ (match_test "SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))")
(match_test "SYMBOL_REF_ZDA_P (XEXP (XEXP (op, 0), 0))"))))
(define_constraint "W"
diff --git a/gcc/config/v850/predicates.md b/gcc/config/v850/predicates.md
index f6cbdaabcaf..8fd93638cd7 100644
--- a/gcc/config/v850/predicates.md
+++ b/gcc/config/v850/predicates.md
@@ -87,7 +87,7 @@
/* Only registers are valid call operands if TARGET_LONG_CALLS. */
if (TARGET_LONG_CALLS)
return REG_P (op);
- return (GET_CODE (op) == SYMBOL_REF || REG_P (op));
+ return (SYMBOL_REF_P (op) || REG_P (op));
})
;; Return true if OP is a valid source operand for SImode move.
@@ -132,7 +132,7 @@
&& satisfies_constraint_K (XEXP (XEXP (op, 0), 1)))
op = XEXP (XEXP (op, 0), 0);
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return (SYMBOL_REF_FLAGS (op)
& (SYMBOL_FLAG_ZDA | SYMBOL_FLAG_TDA | SYMBOL_FLAG_SDA)) != 0;
diff --git a/gcc/config/v850/v850.c b/gcc/config/v850/v850.c
index 9ccc41d7f86..a5a35ec7704 100644
--- a/gcc/config/v850/v850.c
+++ b/gcc/config/v850/v850.c
@@ -407,7 +407,7 @@ v850_print_operand (FILE * file, rtx x, int code)
{
case 'c':
/* We use 'c' operands with symbols for .vtinherit. */
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
output_addr_const(file, x);
break;
@@ -511,7 +511,7 @@ v850_print_operand (FILE * file, rtx x, int code)
if (GET_CODE (x) == CONST)
x = XEXP (XEXP (x, 0), 0);
else
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
if (SYMBOL_REF_ZDA_P (x))
fprintf (file, "zdaoff");
@@ -532,7 +532,7 @@ v850_print_operand (FILE * file, rtx x, int code)
if (GET_CODE (x) == CONST)
x = XEXP (XEXP (x, 0), 0);
else
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
if (SYMBOL_REF_ZDA_P (x))
fprintf (file, "r0");
@@ -873,7 +873,7 @@ output_move_single (rtx * operands)
return "movea %O1(%P1),%Q1,%0";
else if (LABEL_REF_P (src)
- || GET_CODE (src) == SYMBOL_REF
+ || SYMBOL_REF_P (src)
|| GET_CODE (src) == CONST)
{
if (TARGET_V850E_UP)
@@ -1099,7 +1099,7 @@ ep_memory_operand (rtx op, machine_mode mode, int unsigned_load)
if (REG_P (op0) && REGNO (op0) == EP_REGNUM)
return TRUE;
- if (GET_CODE (op0) == SYMBOL_REF && SYMBOL_REF_TDA_P (op0))
+ if (SYMBOL_REF_P (op0) && SYMBOL_REF_TDA_P (op0))
return TRUE;
}
break;
@@ -3023,7 +3023,7 @@ v850_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x)
return (CONST_DOUBLE_P (x)
|| !(GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1))
&& !CONST_OK_FOR_K (INTVAL (XEXP (XEXP (x, 0), 1)))));
}
diff --git a/gcc/config/vax/predicates.md b/gcc/config/vax/predicates.md
index 99c21d57d06..253025ebfc5 100644
--- a/gcc/config/vax/predicates.md
+++ b/gcc/config/vax/predicates.md
@@ -28,7 +28,7 @@
{
if (LABEL_REF_P (op))
return 1;
- if (GET_CODE (op) == SYMBOL_REF)
+ if (SYMBOL_REF_P (op))
return !flag_pic || SYMBOL_REF_LOCAL_P (op);
if (LABEL_REF_P (XEXP (XEXP (op, 0), 0)))
return 1;
@@ -41,7 +41,7 @@
(define_predicate "external_const_operand"
(and (match_code "const")
- (match_test "GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
+ (match_test "SYMBOL_REF_P (XEXP (XEXP (op, 0), 0))
&& !SYMBOL_REF_LOCAL_P (XEXP (XEXP (op, 0), 0))")))
(define_predicate "nonsymbolic_operand"
diff --git a/gcc/config/vax/vax.c b/gcc/config/vax/vax.c
index 2094e852527..dba330facfc 100644
--- a/gcc/config/vax/vax.c
+++ b/gcc/config/vax/vax.c
@@ -439,7 +439,7 @@ print_operand_address (FILE * file, rtx addr)
if (reg1)
{
if (breg
- || (flag_pic && GET_CODE (addr) == SYMBOL_REF)
+ || (flag_pic && SYMBOL_REF_P (addr))
|| (offset
&& (MEM_P (offset)
|| (flag_pic && symbolic_operand (offset, SImode)))))
@@ -463,7 +463,7 @@ print_operand_address (FILE * file, rtx addr)
#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
if (flag_pic > 1 && GET_CODE (offset) == CONST
- && GET_CODE (XEXP (XEXP (offset, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (offset, 0), 0))
&& !SYMBOL_REF_LOCAL_P (XEXP (XEXP (offset, 0), 0)))
{
debug_rtx (orig);
@@ -1637,14 +1637,14 @@ vax_output_int_subtract (rtx_insn *insn, rtx *operands, machine_mode mode)
bool
legitimate_constant_address_p (rtx x)
{
- if (LABEL_REF_P (x) || GET_CODE (x) == SYMBOL_REF
+ if (LABEL_REF_P (x) || SYMBOL_REF_P (x)
|| CONST_INT_P (x) || GET_CODE (x) == HIGH)
return true;
if (GET_CODE (x) != CONST)
return false;
#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
if (flag_pic
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& !SYMBOL_REF_LOCAL_P (XEXP (XEXP (x, 0), 0)))
return false;
#endif
@@ -1671,12 +1671,12 @@ legitimate_constant_address_p (rtx x)
static bool
indirectable_constant_address_p (rtx x, bool indirect)
{
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
return !flag_pic || SYMBOL_REF_LOCAL_P (x) || !indirect;
if (GET_CODE (x) == CONST)
return !flag_pic
- || GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
|| SYMBOL_REF_LOCAL_P (XEXP (XEXP (x, 0), 0));
return CONSTANT_ADDRESS_P (x);
diff --git a/gcc/config/vax/vax.md b/gcc/config/vax/vax.md
index 4017a72e08f..a870fe80d7f 100644
--- a/gcc/config/vax/vax.md
+++ b/gcc/config/vax/vax.md
@@ -142,7 +142,7 @@
#ifdef NO_EXTERNAL_INDIRECT_ADDRESS
if (flag_pic
&& GET_CODE (operands[1]) == CONST
- && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (operands[1], 0), 0))
&& !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
{
rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index 4d62033d810..617c1a90728 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -100,7 +100,7 @@
tree callee;
const char * callee_sec, * caller_sec;
- if (GET_CODE (op) != SYMBOL_REF
+ if (!SYMBOL_REF_P (op)
|| !SYMBOL_REF_LOCAL_P (op) || SYMBOL_REF_EXTERNAL_P (op))
return false;
diff --git a/gcc/config/xtensa/xtensa.c b/gcc/config/xtensa/xtensa.c
index 30b27cb629f..84a05e303da 100644
--- a/gcc/config/xtensa/xtensa.c
+++ b/gcc/config/xtensa/xtensa.c
@@ -570,7 +570,7 @@ constantpool_address_p (const_rtx addr)
sym = XEXP (addr, 0);
}
- if ((GET_CODE (sym) == SYMBOL_REF)
+ if ((SYMBOL_REF_P (sym))
&& CONSTANT_POOL_ADDRESS_P (sym))
return true;
return false;
@@ -596,7 +596,7 @@ xtensa_tls_symbol_p (rtx x)
if (! TARGET_HAVE_TLS)
return false;
- return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0;
+ return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0;
}
@@ -2023,7 +2023,7 @@ xtensa_tls_referenced_p (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0)
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0)
return true;
/* Ignore TLS references that have already been legitimized. */
@@ -2469,7 +2469,7 @@ print_operand (FILE *file, rtx x, int letter)
/* X must be a symbolic constant on ELF. Write an expression
suitable for 'const16' that sets the high or low 16 bits. */
if (GET_CODE (XEXP (x, 0)) != PLUS
- || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF
+ || (!SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& !LABEL_REF_P (XEXP (XEXP (x, 0), 0)))
|| !CONST_INT_P (XEXP (XEXP (x, 0), 1)))
output_operand_lossage ("invalid %%t/%%b value");
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index ccb64520c49..91b4c4895ff 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -624,7 +624,7 @@ typedef struct xtensa_args
valid address. This is defined to be the same as 'CONSTANT_P (X)',
but rejecting CONST_DOUBLE. */
#define CONSTANT_ADDRESS_P(X) \
- ((LABEL_REF_P (X) || GET_CODE (X) == SYMBOL_REF \
+ ((LABEL_REF_P (X) || SYMBOL_REF_P (X) \
|| CONST_INT_P (X) || GET_CODE (X) == HIGH \
|| (GET_CODE (X) == CONST)))
@@ -632,7 +632,7 @@ typedef struct xtensa_args
operand on the target machine when generating position independent
code. */
#define LEGITIMATE_PIC_OPERAND_P(X) \
- ((GET_CODE (X) != SYMBOL_REF \
+ ((!SYMBOL_REF_P (X) \
|| (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \
&& !LABEL_REF_P (X) \
&& GET_CODE (X) != CONST)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 757ece341e6..9530423c600 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -1607,7 +1607,7 @@
""
{
rtx addr = XEXP (operands[0], 0);
- if (flag_pic && GET_CODE (addr) == SYMBOL_REF
+ if (flag_pic && SYMBOL_REF_P (addr)
&& (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
addr = gen_sym_PLT (addr);
if (!call_insn_operand (addr, VOIDmode))
@@ -1632,7 +1632,7 @@
""
{
rtx addr = XEXP (operands[1], 0);
- if (flag_pic && GET_CODE (addr) == SYMBOL_REF
+ if (flag_pic && SYMBOL_REF_P (addr)
&& (!SYMBOL_REF_LOCAL_P (addr) || SYMBOL_REF_EXTERNAL_P (addr)))
addr = gen_sym_PLT (addr);
if (!call_insn_operand (addr, VOIDmode))
diff --git a/gcc/cselib.c b/gcc/cselib.c
index 3575141d601..27be48d2154 100644
--- a/gcc/cselib.c
+++ b/gcc/cselib.c
@@ -1474,7 +1474,7 @@ expand_loc (struct elt_loc_list *p, struct expand_value_data *evd,
fprintf (dump_file, "\n");
}
if (GET_CODE (p->loc) == LO_SUM
- && GET_CODE (XEXP (p->loc, 1)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (p->loc, 1))
&& p->setting_insn
&& (note = find_reg_note (p->setting_insn, REG_EQUAL, NULL_RTX))
&& XEXP (note, 0) == XEXP (p->loc, 1))
diff --git a/gcc/dbxout.c b/gcc/dbxout.c
index a3cdd4ace85..2ecca9a7d81 100644
--- a/gcc/dbxout.c
+++ b/gcc/dbxout.c
@@ -2740,7 +2740,7 @@ dbxout_symbol (tree decl, int local ATTRIBUTE_UNUSED)
if (context && DECL_FROM_INLINE (decl))
break;
if (!MEM_P (decl_rtl)
- || GET_CODE (XEXP (decl_rtl, 0)) != SYMBOL_REF)
+ || !SYMBOL_REF_P (XEXP (decl_rtl, 0)))
break;
if (flag_debug_only_used_symbols)
@@ -3033,7 +3033,7 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
no letter at all, and N_LSYM, for auto variable,
r and N_RSYM for register variable. */
- if (MEM_P (home) && GET_CODE (XEXP (home, 0)) == SYMBOL_REF)
+ if (MEM_P (home) && SYMBOL_REF_P (XEXP (home, 0)))
{
if (TREE_PUBLIC (decl))
{
@@ -3058,13 +3058,13 @@ dbxout_symbol_location (tree decl, tree type, const char *suffix, rtx home)
dumped into a constant pool. Alternatively, the symbol
in the constant pool might be referenced by a different
symbol. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& CONSTANT_POOL_ADDRESS_P (addr))
{
bool marked;
rtx tmp = get_pool_constant_mark (addr, &marked);
- if (GET_CODE (tmp) == SYMBOL_REF)
+ if (SYMBOL_REF_P (tmp))
{
addr = tmp;
if (CONSTANT_POOL_ADDRESS_P (addr))
@@ -3339,7 +3339,7 @@ dbxout_common_check (tree decl, int *value)
sym_addr = XEXP (sym_addr, 0);
if (GET_CODE (sym_addr) == CONST)
sym_addr = XEXP (sym_addr, 0);
- if ((GET_CODE (sym_addr) == SYMBOL_REF || GET_CODE (sym_addr) == PLUS)
+ if ((SYMBOL_REF_P (sym_addr) || GET_CODE (sym_addr) == PLUS)
&& DECL_INITIAL (decl) == 0)
{
diff --git a/gcc/dse.c b/gcc/dse.c
index e76d67b5748..b7511a320da 100644
--- a/gcc/dse.c
+++ b/gcc/dse.c
@@ -2439,7 +2439,7 @@ scan_insn (bb_info_t bb_info, rtx_insn *insn)
if (!const_call
&& (call = get_call_rtx_from (insn))
&& (sym = XEXP (XEXP (call, 0), 0))
- && GET_CODE (sym) == SYMBOL_REF
+ && SYMBOL_REF_P (sym)
&& SYMBOL_REF_DECL (sym)
&& TREE_CODE (SYMBOL_REF_DECL (sym)) == FUNCTION_DECL
&& fndecl_built_in_p (SYMBOL_REF_DECL (sym), BUILT_IN_MEMSET))
diff --git a/gcc/dwarf2asm.c b/gcc/dwarf2asm.c
index 488e54b72ec..fc655272ed8 100644
--- a/gcc/dwarf2asm.c
+++ b/gcc/dwarf2asm.c
@@ -912,7 +912,7 @@ dw2_force_const_mem (rtx x, bool is_public)
if (! indirect_pool)
indirect_pool = hash_map<const char *, tree>::create_ggc (64);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
key = XSTR (x, 0);
tree *slot = indirect_pool->get (key);
@@ -1078,13 +1078,13 @@ dw2_asm_output_encoded_addr_rtx (int encoding, rtx addr, bool is_public,
#ifdef ASM_OUTPUT_DWARF_DATAREL
case DW_EH_PE_datarel:
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
ASM_OUTPUT_DWARF_DATAREL (asm_out_file, size, XSTR (addr, 0));
break;
#endif
case DW_EH_PE_pcrel:
- gcc_assert (GET_CODE (addr) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (addr));
#ifdef ASM_OUTPUT_DWARF_PCREL
ASM_OUTPUT_DWARF_PCREL (asm_out_file, size, XSTR (addr, 0));
#else
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index d1fb7bf494d..b2b4f6d82b2 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -6925,7 +6925,7 @@ attr_checksum (dw_attr_node *at, struct md5_ctx *ctx, int *mark)
case dw_val_class_addr:
r = AT_addr (at);
- gcc_assert (GET_CODE (r) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (r));
CHECKSUM_STRING (XSTR (r, 0));
break;
@@ -7225,7 +7225,7 @@ attr_checksum_ordered (enum dwarf_tag tag, dw_attr_node *at,
case dw_val_class_addr:
r = AT_addr (at);
- gcc_assert (GET_CODE (r) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (r));
CHECKSUM_ULEB128 (DW_FORM_string);
CHECKSUM_STRING (XSTR (r, 0));
break;
@@ -14503,7 +14503,7 @@ const_ok_for_output_1 (rtx rtl)
rather than DECL_THREAD_LOCAL_P is not just an optimization. */
if (flag_checking
&& (XVECLEN (rtl, 0) == 0
- || GET_CODE (XVECEXP (rtl, 0, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XVECEXP (rtl, 0, 0))
|| SYMBOL_REF_TLS_MODEL (XVECEXP (rtl, 0, 0)) == TLS_MODEL_NONE))
inform (current_function_decl
? DECL_SOURCE_LOCATION (current_function_decl)
@@ -14619,7 +14619,7 @@ const_ok_for_output_1 (rtx rtl)
static bool
const_ok_for_output (rtx rtl)
{
- if (GET_CODE (rtl) == SYMBOL_REF)
+ if (SYMBOL_REF_P (rtl))
return const_ok_for_output_1 (rtl);
if (GET_CODE (rtl) == CONST)
@@ -15755,7 +15755,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode,
goto symref;
}
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_TLS_MODEL (rtl) != TLS_MODEL_NONE)
{
dw_loc_descr_ref temp;
@@ -17453,7 +17453,7 @@ cst_pool_loc_descr (tree loc)
gcc_assert (!rtl);
return 0;
}
- gcc_assert (GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (rtl, 0)));
/* TODO: We might get more coverage if we was actually delaying expansion
of all expressions till end of compilation when constant pools are fully
@@ -20063,7 +20063,7 @@ rtl_for_decl_location (tree decl)
{
rtl = make_decl_rtl_for_debug (decl);
if (!MEM_P (rtl)
- || GET_CODE (XEXP (rtl, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (rtl, 0))
|| SYMBOL_REF_DECL (XEXP (rtl, 0)) != decl)
rtl = NULL_RTX;
}
@@ -21798,7 +21798,7 @@ decl_start_label (tree decl)
gcc_assert (MEM_P (x));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
fnname = XSTR (x, 0);
return fnname;
@@ -23816,7 +23816,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die)
if (single_element_loc_list_p (loc)
&& loc->expr->dw_loc_opc == DW_OP_addr
&& loc->expr->dw_loc_next == NULL
- && GET_CODE (loc->expr->dw_loc_oprnd1.v.val_addr) == SYMBOL_REF)
+ && SYMBOL_REF_P (loc->expr->dw_loc_oprnd1.v.val_addr))
{
rtx x = loc->expr->dw_loc_oprnd1.v.val_addr;
loc->expr->dw_loc_oprnd1.v.val_addr
@@ -27334,7 +27334,7 @@ dwarf2out_var_location (rtx_insn *loc_note)
if (GET_CODE (x) == CALL)
x = XEXP (x, 0);
if (!MEM_P (x)
- || GET_CODE (XEXP (x, 0)) != SYMBOL_REF
+ || !SYMBOL_REF_P (XEXP (x, 0))
|| !SYMBOL_REF_DECL (XEXP (x, 0))
|| (TREE_CODE (SYMBOL_REF_DECL (XEXP (x, 0)))
!= FUNCTION_DECL))
@@ -27512,7 +27512,7 @@ create_label:
if (MEM_P (XEXP (x, 0)))
x = XEXP (x, 0);
/* First, look for a memory access to a symbol_ref. */
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& SYMBOL_REF_DECL (XEXP (x, 0))
&& TREE_CODE (SYMBOL_REF_DECL (XEXP (x, 0))) == FUNCTION_DECL)
ca_loc->symbol_ref = XEXP (x, 0);
@@ -29866,7 +29866,7 @@ resolve_one_addr (rtx *addr)
if (!rtl || !MEM_P (rtl))
return false;
rtl = XEXP (rtl, 0);
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_DECL (rtl)
&& !TREE_ASM_WRITTEN (SYMBOL_REF_DECL (rtl)))
return false;
@@ -29875,7 +29875,7 @@ resolve_one_addr (rtx *addr)
return true;
}
- if (GET_CODE (rtl) == SYMBOL_REF
+ if (SYMBOL_REF_P (rtl)
&& SYMBOL_REF_DECL (rtl))
{
if (TREE_CONSTANT_POOL_ADDRESS_P (rtl))
@@ -29915,7 +29915,7 @@ string_cst_pool_decl (tree t)
if (!rtl || !MEM_P (rtl))
return NULL_RTX;
rtl = XEXP (rtl, 0);
- if (GET_CODE (rtl) != SYMBOL_REF
+ if (!SYMBOL_REF_P (rtl)
|| SYMBOL_REF_DECL (rtl) == NULL_TREE)
return NULL_RTX;
@@ -29972,7 +29972,7 @@ optimize_one_addr_into_implicit_ptr (dw_loc_descr_ref loc)
if (!rtl)
return false;
}
- if (GET_CODE (rtl) == SYMBOL_REF && SYMBOL_REF_DECL (rtl))
+ if (SYMBOL_REF_P (rtl) && SYMBOL_REF_DECL (rtl))
{
decl = SYMBOL_REF_DECL (rtl);
if (VAR_P (decl) && !DECL_EXTERNAL (decl))
@@ -30596,7 +30596,7 @@ resolve_addr (dw_die_ref die)
if (l != NULL
&& l->dw_loc_next == NULL
&& l->dw_loc_opc == DW_OP_addr
- && GET_CODE (l->dw_loc_oprnd1.v.val_addr) == SYMBOL_REF
+ && SYMBOL_REF_P (l->dw_loc_oprnd1.v.val_addr)
&& SYMBOL_REF_DECL (l->dw_loc_oprnd1.v.val_addr)
&& a->dw_attr == DW_AT_location)
{
diff --git a/gcc/explow.c b/gcc/explow.c
index bc813d07f2e..441847d02ba 100644
--- a/gcc/explow.c
+++ b/gcc/explow.c
@@ -117,7 +117,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
/* If this is a reference to the constant pool, try replacing it with
a reference to a new constant. If the resulting address isn't
valid, don't return it because we have no way to validize it. */
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
{
rtx cst = get_pool_constant (XEXP (x, 0));
@@ -197,7 +197,7 @@ plus_constant (machine_mode mode, rtx x, poly_int64 c, bool inplace)
if (maybe_ne (c, 0))
x = gen_rtx_PLUS (mode, x, gen_int_mode (c, mode));
- if (GET_CODE (x) == SYMBOL_REF || LABEL_REF_P (x))
+ if (SYMBOL_REF_P (x) || LABEL_REF_P (x))
return x;
else if (all_constant)
return gen_rtx_CONST (mode, x);
@@ -558,7 +558,7 @@ use_anchored_address (rtx x)
}
/* Check whether BASE is suitable for anchors. */
- if (GET_CODE (base) != SYMBOL_REF
+ if (!SYMBOL_REF_P (base)
|| !SYMBOL_REF_HAS_BLOCK_INFO_P (base)
|| SYMBOL_REF_ANCHOR_P (base)
|| SYMBOL_REF_BLOCK (base) == NULL
@@ -680,7 +680,7 @@ force_reg (machine_mode mode, rtx x)
known alignment of that pointer. */
{
unsigned align = 0;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
align = BITS_PER_UNIT;
if (SYMBOL_REF_DECL (x) && DECL_P (SYMBOL_REF_DECL (x)))
@@ -690,7 +690,7 @@ force_reg (machine_mode mode, rtx x)
align = BITS_PER_UNIT;
else if (GET_CODE (x) == CONST
&& GET_CODE (XEXP (x, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (x, 0), 0))
&& CONST_INT_P (XEXP (XEXP (x, 0), 1)))
{
rtx s = XEXP (XEXP (x, 0), 0);
diff --git a/gcc/expr.c b/gcc/expr.c
index bffd3ca50df..e22b02b8868 100644
--- a/gcc/expr.c
+++ b/gcc/expr.c
@@ -3255,7 +3255,7 @@ read_complex_part (rtx cplx, bool imag_p)
ibitsize = GET_MODE_BITSIZE (imode);
/* Special case reads from complex constants that got spilled to memory. */
- if (MEM_P (cplx) && GET_CODE (XEXP (cplx, 0)) == SYMBOL_REF)
+ if (MEM_P (cplx) && SYMBOL_REF_P (XEXP (cplx, 0)))
{
tree decl = SYMBOL_REF_DECL (XEXP (cplx, 0));
if (decl && TREE_CODE (decl) == COMPLEX_CST)
@@ -7448,7 +7448,7 @@ force_operand (rtx value, rtx target)
/* Check for a PIC address load. */
if ((code == PLUS || code == MINUS)
&& XEXP (value, 0) == pic_offset_table_rtx
- && (GET_CODE (XEXP (value, 1)) == SYMBOL_REF
+ && (SYMBOL_REF_P (XEXP (value, 1))
|| LABEL_REF_P (XEXP (value, 1))
|| GET_CODE (XEXP (value, 1)) == CONST))
{
diff --git a/gcc/final.c b/gcc/final.c
index a93acb29539..ec396230a3a 100644
--- a/gcc/final.c
+++ b/gcc/final.c
@@ -1611,7 +1611,7 @@ get_some_local_dynamic_name ()
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (SYMBOL_REF_TLS_MODEL (x) == TLS_MODEL_LOCAL_DYNAMIC)
return some_local_dynamic_name = XSTR (x, 0);
@@ -3093,7 +3093,7 @@ final_scan_insn_1 (rtx_insn *insn, FILE *file, int optimize_p ATTRIBUTE_UNUSED,
{
rtx x = call_from_call_insn (call_insn);
x = XEXP (x, 0);
- if (x && MEM_P (x) && GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
+ if (x && MEM_P (x) && SYMBOL_REF_P (XEXP (x, 0)))
{
tree t;
x = XEXP (x, 0);
@@ -4024,7 +4024,7 @@ mark_symbol_refs_as_used (rtx x)
FOR_EACH_SUBRTX (iter, array, x, ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
if (tree t = SYMBOL_REF_DECL (x))
assemble_external (t);
}
@@ -4183,7 +4183,7 @@ output_addr_const (FILE *file, rtx x)
fprintf (file, "-");
if ((CONST_INT_P (XEXP (x, 1)) && INTVAL (XEXP (x, 1)) >= 0)
|| GET_CODE (XEXP (x, 1)) == PC
- || GET_CODE (XEXP (x, 1)) == SYMBOL_REF)
+ || SYMBOL_REF_P (XEXP (x, 1)))
output_addr_const (file, XEXP (x, 1));
else
{
diff --git a/gcc/gcse.c b/gcc/gcse.c
index 43a0e29eaf7..357f8a2ddb2 100644
--- a/gcc/gcse.c
+++ b/gcc/gcse.c
@@ -1735,7 +1735,7 @@ prune_expressions (bool pre_p)
of the tables. */
if (MEM_P (x))
{
- if (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ if (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)))
continue;
diff --git a/gcc/genattrtab.c b/gcc/genattrtab.c
index 68aa1723073..912d6b4f594 100644
--- a/gcc/genattrtab.c
+++ b/gcc/genattrtab.c
@@ -813,8 +813,8 @@ check_attr_test (file_location loc, rtx exp, attr_desc *attr)
case LE: case LT: case GT: case GE:
case LEU: case LTU: case GTU: case GEU:
case NE: case EQ:
- if (GET_CODE (XEXP (exp, 0)) == SYMBOL_REF
- && GET_CODE (XEXP (exp, 1)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (exp, 0))
+ && SYMBOL_REF_P (XEXP (exp, 1)))
exp = attr_rtx (GET_CODE (exp),
attr_rtx (SYMBOL_REF, XSTR (XEXP (exp, 0), 0)),
attr_rtx (SYMBOL_REF, XSTR (XEXP (exp, 1), 0)));
diff --git a/gcc/ifcvt.c b/gcc/ifcvt.c
index 7a371a43bd9..a62b1265599 100644
--- a/gcc/ifcvt.c
+++ b/gcc/ifcvt.c
@@ -2630,7 +2630,7 @@ noce_try_abs (struct noce_if_info *if_info)
return FALSE;
}
if (MEM_P (c)
- && GET_CODE (XEXP (c, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (c, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (c, 0)))
c = get_pool_constant (XEXP (c, 0));
diff --git a/gcc/lower-subreg.c b/gcc/lower-subreg.c
index dcc6044e7a2..54a8f78cd7b 100644
--- a/gcc/lower-subreg.c
+++ b/gcc/lower-subreg.c
@@ -307,7 +307,7 @@ simple_move_operand (rtx x)
return false;
if (LABEL_REF_P (x)
- || GET_CODE (x) == SYMBOL_REF
+ || SYMBOL_REF_P (x)
|| GET_CODE (x) == HIGH
|| GET_CODE (x) == CONST)
return false;
diff --git a/gcc/optabs.c b/gcc/optabs.c
index 9692ded0f38..77a58bdde2c 100644
--- a/gcc/optabs.c
+++ b/gcc/optabs.c
@@ -5276,7 +5276,7 @@ debug_optab_libfuncs (void)
rtx l = optab_libfunc ((optab) i, (machine_mode) j);
if (l)
{
- gcc_assert (GET_CODE (l) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (l));
fprintf (stderr, "%s\t%s:\t%s\n",
GET_RTX_NAME (optab_to_code ((optab) i)),
GET_MODE_NAME (j),
@@ -5293,7 +5293,7 @@ debug_optab_libfuncs (void)
(machine_mode) k);
if (l)
{
- gcc_assert (GET_CODE (l) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (l));
fprintf (stderr, "%s\t%s\t%s:\t%s\n",
GET_RTX_NAME (optab_to_code ((optab) i)),
GET_MODE_NAME (j),
diff --git a/gcc/postreload.c b/gcc/postreload.c
index 8f2c3448eb4..f1951b305ff 100644
--- a/gcc/postreload.c
+++ b/gcc/postreload.c
@@ -2053,16 +2053,16 @@ reload_cse_move2add (rtx_insn *first)
(set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A))))
...
(set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */
- if ((GET_CODE (src) == SYMBOL_REF
+ if ((SYMBOL_REF_P (src)
|| (GET_CODE (src) == CONST
&& GET_CODE (XEXP (src, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (src, 0), 0))
&& CONST_INT_P (XEXP (XEXP (src, 0), 1))))
&& dbg_cnt (cse2_move2add))
{
rtx sym, off;
- if (GET_CODE (src) == SYMBOL_REF)
+ if (SYMBOL_REF_P (src))
{
sym = src;
off = const0_rtx;
@@ -2204,14 +2204,14 @@ move2add_note_store (rtx dst, const_rtx set, void *data)
rtx off;
note = find_reg_equal_equiv_note (insn);
- if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF)
+ if (note && SYMBOL_REF_P (XEXP (note, 0)))
{
sym = XEXP (note, 0);
off = const0_rtx;
}
else if (note && GET_CODE (XEXP (note, 0)) == CONST
&& GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS
- && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (XEXP (note, 0), 0), 0))
&& CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1)))
{
sym = XEXP (XEXP (XEXP (note, 0), 0), 0);
diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c
index 849e22726d7..53212ce878f 100644
--- a/gcc/print-rtl.c
+++ b/gcc/print-rtl.c
@@ -215,7 +215,7 @@ rtx_writer::print_rtx_operand_code_0 (const_rtx in_rtx ATTRIBUTE_UNUSED,
int idx ATTRIBUTE_UNUSED)
{
#ifndef GENERATOR_FILE
- if (idx == 1 && GET_CODE (in_rtx) == SYMBOL_REF)
+ if (idx == 1 && SYMBOL_REF_P (in_rtx))
{
int flags = SYMBOL_REF_FLAGS (in_rtx);
if (flags)
diff --git a/gcc/reginfo.c b/gcc/reginfo.c
index ce65873b0f6..a3d16005d91 100644
--- a/gcc/reginfo.c
+++ b/gcc/reginfo.c
@@ -1144,20 +1144,20 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn)
&& REG_P (XEXP (SET_SRC (x), 0))
&& REG_POINTER (XEXP (SET_SRC (x), 0)))
|| GET_CODE (SET_SRC (x)) == CONST
- || GET_CODE (SET_SRC (x)) == SYMBOL_REF
+ || SYMBOL_REF_P (SET_SRC (x))
|| LABEL_REF_P (SET_SRC (x))
|| (GET_CODE (SET_SRC (x)) == HIGH
&& (GET_CODE (XEXP (SET_SRC (x), 0)) == CONST
- || GET_CODE (XEXP (SET_SRC (x), 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (SET_SRC (x), 0))
|| LABEL_REF_P (XEXP (SET_SRC (x), 0))))
|| ((GET_CODE (SET_SRC (x)) == PLUS
|| GET_CODE (SET_SRC (x)) == LO_SUM)
&& (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST
- || GET_CODE (XEXP (SET_SRC (x), 1)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (SET_SRC (x), 1))
|| LABEL_REF_P (XEXP (SET_SRC (x), 1))))
|| ((note = find_reg_note (insn, REG_EQUAL, 0)) != 0
&& (GET_CODE (XEXP (note, 0)) == CONST
- || GET_CODE (XEXP (note, 0)) == SYMBOL_REF
+ || SYMBOL_REF_P (XEXP (note, 0))
|| LABEL_REF_P (XEXP (note, 0))))))
REG_POINTER (SET_DEST (x)) = 1;
diff --git a/gcc/reload.c b/gcc/reload.c
index a9efe22d965..52233eb55e1 100644
--- a/gcc/reload.c
+++ b/gcc/reload.c
@@ -5035,7 +5035,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
taken care of above. */
if (ind_levels == 0
- || (GET_CODE (XEXP (tem, 0)) == SYMBOL_REF && ! indirect_symref_ok)
+ || (SYMBOL_REF_P (XEXP (tem, 0)) && ! indirect_symref_ok)
|| MEM_P (XEXP (tem, 0))
|| ! (REG_P (XEXP (tem, 0))
|| (GET_CODE (XEXP (tem, 0)) == PLUS
@@ -5229,7 +5229,7 @@ find_reloads_address (machine_mode mode, rtx *memrefloc, rtx ad,
/* If AD is an address in the constant pool, the MEM rtx may be shared.
Unshare it so we can safely alter it. */
- if (memrefloc && GET_CODE (ad) == SYMBOL_REF
+ if (memrefloc && SYMBOL_REF_P (ad)
&& CONSTANT_POOL_ADDRESS_P (ad))
{
*memrefloc = copy_rtx (*memrefloc);
diff --git a/gcc/rtl.c b/gcc/rtl.c
index d7b8e9877c3..3a678e46236 100644
--- a/gcc/rtl.c
+++ b/gcc/rtl.c
@@ -205,7 +205,7 @@ rtx_size (const_rtx x)
return (RTX_HDR_SIZE
+ sizeof (struct const_poly_int_def)
+ CONST_POLY_INT_COEFFS (x).extra_size ());
- if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_HAS_BLOCK_INFO_P (x))
+ if (SYMBOL_REF_P (x) && SYMBOL_REF_HAS_BLOCK_INFO_P (x))
return RTX_HDR_SIZE + sizeof (struct block_symbol);
return RTX_CODE_SIZE (GET_CODE (x));
}
@@ -272,7 +272,7 @@ shared_const_p (const_rtx orig)
a LABEL_REF, it isn't sharable. */
poly_int64 offset;
return (GET_CODE (XEXP (orig, 0)) == PLUS
- && GET_CODE (XEXP (XEXP (orig, 0), 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (XEXP (orig, 0), 0))
&& poly_int_rtx_p (XEXP (XEXP (orig, 0), 1), &offset));
}
diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c
index a8becc85047..adb0929a1aa 100644
--- a/gcc/rtlanal.c
+++ b/gcc/rtlanal.c
@@ -871,7 +871,7 @@ offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset)
{
tree decl;
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return false;
if (offset == 0)
@@ -3177,7 +3177,7 @@ replace_label (rtx *loc, rtx old_label, rtx new_label, bool update_label_nuses)
rtx *loc = *iter;
if (rtx x = *loc)
{
- if (GET_CODE (x) == SYMBOL_REF
+ if (SYMBOL_REF_P (x)
&& CONSTANT_POOL_ADDRESS_P (x))
{
rtx c = get_pool_constant (x);
@@ -3239,7 +3239,7 @@ rtx_referenced_p (const_rtx x, const_rtx body)
return true;
/* If Y is a reference to pool constant traverse the constant. */
- if (GET_CODE (y) == SYMBOL_REF
+ if (SYMBOL_REF_P (y)
&& CONSTANT_POOL_ADDRESS_P (y))
iter.substitute (get_pool_constant (y));
}
@@ -3296,7 +3296,7 @@ computed_jump_p_1 (const_rtx x)
return 1;
case MEM:
- return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ return ! (SYMBOL_REF_P (XEXP (x, 0))
&& CONSTANT_POOL_ADDRESS_P (XEXP (x, 0)));
case IF_THEN_ELSE:
@@ -6596,7 +6596,7 @@ tls_referenced_p (const_rtx x)
subrtx_iterator::array_type array;
FOR_EACH_SUBRTX (iter, array, x, ALL)
- if (GET_CODE (*iter) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (*iter) != 0)
+ if (SYMBOL_REF_P (*iter) && SYMBOL_REF_TLS_MODEL (*iter) != 0)
return true;
return false;
}
diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c
index 247c3dbbe3f..2d5073dd79a 100644
--- a/gcc/sched-deps.c
+++ b/gcc/sched-deps.c
@@ -3569,7 +3569,7 @@ call_may_noreturn_p (rtx_insn *insn)
return false;
call = get_call_rtx_from (insn);
- if (call && GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (call && SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol)
diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index 98f2fe112f1..2d3ec52bd93 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -247,7 +247,7 @@ avoid_constant_pool_reference (rtx x)
/* If this is a constant pool reference, we can turn it into its
constant and hope that simplifications happen. */
- if (GET_CODE (addr) == SYMBOL_REF
+ if (SYMBOL_REF_P (addr)
&& CONSTANT_POOL_ADDRESS_P (addr))
{
c = get_pool_constant (addr);
@@ -2262,12 +2262,12 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
than HOST_BITS_PER_WIDE_INT. */
if ((GET_CODE (op0) == CONST
- || GET_CODE (op0) == SYMBOL_REF
+ || SYMBOL_REF_P (op0)
|| LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, offset);
else if ((GET_CODE (op1) == CONST
- || GET_CODE (op1) == SYMBOL_REF
+ || SYMBOL_REF_P (op1)
|| LABEL_REF_P (op1))
&& poly_int_rtx_p (op0, &offset))
return plus_constant (mode, op1, offset);
@@ -2541,7 +2541,7 @@ simplify_binary_operation_1 (enum rtx_code code, machine_mode mode,
}
if ((GET_CODE (op0) == CONST
- || GET_CODE (op0) == SYMBOL_REF
+ || SYMBOL_REF_P (op0)
|| LABEL_REF_P (op0))
&& poly_int_rtx_p (op1, &offset))
return plus_constant (mode, op0, trunc_int_for_mode (-offset, mode));
diff --git a/gcc/symtab.c b/gcc/symtab.c
index 63e2820eb93..dbd2221db27 100644
--- a/gcc/symtab.c
+++ b/gcc/symtab.c
@@ -1377,7 +1377,7 @@ symtab_node::make_decl_local (void)
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);
@@ -1432,7 +1432,7 @@ symtab_node::copy_visibility_from (symtab_node *n)
return;
rtx symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
SYMBOL_REF_WEAK (symbol) = DECL_WEAK (decl);
diff --git a/gcc/tree-ssa-address.c b/gcc/tree-ssa-address.c
index 49bd7661fe3..8432a98bd47 100644
--- a/gcc/tree-ssa-address.c
+++ b/gcc/tree-ssa-address.c
@@ -150,7 +150,7 @@ gen_addr_rtx (machine_mode address_mode,
if (offset_p)
*offset_p = &XEXP (act_elem, 1);
- if (GET_CODE (symbol) == SYMBOL_REF
+ if (SYMBOL_REF_P (symbol)
|| LABEL_REF_P (symbol)
|| GET_CODE (symbol) == CONST)
act_elem = gen_rtx_CONST (address_mode, act_elem);
diff --git a/gcc/var-tracking.c b/gcc/var-tracking.c
index e0ee278e044..d978e62cf1a 100644
--- a/gcc/var-tracking.c
+++ b/gcc/var-tracking.c
@@ -5932,12 +5932,12 @@ reverse_op (rtx val, const_rtx expr, rtx_insn *insn)
if (GET_MODE (v->val_rtx) != GET_MODE (val))
return;
arg = XEXP (src, 1);
- if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
+ if (!CONST_INT_P (arg) && !SYMBOL_REF_P (arg))
{
arg = cselib_expand_value_rtx (arg, scratch_regs, 5);
if (arg == NULL_RTX)
return;
- if (!CONST_INT_P (arg) && GET_CODE (arg) != SYMBOL_REF)
+ if (!CONST_INT_P (arg) && !SYMBOL_REF_P (arg))
return;
}
ret = simplify_gen_binary (code, GET_MODE (val), val, arg);
@@ -6254,7 +6254,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
call = get_call_rtx_from (insn);
if (call)
{
- if (GET_CODE (XEXP (XEXP (call, 0), 0)) == SYMBOL_REF)
+ if (SYMBOL_REF_P (XEXP (XEXP (call, 0), 0)))
{
rtx symbol = XEXP (XEXP (call, 0), 0);
if (SYMBOL_REF_DECL (symbol))
@@ -6475,7 +6475,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
gcc_assert (GET_CODE (item) == VALUE);
val = CSELIB_VAL_PTR (item);
for (l = val->locs; l; l = l->next)
- if (GET_CODE (l->loc) == SYMBOL_REF
+ if (SYMBOL_REF_P (l->loc)
&& TREE_CONSTANT_POOL_ADDRESS_P (l->loc)
&& SYMBOL_REF_DECL (l->loc)
&& DECL_INITIAL (SYMBOL_REF_DECL (l->loc)))
@@ -6536,7 +6536,7 @@ prepare_call_arguments (basic_block bb, rtx_insn *insn)
if (x)
{
x = XEXP (XEXP (x, 0), 0);
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
/* Don't record anything. */;
else if (CONSTANT_P (x))
{
diff --git a/gcc/varasm.c b/gcc/varasm.c
index 5d69da0df96..036d8e455f2 100644
--- a/gcc/varasm.c
+++ b/gcc/varasm.c
@@ -1372,7 +1372,7 @@ make_decl_rtl (tree decl)
/* If the symbol has a SYMBOL_REF_BLOCK field, update it based
on the new decl information. */
if (MEM_P (x)
- && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (x, 0))
&& SYMBOL_REF_HAS_BLOCK_INFO_P (XEXP (x, 0)))
change_symbol_block (XEXP (x, 0), get_block_for_decl (decl));
@@ -1720,7 +1720,7 @@ get_fnname_from_decl (tree decl)
rtx x = DECL_RTL (decl);
gcc_assert (MEM_P (x));
x = XEXP (x, 0);
- gcc_assert (GET_CODE (x) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (x));
return XSTR (x, 0);
}
@@ -2247,7 +2247,7 @@ assemble_variable (tree decl, int top_level ATTRIBUTE_UNUSED,
}
gcc_assert (MEM_P (decl_rtl));
- gcc_assert (GET_CODE (XEXP (decl_rtl, 0)) == SYMBOL_REF);
+ gcc_assert (SYMBOL_REF_P (XEXP (decl_rtl, 0)));
symbol = XEXP (decl_rtl, 0);
/* If this symbol belongs to the tree constant pool, output the constant
@@ -2433,7 +2433,7 @@ assemble_external_real (tree decl)
{
rtx rtl = DECL_RTL (decl);
- if (MEM_P (rtl) && GET_CODE (XEXP (rtl, 0)) == SYMBOL_REF
+ if (MEM_P (rtl) && SYMBOL_REF_P (XEXP (rtl, 0))
&& !SYMBOL_REF_USED (XEXP (rtl, 0))
&& !incorporeal_function_p (decl))
{
@@ -4130,7 +4130,7 @@ mark_constants_in_pattern (rtx insn)
FOR_EACH_SUBRTX (iter, array, PATTERN (insn), ALL)
{
const_rtx x = *iter;
- if (GET_CODE (x) == SYMBOL_REF)
+ if (SYMBOL_REF_P (x))
{
if (CONSTANT_POOL_ADDRESS_P (x))
{
@@ -5568,7 +5568,7 @@ mark_weak (tree decl)
if (DECL_RTL_SET_P (decl)
&& MEM_P (DECL_RTL (decl))
&& XEXP (DECL_RTL (decl), 0)
- && GET_CODE (XEXP (DECL_RTL (decl), 0)) == SYMBOL_REF)
+ && SYMBOL_REF_P (XEXP (DECL_RTL (decl), 0)))
SYMBOL_REF_WEAK (XEXP (DECL_RTL (decl), 0)) = 1;
}
@@ -6968,7 +6968,7 @@ default_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
if (!MEM_P (rtl))
return;
symbol = XEXP (rtl, 0);
- if (GET_CODE (symbol) != SYMBOL_REF)
+ if (!SYMBOL_REF_P (symbol))
return;
flags = SYMBOL_REF_FLAGS (symbol) & SYMBOL_FLAG_HAS_BLOCK_INFO;
@@ -7494,7 +7494,7 @@ place_block_symbol (rtx symbol)
rtx target = DECL_RTL (snode->ultimate_alias_target ()->decl);
gcc_assert (MEM_P (target)
- && GET_CODE (XEXP (target, 0)) == SYMBOL_REF
+ && SYMBOL_REF_P (XEXP (target, 0))
&& SYMBOL_REF_HAS_BLOCK_INFO_P (XEXP (target, 0)));
target = XEXP (target, 0);
place_block_symbol (target);
diff --git a/gcc/xcoffout.h b/gcc/xcoffout.h
index d8a031268ff..0ab9e5d09c2 100644
--- a/gcc/xcoffout.h
+++ b/gcc/xcoffout.h
@@ -78,7 +78,7 @@ along with GCC; see the file COPYING3. If not see
\
/* If we are writing a function name, we must ensure that \
there is no storage-class suffix on the name. */ \
- if (CODE == N_FUN && GET_CODE (ADDR) == SYMBOL_REF) \
+ if (CODE == N_FUN && SYMBOL_REF_P (ADDR)) \
{ \
const char *_p = XSTR (ADDR, 0); \
if (*_p == '*') \
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 09/18] Add CONST_STRING_P rtx_code predicate.
2019-08-06 3:11 ` Arvind Sankar
` (15 preceding siblings ...)
2019-08-06 3:13 ` [PATCH v2 11/18] Use REG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh REG Arvind Sankar
@ 2019-08-06 3:19 ` Arvind Sankar
2019-08-06 6:56 ` [PATCH v2 17/18] Use SYMBOL_REF_P macro Arvind Sankar
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 3:19 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* rtl.h: Add a predicate macro for checking CONST_STRING.
1 file changed, 3 insertions(+)
diff --git a/gcc/rtl.h b/gcc/rtl.h
index 45e2b85867d..d02772b65be 100644
--- a/gcc/rtl.h
+++ b/gcc/rtl.h
@@ -821,6 +821,9 @@ struct GTY(()) rtvec_def {
/* Predicate yielding nonzero iff X is an rtx for a vector const. */
#define CONST_VECTOR_P(X) (GET_CODE (X) == CONST_VECTOR)
+/* Predicate yielding nonzero iff X is an rtx for an rtl string const. */
+#define CONST_STRING_P(X) (GET_CODE (X) == CONST_STRING)
+
/* Predicate yielding true iff X is an rtx for a integer const. */
#if TARGET_SUPPORTS_WIDE_INT
#define CONST_SCALAR_INT_P(X) \
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* [PATCH v2 17/18] Use SYMBOL_REF_P macro.
2019-08-06 3:11 ` Arvind Sankar
` (16 preceding siblings ...)
2019-08-06 3:19 ` [PATCH v2 09/18] Add CONST_STRING_P rtx_code predicate Arvind Sankar
@ 2019-08-06 6:56 ` Arvind Sankar
17 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-06 6:56 UTC (permalink / raw)
To: gcc-patches
2019-08-05 Arvind Sankar <nivedita@alum.mit.edu>
gcc/ChangeLog:
* dwarf2out.c: Convert GET_CODE (..) == SYMBOL_REF to
SYMBOL_REF_P (..).
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c
index b2b4f6d82b2..ea38963d177 100644
--- a/gcc/dwarf2out.c
+++ b/gcc/dwarf2out.c
@@ -23747,8 +23747,7 @@ gen_variable_die (tree decl, tree origin, dw_die_ref context_die)
if (single_element_loc_list_p (loc)
&& loc->expr->dw_loc_opc == DW_OP_addr
&& loc->expr->dw_loc_next == NULL
- && GET_CODE (loc->expr->dw_loc_oprnd1.v.val_addr)
- == SYMBOL_REF)
+ && SYMBOL_REF_P (loc->expr->dw_loc_oprnd1.v.val_addr))
{
rtx x = loc->expr->dw_loc_oprnd1.v.val_addr;
loc->expr->dw_loc_oprnd1.v.val_addr
--
2.21.0
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-05 18:29 ` Segher Boessenkool
2019-08-05 18:34 ` Arvind Sankar
@ 2019-08-08 16:48 ` Jeff Law
2019-08-08 17:01 ` Jakub Jelinek
` (2 more replies)
1 sibling, 3 replies; 33+ messages in thread
From: Jeff Law @ 2019-08-08 16:48 UTC (permalink / raw)
To: Segher Boessenkool, Arvind Sankar; +Cc: gcc-patches
On 8/5/19 12:29 PM, Segher Boessenkool wrote:
> On Mon, Aug 05, 2019 at 02:14:50PM -0400, Arvind Sankar wrote:
>> On Mon, Aug 05, 2019 at 12:48:46PM -0500, Segher Boessenkool wrote:
>>> First: do you have a copyright assignment? See
>>> https://gcc.gnu.org/contribute.html
>>> for instructions.
>>
>> Nope, is this really substantial enough to warrant one?
>
> Some might say it is, the sheer amount of code changed :-) If some
> maintainer okays it without assignment, that is fine with me of course.
>
> This is also easier if it is all machine-generated and nice simple
> patches :-)
If it's entirely machine generated and you don't want to do a copyright
assignment, then the way to go will be for someone with an assignment to
run the scripts and commit the change. Then we'd only need an
assignment if we wanted the scripts in the repo.
>
>>>> -/* Predicate yielding true iff X is an rtx for a double-int. */
>>>> +/* Predicate yielding true iff X is an rtx for a floating point constant. */
>>>> #define CONST_DOUBLE_AS_FLOAT_P(X) \
>>>> (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
>>>
>>> Is const_double really only used for floating point these days?
>
>> Are you asking if the CONST_DOUBLE_AS_INT_P possibility is dead code
>> now? That's beyond my current level of understanding of the code,
>> hopefully someone else will chime in.
>
> I am asking if the change to this comment is correct.
I thought we used CONST_DOUBLE for scalar constants that are wider than
a HOST_WIDE_INT, or perhaps wider than 2 HOST_WIDE_INTs. If that's
still the case, then the comment change is wrong.
Jeff
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-08 16:48 ` Jeff Law
@ 2019-08-08 17:01 ` Jakub Jelinek
2019-08-08 17:53 ` Segher Boessenkool
2019-08-08 19:26 ` Arvind Sankar
2 siblings, 0 replies; 33+ messages in thread
From: Jakub Jelinek @ 2019-08-08 17:01 UTC (permalink / raw)
To: Jeff Law; +Cc: Segher Boessenkool, Arvind Sankar, gcc-patches
On Thu, Aug 08, 2019 at 10:42:06AM -0600, Jeff Law wrote:
> >>>> -/* Predicate yielding true iff X is an rtx for a double-int. */
> >>>> +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> >>>> #define CONST_DOUBLE_AS_FLOAT_P(X) \
> >>>> (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
> >>>
> >>> Is const_double really only used for floating point these days?
No. But it is used for integers only if it has VOIDmode, so I
think the above comment change is fine.
CONST_DOUBLE isn't used for integers on targets that define
TARGET_SUPPORTS_WIDE_INT, but that is a minority of targets (though, the
most common ones).
Jakub
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-08 16:48 ` Jeff Law
2019-08-08 17:01 ` Jakub Jelinek
@ 2019-08-08 17:53 ` Segher Boessenkool
2019-08-08 19:26 ` Arvind Sankar
2 siblings, 0 replies; 33+ messages in thread
From: Segher Boessenkool @ 2019-08-08 17:53 UTC (permalink / raw)
To: Jeff Law; +Cc: Arvind Sankar, gcc-patches
On Thu, Aug 08, 2019 at 10:42:06AM -0600, Jeff Law wrote:
> On 8/5/19 12:29 PM, Segher Boessenkool wrote:
> > On Mon, Aug 05, 2019 at 02:14:50PM -0400, Arvind Sankar wrote:
> >> On Mon, Aug 05, 2019 at 12:48:46PM -0500, Segher Boessenkool wrote:
> >>> First: do you have a copyright assignment? See
> >>> https://gcc.gnu.org/contribute.html
> >>> for instructions.
> >>
> >> Nope, is this really substantial enough to warrant one?
> >
> > Some might say it is, the sheer amount of code changed :-) If some
> > maintainer okays it without assignment, that is fine with me of course.
> >
> > This is also easier if it is all machine-generated and nice simple
> > patches :-)
> If it's entirely machine generated and you don't want to do a copyright
> assignment, then the way to go will be for someone with an assignment to
> run the scripts and commit the change. Then we'd only need an
> assignment if we wanted the scripts in the repo.
(/me thinks someone set him up to volunteer for this... Well I guess
that was me who did that? Oh well.)
Yes, I'll do that, and I'll rewrite the script so it is maintainable
(as far as that is possible with REs :-) ).
That leaves the new predicates...
> >>>> -/* Predicate yielding true iff X is an rtx for a double-int. */
> >>>> +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> >>>> #define CONST_DOUBLE_AS_FLOAT_P(X) \
> >>>> (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
> >>>
> >>> Is const_double really only used for floating point these days?
> >
> >> Are you asking if the CONST_DOUBLE_AS_INT_P possibility is dead code
> >> now? That's beyond my current level of understanding of the code,
> >> hopefully someone else will chime in.
> >
> > I am asking if the change to this comment is correct.
> I thought we used CONST_DOUBLE for scalar constants that are wider than
> a HOST_WIDE_INT, or perhaps wider than 2 HOST_WIDE_INTs. If that's
> still the case, then the comment change is wrong.
Some lines above there is
/* Predicate yielding true iff X is an rtx for a double-int. */
#define CONST_DOUBLE_AS_INT_P(X) \
(GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) == VOIDmode)
so the change is actually good? But these macros should be moved
together.
Segher
^ permalink raw reply [flat|nested] 33+ messages in thread
* Re: Use predicates for RTL objects
2019-08-08 16:48 ` Jeff Law
2019-08-08 17:01 ` Jakub Jelinek
2019-08-08 17:53 ` Segher Boessenkool
@ 2019-08-08 19:26 ` Arvind Sankar
2 siblings, 0 replies; 33+ messages in thread
From: Arvind Sankar @ 2019-08-08 19:26 UTC (permalink / raw)
To: Jeff Law; +Cc: Segher Boessenkool, Arvind Sankar, gcc-patches
On Thu, Aug 08, 2019 at 10:42:06AM -0600, Jeff Law wrote:
> On 8/5/19 12:29 PM, Segher Boessenkool wrote:
> > On Mon, Aug 05, 2019 at 02:14:50PM -0400, Arvind Sankar wrote:
> >> On Mon, Aug 05, 2019 at 12:48:46PM -0500, Segher Boessenkool wrote:
> >>> First: do you have a copyright assignment? See
> >>> https://gcc.gnu.org/contribute.html
> >>> for instructions.
> >>
> >> Nope, is this really substantial enough to warrant one?
> >
> > Some might say it is, the sheer amount of code changed :-) If some
> > maintainer okays it without assignment, that is fine with me of course.
> >
> > This is also easier if it is all machine-generated and nice simple
> > patches :-)
> If it's entirely machine generated and you don't want to do a copyright
> assignment, then the way to go will be for someone with an assignment to
> run the scripts and commit the change. Then we'd only need an
> assignment if we wanted the scripts in the repo.
>
I have just got the forms from GNU, probably a few days to actually send
it in. I am not too fussed about how to do this particular change,
whatever's easiest.
>
>
> >
> >>>> -/* Predicate yielding true iff X is an rtx for a double-int. */
> >>>> +/* Predicate yielding true iff X is an rtx for a floating point constant. */
> >>>> #define CONST_DOUBLE_AS_FLOAT_P(X) \
> >>>> (GET_CODE (X) == CONST_DOUBLE && GET_MODE (X) != VOIDmode)
> >>>
> >>> Is const_double really only used for floating point these days?
> >
> >> Are you asking if the CONST_DOUBLE_AS_INT_P possibility is dead code
> >> now? That's beyond my current level of understanding of the code,
> >> hopefully someone else will chime in.
> >
> > I am asking if the change to this comment is correct.
> I thought we used CONST_DOUBLE for scalar constants that are wider than
> a HOST_WIDE_INT, or perhaps wider than 2 HOST_WIDE_INTs. If that's
> still the case, then the comment change is wrong.
>
> Jeff
Please note that this is the comment for CONST_DOUBLE_AS_FLOAT_P, not
CONST_DOUBLE_P. CONST_DOUBLE_AS_INT_P is the predicate to represent a
CONST_DOUBLE being used to store large integers, and, as I understand
it, it will be used if the target does not define TARGET_SUPPORTS_WIDE_INT.
At present, the comment for both CONST_DOUBLE_AS_INT_P and
CONST_DOUBLE_AS_FLOAT_P claim that they are the predicates for
double-int.
^ permalink raw reply [flat|nested] 33+ messages in thread
end of thread, other threads:[~2019-08-08 17:01 UTC | newest]
Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-02 17:38 Use predicates for RTL objects Arvind Sankar
2019-08-02 17:50 ` Segher Boessenkool
2019-08-02 17:55 ` Arvind Sankar
2019-08-02 18:53 ` Segher Boessenkool
2019-08-02 19:22 ` Arvind Sankar
2019-08-05 17:18 ` Arvind Sankar
[not found] ` <20190805170908.GA1044536@rani.riverdale.lan>
2019-08-05 17:49 ` Segher Boessenkool
2019-08-05 18:14 ` Arvind Sankar
2019-08-05 18:29 ` Segher Boessenkool
2019-08-05 18:34 ` Arvind Sankar
2019-08-08 16:48 ` Jeff Law
2019-08-08 17:01 ` Jakub Jelinek
2019-08-08 17:53 ` Segher Boessenkool
2019-08-08 19:26 ` Arvind Sankar
2019-08-06 3:11 ` Arvind Sankar
2019-08-06 3:11 ` [PATCH v2 03/18] Use CONST_INT_P macro Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 01/18] Fix CONST_DOUBLE_AS_FLOAT_P comment Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 14/18] Use LABEL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh LABEL_REF Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 15/18] Use LABEL_REF_P macro Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 06/18] Use CONST_DOUBLE_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_DOUBLE Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 12/18] Use SUBREG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SUBREG Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 13/18] Use MEM_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh MEM Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 08/18] Use CONST_VECTOR_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_VECTOR Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 07/18] Add CONST_VECTOR_P rtx_code predicate Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 10/18] Use CONST_STRING_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_STRING Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 04/18] Use CONST_WIDE_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_WIDE_INT_P Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 02/18] Use CONST_INT_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_INT Arvind Sankar
2019-08-06 3:12 ` [PATCH v2 05/18] Use CONST_FIXED_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh CONST_FIXED Arvind Sankar
2019-08-06 3:13 ` [PATCH v2 16/18] Use SYMBOL_REF_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh SYMBOL_REF Arvind Sankar
2019-08-06 3:13 ` [PATCH v2 18/18] Use DEBUG_INSN_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh DEBUG_INSN_P Arvind Sankar
2019-08-06 3:13 ` [PATCH v2 11/18] Use REG_P macro. Autogenerated patch by running ../contrib/rtl-pred.sh REG Arvind Sankar
2019-08-06 3:19 ` [PATCH v2 09/18] Add CONST_STRING_P rtx_code predicate Arvind Sankar
2019-08-06 6:56 ` [PATCH v2 17/18] Use SYMBOL_REF_P macro Arvind Sankar
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