From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 117387 invoked by alias); 12 Aug 2019 16:56:10 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 117379 invoked by uid 89); 12 Aug 2019 16:56:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-2.3 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.1 spammy=Switch, quarter, occupies X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 12 Aug 2019 16:56:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5733D15AB; Mon, 12 Aug 2019 09:56:07 -0700 (PDT) Received: from arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8AFE23F706; Mon, 12 Aug 2019 09:56:06 -0700 (PDT) Date: Mon, 12 Aug 2019 17:04:00 -0000 From: James Greenhalgh To: gcc-patches@gcc.gnu.org, richard.earnshaw@arm.com, marcus.shawcroft@arm.com, richard.sandiford@arm.com Cc: nd@arm.com Subject: Re: [AArch64] Make aarch64_classify_vector_mode use a switch statement Message-ID: <20190812165604.GB8207@arm.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) X-IsSubscribed: yes X-SW-Source: 2019-08/txt/msg00757.txt.bz2 On Wed, Aug 07, 2019 at 07:24:18PM +0100, Richard Sandiford wrote: > aarch64_classify_vector_mode used properties of a mode to test whether > the mode was a single Advanced SIMD vector, a single SVE vector, or a > tuple of SVE vectors. That works well for current trunk and is simpler > than checking for modes by name. > > However, for the ACLE and for planned autovec improvements, we also > need partial SVE vector modes that hold: > > - half of the available 32-bit elements > - a half or quarter of the available 16-bit elements > - a half, quarter, or eighth of the available 8-bit elements > > These should be packed in memory and unpacked in registers. E.g. > VNx2SI has half the number of elements of VNx4SI, and so is half the > size in memory. When stored in registers, each VNx2SI element occupies > the low 32 bits of a VNx2DI element, with the upper bits being undefined. > > The upshot is that: > > GET_MODE_SIZE (VNx4SImode) == 2 * GET_MODE_SIZE (VNx2SImode) > > since GET_MODE_SIZE must always be the memory size. This in turn means > that for fixed-length SVE, some partial modes can have the same size as > Advanced SIMD modes. We then need to be specific about which mode we're > dealing with. > > This patch prepares for that by switching based on the mode instead > of querying properties. > > A later patch makes sure that Advanced SIMD modes always win over > partial SVE vector modes in normal queries. > > Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. > OK to install? OK. Thanks, James > > Richard > > > 2019-08-07 Richard Sandiford > > gcc/ > * config/aarch64/aarch64.c (aarch64_classify_vector_mode): Switch > based on the mode instead of testing properties of it.