From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 73418 invoked by alias); 14 Aug 2019 22:28:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 73410 invoked by uid 89); 14 Aug 2019 22:28:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-10.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_ASCII_DIVIDERS,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 22:28:06 +0000 Received: from pps.filterd (m0098399.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x7EMDTFs021199 for ; Wed, 14 Aug 2019 18:28:05 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ucshwu2vx-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Wed, 14 Aug 2019 18:28:05 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 14 Aug 2019 23:28:04 +0100 Received: from b03cxnp08026.gho.boulder.ibm.com (9.17.130.18) by e32.co.us.ibm.com (192.168.1.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Wed, 14 Aug 2019 23:28:01 +0100 Received: from b03ledav003.gho.boulder.ibm.com (b03ledav003.gho.boulder.ibm.com [9.17.130.234]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7EMS0jZ55378364 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Wed, 14 Aug 2019 22:28:00 GMT Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 33FF46A04F; Wed, 14 Aug 2019 22:28:00 +0000 (GMT) Received: from b03ledav003.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A2B786A047; Wed, 14 Aug 2019 22:27:59 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.32.77.177]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Wed, 14 Aug 2019 22:27:59 +0000 (GMT) Date: Wed, 14 Aug 2019 23:10:00 -0000 From: Michael Meissner To: gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Michael Meissner , Alan Modra Subject: [PATCH], Patch #6 of 10, Add 'future' support to function attributes Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn , Alan Modra References: <20190814205732.GA11956@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190814205732.GA11956@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) x-cbid: 19081422-0004-0000-0000-00001535EAF9 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011591; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01246885; UDB=6.00658028; IPR=6.01028392; MB=3.00028177; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-14 22:28:03 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19081422-0005-0000-0000-00008CE0E4F4 Message-Id: <20190814222757.GF16578@ibm-toto.the-meissners.org> X-SW-Source: 2019-08/txt/msg01044.txt.bz2 This patch adds support for using cpu=future in the "target" function attribute, "target" pragma support, and "target_clones" function attributes. In addition, it adds support for the following arguments to __builtin_cpu_supports: "arch_3_1" Whether ISA 3.1 is supported by the machine; "mma" Whether the MMA extension is supported by the machine. The hwcap2 bits used in the auxv table will be appearing in future Linux kernels. At this present time, there is no support for: __builtin_cpu_is ("future") I have built each of the patches on a little endian power8 system and there were no regressions in either the bootstrap or make check operations. Can I check this patch into the trunk after the other patches have been checked in? [gcc] 2019-08-14 Michael Meissner * config/rs6000/ppc-auxv.h (PPC_FEATURE2_ARCH_3_1): New hwcap2 bit. (PPC_FEATURE2_MMA): New hwcap2 bit. * config/rs6000/rs6000-call.c (cpu_supports_info): Add arch 3.1 and mma bits. * config/rs6000/rs6000.c (rs6000_clone_map): Add 'future' system to target_clone support. [gcc/testsuite] 2019-08-14 Michael Meissner * gcc.target/powerpc/clone3.c: New test for using 'future' with the target_clones attribute. Index: gcc/config/rs6000/ppc-auxv.h =================================================================== --- gcc/config/rs6000/ppc-auxv.h (revision 274173) +++ gcc/config/rs6000/ppc-auxv.h (working copy) @@ -93,6 +93,9 @@ #define PPC_FEATURE2_SCV 0x00100000 #define PPC_FEATURE2_HTM_NO_SUSPEND 0x00080000 +/* These are not yet official. */ +#define PPC_FEATURE2_ARCH_3_1 0x00040000 +#define PPC_FEATURE2_MMA 0x00020000 /* Thread Control Block (TCB) offsets of the AT_PLATFORM, AT_HWCAP and AT_HWCAP2 values. These must match the values defined in GLIBC. */ Index: gcc/config/rs6000/rs6000-call.c =================================================================== --- gcc/config/rs6000/rs6000-call.c (revision 274173) +++ gcc/config/rs6000/rs6000-call.c (working copy) @@ -171,7 +171,9 @@ static const struct { "arch_3_00", PPC_FEATURE2_ARCH_3_00, 1 }, { "ieee128", PPC_FEATURE2_HAS_IEEE128, 1 }, { "darn", PPC_FEATURE2_DARN, 1 }, - { "scv", PPC_FEATURE2_SCV, 1 } + { "scv", PPC_FEATURE2_SCV, 1 }, + { "arch_3_1", PPC_FEATURE2_ARCH_3_1, 1 }, + { "mma", PPC_FEATURE2_MMA, 1 }, }; static void altivec_init_builtins (void); Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 274178) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -259,6 +259,7 @@ enum { CLONE_ISA_2_06, /* ISA 2.06 (power7). */ CLONE_ISA_2_07, /* ISA 2.07 (power8). */ CLONE_ISA_3_00, /* ISA 3.00 (power9). */ + CLONE_ISA_3_1, /* ISA 3.1 (future). */ CLONE_MAX }; @@ -274,6 +275,7 @@ static const struct clone_map rs6000_clone_map[CLO { OPTION_MASK_POPCNTD, "arch_2_06" }, /* ISA 2.06 (power7). */ { OPTION_MASK_P8_VECTOR, "arch_2_07" }, /* ISA 2.07 (power8). */ { OPTION_MASK_P9_VECTOR, "arch_3_00" }, /* ISA 3.00 (power9). */ + { OPTION_MASK_FUTURE, "arch_3_1" }, /* ISA 3.1 (future). */ }; Index: gcc/testsuite/gcc.target/powerpc/clone3.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/clone3.c (revision 0) +++ gcc/testsuite/gcc.target/powerpc/clone3.c (working copy) @@ -0,0 +1,33 @@ +/* { dg-do compile { target { powerpc*-*-linux* && lp64 } } } */ +/* { dg-options "-mdejagnu-cpu=power8 -O2" } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-require-effective-target ppc_cpu_supports_hw } */ + +/* Power9 (aka, ISA 3.0) has a MODSD instruction to do modulus, while Power8 + (aka, ISA 2.07) has to do modulus with divide and multiply. Make sure + both clone functions are generated. + + FUTURE has pc-relative instructions to access static values, while earlier + systems used TOC addressing. + + Restrict ourselves to Linux, since IFUNC might not be supported in other + operating systems. */ + +static long s; +long *p = &s; + +__attribute__((target_clones("cpu=future,cpu=power9,default"))) +long mod_func (long a, long b) +{ + return (a % b) + s; +} + +long mod_func_or (long a, long b, long c) +{ + return mod_func (a, b) | c; +} + +/* { dg-final { scan-assembler-times {\mdivd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmulld\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mmodsd\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpld\M} 1 } } */ -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.ibm.com, phone: +1 (978) 899-4797