From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 91789 invoked by alias); 3 Sep 2019 17:14:13 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 91781 invoked by uid 89); 3 Sep 2019 17:14:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00,FREEMAIL_FROM,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_NONE,SPF_PASS autolearn=ham version=3.3.1 spammy=HContent-Transfer-Encoding:8bit X-HELO: mail-lf1-f65.google.com Received: from mail-lf1-f65.google.com (HELO mail-lf1-f65.google.com) (209.85.167.65) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Sep 2019 17:14:11 +0000 Received: by mail-lf1-f65.google.com with SMTP id w6so8127940lfl.2 for ; Tue, 03 Sep 2019 10:14:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=ZMNXnvPBOEPQDhzZN4kdoFyscb5KW+K0aPIY7GNwOUk=; b=VcsJZ2FiuYjtN3CKbaYSYjxoopdECsg3Zdgg8OAwVfXh66kkkFFtBmyABrtfkSjQhc hpoEeWaMSBRZ0cfkbFrPqr2ltvEfZi9BFObQyacTtqyqcGDNvmJA8O29svt2gLEbXjbN fjgv3xjZhw3klinBAYmJzyLG6nUGAfkgxxp0UBvtCwK4IKLPGVtqYeA5m71mNKI81P7k +MiQT6BRiHCAB3Yon0XIgcmeOVHlkguW2ApltEsaNrP7qk8vP7c4m1sJ4oNkcDgRqx7Q DM+KWgvhL1Yw2fZtMrpse6zZQAC7M7UWtZbnerrkDFqVa+QAIyGOg7N6KEdDsxvhYA2D iMAQ== Return-Path: Received: from archie.internal.synopsys.com ([2a03:1b20:4:f011::21d]) by smtp.gmail.com with ESMTPSA id h3sm2930492ljj.42.2019.09.03.10.14.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Sep 2019 10:14:08 -0700 (PDT) From: Shahab Vahedi To: Claudiu Zissulescu Cc: Shahab Vahedi , gcc-patches@gcc.gnu.org, Francois Bedard Subject: [PATCH] [ARC] Pass along -mcode-density flag to the assembler Date: Tue, 03 Sep 2019 17:14:00 -0000 Message-Id: <20190903171357.26309-1-shahab.vahedi@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-SW-Source: 2019-09/txt/msg00137.txt.bz2 From: Shahab Vahedi This change makes sure that if the driver is invoked with "-mcode-density" flag, then the assembler will receive it too. gcc/ 2019-09-03 Sahahb Vahedi * config/arc/arc.h (ASM_SPEC): pass -mcode-density * gcc.target/arc/code-density-flag.c: New test. Signed-off-by: Shahab Vahedi --- gcc/config/arc/arc.h | 5 +-- .../gcc.target/arc/code-density-flag.c | 34 +++++++++++++++++++ 2 files changed, 37 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arc/code-density-flag.c diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h index 8dca0d2c4b2..05fba539295 100644 --- a/gcc/config/arc/arc.h +++ b/gcc/config/arc/arc.h @@ -96,8 +96,9 @@ extern const char *arc_cpu_to_as (int argc, const char **argv); #endif #undef ASM_SPEC -#define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ - "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} %{mfpu=fpuda*:-mfpuda}" +#define ASM_SPEC "%{mbig-endian|EB:-EB} %{EL} " \ + "%:cpu_to_as(%{mcpu=*:%*}) %{mspfp*} %{mdpfp*} " \ + "%{mfpu=fpuda*:-mfpuda} %{mcode-density}" #define OPTION_DEFAULT_SPECS \ {"cpu", "%{!mcpu=*:%{!mARC*:%{!marc*:%{!mA7:%{!mA6:-mcpu=%(VALUE)}}}}}" } diff --git a/gcc/testsuite/gcc.target/arc/code-density-flag.c b/gcc/testsuite/gcc.target/arc/code-density-flag.c new file mode 100644 index 00000000000..1ecf1a2ca29 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/code-density-flag.c @@ -0,0 +1,34 @@ +/* Produce code-dense instructions and the assembler must * + * be okay with it. An example would be: * + * * + * sub_s r3, r1, r3 * + * * + * While generally for _short instructions_ , it is not * + * allowed to have different registers as the first and * + * second operands, the code-dense mode allows it. * + * This test is about the fact that if "-mcode-density" is * + * passed to gcc driver as the flag, "as" must receive it * + * as well, else it is going to choke on such encodings. */ + +/* { dg-do assemble } */ +/* { dg-skip-if "" { ! { clmcpu } } } */ +/* { dg-options "-mcpu=em_mini -mcode-density" } */ + +typedef long long uint64_t; + +uint64_t f1(void) +{ + return 1; +} + +void f2(void) +{ + uint64_t start_us = 0; + while ((f1() - start_us) < 2); +} + +/* This is a tricky check, because it hardcodes register * + * numbers. Nevertheless, it is easier than coming up with * + * a regular expression that the first two operands should * + * not be the same. */ +/* { dg-final { scan-assembler "sub_s\\s+r3,r1,r3" } } */ -- 2.23.0