From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 127336 invoked by alias); 9 Sep 2019 15:49:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 127328 invoked by uid 89); 9 Sep 2019 15:49:42 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_0,GIT_PATCH_1,GIT_PATCH_2,GIT_PATCH_3,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx07-00178001.pphosted.com Received: from mx07-00178001.pphosted.com (HELO mx07-00178001.pphosted.com) (62.209.51.94) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 09 Sep 2019 15:49:41 +0000 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id x89FkKNK001257 for ; Mon, 9 Sep 2019 17:49:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=st.com; h=from : to : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=STMicroelectronics; bh=UjTVxNi35+SWpXUmMrOWcjwiZYhMTbLA3TwIKHC/6qA=; b=MxYTLxmiDbxmNeLYfqIHSnC/PD6ahrXZPvxvJJygMnV69VmLopFfSj1p1S0hxgP2iNIZ SezYRlLfXRVtF2qAh2ZpLSudBW2rYZxulnGRbaAwlnTsIELpmHDI7w0L16TCutHACZsx S/lO5EygXLnMIcRohwo7rBV3PG97sM2e32FLC4HO2Xo6AMdgtKCoXJC1+tRPsHxVcQGi CJp2c44+S3Wk+5mxv0LOdHHVvrVhL4DB/4d0DAInLy4mvbrxh/QIRkeGtZuufGI9UQSJ U8fPrEAnC11GT/f7AS7XqrHG6TrZT0b6qBqNoeP5mIQntlQcTOGR+6pIK0Du9y4ItHPH Lg== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com with ESMTP id 2uv212ekj9-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT) for ; Mon, 09 Sep 2019 17:49:39 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 0B28B23 for ; Mon, 9 Sep 2019 15:49:36 +0000 (GMT) Received: from Webmail-eu.st.com (sfhdag5node1.st.com [10.75.127.13]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6C5AE2B25FB for ; Mon, 9 Sep 2019 17:49:35 +0200 (CEST) Received: from gnb.st.com (10.75.127.46) by SFHDAG5NODE1.st.com (10.75.127.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 9 Sep 2019 17:49:35 +0200 From: Christophe Lyon To: Subject: [ARM/FDPIC v6 12/24] [ARM] FDPIC: Restore r9 after we call __aeabi_read_tp Date: Mon, 09 Sep 2019 15:49:00 -0000 Message-ID: <20190909154526.11630-13-christophe.lyon@st.com> In-Reply-To: <20190909154526.11630-1-christophe.lyon@st.com> References: <20190909154526.11630-1-christophe.lyon@st.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-IsSubscribed: yes X-SW-Source: 2019-09/txt/msg00545.txt.bz2 From: Christophe Lyon We call __aeabi_read_tp() to get the thread pointer. Since this is a function call, we have to restore the FDPIC register afterwards. 2019-XX-XX Christophe Lyon Mickaël Guêné gcc/ * config/arm/arm.c (arm_load_tp): Add FDPIC support. * config/arm/arm.md (FDPIC_REGNUM): New constant. (load_tp_soft_fdpic): New pattern. (load_tp_soft): Disable in FDPIC mode. Change-Id: I0811cc7c5df8f44dd8b8b1f4caf54c7d3609c414 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 5f1d2d4..c452771 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -8685,7 +8685,18 @@ arm_load_tp (rtx target) rtx tmp; - emit_insn (gen_load_tp_soft ()); + if (TARGET_FDPIC) + { + rtx fdpic_reg = gen_rtx_REG (Pmode, FDPIC_REGNUM); + rtx initial_fdpic_reg = get_hard_reg_initial_val (Pmode, FDPIC_REGNUM); + + emit_insn (gen_load_tp_soft_fdpic ()); + + /* Restore r9. */ + emit_insn (gen_restore_pic_register_after_call(fdpic_reg, initial_fdpic_reg)); + } + else + emit_insn (gen_load_tp_soft ()); tmp = gen_rtx_REG (SImode, R0_REGNUM); emit_move_insn (target, tmp); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 027febb..918271d 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -31,6 +31,7 @@ [(R0_REGNUM 0) ; First CORE register (R1_REGNUM 1) ; Second CORE register (R4_REGNUM 4) ; Fifth CORE register + (FDPIC_REGNUM 9) ; FDPIC register (IP_REGNUM 12) ; Scratch register (SP_REGNUM 13) ; Stack pointer (LR_REGNUM 14) ; Return address register @@ -11165,12 +11166,25 @@ ) ;; Doesn't clobber R1-R3. Must use r0 for the first operand. +(define_insn "load_tp_soft_fdpic" + [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) + (clobber (reg:SI FDPIC_REGNUM)) + (clobber (reg:SI LR_REGNUM)) + (clobber (reg:SI IP_REGNUM)) + (clobber (reg:CC CC_REGNUM))] + "TARGET_SOFT_TP && TARGET_FDPIC" + "bl\\t__aeabi_read_tp\\t@ load_tp_soft" + [(set_attr "conds" "clob") + (set_attr "type" "branch")] +) + +;; Doesn't clobber R1-R3. Must use r0 for the first operand. (define_insn "load_tp_soft" [(set (reg:SI 0) (unspec:SI [(const_int 0)] UNSPEC_TLS)) (clobber (reg:SI LR_REGNUM)) (clobber (reg:SI IP_REGNUM)) (clobber (reg:CC CC_REGNUM))] - "TARGET_SOFT_TP" + "TARGET_SOFT_TP && !TARGET_FDPIC" "bl\\t__aeabi_read_tp\\t@ load_tp_soft" [(set_attr "conds" "clob") (set_attr "type" "branch")] -- 2.6.3