From: Michael Meissner <meissner@linux.ibm.com>
To: Michael Meissner <meissner@linux.ibm.com>,
gcc-patches@gcc.gnu.org, segher@kernel.crashing.org,
dje.gcc@gmail.com
Subject: [PATCH], V4, patch #16 [Same as patch #5], Support DImode 34-bt constants
Date: Fri, 04 Oct 2019 13:07:00 -0000 [thread overview]
Message-ID: <20191004130746.GH561@ibm-tinman.the-meissners.org> (raw)
In-Reply-To: <20190918234214.GA27521@ibm-toto.the-meissners.org>
This is the same as patch #5, but re-issued after patches 9-15 replaced the old
patch #4.
This patch adds support for using PADDI (PLI) to load up 34-bit DImode
constants.
Using all of the patches in this series, I have bootstrapped the compiler on a
little endian power8 system and ran the regression tests. In addition, I have
built the Spec 2006 and 2017 benchmark suites, for -mcpu=power8, -mcpu=power9,
and -mcpu=future, and all of the benchmarks build. Can I check this into the
trunk?
2019-10-03 Michael Meissner <meissner@linux.ibm.com>
* config/rs6000/rs6000.c (num_insns_constant_gpr): Add support for
PADDI to load up and/or add 34-bit integer constants.
(rs6000_rtx_costs): Treat constants loaded up with PADDI with the
same cost as normal 16-bit constants.
* config/rs6000/rs6000.md (movdi_internal64): Add support to load
up 34-bit integer constants with PADDI.
(movdi integer constant splitter): Add comment about PADDI.
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c (revision 276544)
+++ gcc/config/rs6000/rs6000.c (working copy)
@@ -5523,7 +5523,7 @@ static int
num_insns_constant_gpr (HOST_WIDE_INT value)
{
/* signed constant loadable with addi */
- if (((unsigned HOST_WIDE_INT) value + 0x8000) < 0x10000)
+ if (SIGNED_16BIT_OFFSET_P (value))
return 1;
/* constant loadable with addis */
@@ -5531,6 +5531,10 @@ num_insns_constant_gpr (HOST_WIDE_INT va
&& (value >> 31 == -1 || value >> 31 == 0))
return 1;
+ /* PADDI can support up to 34 bit signed integers. */
+ else if (TARGET_PREFIXED_ADDR && SIGNED_34BIT_OFFSET_P (value))
+ return 1;
+
else if (TARGET_POWERPC64)
{
HOST_WIDE_INT low = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
@@ -20643,7 +20647,8 @@ rs6000_rtx_costs (rtx x, machine_mode mo
|| outer_code == PLUS
|| outer_code == MINUS)
&& (satisfies_constraint_I (x)
- || satisfies_constraint_L (x)))
+ || satisfies_constraint_L (x)
+ || satisfies_constraint_eI (x)))
|| (outer_code == AND
&& (satisfies_constraint_K (x)
|| (mode == SImode
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 276544)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -8805,24 +8805,24 @@ (define_split
[(pc)]
{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
-;; GPR store GPR load GPR move GPR li GPR lis GPR #
-;; FPR store FPR load FPR move AVX store AVX store AVX load
-;; AVX load VSX move P9 0 P9 -1 AVX 0/-1 VSX 0
-;; VSX -1 P9 const AVX const From SPR To SPR SPR<->SPR
-;; VSX->GPR GPR->VSX
+;; GPR store GPR load GPR move GPR li GPR lis GPR pli
+;; GPR # FPR store FPR load FPR move AVX store AVX store
+;; AVX load AVX load VSX move P9 0 P9 -1 AVX 0/-1
+;; VSX 0 VSX -1 P9 const AVX const From SPR To SPR
+;; SPR<->SPR VSX->GPR GPR->VSX
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r, r, r, r,
- m, ^d, ^d, wY, Z, $v,
- $v, ^wa, wa, wa, v, wa,
- wa, v, v, r, *h, *h,
- ?r, ?wa")
+ r, m, ^d, ^d, wY, Z,
+ $v, $v, ^wa, wa, wa, v,
+ wa, wa, v, v, r, *h,
+ *h, ?r, ?wa")
(match_operand:DI 1 "input_operand"
- "r, YZ, r, I, L, nF,
- ^d, m, ^d, ^v, $v, wY,
- Z, ^wa, Oj, wM, OjwM, Oj,
- wM, wS, wB, *h, r, 0,
- wa, r"))]
+ "r, YZ, r, I, L, eI,
+ nF, ^d, m, ^d, ^v, $v,
+ wY, Z, ^wa, Oj, wM, OjwM,
+ Oj, wM, wS, wB, *h, r,
+ 0, wa, r"))]
"TARGET_POWERPC64
&& (gpc_reg_operand (operands[0], DImode)
|| gpc_reg_operand (operands[1], DImode))"
@@ -8832,6 +8832,7 @@ (define_insn "*movdi_internal64"
mr %0,%1
li %0,%1
lis %0,%v1
+ li %0,%1
#
stfd%U0%X0 %1,%0
lfd%U1%X1 %0,%1
@@ -8855,26 +8856,28 @@ (define_insn "*movdi_internal64"
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *, *, *, *,
- fpstore, fpload, fpsimple, fpstore, fpstore, fpload,
- fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical,
- veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr, *,
- mftgpr, mffgpr")
+ *, fpstore, fpload, fpsimple, fpstore, fpstore,
+ fpload, fpload, veclogical,vecsimple, vecsimple, vecsimple,
+ veclogical, veclogical, vecsimple, vecsimple, mfjmpr, mtjmpr,
+ *, mftgpr, mffgpr")
(set_attr "size" "64")
(set_attr "length"
- "*, *, *, *, *, 20,
- *, *, *, *, *, *,
+ "*, *, *, *, *, *,
+ 20, *, *, *, *, *,
*, *, *, *, *, *,
- *, 8, *, *, *, *,
- *, *")
+ *, *, 8, *, *, *,
+ *, *, *")
(set_attr "isa"
- "*, *, *, *, *, *,
- *, *, *, p9v, p7v, p9v,
- p7v, *, p9v, p9v, p7v, *,
- *, p7v, p7v, *, *, *,
- p8v, p8v")])
+ "*, *, *, *, *, fut,
+ *, *, *, *, p9v, p7v,
+ p9v, p7v, *, p9v, p9v, p7v,
+ *, *, p7v, p7v, *, *,
+ *, p8v, p8v")])
; Some DImode loads are best done as a load of -1 followed by a mask
-; instruction.
+; instruction. On systems that support the PADDI (PLI) instruction,
+; num_insns_constant returns 1, so these splitter would not be used for things
+; that be loaded with PLI.
(define_split
[(set (match_operand:DI 0 "int_reg_operand_not_pseudo")
(match_operand:DI 1 "const_int_operand"))]
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797
next prev parent reply other threads:[~2019-10-04 13:07 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-18 23:42 PowerPC future machine patches, version 4 Michael Meissner
2019-09-18 23:49 ` [PATCH] V4, patch #1: Rework prefixed/pc-relative lookup Michael Meissner
2019-09-21 1:29 ` Segher Boessenkool
2019-09-23 17:49 ` Michael Meissner
2019-09-18 23:56 ` [PATCH], V4, patch #2: Add prefixed insn attribute Michael Meissner
2019-09-18 23:58 ` [PATCH], V4, patch #3: Fix up mov<mode>_64bit_dm Michael Meissner
2019-09-27 23:33 ` Segher Boessenkool
2019-09-19 0:06 ` [PATCH], V4, patch #4: Enable prefixed/pc-rel addressing Michael Meissner
2019-09-19 0:09 ` [PATCH] V4, patch #5: Use PLI (PADDI) to load up 34-bit DImode Michael Meissner
2019-09-19 0:11 ` [PATCH] V4, patch #6: Use PLI (PADDI) to load up 32-bit SImode constants Michael Meissner
2019-09-19 0:13 ` [PATCH] V4, patch #7: Use PADDI to add 34-bit constants Michael Meissner
2019-09-19 0:17 ` [PATCH] V4, patch #8: Enable -mpcrel on Linux 64-bit, but not on other targets Michael Meissner
2019-09-24 5:59 ` [PATCH] V4.1, patch #1: Rework prefixed/pc-relative lookup (revised) Michael Meissner
2019-09-27 22:59 ` Segher Boessenkool
2019-09-30 13:51 ` [PATCH, committed] V4.2, patch #1: Rework prefixed/pc-relative lookup (revised #2) Michael Meissner
2019-09-24 6:10 ` [PATCH], V4.1, patch #2: Add prefixed insn attribute (revised) Michael Meissner
2019-09-27 23:27 ` Segher Boessenkool
2019-09-30 13:53 ` [PATCH, committed], V4.2, patch #2: Add prefixed insn attribute (revised #2) Michael Meissner
2019-09-30 14:13 ` [PATCH], V4, patch #4.1: Enable prefixed/pc-rel addressing (revised) Michael Meissner
2019-10-01 23:56 ` Segher Boessenkool
2019-10-02 19:04 ` Michael Meissner
2019-10-02 22:52 ` Segher Boessenkool
2019-10-04 12:29 ` [PATCH], V4, patch #9 [part of patch #4.2], Add prefixed address offset checks Michael Meissner
2019-10-09 22:24 ` Segher Boessenkool
2019-10-09 23:41 ` Michael Meissner
2019-10-10 21:54 ` Segher Boessenkool
2019-10-09 23:44 ` Michael Meissner
2019-10-04 12:35 ` [PATCH], V4, patch #10 [part of patch #4.2], Set prefixed length for 128-bit non-vector type Michael Meissner
2019-10-04 12:41 ` [PATCH], V4, patch #11 [part of patch #4.2], Adjust insn cost for prefixed instructions Michael Meissner
2019-10-04 12:46 ` [PATCH], V4, patch #12 [part of patch #4.2], Update predicates Michael Meissner
2019-10-04 12:51 ` [PATCH], V4, patch #13 [part of patch #4.2], Update stack protect insns for prefixed addresses Michael Meissner
2019-10-04 12:56 ` [PATCH], V4, patch #14 [part of patch #4.2], Update vector 128-bit instruction sizes Michael Meissner
2019-10-04 13:02 ` [PATCH], V4, patch #15 [part of patch #4.2], Make vector extract/insert support prefixed instructions Michael Meissner
2019-10-04 13:07 ` Michael Meissner [this message]
2019-10-04 13:11 ` [PATCH], V4, patch #17 [Same as patch #6], Use PADDI to load up 32-bit SImode constants Michael Meissner
2019-10-04 13:14 ` [PATCH], V4, patch #18 [Same as patch #7], Use PADDI to add 34-bit constants Michael Meissner
2019-10-04 13:18 ` [PATCH], V4, patch #19 [Same as patch #8], Enable -mpcrel on Linux 64-bit systems Michael Meissner
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