Re: [PATCH] RISC-V: Include more registers in SIBCALL_REGS.

[Andrew Burgess <andrew.burgess@embecosm.com>]

* Jim Wilson <jimw@sifive.com> [2019-10-16 14:04:45 -0700]:

> This finishes the part 1 of 2 patch submitted by Andrew Burgess on Aug 19.
> This adds the argument registers but not t0 (aka x5) to SIBCALL_REGS.  It
> also adds the missing riscv_regno_to_class change.
> 
> Tested with cross riscv32-elf and riscv64-linux toolchain build and check.
> There were no regressions.  I see about a 0.01% code size reduction for the
> C and libstdc++ libraries.
> 
> Committed.

Thanks for doing this Jim.

I'm still working on part 2, I'm hoping to have a revised patch posted
by Monday next week.

Thanks again,
Andrew



> 
> Jim
> 
> 	gcc/
> 	* config/riscv/riscv.h (REG_CLASS_CONTENTS): Add argument passing
> 	regs to SIBCALL_REGS.
> 	* config/riscv/riscv.c (riscv_regno_to_class): Change argument
> 	passing regs to SIBCALL_REGS.
> ---
>  gcc/config/riscv/riscv.c | 6 +++---
>  gcc/config/riscv/riscv.h | 2 +-
>  2 files changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
> index b8a8778b92c..77a3ad94aa8 100644
> --- a/gcc/config/riscv/riscv.c
> +++ b/gcc/config/riscv/riscv.c
> @@ -256,9 +256,9 @@ enum riscv_microarchitecture_type riscv_microarchitecture;
>  const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {
>    GR_REGS,	GR_REGS,	GR_REGS,	GR_REGS,
>    GR_REGS,	GR_REGS,	SIBCALL_REGS,	SIBCALL_REGS,
> -  JALR_REGS,	JALR_REGS,	JALR_REGS,	JALR_REGS,
> -  JALR_REGS,	JALR_REGS,	JALR_REGS,	JALR_REGS,
> -  JALR_REGS,	JALR_REGS, 	JALR_REGS,	JALR_REGS,
> +  JALR_REGS,	JALR_REGS,	SIBCALL_REGS,	SIBCALL_REGS,
> +  SIBCALL_REGS,	SIBCALL_REGS,	SIBCALL_REGS,	SIBCALL_REGS,
> +  SIBCALL_REGS,	SIBCALL_REGS,	JALR_REGS,	JALR_REGS,
>    JALR_REGS,	JALR_REGS,	JALR_REGS,	JALR_REGS,
>    JALR_REGS,	JALR_REGS,	JALR_REGS,	JALR_REGS,
>    SIBCALL_REGS,	SIBCALL_REGS,	SIBCALL_REGS,	SIBCALL_REGS,
> diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h
> index 5fc9be8edbf..246494663f6 100644
> --- a/gcc/config/riscv/riscv.h
> +++ b/gcc/config/riscv/riscv.h
> @@ -400,7 +400,7 @@ enum reg_class
>  #define REG_CLASS_CONTENTS						\
>  {									\
>    { 0x00000000, 0x00000000, 0x00000000 },	/* NO_REGS */		\
> -  { 0xf00000c0, 0x00000000, 0x00000000 },	/* SIBCALL_REGS */	\
> +  { 0xf003fcc0, 0x00000000, 0x00000000 },	/* SIBCALL_REGS */	\
>    { 0xffffffc0, 0x00000000, 0x00000000 },	/* JALR_REGS */		\
>    { 0xffffffff, 0x00000000, 0x00000000 },	/* GR_REGS */		\
>    { 0x00000000, 0xffffffff, 0x00000000 },	/* FP_REGS */		\
> -- 
> 2.17.1
>