From: Mihail Ionescu <mihail.ionescu@foss.arm.com>
To: gcc-patches@gcc.gnu.org
Cc: <kyrylo.tkachov@arm.com>, <richard.earnshaw@arm.com>
Subject: [PATCH, GCC/ARM, 2/10] Add command line support for Armv8.1-M Mainline
Date: Wed, 23 Oct 2019 14:31:00 -0000 [thread overview]
Message-ID: <20191023143100.R2l6GRwe6jLhpfyUmgirSXM1oC4YoxugvW7c9rs2uOY@z> (raw)
In-Reply-To: <157182277387.27853.13331885863813614565.scripted-patch-series@arm.com>
[-- Attachment #1: Type: text/plain, Size: 9240 bytes --]
[PATCH, GCC/ARM, 2/10] Add command line support
Hi,
=== Context ===
This patch is part of a patch series to add support for Armv8.1-M
Mainline Security Extensions architecture. Its purpose is to add
command-line support for that new architecture.
=== Patch description ===
Besides the expected enabling of the new value for the -march
command-line option (-march=armv8.1-m.main) and its extensions (see
below), this patch disables support of the Security Extensions for this
newly added architecture. This is done both by not including the cmse
bit in the architecture description and by throwing an error message
when user request Armv8.1-M Mainline Security Extensions. Note that
Armv8-M Baseline and Mainline Security Extensions are still enabled.
Only extensions for already supported instructions are implemented in
this patch. Other extensions (MVE integer and float) will be added in
separate patches. The following configurations are allowed for Armv8.1-M
Mainline with regards to FPU and implemented in this patch:
+ no FPU (+nofp)
+ single precision VFPv5 with FP16 (+fp)
+ double precision VFPv5 with FP16 (+fp.dp)
ChangeLog entry are as follow:
*** gcc/ChangeLog ***
2019-10-23 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2019-10-23 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm-cpus.in (armv8_1m_main): New feature.
(ARMv4, ARMv4t, ARMv5t, ARMv5te, ARMv5tej, ARMv6, ARMv6j, ARMv6k,
ARMv6z, ARMv6kz, ARMv6zk, ARMv6t2, ARMv6m, ARMv7, ARMv7a, ARMv7ve,
ARMv7r, ARMv7m, ARMv7em, ARMv8a, ARMv8_1a, ARMv8_2a, ARMv8_3a,
ARMv8_4a, ARMv8_5a, ARMv8m_base, ARMv8m_main, ARMv8r): Reindent.
(ARMv8_1m_main): New feature group.
(armv8.1-m.main): New architecture.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm.c (arm_arch8_1m_main): Define and default initialize.
(arm_option_reconfigure_globals): Initialize arm_arch8_1m_main.
(arm_options_perform_arch_sanity_checks): Error out when targeting
Armv8.1-M Mainline Security Extensions.
* config/arm/arm.h (arm_arch8_1m_main): Declare.
*** gcc/testsuite/ChangeLog ***
2019-10-23 Mihail-Calin Ionescu <mihail.ionescu@arm.com>
2019-10-23 Thomas Preud'homme <thomas.preudhomme@arm.com>
* lib/target-supports.exp
(check_effective_target_arm_arch_v8_1m_main_ok): Define.
(add_options_for_arm_arch_v8_1m_main): Likewise.
(check_effective_target_arm_arch_v8_1m_main_multilib): Likewise.
Testing: bootstrapped on arm-linux-gnueabihf and arm-none-eabi; testsuite
shows no regression.
Is this ok for trunk?
Best regards,
Mihail
############### Attachment also inlined for ease of reply ###############
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index f8a3b3db67a537163bfe787d78c8f2edc4253ab3..652f2a4be9388fd7a74f0ec4615a292fd1cfcd36 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -126,6 +126,9 @@ define feature armv8_5
# M-Profile security extensions.
define feature cmse
+# Architecture rel 8.1-M.
+define feature armv8_1m_main
+
# Floating point and Neon extensions.
# VFPv1 is not supported in GCC.
@@ -223,21 +226,21 @@ define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_I
# -mfpu support.
define fgroup ALL_FP fp16 ALL_FPU_INTERNAL
-define fgroup ARMv4 armv4 notm
-define fgroup ARMv4t ARMv4 thumb
-define fgroup ARMv5t ARMv4t armv5t
-define fgroup ARMv5te ARMv5t armv5te
-define fgroup ARMv5tej ARMv5te
-define fgroup ARMv6 ARMv5te armv6 be8
-define fgroup ARMv6j ARMv6
-define fgroup ARMv6k ARMv6 armv6k
-define fgroup ARMv6z ARMv6
-define fgroup ARMv6kz ARMv6k quirk_armv6kz
-define fgroup ARMv6zk ARMv6k
-define fgroup ARMv6t2 ARMv6 thumb2
+define fgroup ARMv4 armv4 notm
+define fgroup ARMv4t ARMv4 thumb
+define fgroup ARMv5t ARMv4t armv5t
+define fgroup ARMv5te ARMv5t armv5te
+define fgroup ARMv5tej ARMv5te
+define fgroup ARMv6 ARMv5te armv6 be8
+define fgroup ARMv6j ARMv6
+define fgroup ARMv6k ARMv6 armv6k
+define fgroup ARMv6z ARMv6
+define fgroup ARMv6kz ARMv6k quirk_armv6kz
+define fgroup ARMv6zk ARMv6k
+define fgroup ARMv6t2 ARMv6 thumb2
# This is suspect. ARMv6-m doesn't really pull in any useful features
# from ARMv5* or ARMv6.
-define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8
+define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8
# This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
# integer SIMD instructions that are in ARMv6T2. */
define fgroup ARMv7 ARMv6m thumb2 armv7
@@ -256,6 +259,10 @@ define fgroup ARMv8_5a ARMv8_4a armv8_5 sb predres
define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv
define fgroup ARMv8m_main ARMv7m armv8 cmse
define fgroup ARMv8r ARMv8a
+# Feature cmse is omitted to disable Security Extensions support while secure
+# code compiled by GCC does not preserve FP context as allowed by Armv8.1-M
+# Mainline.
+define fgroup ARMv8_1m_main ARMv7m armv8 armv8_1m_main
# Useful combinations.
define fgroup VFPv2 vfpv2
@@ -644,6 +651,17 @@ begin arch armv8-r
option nofp remove ALL_FP
end arch armv8-r
+begin arch armv8.1-m.main
+ tune for cortex-m7
+ tune flags CO_PROC
+ base 8M_MAIN
+ isa ARMv8_1m_main
+# fp => FPv5-sp-d16; fp.dp => FPv5-d16
+ option fp add FPv5 fp16
+ option fp.dp add FPv5 FP_DBL fp16
+ option nofp remove ALL_FP
+end arch armv8.1-m.main
+
begin arch iwmmxt
tune for iwmmxt
tune flags LDSCHED STRONG XSCALE
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index aeb5b3fbf629e5cfae4d5f6d4d5f1a9c7752a511..d059969904cb39fbe583487e4fbb23d4f9838718 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -353,10 +353,13 @@ EnumValue
Enum(arm_arch) String(armv8-r) Value(28)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(29)
+Enum(arm_arch) String(armv8.1-m.main) Value(29)
EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(30)
+Enum(arm_arch) String(iwmmxt) Value(30)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(31)
Enum
Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8b67c9c3657b312be223ab60c01969958baa9ed3..307f1b59ba4456c901c8cb842d9961a740b6bb8d 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -456,6 +456,10 @@ extern int arm_arch8_3;
/* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
extern int arm_arch8_4;
+/* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline
+ extensions. */
+extern int arm_arch8_1m_main;
+
/* Nonzero if this chip supports the FP16 instructions extension of ARM
Architecture 8.2. */
extern int arm_fp16_inst;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 9f0975dc0710626ef46abecaa3a205e993821118..9aca9484a9cdc26d6afee25e81f06b4047df2174 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -903,6 +903,9 @@ int arm_arch8_3 = 0;
/* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
int arm_arch8_4 = 0;
+/* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline
+ extensions. */
+int arm_arch8_1m_main = 0;
/* Nonzero if this chip supports the FP16 instructions extension of ARM
Architecture 8.2. */
@@ -3642,6 +3645,8 @@ arm_option_reconfigure_globals (void)
arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2);
arm_arch8_3 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_3);
arm_arch8_4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_4);
+ arm_arch8_1m_main = bitmap_bit_p (arm_active_target.isa,
+ isa_bit_armv8_1m_main);
arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
@@ -3727,6 +3732,9 @@ arm_options_perform_arch_sanity_checks (void)
if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
sorry ("__fp16 and no ldrh");
+ if (use_cmse && arm_arch8_1m_main)
+ error ("ARMv8.1-M Mainline Security Extensions are unsupported");
+
if (use_cmse && !arm_arch_cmse)
error ("target CPU does not support ARMv8-M Security Extensions");
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 6a1aaca9691b7fe9ae5e0e5b1874c7af34a3a6e3..5688aa7a6b7e8dad28aa553755b657464071a982 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4242,10 +4242,11 @@ foreach { armfunc armflag armdefs } {
v8a "-march=armv8-a" __ARM_ARCH_8A__
v8_1a "-march=armv8.1-a" __ARM_ARCH_8A__
v8_2a "-march=armv8.2-a" __ARM_ARCH_8A__
+ v8r "-march=armv8-r" __ARM_ARCH_8R__
v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
__ARM_ARCH_8M_BASE__
v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
- v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
+ v8_1m_main "-march=armv8.1-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
proc check_effective_target_arm_arch_FUNC_ok { } {
return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
[-- Attachment #2: diff01.patch --]
[-- Type: text/plain, Size: 6617 bytes --]
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index f8a3b3db67a537163bfe787d78c8f2edc4253ab3..652f2a4be9388fd7a74f0ec4615a292fd1cfcd36 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -126,6 +126,9 @@ define feature armv8_5
# M-Profile security extensions.
define feature cmse
+# Architecture rel 8.1-M.
+define feature armv8_1m_main
+
# Floating point and Neon extensions.
# VFPv1 is not supported in GCC.
@@ -223,21 +226,21 @@ define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_I
# -mfpu support.
define fgroup ALL_FP fp16 ALL_FPU_INTERNAL
-define fgroup ARMv4 armv4 notm
-define fgroup ARMv4t ARMv4 thumb
-define fgroup ARMv5t ARMv4t armv5t
-define fgroup ARMv5te ARMv5t armv5te
-define fgroup ARMv5tej ARMv5te
-define fgroup ARMv6 ARMv5te armv6 be8
-define fgroup ARMv6j ARMv6
-define fgroup ARMv6k ARMv6 armv6k
-define fgroup ARMv6z ARMv6
-define fgroup ARMv6kz ARMv6k quirk_armv6kz
-define fgroup ARMv6zk ARMv6k
-define fgroup ARMv6t2 ARMv6 thumb2
+define fgroup ARMv4 armv4 notm
+define fgroup ARMv4t ARMv4 thumb
+define fgroup ARMv5t ARMv4t armv5t
+define fgroup ARMv5te ARMv5t armv5te
+define fgroup ARMv5tej ARMv5te
+define fgroup ARMv6 ARMv5te armv6 be8
+define fgroup ARMv6j ARMv6
+define fgroup ARMv6k ARMv6 armv6k
+define fgroup ARMv6z ARMv6
+define fgroup ARMv6kz ARMv6k quirk_armv6kz
+define fgroup ARMv6zk ARMv6k
+define fgroup ARMv6t2 ARMv6 thumb2
# This is suspect. ARMv6-m doesn't really pull in any useful features
# from ARMv5* or ARMv6.
-define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8
+define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8
# This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and
# integer SIMD instructions that are in ARMv6T2. */
define fgroup ARMv7 ARMv6m thumb2 armv7
@@ -256,6 +259,10 @@ define fgroup ARMv8_5a ARMv8_4a armv8_5 sb predres
define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv
define fgroup ARMv8m_main ARMv7m armv8 cmse
define fgroup ARMv8r ARMv8a
+# Feature cmse is omitted to disable Security Extensions support while secure
+# code compiled by GCC does not preserve FP context as allowed by Armv8.1-M
+# Mainline.
+define fgroup ARMv8_1m_main ARMv7m armv8 armv8_1m_main
# Useful combinations.
define fgroup VFPv2 vfpv2
@@ -644,6 +651,17 @@ begin arch armv8-r
option nofp remove ALL_FP
end arch armv8-r
+begin arch armv8.1-m.main
+ tune for cortex-m7
+ tune flags CO_PROC
+ base 8M_MAIN
+ isa ARMv8_1m_main
+# fp => FPv5-sp-d16; fp.dp => FPv5-d16
+ option fp add FPv5 fp16
+ option fp.dp add FPv5 FP_DBL fp16
+ option nofp remove ALL_FP
+end arch armv8.1-m.main
+
begin arch iwmmxt
tune for iwmmxt
tune flags LDSCHED STRONG XSCALE
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index aeb5b3fbf629e5cfae4d5f6d4d5f1a9c7752a511..d059969904cb39fbe583487e4fbb23d4f9838718 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -353,10 +353,13 @@ EnumValue
Enum(arm_arch) String(armv8-r) Value(28)
EnumValue
-Enum(arm_arch) String(iwmmxt) Value(29)
+Enum(arm_arch) String(armv8.1-m.main) Value(29)
EnumValue
-Enum(arm_arch) String(iwmmxt2) Value(30)
+Enum(arm_arch) String(iwmmxt) Value(30)
+
+EnumValue
+Enum(arm_arch) String(iwmmxt2) Value(31)
Enum
Name(arm_fpu) Type(enum fpu_type)
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 8b67c9c3657b312be223ab60c01969958baa9ed3..307f1b59ba4456c901c8cb842d9961a740b6bb8d 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -456,6 +456,10 @@ extern int arm_arch8_3;
/* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
extern int arm_arch8_4;
+/* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline
+ extensions. */
+extern int arm_arch8_1m_main;
+
/* Nonzero if this chip supports the FP16 instructions extension of ARM
Architecture 8.2. */
extern int arm_fp16_inst;
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index 9f0975dc0710626ef46abecaa3a205e993821118..9aca9484a9cdc26d6afee25e81f06b4047df2174 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -903,6 +903,9 @@ int arm_arch8_3 = 0;
/* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */
int arm_arch8_4 = 0;
+/* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline
+ extensions. */
+int arm_arch8_1m_main = 0;
/* Nonzero if this chip supports the FP16 instructions extension of ARM
Architecture 8.2. */
@@ -3642,6 +3645,8 @@ arm_option_reconfigure_globals (void)
arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_2);
arm_arch8_3 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_3);
arm_arch8_4 = bitmap_bit_p (arm_active_target.isa, isa_bit_armv8_4);
+ arm_arch8_1m_main = bitmap_bit_p (arm_active_target.isa,
+ isa_bit_armv8_1m_main);
arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb);
arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2);
arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale);
@@ -3727,6 +3732,9 @@ arm_options_perform_arch_sanity_checks (void)
if (!arm_arch4 && arm_fp16_format != ARM_FP16_FORMAT_NONE)
sorry ("__fp16 and no ldrh");
+ if (use_cmse && arm_arch8_1m_main)
+ error ("ARMv8.1-M Mainline Security Extensions are unsupported");
+
if (use_cmse && !arm_arch_cmse)
error ("target CPU does not support ARMv8-M Security Extensions");
diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
index 6a1aaca9691b7fe9ae5e0e5b1874c7af34a3a6e3..5688aa7a6b7e8dad28aa553755b657464071a982 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -4242,10 +4242,11 @@ foreach { armfunc armflag armdefs } {
v8a "-march=armv8-a" __ARM_ARCH_8A__
v8_1a "-march=armv8.1-a" __ARM_ARCH_8A__
v8_2a "-march=armv8.2-a" __ARM_ARCH_8A__
+ v8r "-march=armv8-r" __ARM_ARCH_8R__
v8m_base "-march=armv8-m.base -mthumb -mfloat-abi=soft"
__ARM_ARCH_8M_BASE__
v8m_main "-march=armv8-m.main -mthumb" __ARM_ARCH_8M_MAIN__
- v8r "-march=armv8-r" __ARM_ARCH_8R__ } {
+ v8_1m_main "-march=armv8.1-m.main -mthumb" __ARM_ARCH_8M_MAIN__ } {
eval [string map [list FUNC $armfunc FLAG $armflag DEFS $armdefs ] {
proc check_effective_target_arm_arch_FUNC_ok { } {
return [check_no_compiler_messages arm_arch_FUNC_ok assembly {
next prev parent reply other threads:[~2019-10-23 14:31 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 14:31 [PATCH, GCC/ARM, 0/10] Add support for Armv8.1-M Mainline Security Extension Mihail Ionescu
2019-10-23 14:31 ` Mihail Ionescu [this message]
2019-10-23 14:31 ` [PATCH, GCC/ARM, 5/10] Clear VFP registers with VSCCLRM Mihail Ionescu
2019-10-23 14:31 ` [PATCH, GCC/ARM, 4/10] Clear GPR with CLRM Mihail Ionescu
2019-10-23 14:31 ` [PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions Mihail Ionescu
2019-10-23 14:31 ` [PATCH, GCC/ARM, 1/10] Fix -mcmse check in libgcc Mihail Ionescu
2019-10-23 14:33 ` [PATCH, GCC/ARM, 6/10] Clear GPRs inline when calling nscall function Mihail Ionescu
2019-10-23 14:34 ` [PATCH, GCC/ARM, 7/10] Clear all VFP regs inline in hardfloat nscall functions Mihail Ionescu
2019-10-23 14:34 ` [PATCH, GCC/ARM, 9/10] Call nscall function with blxns Mihail Ionescu
2019-10-23 14:34 ` [PATCH, GCC/ARM, 10/10] Enable -mcmse Mihail Ionescu
2019-10-23 15:07 ` [PATCH, GCC/ARM, 8/10] Do lazy store & load inline when calling nscall function Mihail Ionescu
[not found] ` <27d47273-6c06-450c-81a3-cee0c7355577@VE1EUR03FT028.eop-EUR03.prod.protection.outlook.com>
2019-11-04 16:44 ` [PATCH, GCC/ARM, 1/10] Fix -mcmse check in libgcc Kyrill Tkachov
[not found] ` <b3358cc4-8ee5-4039-891d-229a653270cb@VE1EUR03FT005.eop-EUR03.prod.protection.outlook.com>
2019-11-04 16:49 ` [PATCH, GCC/ARM, 2/10] Add command line support for Armv8.1-M Mainline Kyrill Tkachov
2019-11-06 15:59 ` Kyrill Tkachov
2019-12-16 18:29 ` Mihail Ionescu
2019-12-17 10:24 ` Kyrill Tkachov
[not found] ` <38378aaf-a33f-40b1-8595-b65b16f74363@AM5EUR03FT051.eop-EUR03.prod.protection.outlook.com>
2019-11-06 16:12 ` [PATCH, GCC/ARM, 3/10] Save/restore FPCXTNS in nsentry functions Kyrill Tkachov
2019-12-16 18:30 ` Mihail Ionescu
2019-12-17 10:26 ` Kyrill Tkachov
[not found] ` <58a87082-6686-466f-84ed-1a8da281ecbb@DB5EUR03FT053.eop-EUR03.prod.protection.outlook.com>
2019-11-12 9:56 ` [PATCH, GCC/ARM, 4/10] Clear GPR with CLRM Kyrill Tkachov
2019-12-16 19:16 ` Mihail Ionescu
2019-12-17 10:27 ` Kyrill Tkachov
2019-12-18 13:29 ` Mihail Ionescu
2020-01-13 17:30 ` Kyrill Tkachov
2020-01-17 21:06 ` [PATCH] arm: fix rtl checking bootstrap (PR target/93312) Jakub Jelinek
2020-01-18 1:42 ` Jeff Law
[not found] ` <b15c924d-b109-4221-aded-5d859a1c48c6@AM5EUR03FT012.eop-EUR03.prod.protection.outlook.com>
2019-11-12 10:13 ` [PATCH, GCC/ARM, 5/10] Clear VFP registers with VSCCLRM Kyrill Tkachov
[not found] ` <67d2e066-3981-4959-b56d-05d59d8afa12@VE1EUR03FT030.eop-EUR03.prod.protection.outlook.com>
2019-11-12 10:19 ` [PATCH, GCC/ARM, 6/10] Clear GPRs inline when calling nscall function Kyrill Tkachov
[not found] ` <6f7c01d4-0459-41c8-bd16-928eb034c1be@VE1EUR03FT044.eop-EUR03.prod.protection.outlook.com>
2019-11-12 10:22 ` [PATCH, GCC/ARM, 7/10] Clear all VFP regs inline in hardfloat nscall functions Kyrill Tkachov
[not found] ` <ad64c6ab-11ff-4aad-942e-04e0f6d1d705@VE1EUR03FT027.eop-EUR03.prod.protection.outlook.com>
2019-11-12 10:24 ` [PATCH, GCC/ARM, 8/10] Do lazy store & load inline when calling nscall function Kyrill Tkachov
2019-12-18 13:39 ` Mihail Ionescu
[not found] ` <c58f33d1-930f-4d24-9564-26b812bd8b07@VE1EUR03FT028.eop-EUR03.prod.protection.outlook.com>
2019-11-12 10:25 ` [PATCH, GCC/ARM, 9/10] Call nscall function with blxns Kyrill Tkachov
2019-12-18 13:52 ` Mihail Ionescu
2019-12-18 17:00 ` Kyrill Tkachov
[not found] ` <e5be4cd4-6c85-48ba-809a-ee489e9da01a@AM5EUR03FT012.eop-EUR03.prod.protection.outlook.com>
2019-11-12 10:31 ` [PATCH, GCC/ARM, 10/10] Enable -mcmse Kyrill Tkachov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20191023143100.R2l6GRwe6jLhpfyUmgirSXM1oC4YoxugvW7c9rs2uOY@z \
--to=mihail.ionescu@foss.arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=kyrylo.tkachov@arm.com \
--cc=richard.earnshaw@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).