[PATCH 0/3][rs6000] Update RTL patterns for vector conversion

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* [PATCH 0/3][rs6000] Update RTL patterns for vector conversion
@ 2019-10-23  9:39 Kewen.Lin
  2019-10-23  9:40 ` [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp Kewen.Lin
                   ` (2 more replies)
  0 siblings, 3 replies; 10+ messages in thread
From: Kewen.Lin @ 2019-10-23  9:39 UTC (permalink / raw)
  To: GCC Patches; +Cc: Segher Boessenkool, Bill Schmidt

Hi,

This series of patches refactor and update RTL patterns for 
conversion between vector float and vector int. We use UNSPEC
in RTL pattern, but they can be replaced with some RTL operations
like fix/float/unsigned_fix/unsigned_float etc, to make them
common and general RTL optimization can recognize and optimize
them if possible.


   [rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp
   [rs6000] RTL pattern update on vector conversion with same vector
            element unit size
   [rs6000] RTL pattern update on vector conversion with different
            vector element unit size

 gcc/config/rs6000/rs6000-modes.def |   4 ++
 gcc/config/rs6000/rs6000.c         |   4 +-
 gcc/config/rs6000/vsx.md           | 352 ++++++++++++++++++++++++++++++++++++++++++++++++++++++----------------------------------------
 3 files changed, 210 insertions(+), 150 deletions(-)

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp
  2019-10-23  9:39 [PATCH 0/3][rs6000] Update RTL patterns for vector conversion Kewen.Lin
@ 2019-10-23  9:40 ` Kewen.Lin
  2019-10-30 18:02   ` Segher Boessenkool
  2019-10-23  9:42 ` [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size Kewen.Lin
  2019-10-23 10:15 ` [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff " Kewen.Lin
  2 siblings, 1 reply; 10+ messages in thread
From: Kewen.Lin @ 2019-10-23  9:40 UTC (permalink / raw)
  To: GCC Patches; +Cc: Segher Boessenkool, Bill Schmidt

[-- Attachment #1: Type: text/plain, Size: 476 bytes --]

Hi,

I noticed that vsx_xvcdpsp and vsx_xvcvdpsp are almost the same,
and vsx_xvcdpsp looks replaceable with vsx_xvcvdpsp since it's only
called by gen_*.

Bootstrapped and regress tested on powerpc64le-linux-gnu.


gcc/ChangeLog

2019-10-23  Kewen Lin  <linkw@gcc.gnu.org>

	* config/rs6000/vsx.md (vsx_xvcdpsp): Remove define_insn.
	(UNSPEC_VSX_XVCDPSP): Remove.
	* config/rs6000/rs6000.c (rs6000_generate_float2_double_code):
	Replace gen_vsx_xvcdpsp by gen_vsx_xvcvdpsp.


[-- Attachment #2: 0001.patch --]
[-- Type: text/plain, Size: 1819 bytes --]

From 8c6309c131b7614ed8d6aeb4ca2d3d89ab0b8d38 Mon Sep 17 00:00:00 2001
From: Kewen Lin <linkw@linux.ibm.com>
Date: Tue, 8 Oct 2019 01:51:06 -0500
Subject: [PATCH 1/3] Replace vsx_xvcdpsp by vsx_xvcvdpsp

---
 gcc/config/rs6000/rs6000.c | 4 ++--
 gcc/config/rs6000/vsx.md   | 9 ---------
 2 files changed, 2 insertions(+), 11 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index c2834bd..23898b1 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -25549,8 +25549,8 @@ rs6000_generate_float2_double_code (rtx dst, rtx src1, rtx src2)
   rtx_tmp2 = gen_reg_rtx (V4SFmode);
   rtx_tmp3 = gen_reg_rtx (V4SFmode);
 
-  emit_insn (gen_vsx_xvcdpsp (rtx_tmp2, rtx_tmp0));
-  emit_insn (gen_vsx_xvcdpsp (rtx_tmp3, rtx_tmp1));
+  emit_insn (gen_vsx_xvcvdpsp (rtx_tmp2, rtx_tmp0));
+  emit_insn (gen_vsx_xvcvdpsp (rtx_tmp3, rtx_tmp1));
 
   if (BYTES_BIG_ENDIAN)
     emit_insn (gen_p8_vmrgew_v4sf (dst, rtx_tmp2, rtx_tmp3));
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f54d343..d6f079c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -301,7 +301,6 @@
    UNSPEC_VSX_XVCVSXDDP
    UNSPEC_VSX_XVCVUXDDP
    UNSPEC_VSX_XVCVDPSXDS
-   UNSPEC_VSX_XVCDPSP
    UNSPEC_VSX_XVCVDPUXDS
    UNSPEC_VSX_SIGN_EXTEND
    UNSPEC_VSX_XVCVSPSXWS
@@ -2367,14 +2366,6 @@
   "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcdpsp"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-	(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_XVCDPSP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvdpsp %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 ;; Convert from 32-bit to 64-bit types
 ;; Provide both vector and scalar targets
 (define_insn "vsx_xvcvsxwdp"
-- 
2.7.4


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp
  2019-10-23  9:40 ` [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp Kewen.Lin
@ 2019-10-30 18:02   ` Segher Boessenkool
  0 siblings, 0 replies; 10+ messages in thread
From: Segher Boessenkool @ 2019-10-30 18:02 UTC (permalink / raw)
  To: Kewen.Lin; +Cc: GCC Patches, Bill Schmidt

Hi!

On Wed, Oct 23, 2019 at 05:39:14PM +0800, Kewen.Lin wrote:
> I noticed that vsx_xvcdpsp and vsx_xvcvdpsp are almost the same,
> and vsx_xvcdpsp looks replaceable with vsx_xvcvdpsp since it's only
> called by gen_*.

Okay for trunk.  Thanks!


Segher


> 2019-10-23  Kewen Lin  <linkw@gcc.gnu.org>
> 
> 	* config/rs6000/vsx.md (vsx_xvcdpsp): Remove define_insn.
> 	(UNSPEC_VSX_XVCDPSP): Remove.
> 	* config/rs6000/rs6000.c (rs6000_generate_float2_double_code):
> 	Replace gen_vsx_xvcdpsp by gen_vsx_xvcvdpsp.

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size
  2019-10-23  9:39 [PATCH 0/3][rs6000] Update RTL patterns for vector conversion Kewen.Lin
  2019-10-23  9:40 ` [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp Kewen.Lin
@ 2019-10-23  9:42 ` Kewen.Lin
  2019-10-30 18:04   ` Segher Boessenkool
  2019-10-23 10:15 ` [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff " Kewen.Lin
  2 siblings, 1 reply; 10+ messages in thread
From: Kewen.Lin @ 2019-10-23  9:42 UTC (permalink / raw)
  To: GCC Patches; +Cc: Segher Boessenkool, Bill Schmidt

[-- Attachment #1: Type: text/plain, Size: 620 bytes --]

Hi,

For those fixed point <-> floating point vector conversion with
same element unit size, such as: SP <-> SI, DP <-> DI, it's fine
to use the existing RTL operations like any_fix/any_float for them.

This patch is to update them with any_fix/any_float.

Bootstrapped and regress tested on powerpc64le-linux-gnu.


gcc/ChangeLog

2019-10-23  Kewen Lin  <linkw@gcc.gnu.org>

	* config/rs6000/vsx.md (UNSPEC_VSX_CV[SU]XWSP,
	UNSPEC_VSX_XVCV[SU]XDDP, UNSPEC_VSX_XVCVDP[SU]XDS,
	UNSPEC_VSX_XVCVSPSXWS): Remove.
	(vsx_xvcv[su]xddp, vsx_xvcvdp[su]xds, vsx_xvcvsp[su]xws,
	vsx_xvcv[su]xwsp): Update define_insn RTL patterns.

[-- Attachment #2: 0002.patch --]
[-- Type: text/plain, Size: 5995 bytes --]

From 39ae875d4ae6ce22e170aeb456ef307a1f5fd1e0 Mon Sep 17 00:00:00 2001
From: Kewen Lin <linkw@linux.ibm.com>
Date: Wed, 23 Oct 2019 02:56:48 -0500
Subject: [PATCH 2/3] Update RTL pattern on vector SP<->[SU]W DP<->[SU]D
 conversion

---
 gcc/config/rs6000/vsx.md | 105 +++++++++++++----------------------------------
 1 file changed, 28 insertions(+), 77 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d6f079c..83e4071 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -277,8 +277,6 @@
    UNSPEC_VSX_CVUXDSP
    UNSPEC_VSX_CVSPSXDS
    UNSPEC_VSX_CVSPUXDS
-   UNSPEC_VSX_CVSXWSP
-   UNSPEC_VSX_CVUXWSP
    UNSPEC_VSX_FLOAT2
    UNSPEC_VSX_UNS_FLOAT2
    UNSPEC_VSX_FLOATE
@@ -298,12 +296,7 @@
    UNSPEC_VSX_DIVSD
    UNSPEC_VSX_DIVUD
    UNSPEC_VSX_MULSD
-   UNSPEC_VSX_XVCVSXDDP
-   UNSPEC_VSX_XVCVUXDDP
-   UNSPEC_VSX_XVCVDPSXDS
-   UNSPEC_VSX_XVCVDPUXDS
    UNSPEC_VSX_SIGN_EXTEND
-   UNSPEC_VSX_XVCVSPSXWS
    UNSPEC_VSX_XVCVSPSXDS
    UNSPEC_VSX_VSLO
    UNSPEC_VSX_EXTRACT
@@ -2202,6 +2195,34 @@
 
 ;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long)
 
+(define_insn "vsx_xvcv<su>xwsp"
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+     (any_float:V4SF (match_operand:V4SI 1 "vsx_register_operand" "wa")))]
+  "VECTOR_UNIT_VSX_P (V4SFmode)"
+  "xvcv<su>xwsp %x0,%x1"
+  [(set_attr "type" "vecfloat")])
+
+(define_insn "vsx_xvcv<su>xddp"
+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
+        (any_float:V2DF (match_operand:V2DI 1 "vsx_register_operand" "wa")))]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+  "xvcv<su>xddp %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_insn "vsx_xvcvsp<su>xws"
+  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
+        (any_fix:V4SI (match_operand:V4SF 1 "vsx_register_operand" "wa")))]
+  "VECTOR_UNIT_VSX_P (V4SFmode)"
+  "xvcvsp<su>xws %x0,%x1"
+  [(set_attr "type" "vecfloat")])
+
+(define_insn "vsx_xvcvdp<su>xds"
+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
+        (any_fix:V2DI (match_operand:V2DF 1 "vsx_register_operand" "wa")))]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+  "xvcvdp<su>xds %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
 (define_expand "vsx_xvcvsxddp_scale"
   [(match_operand:V2DF 0 "vsx_register_operand")
    (match_operand:V2DI 1 "vsx_register_operand")
@@ -2217,14 +2238,6 @@
   DONE;
 })
 
-(define_insn "vsx_xvcvsxddp"
-  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-        (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
-                     UNSPEC_VSX_XVCVSXDDP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvsxddp %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 (define_expand "vsx_xvcvuxddp_scale"
   [(match_operand:V2DF 0 "vsx_register_operand")
    (match_operand:V2DI 1 "vsx_register_operand")
@@ -2240,14 +2253,6 @@
   DONE;
 })
 
-(define_insn "vsx_xvcvuxddp"
-  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-        (unspec:V2DF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
-                     UNSPEC_VSX_XVCVUXDDP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxddp %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 (define_expand "vsx_xvcvdpsxds_scale"
   [(match_operand:V2DI 0 "vsx_register_operand")
    (match_operand:V2DF 1 "vsx_register_operand")
@@ -2270,26 +2275,6 @@
 })
 
 ;; convert vector of 64-bit floating point numbers to vector of
-;; 64-bit signed integer
-(define_insn "vsx_xvcvdpsxds"
-  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-        (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
-                     UNSPEC_VSX_XVCVDPSXDS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvdpsxds %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
-;; convert vector of 32-bit floating point numbers to vector of
-;; 32-bit signed integer
-(define_insn "vsx_xvcvspsxws"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
-	(unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_XVCVSPSXWS))]
-  "VECTOR_UNIT_VSX_P (V4SFmode)"
-  "xvcvspsxws %x0,%x1"
-  [(set_attr "type" "vecfloat")])
-
-;; convert vector of 64-bit floating point numbers to vector of
 ;; 64-bit unsigned integer
 (define_expand "vsx_xvcvdpuxds_scale"
   [(match_operand:V2DI 0 "vsx_register_operand")
@@ -2312,24 +2297,6 @@
   DONE;
 })
 
-;; convert vector of 32-bit floating point numbers to vector of
-;; 32-bit unsigned integer
-(define_insn "vsx_xvcvspuxws"
-  [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa")
-	(unspec:V4SI [(match_operand:V4SF 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_XVCVSPSXWS))]
-  "VECTOR_UNIT_VSX_P (V4SFmode)"
-  "xvcvspuxws %x0,%x1"
-  [(set_attr "type" "vecfloat")])
-
-(define_insn "vsx_xvcvdpuxds"
-  [(set (match_operand:V2DI 0 "vsx_register_operand" "=wa")
-        (unspec:V2DI [(match_operand:V2DF 1 "vsx_register_operand" "wa")]
-                     UNSPEC_VSX_XVCVDPUXDS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvdpuxds %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 ;; Convert from 64-bit to 32-bit types
 ;; Note, favor the Altivec registers since the usual use of these instructions
 ;; is in vector converts and we need to use the Altivec vperm instruction.
@@ -2416,22 +2383,6 @@
   "xvcvspuxds %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvsxwsp"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-	(unspec:V4SF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVSXWSP))]
-  "VECTOR_UNIT_VSX_P (V4SFmode)"
-  "xvcvsxwsp %x0,%x1"
-  [(set_attr "type" "vecfloat")])
-
-(define_insn "vsx_xvcvuxwsp"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-	(unspec:V4SF[(match_operand:V4SI 1 "vsx_register_operand" "wa")]
-		    UNSPEC_VSX_CVUXWSP))]
-  "VECTOR_UNIT_VSX_P (V4SFmode)"
-  "xvcvuxwsp %x0,%x1"
-  [(set_attr "type" "vecfloat")])
-
 ;; Generate float2 double
 ;; convert two double to float
 (define_expand "float2_v2df"
-- 
2.7.4


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size
  2019-10-23  9:42 ` [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size Kewen.Lin
@ 2019-10-30 18:04   ` Segher Boessenkool
  0 siblings, 0 replies; 10+ messages in thread
From: Segher Boessenkool @ 2019-10-30 18:04 UTC (permalink / raw)
  To: Kewen.Lin; +Cc: GCC Patches, Bill Schmidt

Hi!

On Wed, Oct 23, 2019 at 05:40:35PM +0800, Kewen.Lin wrote:
> For those fixed point <-> floating point vector conversion with
> same element unit size, such as: SP <-> SI, DP <-> DI, it's fine
> to use the existing RTL operations like any_fix/any_float for them.
> 
> This patch is to update them with any_fix/any_float.

Okay for trunk.  Thanks!


Segher


> 2019-10-23  Kewen Lin  <linkw@gcc.gnu.org>
> 
> 	* config/rs6000/vsx.md (UNSPEC_VSX_CV[SU]XWSP,
> 	UNSPEC_VSX_XVCV[SU]XDDP, UNSPEC_VSX_XVCVDP[SU]XDS,
> 	UNSPEC_VSX_XVCVSPSXWS): Remove.
> 	(vsx_xvcv[su]xddp, vsx_xvcvdp[su]xds, vsx_xvcvsp[su]xws,
> 	vsx_xvcv[su]xwsp): Update define_insn RTL patterns.

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff unit size
  2019-10-23  9:39 [PATCH 0/3][rs6000] Update RTL patterns for vector conversion Kewen.Lin
  2019-10-23  9:40 ` [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp Kewen.Lin
  2019-10-23  9:42 ` [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size Kewen.Lin
@ 2019-10-23 10:15 ` Kewen.Lin
  2019-10-30 19:06   ` Segher Boessenkool
  2 siblings, 1 reply; 10+ messages in thread
From: Kewen.Lin @ 2019-10-23 10:15 UTC (permalink / raw)
  To: GCC Patches; +Cc: Segher Boessenkool, Bill Schmidt

[-- Attachment #1: Type: text/plain, Size: 1367 bytes --]

Hi,

Following the previous one 2/3, this patch is to update the
vector conversions between fixed point and floating point
with different element unit sizes, such as: SP <-> DI, DP <-> SI.

Bootstrap and regression testing just launched.


gcc/ChangeLog

2019-10-23  Kewen Lin  <linkw@gcc.gnu.org>

	* config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes.
	* config/rs6000/vsx.md (UNSPEC_VSX_CVDPSXWS, UNSPEC_VSX_CVSXDSP, 
	UNSPEC_VSX_CVUXDSP, UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove.
	(vsx_xvcvspdp): New define_expand, old one split to...
	(vsx_xvcvspdp_be): ... this.  New.  And...
	(vsx_xvcvspdp_le): ... this.  New.
	(vsx_xvcvdpsp): New define_expand, old one split to...
	(vsx_xvcvdpsp_be): ... this.  New.  And...
	(vsx_xvcvdpsp_le): ... this.  New.
	(vsx_xvcvdp[su]xws): New define_expand, old one split to...
	(vsx_xvcvdp<su>xws_be): ... this.  New.  And...
	(vsx_xvcvdp<su>xws_le): ... this.  New.
	(vsx_xvcv[su]xdsp): New define_expand, old one split to...
	(vsx_xvcv<su>xdsp_be): ... this.  New.  And...
	(vsx_xvcv<su>xdsp_le): ... this.  New.
	(vsx_xvcv[su]xwdp): New define_expand, old one split to...
	(vsx_xvcv<su>xwdp_be): ... this.  New.  And...
	(vsx_xvcv<su>xwdp_le): ... this.  New.
	(vsx_xvcvsp[su]xds): New define_expand, old one split to...
	(vsx_xvcvsp<su>xds_be): ... this.  New.  And...
	(vsx_xvcvsp<su>xds_le): ... this.  New.

[-- Attachment #2: 0003.patch --]
[-- Type: text/plain, Size: 12168 bytes --]

From 5315810c391b75661de9027ea2848d31390e1d8b Mon Sep 17 00:00:00 2001
From: Kewen Lin <linkw@linux.ibm.com>
Date: Wed, 23 Oct 2019 04:02:00 -0500
Subject: [PATCH 3/3] Update RTL pattern on vector fp/int 32bit <-> 64bit
 conversion

---
 gcc/config/rs6000/rs6000-modes.def |   4 +
 gcc/config/rs6000/vsx.md           | 240 +++++++++++++++++++++++++++----------
 2 files changed, 181 insertions(+), 63 deletions(-)

diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 677062c..449e176 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16);     /*       V8HF  V4SF V2DF */
 VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
 VECTOR_MODES (FLOAT, 32);     /*       V16HF V8SF V4DF */
 
+/* Half VMX/VSX vector (for select)  */
+VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
+VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */
+
 /* Replacement for TImode that only is allowed in GPRs.  We also use PTImode
    for quad memory atomic operations to force getting an even/odd register
    combination.  */
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 83e4071..44025f6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -265,7 +265,6 @@
 ;; Constants for creating unspecs
 (define_c_enum "unspec"
   [UNSPEC_VSX_CONCAT
-   UNSPEC_VSX_CVDPSXWS
    UNSPEC_VSX_CVDPUXWS
    UNSPEC_VSX_CVSPDP
    UNSPEC_VSX_CVHPSP
@@ -273,10 +272,6 @@
    UNSPEC_VSX_CVDPSPN
    UNSPEC_VSX_CVSXWDP
    UNSPEC_VSX_CVUXWDP
-   UNSPEC_VSX_CVSXDSP
-   UNSPEC_VSX_CVUXDSP
-   UNSPEC_VSX_CVSPSXDS
-   UNSPEC_VSX_CVSPUXDS
    UNSPEC_VSX_FLOAT2
    UNSPEC_VSX_UNS_FLOAT2
    UNSPEC_VSX_FLOATE
@@ -2106,22 +2101,69 @@
   "xscvdpsp %x0,%x1"
   [(set_attr "type" "fp")])
 
-(define_insn "vsx_xvcvspdp"
+(define_insn "vsx_xvcvspdp_be"
   [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-			      UNSPEC_VSX_CVSPDP))]
-  "VECTOR_UNIT_VSX_P (V4SFmode)"
+     (float_extend:V2DF
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 0) (const_int 2)]))))]
+  "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN"
+  "xvcvspdp %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_insn "vsx_xvcvspdp_le"
+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
+     (float_extend:V2DF
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 1) (const_int 3)]))))]
+  "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN"
   "xvcvspdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvdpsp"
+(define_expand "vsx_xvcvspdp"
+  [(match_operand:V2DF 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V4SFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1]));
+  DONE;
+})
+
+(define_insn "vsx_xvcvdpsp_be"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
-	(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")]
-			      UNSPEC_VSX_CVSPDP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
+     (float_truncate:V4SF
+       (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "v,wa")
+	 (vec_select:V2DF (match_dup 1)
+	   (parallel [(const_int 1) (const_int 0)])))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
   "xvcvdpsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
+(define_insn "vsx_xvcvdpsp_le"
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
+     (float_truncate:V4SF
+       (vec_concat:V4DF
+	 (vec_select:V2DF (match_operand:V2DF 1 "vsx_register_operand" "v,wa")
+	   (parallel [(const_int 1) (const_int 0)]))
+	 (match_dup 1))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
+  "xvcvdpsp %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_expand "vsx_xvcvdpsp"
+  [(match_operand:V4SF 0 "vsx_register_operand")
+   (match_operand:V2DF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvdpsp_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcvdpsp_le (operands[0], operands[1]));
+  DONE;
+})
+
 ;; xscvspdp, represent the scalar SF type as V4SF
 (define_insn "vsx_xscvspdp"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
@@ -2301,48 +2343,144 @@
 ;; Note, favor the Altivec registers since the usual use of these instructions
 ;; is in vector converts and we need to use the Altivec vperm instruction.
 
-(define_insn "vsx_xvcvdpsxws"
+;; Convert vector of 64-bit floating point numbers to vector of
+;; 32-bit signed/unsigned integers.
+(define_insn "vsx_xvcvdp<su>xws_be"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")]
-		     UNSPEC_VSX_CVDPSXWS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvdpsxws %x0,%x1"
+     (any_fix:V4SI
+       (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa")
+	 (vec_select:V2DF (match_dup 1)
+	   (parallel [(const_int 1) (const_int 0)])))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
+  "xvcvdp<su>xws %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvdpuxws"
+(define_insn "vsx_xvcvdp<su>xws_le"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")]
-		     UNSPEC_VSX_CVDPUXWS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvdpuxws %x0,%x1"
+     (any_fix:V4SI
+       (vec_concat:V4DF
+	 (vec_select:V2DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa")
+	   (parallel [(const_int 1) (const_int 0)]))
+	 (match_dup 1))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
+  "xvcvdp<su>xws %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvsxdsp"
-  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-	(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVSXDSP))]
+(define_expand "vsx_xvcvdp<su>xws"
+  [(match_operand:V4SI 0 "vsx_register_operand")
+   (match_operand:V2DF 1 "vsx_register_operand")
+   (any_fix (pc))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvsxdsp %x0,%x1"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvdp<su>xws_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcvdp<su>xws_le (operands[0], operands[1]));
+  DONE;
+})
+
+;; Convert vector of 64-bit signed/unsigned integers to vector of
+;; 32-bit floating point numbers.
+(define_insn "vsx_xvcv<su>xdsp_be"
+  [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
+     (any_float:V4SF
+       (vec_concat:V4DI (match_operand:V2DI 1 "vsx_register_operand" "wa")
+	 (vec_select:V2DI (match_dup 1)
+	   (parallel [(const_int 1) (const_int 0)])))))]
+  "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN"
+  "xvcv<su>xdsp %x0,%x1"
   [(set_attr "type" "vecfloat")])
 
-(define_insn "vsx_xvcvuxdsp"
+(define_insn "vsx_xvcv<su>xdsp_le"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa")
-	(unspec:V4SF [(match_operand:V2DI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVUXDSP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxdsp %x0,%x1"
+     (any_float:V4SF
+       (vec_concat:V4DI
+	 (vec_select:V2DI (match_operand:V2DI 1 "vsx_register_operand" "wa")
+	   (parallel [(const_int 1) (const_int 0)]))
+	 (match_dup 1))))]
+  "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN"
+  "xvcv<su>xdsp %x0,%x1"
+  [(set_attr "type" "vecfloat")])
+
+(define_expand "vsx_xvcv<su>xdsp"
+  [(match_operand:V4SF 0 "vsx_register_operand")
+   (match_operand:V2DI 1 "vsx_register_operand")
+   (any_float (pc))]
+  "VECTOR_UNIT_VSX_P (V4SFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcv<su>xdsp_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcv<su>xdsp_le (operands[0], operands[1]));
+  DONE;
+})
+
+;; Convert vector of 32-bit signed/unsigned integers to vector of
+;; 64-bit floating point numbers.
+(define_insn "vsx_xvcv<su>xwdp_be"
+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
+     (any_float:V2DF
+       (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
+	 (parallel [(const_int 0) (const_int 2)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
+  "xvcv<su>xwdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-;; Convert from 32-bit to 64-bit types
-;; Provide both vector and scalar targets
-(define_insn "vsx_xvcvsxwdp"
+(define_insn "vsx_xvcv<su>xwdp_le"
   [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-	(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVSXWDP))]
+     (any_float:V2DF
+       (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
+	 (parallel [(const_int 1) (const_int 3)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
+  "xvcv<su>xwdp %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_expand "vsx_xvcv<su>xwdp"
+  [(match_operand:V2DF 0 "vsx_register_operand")
+   (match_operand:V4SI 1 "vsx_register_operand")
+   (any_float (pc))]
   "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvsxwdp %x0,%x1"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcv<su>xwdp_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcv<su>xwdp_le (operands[0], operands[1]));
+  DONE;
+})
+
+;; Convert vector of 32-bit floating point numbers to vector of
+;; 64-bit signed/unsigned integers.
+(define_insn "vsx_xvcvsp<su>xds_be"
+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
+     (any_fix:V2DI
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 0) (const_int 2)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
+  "xvcvsp<su>xds %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_insn "vsx_xvcvsp<su>xds_le"
+  [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
+     (any_fix:V2DI
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 1) (const_int 3)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
+  "xvcvsp<su>xds %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
+(define_expand "vsx_xvcvsp<su>xds"
+  [(match_operand:V2DI 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")
+   (any_fix (pc))]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvsp<su>xds_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcvsp<su>xds_le (operands[0], operands[1]));
+  DONE;
+})
+
 (define_insn "vsx_xvcvsxwdp_df"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
@@ -2351,14 +2489,6 @@
   "xvcvsxwdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvuxwdp"
-  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-	(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVUXWDP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxwdp %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 (define_insn "vsx_xvcvuxwdp_df"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
@@ -2367,22 +2497,6 @@
   "xvcvuxwdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvspsxds"
-  [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-		     UNSPEC_VSX_CVSPSXDS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvspsxds %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
-(define_insn "vsx_xvcvspuxds"
-  [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-		     UNSPEC_VSX_CVSPUXDS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvspuxds %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 ;; Generate float2 double
 ;; convert two double to float
 (define_expand "float2_v2df"
-- 
2.7.4


^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff unit size
  2019-10-23 10:15 ` [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff " Kewen.Lin
@ 2019-10-30 19:06   ` Segher Boessenkool
  2019-10-31  9:35     ` [PATCH 3/3 V2][rs6000] " Kewen.Lin
  0 siblings, 1 reply; 10+ messages in thread
From: Segher Boessenkool @ 2019-10-30 19:06 UTC (permalink / raw)
  To: Kewen.Lin; +Cc: GCC Patches, Bill Schmidt

Hi!

On Wed, Oct 23, 2019 at 05:42:45PM +0800, Kewen.Lin wrote:
> Following the previous one 2/3, this patch is to update the
> vector conversions between fixed point and floating point
> with different element unit sizes, such as: SP <-> DI, DP <-> SI.

> 	(vsx_xvcvdp[su]xws): New define_expand, old one split to...

You mean <su> here, please fix (never use wildcards like [su] in changelogs:
people grep for things in changelogs, which misses entries with wildcards).

> +/* Half VMX/VSX vector (for select)  */
> +VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
> +VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */

Or "for internal use", in general.  What happens if a user tries to create
something of such a mode?  I hope we don't ICE :-/

> -(define_insn "vsx_xvcvspdp"
> +(define_insn "vsx_xvcvspdp_be"
>    [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
> -	(unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
> -			      UNSPEC_VSX_CVSPDP))]
> -  "VECTOR_UNIT_VSX_P (V4SFmode)"
> +     (float_extend:V2DF
> +       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
> +	 (parallel [(const_int 0) (const_int 2)]))))]
> +  "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN"
> +  "xvcvspdp %x0,%x1"
> +  [(set_attr "type" "vecdouble")])
> +
> +(define_insn "vsx_xvcvspdp_le"
> +  [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
> +     (float_extend:V2DF
> +       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
> +	 (parallel [(const_int 1) (const_int 3)]))))]
> +  "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN"
>    "xvcvspdp %x0,%x1"
>    [(set_attr "type" "vecdouble")])

It would be nice if there was a nicer way to describe this, but this is
the best I can see to do as well.

> +;; Convert vector of 64-bit floating point numbers to vector of
> +;; 32-bit signed/unsigned integers.
> +(define_insn "vsx_xvcvdp<su>xws_be"
>    [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa")
> -	(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")]
> -		     UNSPEC_VSX_CVDPSXWS))]
> -  "VECTOR_UNIT_VSX_P (V2DFmode)"
> -  "xvcvdpsxws %x0,%x1"
> +     (any_fix:V4SI
> +       (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa")
> +	 (vec_select:V2DF (match_dup 1)
> +	   (parallel [(const_int 1) (const_int 0)])))))]
> +  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
> +  "xvcvdp<su>xws %x0,%x1"
>    [(set_attr "type" "vecdouble")])

This doesn't work, I think: the insns actually leaves words 1 and 3
undefined, but this pattern gives them a meaning.

I don't think we can do better than unspecs for such insns.  Or change
the pattern to only describe the defined parts (this works for e.g. mulhw
that describes its result as SImode: its DImode result has the high half
undefined).

> +;; Convert vector of 32-bit signed/unsigned integers to vector of
> +;; 64-bit floating point numbers.
> +(define_insn "vsx_xvcv<su>xwdp_be"
> +  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
> +     (any_float:V2DF
> +       (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
> +	 (parallel [(const_int 0) (const_int 2)]))))]
> +  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
> +  "xvcv<su>xwdp %x0,%x1"
>    [(set_attr "type" "vecdouble")])

This one for example is fine: words 1 and 3 of the input are unused, but
that is just fine.


Segher

^ permalink raw reply	[flat|nested] 10+ messages in thread

* [PATCH 3/3 V2][rs6000] vector conversion RTL pattern update for diff unit size
  2019-10-30 19:06   ` Segher Boessenkool
@ 2019-10-31  9:35     ` Kewen.Lin
  2019-10-31 18:54       ` Segher Boessenkool
  0 siblings, 1 reply; 10+ messages in thread
From: Kewen.Lin @ 2019-10-31  9:35 UTC (permalink / raw)
  To: Segher Boessenkool; +Cc: GCC Patches, Bill Schmidt

[-- Attachment #1: Type: text/plain, Size: 3288 bytes --]

Hi Segher,

Thanks a lot for the comments.

on 2019/10/31 脡脧脦莽2:49, Segher Boessenkool wrote:
> Hi!
> 
> On Wed, Oct 23, 2019 at 05:42:45PM +0800, Kewen.Lin wrote:
>> Following the previous one 2/3, this patch is to update the
>> vector conversions between fixed point and floating point
>> with different element unit sizes, such as: SP <-> DI, DP <-> SI.
> 
>> 	(vsx_xvcvdp[su]xws): New define_expand, old one split to...
> 
> You mean <su> here, please fix (never use wildcards like [su] in changelogs:
> people grep for things in changelogs, which misses entries with wildcards).
> 

OK, will fix it.

>> +/* Half VMX/VSX vector (for select)  */
>> +VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
>> +VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */
> 
> Or "for internal use", in general.  What happens if a user tries to create
> something of such a mode?  I hope we don't ICE :-/
> 

I did some testings, it failed (ICE) if we constructed one insn with these 
modes artificially.  But I also checked the existing V8SF/V8SI/V4DF/... etc.,
they have same issues.  It looks more like a new issue to avoid that.

>> +;; Convert vector of 64-bit floating point numbers to vector of
>> +;; 32-bit signed/unsigned integers.
>> +(define_insn "vsx_xvcvdp<su>xws_be"
>>    [(set (match_operand:V4SI 0 "vsx_register_operand" "=v,?wa")
>> -	(unspec:V4SI [(match_operand:V2DF 1 "vsx_register_operand" "wa,wa")]
>> -		     UNSPEC_VSX_CVDPSXWS))]
>> -  "VECTOR_UNIT_VSX_P (V2DFmode)"
>> -  "xvcvdpsxws %x0,%x1"
>> +     (any_fix:V4SI
>> +       (vec_concat:V4DF (match_operand:V2DF 1 "vsx_register_operand" "wa,wa")
>> +	 (vec_select:V2DF (match_dup 1)
>> +	   (parallel [(const_int 1) (const_int 0)])))))]
>> +  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
>> +  "xvcvdp<su>xws %x0,%x1"
>>    [(set_attr "type" "vecdouble")])
> 
> This doesn't work, I think: the insns actually leaves words 1 and 3
> undefined, but this pattern gives them a meaning.
> 
> I don't think we can do better than unspecs for such insns.  Or change
> the pattern to only describe the defined parts (this works for e.g. mulhw
> that describes its result as SImode: its DImode result has the high half
> undefined).
> 

Good point, thanks!  I agree, the current implementation for 64bit -> 32bit
RTL pattern has different semantics to what the instructions represent.
I was trying to find something represent undefined or random register value
and with twice vec_concat, but failed to.  I'll recover the change for the 
64bit -> 32bit part.

Updated patch attached, new regression testing just launched.


BR,
Kewen

-----------------

gcc/ChangeLog

2019-10-31  Kewen Lin  <linkw@gcc.gnu.org>

	* config/rs6000/rs6000-modes.def (V2SF, V2SI): New modes.
	* config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove.
	(vsx_xvcvspdp): New define_expand, old define_insn split to...
	(vsx_xvcvspdp_be): ... this.  New.  And...
	(vsx_xvcvspdp_le): ... this.  New.
	(vsx_xvcv<su>xwdp): New define_expand, old define_insn split to...
	(vsx_xvcv<su>xwdp_be): ... this.  New.  And...
	(vsx_xvcv<su>xwdp_le): ... this.  New.
	(vsx_xvcvsp<su>xds): New define_expand, old define_insn split to...
	(vsx_xvcvsp<su>xds_be): ... this.  New.  And...
	(vsx_xvcvsp<su>xds_le): ... this.  New.

[-- Attachment #2: unspecv2.diff --]
[-- Type: text/plain, Size: 6594 bytes --]

diff --git a/gcc/config/rs6000/rs6000-modes.def b/gcc/config/rs6000/rs6000-modes.def
index 677062c..2051358 100644
--- a/gcc/config/rs6000/rs6000-modes.def
+++ b/gcc/config/rs6000/rs6000-modes.def
@@ -74,6 +74,10 @@ VECTOR_MODES (FLOAT, 16);     /*       V8HF  V4SF V2DF */
 VECTOR_MODES (INT, 32);       /* V32QI V16HI V8SI V4DI */
 VECTOR_MODES (FLOAT, 32);     /*       V16HF V8SF V4DF */
 
+/* Half VMX/VSX vector (for internal use)  */
+VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
+VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */
+
 /* Replacement for TImode that only is allowed in GPRs.  We also use PTImode
    for quad memory atomic operations to force getting an even/odd register
    combination.  */
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 83e4071..99b51cb 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -275,8 +275,6 @@
    UNSPEC_VSX_CVUXWDP
    UNSPEC_VSX_CVSXDSP
    UNSPEC_VSX_CVUXDSP
-   UNSPEC_VSX_CVSPSXDS
-   UNSPEC_VSX_CVSPUXDS
    UNSPEC_VSX_FLOAT2
    UNSPEC_VSX_UNS_FLOAT2
    UNSPEC_VSX_FLOATE
@@ -2106,14 +2104,36 @@
   "xscvdpsp %x0,%x1"
   [(set_attr "type" "fp")])
 
-(define_insn "vsx_xvcvspdp"
+(define_insn "vsx_xvcvspdp_be"
   [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V2DF [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-			      UNSPEC_VSX_CVSPDP))]
-  "VECTOR_UNIT_VSX_P (V4SFmode)"
+     (float_extend:V2DF
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 0) (const_int 2)]))))]
+  "VECTOR_UNIT_VSX_P (V4SFmode) && BYTES_BIG_ENDIAN"
+  "xvcvspdp %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_insn "vsx_xvcvspdp_le"
+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=v,?wa")
+     (float_extend:V2DF
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 1) (const_int 3)]))))]
+  "VECTOR_UNIT_VSX_P (V4SFmode) && !BYTES_BIG_ENDIAN"
   "xvcvspdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
+(define_expand "vsx_xvcvspdp"
+  [(match_operand:V2DF 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")]
+  "VECTOR_UNIT_VSX_P (V4SFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvspdp_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcvspdp_le (operands[0], operands[1]));
+  DONE;
+})
+
 (define_insn "vsx_xvcvdpsp"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,?wa")
 	(unspec:V4SF [(match_operand:V2DF 1 "vsx_register_operand" "v,wa")]
@@ -2333,16 +2353,39 @@
   "xvcvuxdsp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-;; Convert from 32-bit to 64-bit types
-;; Provide both vector and scalar targets
-(define_insn "vsx_xvcvsxwdp"
+;; Convert vector of 32-bit signed/unsigned integers to vector of
+;; 64-bit floating point numbers.
+(define_insn "vsx_xvcv<su>xwdp_be"
   [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-	(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVSXWDP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvsxwdp %x0,%x1"
+     (any_float:V2DF
+       (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
+	 (parallel [(const_int 0) (const_int 2)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
+  "xvcv<su>xwdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
+(define_insn "vsx_xvcv<su>xwdp_le"
+  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
+     (any_float:V2DF
+       (vec_select:V2SI (match_operand:V4SI 1 "vsx_register_operand" "wa")
+	 (parallel [(const_int 1) (const_int 3)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
+  "xvcv<su>xwdp %x0,%x1"
+  [(set_attr "type" "vecdouble")])
+
+(define_expand "vsx_xvcv<su>xwdp"
+  [(match_operand:V2DF 0 "vsx_register_operand")
+   (match_operand:V4SI 1 "vsx_register_operand")
+   (any_float (pc))]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcv<su>xwdp_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcv<su>xwdp_le (operands[0], operands[1]));
+  DONE;
+})
+
 (define_insn "vsx_xvcvsxwdp_df"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
@@ -2351,14 +2394,6 @@
   "xvcvsxwdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvuxwdp"
-  [(set (match_operand:V2DF 0 "vsx_register_operand" "=wa")
-	(unspec:V2DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
-		     UNSPEC_VSX_CVUXWDP))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvuxwdp %x0,%x1"
-  [(set_attr "type" "vecdouble")])
-
 (define_insn "vsx_xvcvuxwdp_df"
   [(set (match_operand:DF 0 "vsx_register_operand" "=wa")
 	(unspec:DF [(match_operand:V4SI 1 "vsx_register_operand" "wa")]
@@ -2367,22 +2402,39 @@
   "xvcvuxwdp %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvspsxds"
+;; Convert vector of 32-bit floating point numbers to vector of
+;; 64-bit signed/unsigned integers.
+(define_insn "vsx_xvcvsp<su>xds_be"
   [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-		     UNSPEC_VSX_CVSPSXDS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvspsxds %x0,%x1"
+     (any_fix:V2DI
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 0) (const_int 2)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && BYTES_BIG_ENDIAN"
+  "xvcvsp<su>xds %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
-(define_insn "vsx_xvcvspuxds"
+(define_insn "vsx_xvcvsp<su>xds_le"
   [(set (match_operand:V2DI 0 "vsx_register_operand" "=v,?wa")
-	(unspec:V2DI [(match_operand:V4SF 1 "vsx_register_operand" "wa,wa")]
-		     UNSPEC_VSX_CVSPUXDS))]
-  "VECTOR_UNIT_VSX_P (V2DFmode)"
-  "xvcvspuxds %x0,%x1"
+     (any_fix:V2DI
+       (vec_select:V2SF (match_operand:V4SF 1 "vsx_register_operand" "wa,wa")
+	 (parallel [(const_int 1) (const_int 3)]))))]
+  "VECTOR_UNIT_VSX_P (V2DFmode) && !BYTES_BIG_ENDIAN"
+  "xvcvsp<su>xds %x0,%x1"
   [(set_attr "type" "vecdouble")])
 
+(define_expand "vsx_xvcvsp<su>xds"
+  [(match_operand:V2DI 0 "vsx_register_operand")
+   (match_operand:V4SF 1 "vsx_register_operand")
+   (any_fix (pc))]
+  "VECTOR_UNIT_VSX_P (V2DFmode)"
+{
+  if (BYTES_BIG_ENDIAN)
+    emit_insn (gen_vsx_xvcvsp<su>xds_be (operands[0], operands[1]));
+  else
+    emit_insn (gen_vsx_xvcvsp<su>xds_le (operands[0], operands[1]));
+  DONE;
+})
+
 ;; Generate float2 double
 ;; convert two double to float
 (define_expand "float2_v2df"

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 3/3 V2][rs6000] vector conversion RTL pattern update for diff unit size
  2019-10-31  9:35     ` [PATCH 3/3 V2][rs6000] " Kewen.Lin
@ 2019-10-31 18:54       ` Segher Boessenkool
  2019-11-01  2:21         ` Kewen.Lin
  0 siblings, 1 reply; 10+ messages in thread
From: Segher Boessenkool @ 2019-10-31 18:54 UTC (permalink / raw)
  To: Kewen.Lin; +Cc: GCC Patches, Bill Schmidt

Hi!

On Thu, Oct 31, 2019 at 05:35:22PM +0800, Kewen.Lin wrote:
> >> +/* Half VMX/VSX vector (for select)  */
> >> +VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
> >> +VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */
> > 
> > Or "for internal use", in general.  What happens if a user tries to create
> > something of such a mode?  I hope we don't ICE :-/
> 
> I did some testings, it failed (ICE) if we constructed one insn with these 
> modes artificially.  But I also checked the existing V8SF/V8SI/V4DF/... etc.,
> they have same issues.  It looks more like a new issue to avoid that.

What does "artificially" mean?  If you had to change the compiler for your
test, that doesn't count; otherwise, please file a PR.

> 	* config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove.

(line too long)

Okay for trunk.  Thanks!


Segher

^ permalink raw reply	[flat|nested] 10+ messages in thread

* Re: [PATCH 3/3 V2][rs6000] vector conversion RTL pattern update for diff unit size
  2019-10-31 18:54       ` Segher Boessenkool
@ 2019-11-01  2:21         ` Kewen.Lin
  0 siblings, 0 replies; 10+ messages in thread
From: Kewen.Lin @ 2019-11-01  2:21 UTC (permalink / raw)
  To: Segher Boessenkool; +Cc: GCC Patches, Bill Schmidt

Hi Segher,

on 2019/11/1 脡脧脦莽2:49, Segher Boessenkool wrote:
> Hi!
> 
> On Thu, Oct 31, 2019 at 05:35:22PM +0800, Kewen.Lin wrote:
>>>> +/* Half VMX/VSX vector (for select)  */
>>>> +VECTOR_MODE (FLOAT, SF, 2);   /*                 V2SF  */
>>>> +VECTOR_MODE (INT, SI, 2);     /*                 V2SI  */
>>>
>>> Or "for internal use", in general.  What happens if a user tries to create
>>> something of such a mode?  I hope we don't ICE :-/
>>
>> I did some testings, it failed (ICE) if we constructed one insn with these 
>> modes artificially.  But I also checked the existing V8SF/V8SI/V4DF/... etc.,
>> they have same issues.  It looks more like a new issue to avoid that.
> 
> What does "artificially" mean?  If you had to change the compiler for your
> test, that doesn't count; otherwise, please file a PR.
> 

Yes, I hacked the compiler to emit it directly.  OK, it's fine then.  :)

>> 	* config/rs6000/vsx.md (UNSPEC_VSX_CVSPSXDS, UNSPEC_VSX_CVSPUXDS): Remove.
> 
> (line too long)

Will fix it.

> 
> Okay for trunk.  Thanks!
> 

Thanks for your time!


BR,
Kewen

^ permalink raw reply	[flat|nested] 10+ messages in thread

end of thread, other threads:[~2019-11-01  2:21 UTC | newest]

Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-23  9:39 [PATCH 0/3][rs6000] Update RTL patterns for vector conversion Kewen.Lin
2019-10-23  9:40 ` [PATCH 1/3][rs6000] Replace vsx_xvcdpsp by vsx_xvcvdpsp Kewen.Lin
2019-10-30 18:02   ` Segher Boessenkool
2019-10-23  9:42 ` [PATCH 2/3][rs6000] vector conversion RTL pattern update for same unit size Kewen.Lin
2019-10-30 18:04   ` Segher Boessenkool
2019-10-23 10:15 ` [PATCH 3/3][rs6000] vector conversion RTL pattern update for diff " Kewen.Lin
2019-10-30 19:06   ` Segher Boessenkool
2019-10-31  9:35     ` [PATCH 3/3 V2][rs6000] " Kewen.Lin
2019-10-31 18:54       ` Segher Boessenkool
2019-11-01  2:21         ` Kewen.Lin

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