* [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64
@ 2019-11-14 10:07 Richard Henderson
2019-11-14 10:07 ` [PATCH v2 1/6] aarch64: Add "c" constraint Richard Henderson
` (6 more replies)
0 siblings, 7 replies; 26+ messages in thread
From: Richard Henderson @ 2019-11-14 10:07 UTC (permalink / raw)
To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford
I've put the implementation into config/arm/aarch-common.c, so
that it can be shared between the two targets. This required
a little bit of cleanup to the CC modes and constraints to get
the two targets to match up.
Changes for v2:
* Document overflow flags.
* Add "hs" and "lo" as aliases of "cs" and "cc".
* Add unsigned cmp tests to asm-flag-6.c.
Richard Sandiford has given his ack for the aarch64 side.
I'm still looking for an ack for the arm side.
r~
Richard Henderson (6):
aarch64: Add "c" constraint
arm: Fix the "c" constraint
arm: Rename CC_NOOVmode to CC_NZmode
arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__
arm: Add testsuite checks for asm-flag
aarch64: Add testsuite checks for asm-flag
gcc/config/arm/aarch-common-protos.h | 6 +
gcc/config/aarch64/aarch64-c.c | 2 +
gcc/config/aarch64/aarch64.c | 3 +
gcc/config/arm/aarch-common.c | 136 +++++++++++++
gcc/config/arm/arm-c.c | 1 +
gcc/config/arm/arm.c | 15 +-
gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 ++++
gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++
gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++
gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 ++++++
gcc/testsuite/gcc.target/arm/asm-flag-1.c | 36 ++++
gcc/testsuite/gcc.target/arm/asm-flag-3.c | 38 ++++
gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 +++
gcc/testsuite/gcc.target/arm/asm-flag-6.c | 62 ++++++
gcc/config/aarch64/constraints.md | 4 +
gcc/config/arm/arm-modes.def | 4 +-
gcc/config/arm/arm.md | 186 +++++++++---------
gcc/config/arm/constraints.md | 5 +-
gcc/config/arm/predicates.md | 2 +-
gcc/config/arm/thumb1.md | 8 +-
gcc/config/arm/thumb2.md | 34 ++--
gcc/doc/extend.texi | 39 ++++
22 files changed, 651 insertions(+), 125 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c
create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c
--
2.17.1
^ permalink raw reply [flat|nested] 26+ messages in thread* [PATCH v2 1/6] aarch64: Add "c" constraint 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson @ 2019-11-14 10:07 ` Richard Henderson 2019-11-14 10:07 ` [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson ` (5 subsequent siblings) 6 siblings, 0 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-14 10:07 UTC (permalink / raw) To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford Mirror arm in letting "c" match the condition code register. * config/aarch64/constraints.md (c): New constraint. --- gcc/config/aarch64/constraints.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md index d0c3dd5bc1f..b9e5d13e851 100644 --- a/gcc/config/aarch64/constraints.md +++ b/gcc/config/aarch64/constraints.md @@ -39,6 +39,10 @@ (define_register_constraint "y" "FP_LO8_REGS" "Floating point and SIMD vector registers V0 - V7.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) + (define_constraint "I" "A constant that can be used with an ADD operation." (and (match_code "const_int") -- 2.17.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson 2019-11-14 10:07 ` [PATCH v2 1/6] aarch64: Add "c" constraint Richard Henderson @ 2019-11-14 10:07 ` Richard Henderson 2019-11-14 14:42 ` Richard Earnshaw (lists) 2019-11-14 10:07 ` [PATCH v2 2/6] arm: Fix the "c" constraint Richard Henderson ` (4 subsequent siblings) 6 siblings, 1 reply; 26+ messages in thread From: Richard Henderson @ 2019-11-14 10:07 UTC (permalink / raw) To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford CC_NZmode is a more accurate description of what we require from the mode, and matches up with the definition in aarch64. Rename noov_comparison_operator to nz_comparison_operator in order to match. * config/arm/arm-modes.def (CC_NZ): Rename from CC_NOOV. * config/arm/predicates.md (nz_comparison_operator): Rename from noov_comparison_operator. * config/arm/arm.c (arm_select_cc_mode): Use CC_NZmode name. (arm_gen_dicompare_reg): Likewise. (maybe_get_arm_condition_code): Likewise. (thumb1_final_prescan_insn): Likewise. (arm_emit_coreregs_64bit_shift): Likewise. * config/arm/arm.md (addsi3_compare0): Likewise. (*addsi3_compare0_scratch, subsi3_compare0): Likewise. (*mulsi3_compare0, *mulsi3_compare0_v6): Likewise. (*mulsi3_compare0_scratch, *mulsi3_compare0_scratch_v6): Likewise. (*mulsi3addsi_compare0, *mulsi3addsi_compare0_v6): Likewise. (*mulsi3addsi_compare0_scratch): Likewise. (*mulsi3addsi_compare0_scratch_v6): Likewise. (*andsi3_compare0, *andsi3_compare0_scratch): Likewise. (*zeroextractsi_compare0_scratch): Likewise. (*ne_zeroextractsi, *ne_zeroextractsi_shifted): Likewise. (*ite_ne_zeroextractsi, *ite_ne_zeroextractsi_shifted): Likewise. (andsi_not_shiftsi_si_scc_no_reuse): Likewise. (andsi_not_shiftsi_si_scc): Likewise. (*andsi_notsi_si_compare0, *andsi_notsi_si_compare0_scratch): Likewise. (*iorsi3_compare0, *iorsi3_compare0_scratch): Likewise. (*xorsi3_compare0, *xorsi3_compare0_scratch): Likewise. (*shiftsi3_compare0, *shiftsi3_compare0_scratch): Likewise. (*not_shiftsi_compare0, *not_shiftsi_compare0_scratch): Likewise. (*notsi_compare0, *notsi_compare0_scratch): Likewise. (return_addr_mask, *check_arch2): Likewise. (*arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch): Likewise. (*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch): Likewise. (compare_scc splitters): Likewise. (movcond_addsi): Likewise. * config/arm/thumb2.md (thumb2_addsi3_compare0): Likewise. (*thumb2_addsi3_compare0_scratch): Likewise. (*thumb2_mulsi_short_compare0): Likewise. (*thumb2_mulsi_short_compare0_scratch): Likewise. (compare peephole2s): Likewise. * config/arm/thumb1.md (thumb1_cbz): Use CC_NZmode and nz_comparison_operator names. (cbranchsi4_insn): Likewise. --- gcc/config/arm/arm.c | 12 +-- gcc/config/arm/arm-modes.def | 4 +- gcc/config/arm/arm.md | 186 +++++++++++++++++------------------ gcc/config/arm/predicates.md | 2 +- gcc/config/arm/thumb1.md | 8 +- gcc/config/arm/thumb2.md | 34 +++---- 6 files changed, 123 insertions(+), 123 deletions(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 9086cf65953..d996207853c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -15376,7 +15376,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT || GET_CODE (x) == ROTATERT || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) - return CC_NOOVmode; + return CC_NZmode; /* A comparison of ~reg with a const is really a special canoncialization of compare (~const, reg), which is a reverse @@ -15492,11 +15492,11 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y, rtx scratch) } rtx clobber = gen_rtx_CLOBBER (VOIDmode, scratch); - cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); + cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); rtx set = gen_rtx_SET (cc_reg, - gen_rtx_COMPARE (CC_NOOVmode, + gen_rtx_COMPARE (CC_NZmode, gen_rtx_IOR (SImode, x_lo, x_hi), const0_rtx)); emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, @@ -23881,7 +23881,7 @@ maybe_get_arm_condition_code (rtx comparison) return code; return ARM_NV; - case E_CC_NOOVmode: + case E_CC_NZmode: switch (comp_code) { case NE: return ARM_NE; @@ -25304,7 +25304,7 @@ thumb1_final_prescan_insn (rtx_insn *insn) cfun->machine->thumb1_cc_insn = insn; cfun->machine->thumb1_cc_op0 = SET_DEST (set); cfun->machine->thumb1_cc_op1 = const0_rtx; - cfun->machine->thumb1_cc_mode = CC_NOOVmode; + cfun->machine->thumb1_cc_mode = CC_NZmode; if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn) { rtx src1 = XEXP (SET_SRC (set), 1); @@ -30486,7 +30486,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in, else { /* We have a shift-by-register. */ - rtx cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); + rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); /* This alternative requires the scratch registers. */ gcc_assert (scratch1 && REG_P (scratch1)); diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def index a6b520df32d..2ce53e0efba 100644 --- a/gcc/config/arm/arm-modes.def +++ b/gcc/config/arm/arm-modes.def @@ -29,7 +29,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) /* CCFPEmode should be used with floating inequalities, CCFPmode should be used with floating equalities. - CC_NOOVmode should be used with SImode integer equalities. + CC_NZmode should be used if only the N and Z bits are set correctly. CC_Zmode should be used if only the Z flag is set correctly CC_Cmode should be used if only the C flag is set correctly, after an addition. @@ -47,7 +47,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) against one of the other operands. CCmode should be used otherwise. */ -CC_MODE (CC_NOOV); +CC_MODE (CC_NZ); CC_MODE (CC_Z); CC_MODE (CC_NV); CC_MODE (CC_SWP); diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index f1d27ffbb4a..823312e7eac 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1078,8 +1078,8 @@ ) (define_insn "addsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r") (match_operand:SI 2 "arm_add_operand" "I,L,r")) (const_int 0))) @@ -1095,8 +1095,8 @@ ) (define_insn "*addsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r") (match_operand:SI 1 "arm_add_operand" "I,L, r")) (const_int 0)))] @@ -2017,8 +2017,8 @@ ) (define_insn "subsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I") (match_operand:SI 2 "arm_rhs_operand" "I,r,r")) (const_int 0))) @@ -2256,8 +2256,8 @@ ) (define_insn "*mulsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%0,r")) (const_int 0))) @@ -2270,8 +2270,8 @@ ) (define_insn "*mulsi3_compare0_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -2284,8 +2284,8 @@ ) (define_insn "*mulsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r,r") (match_operand:SI 1 "s_register_operand" "%0,r")) (const_int 0))) @@ -2297,8 +2297,8 @@ ) (define_insn "*mulsi_compare0_scratch_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (mult:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -2310,8 +2310,8 @@ ) (define_insn "*mulsi3addsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) @@ -2327,8 +2327,8 @@ ) (define_insn "*mulsi3addsi_compare0_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) @@ -2344,8 +2344,8 @@ ) (define_insn "*mulsi3addsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r,r,r,r") (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) @@ -2359,8 +2359,8 @@ ) (define_insn "*mulsi3addsi_compare0_scratch_v6" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (mult:SI (match_operand:SI 2 "s_register_operand" "r") (match_operand:SI 1 "s_register_operand" "r")) @@ -3004,8 +3004,8 @@ ) (define_insn "*andsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") (match_operand:SI 2 "arm_not_operand" "I,K,r")) (const_int 0))) @@ -3021,8 +3021,8 @@ ) (define_insn "*andsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r") (match_operand:SI 1 "arm_not_operand" "I,K,r")) (const_int 0))) @@ -3037,8 +3037,8 @@ ) (define_insn "*zeroextractsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (zero_extract:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (zero_extract:SI (match_operand:SI 0 "s_register_operand" "r") (match_operand 1 "const_int_operand" "n") (match_operand 2 "const_int_operand" "n")) @@ -3078,12 +3078,12 @@ && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (const_int 1)))] " operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) @@ -3108,12 +3108,12 @@ "TARGET_ARM" "#" "TARGET_ARM" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (const_int 1)))] " operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -3146,12 +3146,12 @@ && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32) && !reg_overlap_mentioned_p (operands[0], operands[4])" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (match_dup 4)))] " operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) @@ -3175,12 +3175,12 @@ "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" "#" "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) (set (match_dup 0) - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) (match_dup 0) (match_dup 3)))] " operands[2] = GEN_INT (32 - INTVAL (operands[2])); @@ -3498,8 +3498,8 @@ ;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2 ;; does not support shift by register. (define_insn "andsi_not_shiftsi_si_scc_no_reuse" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operator:SI 0 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -3518,8 +3518,8 @@ ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also ;; getting reused later. (define_insn "andsi_not_shiftsi_si_scc" - [(parallel [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(parallel [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operator:SI 0 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -3540,8 +3540,8 @@ ) (define_insn "*andsi_notsi_si_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -3554,8 +3554,8 @@ ) (define_insn "*andsi_notsi_si_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) @@ -3644,8 +3644,8 @@ ) (define_insn "*iorsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) (const_int 0))) @@ -3660,8 +3660,8 @@ ) (define_insn "*iorsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) (const_int 0))) @@ -3734,8 +3734,8 @@ ) (define_insn "*xorsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "I,r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r,r") @@ -3747,8 +3747,8 @@ ) (define_insn "*xorsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") (match_operand:SI 1 "arm_rhs_operand" "I,r")) (const_int 0)))] "TARGET_32BIT" @@ -4524,8 +4524,8 @@ ) (define_insn "*shiftsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) @@ -4539,8 +4539,8 @@ ) (define_insn "*shiftsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "arm_rhs_operand" "M,r")]) (const_int 0))) @@ -4565,8 +4565,8 @@ (set_attr "type" "mvn_shift,mvn_shift_reg")]) (define_insn "*not_shiftsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -4581,8 +4581,8 @@ (set_attr "type" "mvn_shift,mvn_shift_reg")]) (define_insn "*not_shiftsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operator:SI 3 "shift_operator" [(match_operand:SI 1 "s_register_operand" "r,r") (match_operand:SI 2 "shift_amount_operand" "M,r")])) @@ -5172,8 +5172,8 @@ ) (define_insn "*notsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (set (match_operand:SI 0 "s_register_operand" "=r") (not:SI (match_dup 1)))] @@ -5184,8 +5184,8 @@ ) (define_insn "*notsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 0 "=r"))] "TARGET_32BIT" @@ -8787,7 +8787,7 @@ (define_expand "return_addr_mask" [(set (match_dup 1) - (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) + (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) (const_int 0))) (set (match_operand:SI 0 "s_register_operand") (if_then_else:SI (eq (match_dup 1) (const_int 0)) @@ -8795,12 +8795,12 @@ (const_int 67108860)))] ; 0x03fffffc "TARGET_ARM" " - operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); + operands[1] = gen_rtx_REG (CC_NZmode, CC_REGNUM); ") (define_insn "*check_arch2" - [(set (match_operand:CC_NOOV 0 "cc_register" "") - (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) + [(set (match_operand:CC_NZ 0 "cc_register" "") + (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) (const_int 0)))] "TARGET_ARM" "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc" @@ -9336,8 +9336,8 @@ "") (define_insn "*arith_shiftsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r,r") @@ -9355,8 +9355,8 @@ (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*arith_shiftsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (match_operator:SI 1 "shiftable_operator" [(match_operator:SI 3 "shift_operator" [(match_operand:SI 4 "s_register_operand" "r,r") @@ -9386,8 +9386,8 @@ (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r,r") @@ -9404,8 +9404,8 @@ (set_attr "type" "alus_shift_imm,alus_shift_reg")]) (define_insn "*sub_shiftsi_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") (match_operator:SI 2 "shift_operator" [(match_operand:SI 3 "s_register_operand" "r,r") @@ -9549,11 +9549,11 @@ (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && reload_completed" [(parallel - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2)) + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (minus:SI (match_dup 1) (match_dup 2)) (const_int 0))) (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) - (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0)) + (cond_exec (ne:CC_NZ (reg:CC_NZ CC_REGNUM) (const_int 0)) (set (match_dup 0) (const_int 1)))]) (define_insn_and_split "*compare_scc" @@ -10258,8 +10258,8 @@ ) (define_split - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (and:SI (match_operand:SI 0 "s_register_operand" "") (const_int 1)) (match_operator:SI 1 "arm_comparison_operator" @@ -10271,14 +10271,14 @@ [(set (match_dup 4) (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) (match_dup 0))) - (set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) + (set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 4) (const_int 1)) (const_int 0)))] "") (define_split - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (ior:SI + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (ior:SI (match_operator:SI 1 "arm_comparison_operator" [(match_operand:SI 2 "s_register_operand" "") (match_operand:SI 3 "arm_add_operand" "")]) @@ -10290,8 +10290,8 @@ [(set (match_dup 4) (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) (match_dup 0))) - (set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) + (set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (and:SI (match_dup 4) (const_int 1)) (const_int 0)))] "") ;; ??? The conditional patterns above need checking for Thumb-2 usefulness @@ -10380,8 +10380,8 @@ "TARGET_32BIT" "#" "&& reload_completed" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_dup 3) (match_dup 4)) (const_int 0))) diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index c1f655c7040..6e9263553cc 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -430,7 +430,7 @@ (match_operand 0 "arm_vsel_comparison_operator")) (match_operand 0 "expandable_comparison_operator"))) -(define_special_predicate "noov_comparison_operator" +(define_special_predicate "nz_comparison_operator" (match_code "lt,ge,eq,ne")) (define_special_predicate "minmax_operator" diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index 5c70200bef3..9df793cc47c 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -1023,9 +1023,9 @@ if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1]) || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2])) t = NULL_RTX; - if (cfun->machine->thumb1_cc_mode == CC_NOOVmode) + if (cfun->machine->thumb1_cc_mode == CC_NZmode) { - if (!noov_comparison_operator (operands[0], VOIDmode)) + if (!nz_comparison_operator (operands[0], VOIDmode)) t = NULL_RTX; } else if (cfun->machine->thumb1_cc_mode != CCmode) @@ -1097,9 +1097,9 @@ if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1]) || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2])) t = NULL_RTX; - if (cfun->machine->thumb1_cc_mode == CC_NOOVmode) + if (cfun->machine->thumb1_cc_mode == CC_NZmode) { - if (!noov_comparison_operator (operands[0], VOIDmode)) + if (!nz_comparison_operator (operands[0], VOIDmode)) t = NULL_RTX; } else if (cfun->machine->thumb1_cc_mode != CCmode) diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 7fce50b045b..2558e404b88 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1287,8 +1287,8 @@ ) (define_insn "thumb2_addsi3_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL")) (const_int 0))) @@ -1321,8 +1321,8 @@ ) (define_insn "*thumb2_addsi3_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) (const_int 0)))] @@ -1359,8 +1359,8 @@ (set_attr "type" "muls")]) (define_insn "*thumb2_mulsi_short_compare0" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")) (const_int 0))) @@ -1372,8 +1372,8 @@ (set_attr "type" "muls")]) (define_insn "*thumb2_mulsi_short_compare0_scratch" - [(set (reg:CC_NOOV CC_REGNUM) - (compare:CC_NOOV + [(set (reg:CC_NZ CC_REGNUM) + (compare:CC_NZ (mult:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "l")) (const_int 0))) @@ -1477,15 +1477,15 @@ ) (define_peephole2 - [(set (match_operand:CC_NOOV 0 "cc_register" "") - (compare:CC_NOOV (zero_extract:SI + [(set (match_operand:CC_NZ 0 "cc_register" "") + (compare:CC_NZ (zero_extract:SI (match_operand:SI 1 "low_register_operand" "") (const_int 1) (match_operand:SI 2 "const_int_operand" "")) (const_int 0))) (match_scratch:SI 3 "l") (set (pc) - (if_then_else (match_operator:CC_NOOV 4 "equality_operator" + (if_then_else (match_operator:CC_NZ 4 "equality_operator" [(match_dup 0) (const_int 0)]) (match_operand 5 "" "") (match_operand 6 "" "")))] @@ -1493,7 +1493,7 @@ && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) && peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 0) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) (const_int 0))) (clobber (match_dup 3))]) (set (pc) @@ -1506,15 +1506,15 @@ ") (define_peephole2 - [(set (match_operand:CC_NOOV 0 "cc_register" "") - (compare:CC_NOOV (zero_extract:SI + [(set (match_operand:CC_NZ 0 "cc_register" "") + (compare:CC_NZ (zero_extract:SI (match_operand:SI 1 "low_register_operand" "") (match_operand:SI 2 "const_int_operand" "") (const_int 0)) (const_int 0))) (match_scratch:SI 3 "l") (set (pc) - (if_then_else (match_operator:CC_NOOV 4 "equality_operator" + (if_then_else (match_operator:CC_NZ 4 "equality_operator" [(match_dup 0) (const_int 0)]) (match_operand 5 "" "") (match_operand 6 "" "")))] @@ -1522,8 +1522,8 @@ && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32) && peep2_reg_dead_p (2, operands[0])" [(parallel [(set (match_dup 0) - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) - (const_int 0))) + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) + (const_int 0))) (clobber (match_dup 3))]) (set (pc) (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)]) -- 2.17.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode 2019-11-14 10:07 ` [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson @ 2019-11-14 14:42 ` Richard Earnshaw (lists) 0 siblings, 0 replies; 26+ messages in thread From: Richard Earnshaw (lists) @ 2019-11-14 14:42 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford On 14/11/2019 10:07, Richard Henderson wrote: > CC_NZmode is a more accurate description of what we require > from the mode, and matches up with the definition in aarch64. > > Rename noov_comparison_operator to nz_comparison_operator > in order to match. > > * config/arm/arm-modes.def (CC_NZ): Rename from CC_NOOV. > * config/arm/predicates.md (nz_comparison_operator): Rename > from noov_comparison_operator. > * config/arm/arm.c (arm_select_cc_mode): Use CC_NZmode name. > (arm_gen_dicompare_reg): Likewise. > (maybe_get_arm_condition_code): Likewise. > (thumb1_final_prescan_insn): Likewise. > (arm_emit_coreregs_64bit_shift): Likewise. > * config/arm/arm.md (addsi3_compare0): Likewise. > (*addsi3_compare0_scratch, subsi3_compare0): Likewise. > (*mulsi3_compare0, *mulsi3_compare0_v6): Likewise. > (*mulsi3_compare0_scratch, *mulsi3_compare0_scratch_v6): Likewise. > (*mulsi3addsi_compare0, *mulsi3addsi_compare0_v6): Likewise. > (*mulsi3addsi_compare0_scratch): Likewise. > (*mulsi3addsi_compare0_scratch_v6): Likewise. > (*andsi3_compare0, *andsi3_compare0_scratch): Likewise. > (*zeroextractsi_compare0_scratch): Likewise. > (*ne_zeroextractsi, *ne_zeroextractsi_shifted): Likewise. > (*ite_ne_zeroextractsi, *ite_ne_zeroextractsi_shifted): Likewise. > (andsi_not_shiftsi_si_scc_no_reuse): Likewise. > (andsi_not_shiftsi_si_scc): Likewise. > (*andsi_notsi_si_compare0, *andsi_notsi_si_compare0_scratch): Likewise. > (*iorsi3_compare0, *iorsi3_compare0_scratch): Likewise. > (*xorsi3_compare0, *xorsi3_compare0_scratch): Likewise. > (*shiftsi3_compare0, *shiftsi3_compare0_scratch): Likewise. > (*not_shiftsi_compare0, *not_shiftsi_compare0_scratch): Likewise. > (*notsi_compare0, *notsi_compare0_scratch): Likewise. > (return_addr_mask, *check_arch2): Likewise. > (*arith_shiftsi_compare0, *arith_shiftsi_compare0_scratch): Likewise. > (*sub_shiftsi_compare0, *sub_shiftsi_compare0_scratch): Likewise. > (compare_scc splitters): Likewise. > (movcond_addsi): Likewise. > * config/arm/thumb2.md (thumb2_addsi3_compare0): Likewise. > (*thumb2_addsi3_compare0_scratch): Likewise. > (*thumb2_mulsi_short_compare0): Likewise. > (*thumb2_mulsi_short_compare0_scratch): Likewise. > (compare peephole2s): Likewise. > * config/arm/thumb1.md (thumb1_cbz): Use CC_NZmode and > nz_comparison_operator names. > (cbranchsi4_insn): Likewise. I take it this is a rototill change. OK. R. > --- > gcc/config/arm/arm.c | 12 +-- > gcc/config/arm/arm-modes.def | 4 +- > gcc/config/arm/arm.md | 186 +++++++++++++++++------------------ > gcc/config/arm/predicates.md | 2 +- > gcc/config/arm/thumb1.md | 8 +- > gcc/config/arm/thumb2.md | 34 +++---- > 6 files changed, 123 insertions(+), 123 deletions(-) > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 9086cf65953..d996207853c 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -15376,7 +15376,7 @@ arm_select_cc_mode (enum rtx_code op, rtx x, rtx y) > || GET_CODE (x) == ASHIFT || GET_CODE (x) == ASHIFTRT > || GET_CODE (x) == ROTATERT > || (TARGET_32BIT && GET_CODE (x) == ZERO_EXTRACT))) > - return CC_NOOVmode; > + return CC_NZmode; > > /* A comparison of ~reg with a const is really a special > canoncialization of compare (~const, reg), which is a reverse > @@ -15492,11 +15492,11 @@ arm_gen_dicompare_reg (rtx_code code, rtx x, rtx y, rtx scratch) > } > > rtx clobber = gen_rtx_CLOBBER (VOIDmode, scratch); > - cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); > + cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); > > rtx set > = gen_rtx_SET (cc_reg, > - gen_rtx_COMPARE (CC_NOOVmode, > + gen_rtx_COMPARE (CC_NZmode, > gen_rtx_IOR (SImode, x_lo, x_hi), > const0_rtx)); > emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, set, > @@ -23881,7 +23881,7 @@ maybe_get_arm_condition_code (rtx comparison) > return code; > return ARM_NV; > > - case E_CC_NOOVmode: > + case E_CC_NZmode: > switch (comp_code) > { > case NE: return ARM_NE; > @@ -25304,7 +25304,7 @@ thumb1_final_prescan_insn (rtx_insn *insn) > cfun->machine->thumb1_cc_insn = insn; > cfun->machine->thumb1_cc_op0 = SET_DEST (set); > cfun->machine->thumb1_cc_op1 = const0_rtx; > - cfun->machine->thumb1_cc_mode = CC_NOOVmode; > + cfun->machine->thumb1_cc_mode = CC_NZmode; > if (INSN_CODE (insn) == CODE_FOR_thumb1_subsi3_insn) > { > rtx src1 = XEXP (SET_SRC (set), 1); > @@ -30486,7 +30486,7 @@ arm_emit_coreregs_64bit_shift (enum rtx_code code, rtx out, rtx in, > else > { > /* We have a shift-by-register. */ > - rtx cc_reg = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); > + rtx cc_reg = gen_rtx_REG (CC_NZmode, CC_REGNUM); > > /* This alternative requires the scratch registers. */ > gcc_assert (scratch1 && REG_P (scratch1)); > diff --git a/gcc/config/arm/arm-modes.def b/gcc/config/arm/arm-modes.def > index a6b520df32d..2ce53e0efba 100644 > --- a/gcc/config/arm/arm-modes.def > +++ b/gcc/config/arm/arm-modes.def > @@ -29,7 +29,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) > > /* CCFPEmode should be used with floating inequalities, > CCFPmode should be used with floating equalities. > - CC_NOOVmode should be used with SImode integer equalities. > + CC_NZmode should be used if only the N and Z bits are set correctly. > CC_Zmode should be used if only the Z flag is set correctly > CC_Cmode should be used if only the C flag is set correctly, after an > addition. > @@ -47,7 +47,7 @@ ADJUST_FLOAT_FORMAT (HF, ((arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) > against one of the other operands. > CCmode should be used otherwise. */ > > -CC_MODE (CC_NOOV); > +CC_MODE (CC_NZ); > CC_MODE (CC_Z); > CC_MODE (CC_NV); > CC_MODE (CC_SWP); > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index f1d27ffbb4a..823312e7eac 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -1078,8 +1078,8 @@ > ) > > (define_insn "addsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (match_operand:SI 1 "s_register_operand" "r, r,r") > (match_operand:SI 2 "arm_add_operand" "I,L,r")) > (const_int 0))) > @@ -1095,8 +1095,8 @@ > ) > > (define_insn "*addsi3_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (match_operand:SI 0 "s_register_operand" "r, r, r") > (match_operand:SI 1 "arm_add_operand" "I,L, r")) > (const_int 0)))] > @@ -2017,8 +2017,8 @@ > ) > > (define_insn "subsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (minus:SI (match_operand:SI 1 "arm_rhs_operand" "r,r,I") > (match_operand:SI 2 "arm_rhs_operand" "I,r,r")) > (const_int 0))) > @@ -2256,8 +2256,8 @@ > ) > > (define_insn "*mulsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (mult:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (mult:SI > (match_operand:SI 2 "s_register_operand" "r,r") > (match_operand:SI 1 "s_register_operand" "%0,r")) > (const_int 0))) > @@ -2270,8 +2270,8 @@ > ) > > (define_insn "*mulsi3_compare0_v6" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (mult:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (mult:SI > (match_operand:SI 2 "s_register_operand" "r") > (match_operand:SI 1 "s_register_operand" "r")) > (const_int 0))) > @@ -2284,8 +2284,8 @@ > ) > > (define_insn "*mulsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (mult:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (mult:SI > (match_operand:SI 2 "s_register_operand" "r,r") > (match_operand:SI 1 "s_register_operand" "%0,r")) > (const_int 0))) > @@ -2297,8 +2297,8 @@ > ) > > (define_insn "*mulsi_compare0_scratch_v6" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (mult:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (mult:SI > (match_operand:SI 2 "s_register_operand" "r") > (match_operand:SI 1 "s_register_operand" "r")) > (const_int 0))) > @@ -2310,8 +2310,8 @@ > ) > > (define_insn "*mulsi3addsi_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (mult:SI > (match_operand:SI 2 "s_register_operand" "r,r,r,r") > (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) > @@ -2327,8 +2327,8 @@ > ) > > (define_insn "*mulsi3addsi_compare0_v6" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (mult:SI > (match_operand:SI 2 "s_register_operand" "r") > (match_operand:SI 1 "s_register_operand" "r")) > @@ -2344,8 +2344,8 @@ > ) > > (define_insn "*mulsi3addsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (mult:SI > (match_operand:SI 2 "s_register_operand" "r,r,r,r") > (match_operand:SI 1 "s_register_operand" "%0,r,0,r")) > @@ -2359,8 +2359,8 @@ > ) > > (define_insn "*mulsi3addsi_compare0_scratch_v6" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (mult:SI > (match_operand:SI 2 "s_register_operand" "r") > (match_operand:SI 1 "s_register_operand" "r")) > @@ -3004,8 +3004,8 @@ > ) > > (define_insn "*andsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (and:SI (match_operand:SI 1 "s_register_operand" "r,r,r") > (match_operand:SI 2 "arm_not_operand" "I,K,r")) > (const_int 0))) > @@ -3021,8 +3021,8 @@ > ) > > (define_insn "*andsi3_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (and:SI (match_operand:SI 0 "s_register_operand" "r,r,r") > (match_operand:SI 1 "arm_not_operand" "I,K,r")) > (const_int 0))) > @@ -3037,8 +3037,8 @@ > ) > > (define_insn "*zeroextractsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (zero_extract:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (zero_extract:SI > (match_operand:SI 0 "s_register_operand" "r") > (match_operand 1 "const_int_operand" "n") > (match_operand 2 "const_int_operand" "n")) > @@ -3078,12 +3078,12 @@ > && INTVAL (operands[2]) > 0 > && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 > && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32)" > - [(parallel [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) > + [(parallel [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2)) > (const_int 0))) > (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) > (set (match_dup 0) > - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) > + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) > (match_dup 0) (const_int 1)))] > " > operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) > @@ -3108,12 +3108,12 @@ > "TARGET_ARM" > "#" > "TARGET_ARM" > - [(parallel [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) > + [(parallel [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) > (const_int 0))) > (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) > (set (match_dup 0) > - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) > + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) > (match_dup 0) (const_int 1)))] > " > operands[2] = GEN_INT (32 - INTVAL (operands[2])); > @@ -3146,12 +3146,12 @@ > && INTVAL (operands[2]) + (INTVAL (operands[3]) & 1) <= 8 > && INTVAL (operands[2]) + INTVAL (operands[3]) <= 32) > && !reg_overlap_mentioned_p (operands[0], operands[4])" > - [(parallel [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (and:SI (match_dup 1) (match_dup 2)) > + [(parallel [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (and:SI (match_dup 1) (match_dup 2)) > (const_int 0))) > (set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))]) > (set (match_dup 0) > - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) > + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) > (match_dup 0) (match_dup 4)))] > " > operands[2] = GEN_INT (((1 << INTVAL (operands[2])) - 1) > @@ -3175,12 +3175,12 @@ > "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" > "#" > "TARGET_ARM && !reg_overlap_mentioned_p (operands[0], operands[3])" > - [(parallel [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) > + [(parallel [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) > (const_int 0))) > (set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2)))]) > (set (match_dup 0) > - (if_then_else:SI (eq (reg:CC_NOOV CC_REGNUM) (const_int 0)) > + (if_then_else:SI (eq (reg:CC_NZ CC_REGNUM) (const_int 0)) > (match_dup 0) (match_dup 3)))] > " > operands[2] = GEN_INT (32 - INTVAL (operands[2])); > @@ -3498,8 +3498,8 @@ > ;; bics output. Pattern restricts Thumb2 shift operand as bics for Thumb2 > ;; does not support shift by register. > (define_insn "andsi_not_shiftsi_si_scc_no_reuse" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (and:SI (not:SI (match_operator:SI 0 "shift_operator" > [(match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "shift_amount_operand" "M,r")])) > @@ -3518,8 +3518,8 @@ > ;; Same as andsi_not_shiftsi_si_scc_no_reuse, but the bics result is also > ;; getting reused later. > (define_insn "andsi_not_shiftsi_si_scc" > - [(parallel [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(parallel [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (and:SI (not:SI (match_operator:SI 0 "shift_operator" > [(match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "shift_amount_operand" "M,r")])) > @@ -3540,8 +3540,8 @@ > ) > > (define_insn "*andsi_notsi_si_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) > (match_operand:SI 1 "s_register_operand" "r")) > (const_int 0))) > @@ -3554,8 +3554,8 @@ > ) > > (define_insn "*andsi_notsi_si_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (and:SI (not:SI (match_operand:SI 2 "s_register_operand" "r")) > (match_operand:SI 1 "s_register_operand" "r")) > (const_int 0))) > @@ -3644,8 +3644,8 @@ > ) > > (define_insn "*iorsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") > (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) > (const_int 0))) > @@ -3660,8 +3660,8 @@ > ) > > (define_insn "*iorsi3_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (ior:SI (match_operand:SI 1 "s_register_operand" "%r,0,r") > (match_operand:SI 2 "arm_rhs_operand" "I,l,r")) > (const_int 0))) > @@ -3734,8 +3734,8 @@ > ) > > (define_insn "*xorsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (xor:SI (match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "arm_rhs_operand" "I,r")) > (const_int 0))) > (set (match_operand:SI 0 "s_register_operand" "=r,r") > @@ -3747,8 +3747,8 @@ > ) > > (define_insn "*xorsi3_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (xor:SI (match_operand:SI 0 "s_register_operand" "r,r") > (match_operand:SI 1 "arm_rhs_operand" "I,r")) > (const_int 0)))] > "TARGET_32BIT" > @@ -4524,8 +4524,8 @@ > ) > > (define_insn "*shiftsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (match_operator:SI 3 "shift_operator" > [(match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "arm_rhs_operand" "M,r")]) > (const_int 0))) > @@ -4539,8 +4539,8 @@ > ) > > (define_insn "*shiftsi3_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (match_operator:SI 3 "shift_operator" > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (match_operator:SI 3 "shift_operator" > [(match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "arm_rhs_operand" "M,r")]) > (const_int 0))) > @@ -4565,8 +4565,8 @@ > (set_attr "type" "mvn_shift,mvn_shift_reg")]) > > (define_insn "*not_shiftsi_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (not:SI (match_operator:SI 3 "shift_operator" > [(match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "shift_amount_operand" "M,r")])) > @@ -4581,8 +4581,8 @@ > (set_attr "type" "mvn_shift,mvn_shift_reg")]) > > (define_insn "*not_shiftsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (not:SI (match_operator:SI 3 "shift_operator" > [(match_operand:SI 1 "s_register_operand" "r,r") > (match_operand:SI 2 "shift_amount_operand" "M,r")])) > @@ -5172,8 +5172,8 @@ > ) > > (define_insn "*notsi_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r")) > (const_int 0))) > (set (match_operand:SI 0 "s_register_operand" "=r") > (not:SI (match_dup 1)))] > @@ -5184,8 +5184,8 @@ > ) > > (define_insn "*notsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (not:SI (match_operand:SI 1 "s_register_operand" "r")) > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (not:SI (match_operand:SI 1 "s_register_operand" "r")) > (const_int 0))) > (clobber (match_scratch:SI 0 "=r"))] > "TARGET_32BIT" > @@ -8787,7 +8787,7 @@ > > (define_expand "return_addr_mask" > [(set (match_dup 1) > - (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) > + (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) > (const_int 0))) > (set (match_operand:SI 0 "s_register_operand") > (if_then_else:SI (eq (match_dup 1) (const_int 0)) > @@ -8795,12 +8795,12 @@ > (const_int 67108860)))] ; 0x03fffffc > "TARGET_ARM" > " > - operands[1] = gen_rtx_REG (CC_NOOVmode, CC_REGNUM); > + operands[1] = gen_rtx_REG (CC_NZmode, CC_REGNUM); > ") > > (define_insn "*check_arch2" > - [(set (match_operand:CC_NOOV 0 "cc_register" "") > - (compare:CC_NOOV (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) > + [(set (match_operand:CC_NZ 0 "cc_register" "") > + (compare:CC_NZ (unspec [(const_int 0)] UNSPEC_CHECK_ARCH) > (const_int 0)))] > "TARGET_ARM" > "teq\\t%|r0, %|r0\;teq\\t%|pc, %|pc" > @@ -9336,8 +9336,8 @@ > "") > > (define_insn "*arith_shiftsi_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (match_operator:SI 1 "shiftable_operator" > [(match_operator:SI 3 "shift_operator" > [(match_operand:SI 4 "s_register_operand" "r,r") > @@ -9355,8 +9355,8 @@ > (set_attr "type" "alus_shift_imm,alus_shift_reg")]) > > (define_insn "*arith_shiftsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (match_operator:SI 1 "shiftable_operator" > [(match_operator:SI 3 "shift_operator" > [(match_operand:SI 4 "s_register_operand" "r,r") > @@ -9386,8 +9386,8 @@ > (set_attr "type" "alus_shift_imm,alus_shift_reg")]) > > (define_insn "*sub_shiftsi_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") > (match_operator:SI 2 "shift_operator" > [(match_operand:SI 3 "s_register_operand" "r,r") > @@ -9404,8 +9404,8 @@ > (set_attr "type" "alus_shift_imm,alus_shift_reg")]) > > (define_insn "*sub_shiftsi_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (minus:SI (match_operand:SI 1 "s_register_operand" "r,r") > (match_operator:SI 2 "shift_operator" > [(match_operand:SI 3 "s_register_operand" "r,r") > @@ -9549,11 +9549,11 @@ > (clobber (reg:CC CC_REGNUM))] > "TARGET_32BIT && reload_completed" > [(parallel > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (minus:SI (match_dup 1) (match_dup 2)) > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (minus:SI (match_dup 1) (match_dup 2)) > (const_int 0))) > (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) > - (cond_exec (ne:CC_NOOV (reg:CC_NOOV CC_REGNUM) (const_int 0)) > + (cond_exec (ne:CC_NZ (reg:CC_NZ CC_REGNUM) (const_int 0)) > (set (match_dup 0) (const_int 1)))]) > > (define_insn_and_split "*compare_scc" > @@ -10258,8 +10258,8 @@ > ) > > (define_split > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (ior:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (ior:SI > (and:SI (match_operand:SI 0 "s_register_operand" "") > (const_int 1)) > (match_operator:SI 1 "arm_comparison_operator" > @@ -10271,14 +10271,14 @@ > [(set (match_dup 4) > (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) > (match_dup 0))) > - (set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) > + (set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (and:SI (match_dup 4) (const_int 1)) > (const_int 0)))] > "") > > (define_split > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (ior:SI > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (ior:SI > (match_operator:SI 1 "arm_comparison_operator" > [(match_operand:SI 2 "s_register_operand" "") > (match_operand:SI 3 "arm_add_operand" "")]) > @@ -10290,8 +10290,8 @@ > [(set (match_dup 4) > (ior:SI (match_op_dup 1 [(match_dup 2) (match_dup 3)]) > (match_dup 0))) > - (set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV (and:SI (match_dup 4) (const_int 1)) > + (set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ (and:SI (match_dup 4) (const_int 1)) > (const_int 0)))] > "") > ;; ??? The conditional patterns above need checking for Thumb-2 usefulness > @@ -10380,8 +10380,8 @@ > "TARGET_32BIT" > "#" > "&& reload_completed" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (match_dup 3) > (match_dup 4)) > (const_int 0))) > diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md > index c1f655c7040..6e9263553cc 100644 > --- a/gcc/config/arm/predicates.md > +++ b/gcc/config/arm/predicates.md > @@ -430,7 +430,7 @@ > (match_operand 0 "arm_vsel_comparison_operator")) > (match_operand 0 "expandable_comparison_operator"))) > > -(define_special_predicate "noov_comparison_operator" > +(define_special_predicate "nz_comparison_operator" > (match_code "lt,ge,eq,ne")) > > (define_special_predicate "minmax_operator" > diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md > index 5c70200bef3..9df793cc47c 100644 > --- a/gcc/config/arm/thumb1.md > +++ b/gcc/config/arm/thumb1.md > @@ -1023,9 +1023,9 @@ > if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1]) > || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2])) > t = NULL_RTX; > - if (cfun->machine->thumb1_cc_mode == CC_NOOVmode) > + if (cfun->machine->thumb1_cc_mode == CC_NZmode) > { > - if (!noov_comparison_operator (operands[0], VOIDmode)) > + if (!nz_comparison_operator (operands[0], VOIDmode)) > t = NULL_RTX; > } > else if (cfun->machine->thumb1_cc_mode != CCmode) > @@ -1097,9 +1097,9 @@ > if (!rtx_equal_p (cfun->machine->thumb1_cc_op0, operands[1]) > || !rtx_equal_p (cfun->machine->thumb1_cc_op1, operands[2])) > t = NULL_RTX; > - if (cfun->machine->thumb1_cc_mode == CC_NOOVmode) > + if (cfun->machine->thumb1_cc_mode == CC_NZmode) > { > - if (!noov_comparison_operator (operands[0], VOIDmode)) > + if (!nz_comparison_operator (operands[0], VOIDmode)) > t = NULL_RTX; > } > else if (cfun->machine->thumb1_cc_mode != CCmode) > diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > index 7fce50b045b..2558e404b88 100644 > --- a/gcc/config/arm/thumb2.md > +++ b/gcc/config/arm/thumb2.md > @@ -1287,8 +1287,8 @@ > ) > > (define_insn "thumb2_addsi3_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (match_operand:SI 1 "s_register_operand" "l, 0, r") > (match_operand:SI 2 "arm_add_operand" "lPt,Ps,rIL")) > (const_int 0))) > @@ -1321,8 +1321,8 @@ > ) > > (define_insn "*thumb2_addsi3_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (plus:SI (match_operand:SI 0 "s_register_operand" "l, r") > (match_operand:SI 1 "arm_add_operand" "lPv,rIL")) > (const_int 0)))] > @@ -1359,8 +1359,8 @@ > (set_attr "type" "muls")]) > > (define_insn "*thumb2_mulsi_short_compare0" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (mult:SI (match_operand:SI 1 "register_operand" "%0") > (match_operand:SI 2 "register_operand" "l")) > (const_int 0))) > @@ -1372,8 +1372,8 @@ > (set_attr "type" "muls")]) > > (define_insn "*thumb2_mulsi_short_compare0_scratch" > - [(set (reg:CC_NOOV CC_REGNUM) > - (compare:CC_NOOV > + [(set (reg:CC_NZ CC_REGNUM) > + (compare:CC_NZ > (mult:SI (match_operand:SI 1 "register_operand" "%0") > (match_operand:SI 2 "register_operand" "l")) > (const_int 0))) > @@ -1477,15 +1477,15 @@ > ) > > (define_peephole2 > - [(set (match_operand:CC_NOOV 0 "cc_register" "") > - (compare:CC_NOOV (zero_extract:SI > + [(set (match_operand:CC_NZ 0 "cc_register" "") > + (compare:CC_NZ (zero_extract:SI > (match_operand:SI 1 "low_register_operand" "") > (const_int 1) > (match_operand:SI 2 "const_int_operand" "")) > (const_int 0))) > (match_scratch:SI 3 "l") > (set (pc) > - (if_then_else (match_operator:CC_NOOV 4 "equality_operator" > + (if_then_else (match_operator:CC_NZ 4 "equality_operator" > [(match_dup 0) (const_int 0)]) > (match_operand 5 "" "") > (match_operand 6 "" "")))] > @@ -1493,7 +1493,7 @@ > && (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) > && peep2_reg_dead_p (2, operands[0])" > [(parallel [(set (match_dup 0) > - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) > + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) > (const_int 0))) > (clobber (match_dup 3))]) > (set (pc) > @@ -1506,15 +1506,15 @@ > ") > > (define_peephole2 > - [(set (match_operand:CC_NOOV 0 "cc_register" "") > - (compare:CC_NOOV (zero_extract:SI > + [(set (match_operand:CC_NZ 0 "cc_register" "") > + (compare:CC_NZ (zero_extract:SI > (match_operand:SI 1 "low_register_operand" "") > (match_operand:SI 2 "const_int_operand" "") > (const_int 0)) > (const_int 0))) > (match_scratch:SI 3 "l") > (set (pc) > - (if_then_else (match_operator:CC_NOOV 4 "equality_operator" > + (if_then_else (match_operator:CC_NZ 4 "equality_operator" > [(match_dup 0) (const_int 0)]) > (match_operand 5 "" "") > (match_operand 6 "" "")))] > @@ -1522,8 +1522,8 @@ > && (INTVAL (operands[2]) > 0 && INTVAL (operands[2]) < 32) > && peep2_reg_dead_p (2, operands[0])" > [(parallel [(set (match_dup 0) > - (compare:CC_NOOV (ashift:SI (match_dup 1) (match_dup 2)) > - (const_int 0))) > + (compare:CC_NZ (ashift:SI (match_dup 1) (match_dup 2)) > + (const_int 0))) > (clobber (match_dup 3))]) > (set (pc) > (if_then_else (match_op_dup 4 [(match_dup 0) (const_int 0)]) > ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 2/6] arm: Fix the "c" constraint 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson 2019-11-14 10:07 ` [PATCH v2 1/6] aarch64: Add "c" constraint Richard Henderson 2019-11-14 10:07 ` [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson @ 2019-11-14 10:07 ` Richard Henderson 2019-11-14 13:08 ` Kyrill Tkachov 2019-11-14 10:07 ` [PATCH v2 5/6] arm: Add testsuite checks for asm-flag Richard Henderson ` (3 subsequent siblings) 6 siblings, 1 reply; 26+ messages in thread From: Richard Henderson @ 2019-11-14 10:07 UTC (permalink / raw) To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford The existing definition using register class CC_REG does not work because CC_REGNUM does not support normal modes, and so fails to match register_operand. Use a non-register constraint and the cc_register predicate instead. * config/arm/constraints.md (c): Use cc_register predicate. --- gcc/config/arm/constraints.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index b76de81b85c..e02b678d26d 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -94,8 +94,9 @@ "@internal Thumb only. The union of the low registers and the stack register.") -(define_register_constraint "c" "CC_REG" - "@internal The condition code register.") +(define_constraint "c" + "@internal The condition code register." + (match_operand 0 "cc_register")) (define_register_constraint "Cs" "CALLER_SAVE_REGS" "@internal The caller save registers. Useful for sibcalls.") -- 2.17.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 2/6] arm: Fix the "c" constraint 2019-11-14 10:07 ` [PATCH v2 2/6] arm: Fix the "c" constraint Richard Henderson @ 2019-11-14 13:08 ` Kyrill Tkachov 2019-11-14 13:36 ` Richard Henderson 0 siblings, 1 reply; 26+ messages in thread From: Kyrill Tkachov @ 2019-11-14 13:08 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: Richard Earnshaw, Richard Sandiford On 11/14/19 10:07 AM, Richard Henderson wrote: > The existing definition using register class CC_REG does not > work because CC_REGNUM does not support normal modes, and so > fails to match register_operand. Use a non-register constraint > and the cc_register predicate instead. > >        * config/arm/constraints.md (c): Use cc_register predicate. Ok. Does this need a backport to the branches? Thanks, Kyrill > --- >  gcc/config/arm/constraints.md | 5 +++-- >  1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md > index b76de81b85c..e02b678d26d 100644 > --- a/gcc/config/arm/constraints.md > +++ b/gcc/config/arm/constraints.md > @@ -94,8 +94,9 @@ >  "@internal >   Thumb only. The union of the low registers and the stack register.") > > -(define_register_constraint "c" "CC_REG" > - "@internal The condition code register.") > +(define_constraint "c" > + "@internal The condition code register." > + (match_operand 0 "cc_register")) > >  (define_register_constraint "Cs" "CALLER_SAVE_REGS" >  "@internal The caller save registers. Useful for sibcalls.") > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 2/6] arm: Fix the "c" constraint 2019-11-14 13:08 ` Kyrill Tkachov @ 2019-11-14 13:36 ` Richard Henderson 0 siblings, 0 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-14 13:36 UTC (permalink / raw) To: Kyrill Tkachov, Richard Henderson, gcc-patches Cc: Richard Earnshaw, Richard Sandiford On 11/14/19 2:07 PM, Kyrill Tkachov wrote: > > On 11/14/19 10:07 AM, Richard Henderson wrote: >> The existing definition using register class CC_REG does not >> work because CC_REGNUM does not support normal modes, and so >> fails to match register_operand. Use a non-register constraint >> and the cc_register predicate instead. >> >>        * config/arm/constraints.md (c): Use cc_register predicate. > > > Ok. > > Does this need a backport to the branches? I don't think so, because it is currently unused. I tried to track down if it was *ever* used and did not succeed. The first reference I see is commit cffb2a26c44c682185b6bb405d48fcbe1fbc0b37 Author: rearnsha <rearnsha@138bc75d-0d04-0410-961f-82ee72b054a4> Date: Sat Apr 8 14:29:53 2000 +0000 Merge changes from merged-arm-thumb-backend-branch onto trunk. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@33028 \ 138bc75d-0d04-0410-961f-82ee72b054a4 within REG_CLASS_FROM_LETTER. But I cannot find a user of the constraint within a checkout of that revision. Unless I miss something, it seems to have been garbage for a very long time. r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 5/6] arm: Add testsuite checks for asm-flag 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson ` (2 preceding siblings ...) 2019-11-14 10:07 ` [PATCH v2 2/6] arm: Fix the "c" constraint Richard Henderson @ 2019-11-14 10:07 ` Richard Henderson 2019-11-14 14:48 ` Richard Earnshaw (lists) 2019-11-18 12:28 ` Christophe Lyon 2019-11-14 10:07 ` [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson ` (2 subsequent siblings) 6 siblings, 2 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-14 10:07 UTC (permalink / raw) To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/arm/asm-flag-1.c: New test. * gcc.target/arm/asm-flag-3.c: New test. * gcc.target/arm/asm-flag-5.c: New test. * gcc.target/arm/asm-flag-6.c: New test. --- gcc/testsuite/gcc.target/arm/asm-flag-1.c | 36 +++++++++++++ gcc/testsuite/gcc.target/arm/asm-flag-3.c | 38 ++++++++++++++ gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 +++++++++++ gcc/testsuite/gcc.target/arm/asm-flag-6.c | 62 +++++++++++++++++++++++ 4 files changed, 166 insertions(+) create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c new file mode 100644 index 00000000000..9707ebfcebb --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c @@ -0,0 +1,36 @@ +/* Test the valid @cc<cc> asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#ifndef __GCC_ASM_FLAG_OUTPUTS__ +#error "missing preprocessor define" +#endif + +void f(char *out) +{ + asm("" + : "=@ccne"(out[0]), "=@cceq"(out[1]), + "=@cccs"(out[2]), "=@cccc"(out[3]), + "=@ccmi"(out[4]), "=@ccpl"(out[5]), + "=@ccvs"(out[6]), "=@ccvc"(out[7]), + "=@cchi"(out[8]), "=@ccls"(out[9]), + "=@ccge"(out[10]), "=@cclt"(out[11]), + "=@ccgt"(out[12]), "=@ccle"(out[13]), + "=@cchs"(out[14]), "=@cclo"(out[15])); +} + +/* There will be at least one of each. */ +/* { dg-final { scan-assembler "movne" } } */ +/* { dg-final { scan-assembler "moveq" } } */ +/* { dg-final { scan-assembler "movcs" } } */ +/* { dg-final { scan-assembler "movcc" } } */ +/* { dg-final { scan-assembler "movmi" } } */ +/* { dg-final { scan-assembler "movpl" } } */ +/* { dg-final { scan-assembler "movvs" } } */ +/* { dg-final { scan-assembler "movvc" } } */ +/* { dg-final { scan-assembler "movhi" } } */ +/* { dg-final { scan-assembler "movls" } } */ +/* { dg-final { scan-assembler "movge" } } */ +/* { dg-final { scan-assembler "movls" } } */ +/* { dg-final { scan-assembler "movgt" } } */ +/* { dg-final { scan-assembler "movle" } } */ diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c new file mode 100644 index 00000000000..e84e3431277 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c @@ -0,0 +1,38 @@ +/* Test some of the valid @cc<cc> asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#define DO(C) \ +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } + +DO(ne) +DO(eq) +DO(cs) +DO(cc) +DO(hs) +DO(lo) +DO(mi) +DO(pl) +DO(vs) +DO(vc) +DO(hi) +DO(ls) +DO(ge) +DO(lt) +DO(gt) +DO(le) + +/* { dg-final { scan-assembler "bne" } } */ +/* { dg-final { scan-assembler "beq" } } */ +/* { dg-final { scan-assembler "bcs" } } */ +/* { dg-final { scan-assembler "bcc" } } */ +/* { dg-final { scan-assembler "bmi" } } */ +/* { dg-final { scan-assembler "bpl" } } */ +/* { dg-final { scan-assembler "bvs" } } */ +/* { dg-final { scan-assembler "bvc" } } */ +/* { dg-final { scan-assembler "bhi" } } */ +/* { dg-final { scan-assembler "bls" } } */ +/* { dg-final { scan-assembler "bge" } } */ +/* { dg-final { scan-assembler "blt" } } */ +/* { dg-final { scan-assembler "bgt" } } */ +/* { dg-final { scan-assembler "ble" } } */ diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c new file mode 100644 index 00000000000..4d4394e1478 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c @@ -0,0 +1,30 @@ +/* Test error conditions of asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } +void f_c(void) { char x; asm("" : "=@cccc"(x)); } +void f_s(void) { short x; asm("" : "=@cccc"(x)); } +void f_i(void) { int x; asm("" : "=@cccc"(x)); } +void f_l(void) { long x; asm("" : "=@cccc"(x)); } +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } + +void f_f(void) +{ + float x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +void f_d(void) +{ + double x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +struct S { int x[3]; }; + +void f_S(void) +{ + struct S x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c new file mode 100644 index 00000000000..09174e04ae6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c @@ -0,0 +1,62 @@ +/* Executable testcase for 'output flags.' */ +/* { dg-do run } */ + +int test_bits (long nzcv) +{ + long n, z, c, v; + + __asm__ ("msr APSR_nzcvq, %[in]" + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) + : [in] "r"(nzcv << 28)); + + return n * 8 + z * 4 + c * 2 + v == nzcv; +} + +int test_cmps (long x, long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int test_cmpu (unsigned long x, unsigned long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int main () +{ + long i, j; + + for (i = 0; i < 16; ++i) + if (!test_bits (i)) + __builtin_abort (); + + for (i = -1; i <= 1; ++i) + for (j = -1; j <= 1; ++j) + if (!test_cmps (i, j)) + __builtin_abort (); + + for (i = 0; i <= 2; ++i) + for (j = 0; j <= 2; ++j) + if (!test_cmpu (i, j)) + __builtin_abort (); + + return 0; +} -- 2.17.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 5/6] arm: Add testsuite checks for asm-flag 2019-11-14 10:07 ` [PATCH v2 5/6] arm: Add testsuite checks for asm-flag Richard Henderson @ 2019-11-14 14:48 ` Richard Earnshaw (lists) 2019-11-18 12:28 ` Christophe Lyon 1 sibling, 0 replies; 26+ messages in thread From: Richard Earnshaw (lists) @ 2019-11-14 14:48 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford On 14/11/2019 10:07, Richard Henderson wrote: > Inspired by the tests in gcc.target/i386. Testing code generation, > diagnostics, and execution. > > * gcc.target/arm/asm-flag-1.c: New test. > * gcc.target/arm/asm-flag-3.c: New test. > * gcc.target/arm/asm-flag-5.c: New test. > * gcc.target/arm/asm-flag-6.c: New test. > --- > gcc/testsuite/gcc.target/arm/asm-flag-1.c | 36 +++++++++++++ > gcc/testsuite/gcc.target/arm/asm-flag-3.c | 38 ++++++++++++++ > gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 +++++++++++ > gcc/testsuite/gcc.target/arm/asm-flag-6.c | 62 +++++++++++++++++++++++ > 4 files changed, 166 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c These will/should clearly not work on thumb1 targets where the condition register is not exposed. On thumb2 I'd expect to see some testing for the correct IT instruction. R. > > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c > new file mode 100644 > index 00000000000..9707ebfcebb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c > @@ -0,0 +1,36 @@ > +/* Test the valid @cc<cc> asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "-O" } */ > + > +#ifndef __GCC_ASM_FLAG_OUTPUTS__ > +#error "missing preprocessor define" > +#endif > + > +void f(char *out) > +{ > + asm("" > + : "=@ccne"(out[0]), "=@cceq"(out[1]), > + "=@cccs"(out[2]), "=@cccc"(out[3]), > + "=@ccmi"(out[4]), "=@ccpl"(out[5]), > + "=@ccvs"(out[6]), "=@ccvc"(out[7]), > + "=@cchi"(out[8]), "=@ccls"(out[9]), > + "=@ccge"(out[10]), "=@cclt"(out[11]), > + "=@ccgt"(out[12]), "=@ccle"(out[13]), > + "=@cchs"(out[14]), "=@cclo"(out[15])); > +} > + > +/* There will be at least one of each. */ > +/* { dg-final { scan-assembler "movne" } } */ > +/* { dg-final { scan-assembler "moveq" } } */ > +/* { dg-final { scan-assembler "movcs" } } */ > +/* { dg-final { scan-assembler "movcc" } } */ > +/* { dg-final { scan-assembler "movmi" } } */ > +/* { dg-final { scan-assembler "movpl" } } */ > +/* { dg-final { scan-assembler "movvs" } } */ > +/* { dg-final { scan-assembler "movvc" } } */ > +/* { dg-final { scan-assembler "movhi" } } */ > +/* { dg-final { scan-assembler "movls" } } */ > +/* { dg-final { scan-assembler "movge" } } */ > +/* { dg-final { scan-assembler "movls" } } */ > +/* { dg-final { scan-assembler "movgt" } } */ > +/* { dg-final { scan-assembler "movle" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c > new file mode 100644 > index 00000000000..e84e3431277 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c > @@ -0,0 +1,38 @@ > +/* Test some of the valid @cc<cc> asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "-O" } */ > + > +#define DO(C) \ > +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } > + > +DO(ne) > +DO(eq) > +DO(cs) > +DO(cc) > +DO(hs) > +DO(lo) > +DO(mi) > +DO(pl) > +DO(vs) > +DO(vc) > +DO(hi) > +DO(ls) > +DO(ge) > +DO(lt) > +DO(gt) > +DO(le) > + > +/* { dg-final { scan-assembler "bne" } } */ > +/* { dg-final { scan-assembler "beq" } } */ > +/* { dg-final { scan-assembler "bcs" } } */ > +/* { dg-final { scan-assembler "bcc" } } */ > +/* { dg-final { scan-assembler "bmi" } } */ > +/* { dg-final { scan-assembler "bpl" } } */ > +/* { dg-final { scan-assembler "bvs" } } */ > +/* { dg-final { scan-assembler "bvc" } } */ > +/* { dg-final { scan-assembler "bhi" } } */ > +/* { dg-final { scan-assembler "bls" } } */ > +/* { dg-final { scan-assembler "bge" } } */ > +/* { dg-final { scan-assembler "blt" } } */ > +/* { dg-final { scan-assembler "bgt" } } */ > +/* { dg-final { scan-assembler "ble" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c > new file mode 100644 > index 00000000000..4d4394e1478 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c > @@ -0,0 +1,30 @@ > +/* Test error conditions of asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "" } */ > + > +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } > +void f_c(void) { char x; asm("" : "=@cccc"(x)); } > +void f_s(void) { short x; asm("" : "=@cccc"(x)); } > +void f_i(void) { int x; asm("" : "=@cccc"(x)); } > +void f_l(void) { long x; asm("" : "=@cccc"(x)); } > +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } > + > +void f_f(void) > +{ > + float x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > + > +void f_d(void) > +{ > + double x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > + > +struct S { int x[3]; }; > + > +void f_S(void) > +{ > + struct S x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c > new file mode 100644 > index 00000000000..09174e04ae6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c > @@ -0,0 +1,62 @@ > +/* Executable testcase for 'output flags.' */ > +/* { dg-do run } */ > + > +int test_bits (long nzcv) > +{ > + long n, z, c, v; > + > + __asm__ ("msr APSR_nzcvq, %[in]" > + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) > + : [in] "r"(nzcv << 28)); > + > + return n * 8 + z * 4 + c * 2 + v == nzcv; > +} > + > +int test_cmps (long x, long y) > +{ > + long gt, lt, ge, le; > + > + __asm__ ("cmp %[x], %[y]" > + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) > + : [x] "r"(x), [y] "r"(y)); > + > + return (gt == (x > y) > + && lt == (x < y) > + && ge == (x >= y) > + && le == (x <= y)); > +} > + > +int test_cmpu (unsigned long x, unsigned long y) > +{ > + long gt, lt, ge, le; > + > + __asm__ ("cmp %[x], %[y]" > + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) > + : [x] "r"(x), [y] "r"(y)); > + > + return (gt == (x > y) > + && lt == (x < y) > + && ge == (x >= y) > + && le == (x <= y)); > +} > + > +int main () > +{ > + long i, j; > + > + for (i = 0; i < 16; ++i) > + if (!test_bits (i)) > + __builtin_abort (); > + > + for (i = -1; i <= 1; ++i) > + for (j = -1; j <= 1; ++j) > + if (!test_cmps (i, j)) > + __builtin_abort (); > + > + for (i = 0; i <= 2; ++i) > + for (j = 0; j <= 2; ++j) > + if (!test_cmpu (i, j)) > + __builtin_abort (); > + > + return 0; > +} > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 5/6] arm: Add testsuite checks for asm-flag 2019-11-14 10:07 ` [PATCH v2 5/6] arm: Add testsuite checks for asm-flag Richard Henderson 2019-11-14 14:48 ` Richard Earnshaw (lists) @ 2019-11-18 12:28 ` Christophe Lyon 2019-11-18 13:32 ` Richard Henderson 1 sibling, 1 reply; 26+ messages in thread From: Christophe Lyon @ 2019-11-18 12:28 UTC (permalink / raw) To: Richard Henderson Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford Hi Richard On Thu, 14 Nov 2019 at 11:08, Richard Henderson <richard.henderson@linaro.org> wrote: > > Inspired by the tests in gcc.target/i386. Testing code generation, > diagnostics, and execution. > > * gcc.target/arm/asm-flag-1.c: New test. > * gcc.target/arm/asm-flag-3.c: New test. > * gcc.target/arm/asm-flag-5.c: New test. > * gcc.target/arm/asm-flag-6.c: New test. I've noticed ICEs when using -march=armv5t, but I believe these are fixed by your follow-up patch for thumb1. However, I've also noticed that asm-flag-6 fails at execution time when generating code for cortex-m (I have m3, m4, and m33 in my list) QEMU complains with: qemu: fatal: v7m_msr 2048 Indeed, it crashes on 0x000081c4: f383 8800 msr apsr, r3 Which looks like a qemu bug, probably similar to the vmsr one I fixed recently. While reading the ARM ARM, I also noticed that "apsr" is deprecated and should be "APSR_nzcvq" (as emitted by GCC), so it seems qemu's disassembler needs an update too. Do you want me to have a look at the qemu problems, or will you handle them? Thanks, Christophe > --- > gcc/testsuite/gcc.target/arm/asm-flag-1.c | 36 +++++++++++++ > gcc/testsuite/gcc.target/arm/asm-flag-3.c | 38 ++++++++++++++ > gcc/testsuite/gcc.target/arm/asm-flag-5.c | 30 +++++++++++ > gcc/testsuite/gcc.target/arm/asm-flag-6.c | 62 +++++++++++++++++++++++ > 4 files changed, 166 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c > create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c > > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-1.c b/gcc/testsuite/gcc.target/arm/asm-flag-1.c > new file mode 100644 > index 00000000000..9707ebfcebb > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-1.c > @@ -0,0 +1,36 @@ > +/* Test the valid @cc<cc> asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "-O" } */ > + > +#ifndef __GCC_ASM_FLAG_OUTPUTS__ > +#error "missing preprocessor define" > +#endif > + > +void f(char *out) > +{ > + asm("" > + : "=@ccne"(out[0]), "=@cceq"(out[1]), > + "=@cccs"(out[2]), "=@cccc"(out[3]), > + "=@ccmi"(out[4]), "=@ccpl"(out[5]), > + "=@ccvs"(out[6]), "=@ccvc"(out[7]), > + "=@cchi"(out[8]), "=@ccls"(out[9]), > + "=@ccge"(out[10]), "=@cclt"(out[11]), > + "=@ccgt"(out[12]), "=@ccle"(out[13]), > + "=@cchs"(out[14]), "=@cclo"(out[15])); > +} > + > +/* There will be at least one of each. */ > +/* { dg-final { scan-assembler "movne" } } */ > +/* { dg-final { scan-assembler "moveq" } } */ > +/* { dg-final { scan-assembler "movcs" } } */ > +/* { dg-final { scan-assembler "movcc" } } */ > +/* { dg-final { scan-assembler "movmi" } } */ > +/* { dg-final { scan-assembler "movpl" } } */ > +/* { dg-final { scan-assembler "movvs" } } */ > +/* { dg-final { scan-assembler "movvc" } } */ > +/* { dg-final { scan-assembler "movhi" } } */ > +/* { dg-final { scan-assembler "movls" } } */ > +/* { dg-final { scan-assembler "movge" } } */ > +/* { dg-final { scan-assembler "movls" } } */ > +/* { dg-final { scan-assembler "movgt" } } */ > +/* { dg-final { scan-assembler "movle" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-3.c b/gcc/testsuite/gcc.target/arm/asm-flag-3.c > new file mode 100644 > index 00000000000..e84e3431277 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-3.c > @@ -0,0 +1,38 @@ > +/* Test some of the valid @cc<cc> asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "-O" } */ > + > +#define DO(C) \ > +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } > + > +DO(ne) > +DO(eq) > +DO(cs) > +DO(cc) > +DO(hs) > +DO(lo) > +DO(mi) > +DO(pl) > +DO(vs) > +DO(vc) > +DO(hi) > +DO(ls) > +DO(ge) > +DO(lt) > +DO(gt) > +DO(le) > + > +/* { dg-final { scan-assembler "bne" } } */ > +/* { dg-final { scan-assembler "beq" } } */ > +/* { dg-final { scan-assembler "bcs" } } */ > +/* { dg-final { scan-assembler "bcc" } } */ > +/* { dg-final { scan-assembler "bmi" } } */ > +/* { dg-final { scan-assembler "bpl" } } */ > +/* { dg-final { scan-assembler "bvs" } } */ > +/* { dg-final { scan-assembler "bvc" } } */ > +/* { dg-final { scan-assembler "bhi" } } */ > +/* { dg-final { scan-assembler "bls" } } */ > +/* { dg-final { scan-assembler "bge" } } */ > +/* { dg-final { scan-assembler "blt" } } */ > +/* { dg-final { scan-assembler "bgt" } } */ > +/* { dg-final { scan-assembler "ble" } } */ > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-5.c b/gcc/testsuite/gcc.target/arm/asm-flag-5.c > new file mode 100644 > index 00000000000..4d4394e1478 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-5.c > @@ -0,0 +1,30 @@ > +/* Test error conditions of asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "" } */ > + > +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } > +void f_c(void) { char x; asm("" : "=@cccc"(x)); } > +void f_s(void) { short x; asm("" : "=@cccc"(x)); } > +void f_i(void) { int x; asm("" : "=@cccc"(x)); } > +void f_l(void) { long x; asm("" : "=@cccc"(x)); } > +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } > + > +void f_f(void) > +{ > + float x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > + > +void f_d(void) > +{ > + double x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > + > +struct S { int x[3]; }; > + > +void f_S(void) > +{ > + struct S x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > diff --git a/gcc/testsuite/gcc.target/arm/asm-flag-6.c b/gcc/testsuite/gcc.target/arm/asm-flag-6.c > new file mode 100644 > index 00000000000..09174e04ae6 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/asm-flag-6.c > @@ -0,0 +1,62 @@ > +/* Executable testcase for 'output flags.' */ > +/* { dg-do run } */ > + > +int test_bits (long nzcv) > +{ > + long n, z, c, v; > + > + __asm__ ("msr APSR_nzcvq, %[in]" > + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) > + : [in] "r"(nzcv << 28)); > + > + return n * 8 + z * 4 + c * 2 + v == nzcv; > +} > + > +int test_cmps (long x, long y) > +{ > + long gt, lt, ge, le; > + > + __asm__ ("cmp %[x], %[y]" > + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) > + : [x] "r"(x), [y] "r"(y)); > + > + return (gt == (x > y) > + && lt == (x < y) > + && ge == (x >= y) > + && le == (x <= y)); > +} > + > +int test_cmpu (unsigned long x, unsigned long y) > +{ > + long gt, lt, ge, le; > + > + __asm__ ("cmp %[x], %[y]" > + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) > + : [x] "r"(x), [y] "r"(y)); > + > + return (gt == (x > y) > + && lt == (x < y) > + && ge == (x >= y) > + && le == (x <= y)); > +} > + > +int main () > +{ > + long i, j; > + > + for (i = 0; i < 16; ++i) > + if (!test_bits (i)) > + __builtin_abort (); > + > + for (i = -1; i <= 1; ++i) > + for (j = -1; j <= 1; ++j) > + if (!test_cmps (i, j)) > + __builtin_abort (); > + > + for (i = 0; i <= 2; ++i) > + for (j = 0; j <= 2; ++j) > + if (!test_cmpu (i, j)) > + __builtin_abort (); > + > + return 0; > +} > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 5/6] arm: Add testsuite checks for asm-flag 2019-11-18 12:28 ` Christophe Lyon @ 2019-11-18 13:32 ` Richard Henderson 0 siblings, 0 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-18 13:32 UTC (permalink / raw) To: Christophe Lyon Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford On 11/18/19 1:25 PM, Christophe Lyon wrote: > Hi Richard > > On Thu, 14 Nov 2019 at 11:08, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> Inspired by the tests in gcc.target/i386. Testing code generation, >> diagnostics, and execution. >> >> * gcc.target/arm/asm-flag-1.c: New test. >> * gcc.target/arm/asm-flag-3.c: New test. >> * gcc.target/arm/asm-flag-5.c: New test. >> * gcc.target/arm/asm-flag-6.c: New test. > > I've noticed ICEs when using -march=armv5t, but I believe these are > fixed by your follow-up patch for thumb1. > > However, I've also noticed that asm-flag-6 fails at execution time > when generating code for cortex-m (I have m3, m4, and m33 in my list) > QEMU complains with: > qemu: fatal: v7m_msr 2048 > > Indeed, it crashes on > 0x000081c4: f383 8800 msr apsr, r3 > > Which looks like a qemu bug, probably similar to the vmsr one I fixed > recently. While reading the ARM ARM, I also noticed that "apsr" is > deprecated and should be "APSR_nzcvq" (as emitted by GCC), so it seems > qemu's disassembler needs an update too. Do you want me to have a look > at the qemu problems, or will you handle them? I can handle them. Thanks for the report. r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson ` (3 preceding siblings ...) 2019-11-14 10:07 ` [PATCH v2 5/6] arm: Add testsuite checks for asm-flag Richard Henderson @ 2019-11-14 10:07 ` Richard Henderson 2019-11-14 14:40 ` Richard Earnshaw (lists) 2019-11-14 14:53 ` Richard Earnshaw (lists) 2019-11-14 10:12 ` [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson 2019-11-14 13:13 ` [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Kyrill Tkachov 6 siblings, 2 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-14 10:07 UTC (permalink / raw) To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford Since all but a couple of lines is shared between the two targets, enable them both at once. * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare. * config/arm/aarch-common.c (arm_md_asm_adjust): New. * config/arm/arm-c.c (arm_cpu_builtins): Define __GCC_ASM_FLAG_OUTPUTS__. * config/arm/arm.c (TARGET_MD_ASM_ADJUST): New. * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): Define __GCC_ASM_FLAG_OUTPUTS__. * config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New. * doc/extend.texi (FlagOutputOperands): Add documentation for ARM and AArch64. --- gcc/config/arm/aarch-common-protos.h | 6 ++ gcc/config/aarch64/aarch64-c.c | 2 + gcc/config/aarch64/aarch64.c | 3 + gcc/config/arm/aarch-common.c | 136 +++++++++++++++++++++++++++ gcc/config/arm/arm-c.c | 1 + gcc/config/arm/arm.c | 3 + gcc/doc/extend.texi | 39 ++++++++ 7 files changed, 190 insertions(+) diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 3bf38a104f6..f15cf336e9d 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -23,6 +23,8 @@ #ifndef GCC_AARCH_COMMON_PROTOS_H #define GCC_AARCH_COMMON_PROTOS_H +#include "hard-reg-set.h" + extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *); extern bool aarch_rev16_p (rtx); extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); @@ -141,5 +143,9 @@ struct cpu_cost_table const struct vector_cost_table vect; }; +rtx_insn * +arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/, + vec<const char *> &constraints, + vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs); #endif /* GCC_AARCH_COMMON_PROTOS_H */ diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index 7c322ca0813..0af859f1c14 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -69,6 +69,8 @@ aarch64_define_unconditional_macros (cpp_reader *pfile) builtin_define ("__ARM_FEATURE_UNALIGNED"); builtin_define ("__ARM_PCS_AAPCS64"); builtin_define_with_int_value ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); + + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); } /* Undefine/redefine macros that depend on the current backend state and may diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d2a3c7ef90a..9a5f27fea3a 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -21933,6 +21933,9 @@ aarch64_libgcc_floating_mode_supported_p #undef TARGET_STRICT_ARGUMENT_NAMING #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true +#undef TARGET_MD_ASM_ADJUST +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-aarch64.h" diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c index 965a07a43e3..760ef6c9c0a 100644 --- a/gcc/config/arm/aarch-common.c +++ b/gcc/config/arm/aarch-common.c @@ -26,10 +26,16 @@ #include "config.h" #include "system.h" #include "coretypes.h" +#include "insn-modes.h" #include "tm.h" #include "rtl.h" #include "rtl-iter.h" #include "memmodel.h" +#include "diagnostic.h" +#include "tree.h" +#include "expr.h" +#include "function.h" +#include "emit-rtl.h" /* Return TRUE if X is either an arithmetic shift left, or is a multiplication by a power of two. */ @@ -520,3 +526,133 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) && !reg_overlap_mentioned_p (mul_result, mac_op0) && !reg_overlap_mentioned_p (mul_result, mac_op1)); } + +/* Worker function for TARGET_MD_ASM_ADJUST. + We implement asm flag outputs. */ + +rtx_insn * +arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/, + vec<const char *> &constraints, + vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/) +{ + bool saw_asm_flag = false; + + start_sequence (); + for (unsigned i = 0, n = outputs.length (); i < n; ++i) + { + const char *con = constraints[i]; + if (strncmp (con, "=@cc", 4) != 0) + continue; + con += 4; + if (strchr (con, ',') != NULL) + { + error ("alternatives not allowed in %<asm%> flag output"); + continue; + } + + machine_mode mode; + rtx_code code; + int con01 = 0; + +#define C(X, Y) (unsigned char)(X) * 256 + (unsigned char)(Y) + + /* All of the condition codes are two characters. */ + if (con[0] != 0 && con[1] != 0 && con[2] == 0) + con01 = C(con[0], con[1]); + + switch (con01) + { + case C('c', 'c'): + case C('l', 'o'): + mode = CC_Cmode, code = GEU; + break; + case C('c', 's'): + case C('h', 's'): + mode = CC_Cmode, code = LTU; + break; + case C('e', 'q'): + mode = CC_NZmode, code = EQ; + break; + case C('g', 'e'): + mode = CCmode, code = GE; + break; + case C('g', 't'): + mode = CCmode, code = GT; + break; + case C('h', 'i'): + mode = CCmode, code = GTU; + break; + case C('l', 'e'): + mode = CCmode, code = LE; + break; + case C('l', 's'): + mode = CCmode, code = LEU; + break; + case C('l', 't'): + mode = CCmode, code = LT; + break; + case C('m', 'i'): + mode = CC_NZmode, code = LT; + break; + case C('n', 'e'): + mode = CC_NZmode, code = NE; + break; + case C('p', 'l'): + mode = CC_NZmode, code = GE; + break; + case C('v', 'c'): + mode = CC_Vmode, code = EQ; + break; + case C('v', 's'): + mode = CC_Vmode, code = NE; + break; + default: + error ("unknown %<asm%> flag output %qs", constraints[i]); + continue; + } + +#undef C + + rtx dest = outputs[i]; + machine_mode dest_mode = GET_MODE (dest); + if (!SCALAR_INT_MODE_P (dest_mode)) + { + error ("invalid type for %<asm%> flag output"); + continue; + } + + if (!saw_asm_flag) + { + /* This is the first asm flag output. Here we put the flags + register in as the real output and adjust the condition to + allow it. */ + constraints[i] = "=c"; + outputs[i] = gen_rtx_REG (CCmode, CC_REGNUM); + saw_asm_flag = true; + } + else + { + /* We don't need the flags register as output twice. */ + constraints[i] = "=X"; + outputs[i] = gen_rtx_SCRATCH (word_mode); + } + + rtx x = gen_rtx_REG (mode, CC_REGNUM); + x = gen_rtx_fmt_ee (code, word_mode, x, const0_rtx); + + if (dest_mode == word_mode) + emit_insn (gen_rtx_SET (dest, x)); + else + { + rtx tmp = gen_reg_rtx (word_mode); + emit_insn (gen_rtx_SET (tmp, x)); + + tmp = convert_modes (dest_mode, word_mode, tmp, true); + emit_move_insn (dest, tmp); + } + } + rtx_insn *seq = get_insns (); + end_sequence (); + + return saw_asm_flag ? seq : NULL; +} diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c index 34695fa0112..c4485ce7af1 100644 --- a/gcc/config/arm/arm-c.c +++ b/gcc/config/arm/arm-c.c @@ -122,6 +122,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) if (arm_arch_notm) builtin_define ("__ARM_ARCH_ISA_ARM"); builtin_define ("__APCS_32__"); + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB); def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2); diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d996207853c..fea3882a2a6 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -816,6 +816,9 @@ static const struct attribute_spec arm_attribute_table[] = #undef TARGET_CONSTANT_ALIGNMENT #define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment + +#undef TARGET_MD_ASM_ADJUST +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust \f /* Obstack for minipool constant handling. */ static struct obstack minipool_obstack; diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index 9db4f9b1d29..1c8ae0d5cd3 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -9771,6 +9771,45 @@ referenced within the assembler template via @code{%0} etc, as there's no corresponding text in the assembly language. @table @asis +@item ARM +@itemx AArch64 +The flag output constraints for the ARM family are of the form +@samp{=@@cc@var{cond}} where @var{cond} is one of the standard +conditions defined in the ARM ARM for @code{ConditionHolds}. + +@table @code +@item eq +Z flag set, or equal +@item ne +Z flag clear or not equal +@item cs +@itemx hs +C flag set or unsigned greater than equal +@item cc +@itemx lo +C flag clear or unsigned less than +@item mi +N flag set or ``minus'' +@item pl +N flag clear or ``plus'' +@item vs +V flag set or signed overflow +@item vc +V flag clear +@item hi +unsigned greater than +@item ls +unsigned less than equal +@item ge +signed greater than equal +@item lt +signed less than +@item gt +signed greater than +@item le +signed less than equal +@end table + @item x86 family The flag output constraints for the x86 family are of the form @samp{=@@cc@var{cond}} where @var{cond} is one of the standard -- 2.17.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ 2019-11-14 10:07 ` [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson @ 2019-11-14 14:40 ` Richard Earnshaw (lists) 2019-11-14 15:09 ` Richard Henderson 2019-11-14 14:53 ` Richard Earnshaw (lists) 1 sibling, 1 reply; 26+ messages in thread From: Richard Earnshaw (lists) @ 2019-11-14 14:40 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford Not had a chance to look at this in detail, but I don't see any support for 1) Thumb1 where we do not expose the condition codes at all 2) Thumb2 where we need IT instructions along-side the conditional instructions themselves. How have you tested this for those targets? R. On 14/11/2019 10:07, Richard Henderson wrote: > Since all but a couple of lines is shared between the two targets, > enable them both at once. > > * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare. > * config/arm/aarch-common.c (arm_md_asm_adjust): New. > * config/arm/arm-c.c (arm_cpu_builtins): Define > __GCC_ASM_FLAG_OUTPUTS__. > * config/arm/arm.c (TARGET_MD_ASM_ADJUST): New. > * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): > Define __GCC_ASM_FLAG_OUTPUTS__. > * config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New. > * doc/extend.texi (FlagOutputOperands): Add documentation > for ARM and AArch64. > --- > gcc/config/arm/aarch-common-protos.h | 6 ++ > gcc/config/aarch64/aarch64-c.c | 2 + > gcc/config/aarch64/aarch64.c | 3 + > gcc/config/arm/aarch-common.c | 136 +++++++++++++++++++++++++++ > gcc/config/arm/arm-c.c | 1 + > gcc/config/arm/arm.c | 3 + > gcc/doc/extend.texi | 39 ++++++++ > 7 files changed, 190 insertions(+) > > diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h > index 3bf38a104f6..f15cf336e9d 100644 > --- a/gcc/config/arm/aarch-common-protos.h > +++ b/gcc/config/arm/aarch-common-protos.h > @@ -23,6 +23,8 @@ > #ifndef GCC_AARCH_COMMON_PROTOS_H > #define GCC_AARCH_COMMON_PROTOS_H > > +#include "hard-reg-set.h" > + > extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *); > extern bool aarch_rev16_p (rtx); > extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); > @@ -141,5 +143,9 @@ struct cpu_cost_table > const struct vector_cost_table vect; > }; > > +rtx_insn * > +arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/, > + vec<const char *> &constraints, > + vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs); > > #endif /* GCC_AARCH_COMMON_PROTOS_H */ > diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c > index 7c322ca0813..0af859f1c14 100644 > --- a/gcc/config/aarch64/aarch64-c.c > +++ b/gcc/config/aarch64/aarch64-c.c > @@ -69,6 +69,8 @@ aarch64_define_unconditional_macros (cpp_reader *pfile) > builtin_define ("__ARM_FEATURE_UNALIGNED"); > builtin_define ("__ARM_PCS_AAPCS64"); > builtin_define_with_int_value ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); > + > + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); > } > > /* Undefine/redefine macros that depend on the current backend state and may > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index d2a3c7ef90a..9a5f27fea3a 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -21933,6 +21933,9 @@ aarch64_libgcc_floating_mode_supported_p > #undef TARGET_STRICT_ARGUMENT_NAMING > #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true > > +#undef TARGET_MD_ASM_ADJUST > +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust > + > struct gcc_target targetm = TARGET_INITIALIZER; > > #include "gt-aarch64.h" > diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c > index 965a07a43e3..760ef6c9c0a 100644 > --- a/gcc/config/arm/aarch-common.c > +++ b/gcc/config/arm/aarch-common.c > @@ -26,10 +26,16 @@ > #include "config.h" > #include "system.h" > #include "coretypes.h" > +#include "insn-modes.h" > #include "tm.h" > #include "rtl.h" > #include "rtl-iter.h" > #include "memmodel.h" > +#include "diagnostic.h" > +#include "tree.h" > +#include "expr.h" > +#include "function.h" > +#include "emit-rtl.h" > > /* Return TRUE if X is either an arithmetic shift left, or > is a multiplication by a power of two. */ > @@ -520,3 +526,133 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) > && !reg_overlap_mentioned_p (mul_result, mac_op0) > && !reg_overlap_mentioned_p (mul_result, mac_op1)); > } > + > +/* Worker function for TARGET_MD_ASM_ADJUST. > + We implement asm flag outputs. */ > + > +rtx_insn * > +arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/, > + vec<const char *> &constraints, > + vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/) > +{ > + bool saw_asm_flag = false; > + > + start_sequence (); > + for (unsigned i = 0, n = outputs.length (); i < n; ++i) > + { > + const char *con = constraints[i]; > + if (strncmp (con, "=@cc", 4) != 0) > + continue; > + con += 4; > + if (strchr (con, ',') != NULL) > + { > + error ("alternatives not allowed in %<asm%> flag output"); > + continue; > + } > + > + machine_mode mode; > + rtx_code code; > + int con01 = 0; > + > +#define C(X, Y) (unsigned char)(X) * 256 + (unsigned char)(Y) > + > + /* All of the condition codes are two characters. */ > + if (con[0] != 0 && con[1] != 0 && con[2] == 0) > + con01 = C(con[0], con[1]); > + > + switch (con01) > + { > + case C('c', 'c'): > + case C('l', 'o'): > + mode = CC_Cmode, code = GEU; > + break; > + case C('c', 's'): > + case C('h', 's'): > + mode = CC_Cmode, code = LTU; > + break; > + case C('e', 'q'): > + mode = CC_NZmode, code = EQ; > + break; > + case C('g', 'e'): > + mode = CCmode, code = GE; > + break; > + case C('g', 't'): > + mode = CCmode, code = GT; > + break; > + case C('h', 'i'): > + mode = CCmode, code = GTU; > + break; > + case C('l', 'e'): > + mode = CCmode, code = LE; > + break; > + case C('l', 's'): > + mode = CCmode, code = LEU; > + break; > + case C('l', 't'): > + mode = CCmode, code = LT; > + break; > + case C('m', 'i'): > + mode = CC_NZmode, code = LT; > + break; > + case C('n', 'e'): > + mode = CC_NZmode, code = NE; > + break; > + case C('p', 'l'): > + mode = CC_NZmode, code = GE; > + break; > + case C('v', 'c'): > + mode = CC_Vmode, code = EQ; > + break; > + case C('v', 's'): > + mode = CC_Vmode, code = NE; > + break; > + default: > + error ("unknown %<asm%> flag output %qs", constraints[i]); > + continue; > + } > + > +#undef C > + > + rtx dest = outputs[i]; > + machine_mode dest_mode = GET_MODE (dest); > + if (!SCALAR_INT_MODE_P (dest_mode)) > + { > + error ("invalid type for %<asm%> flag output"); > + continue; > + } > + > + if (!saw_asm_flag) > + { > + /* This is the first asm flag output. Here we put the flags > + register in as the real output and adjust the condition to > + allow it. */ > + constraints[i] = "=c"; > + outputs[i] = gen_rtx_REG (CCmode, CC_REGNUM); > + saw_asm_flag = true; > + } > + else > + { > + /* We don't need the flags register as output twice. */ > + constraints[i] = "=X"; > + outputs[i] = gen_rtx_SCRATCH (word_mode); > + } > + > + rtx x = gen_rtx_REG (mode, CC_REGNUM); > + x = gen_rtx_fmt_ee (code, word_mode, x, const0_rtx); > + > + if (dest_mode == word_mode) > + emit_insn (gen_rtx_SET (dest, x)); > + else > + { > + rtx tmp = gen_reg_rtx (word_mode); > + emit_insn (gen_rtx_SET (tmp, x)); > + > + tmp = convert_modes (dest_mode, word_mode, tmp, true); > + emit_move_insn (dest, tmp); > + } > + } > + rtx_insn *seq = get_insns (); > + end_sequence (); > + > + return saw_asm_flag ? seq : NULL; > +} > diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c > index 34695fa0112..c4485ce7af1 100644 > --- a/gcc/config/arm/arm-c.c > +++ b/gcc/config/arm/arm-c.c > @@ -122,6 +122,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) > if (arm_arch_notm) > builtin_define ("__ARM_ARCH_ISA_ARM"); > builtin_define ("__APCS_32__"); > + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); > > def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB); > def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2); > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index d996207853c..fea3882a2a6 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -816,6 +816,9 @@ static const struct attribute_spec arm_attribute_table[] = > > #undef TARGET_CONSTANT_ALIGNMENT > #define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment > + > +#undef TARGET_MD_ASM_ADJUST > +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust > \f > /* Obstack for minipool constant handling. */ > static struct obstack minipool_obstack; > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 9db4f9b1d29..1c8ae0d5cd3 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -9771,6 +9771,45 @@ referenced within the assembler template via @code{%0} etc, as there's > no corresponding text in the assembly language. > > @table @asis > +@item ARM > +@itemx AArch64 > +The flag output constraints for the ARM family are of the form > +@samp{=@@cc@var{cond}} where @var{cond} is one of the standard > +conditions defined in the ARM ARM for @code{ConditionHolds}. > + > +@table @code > +@item eq > +Z flag set, or equal > +@item ne > +Z flag clear or not equal > +@item cs > +@itemx hs > +C flag set or unsigned greater than equal > +@item cc > +@itemx lo > +C flag clear or unsigned less than > +@item mi > +N flag set or ``minus'' > +@item pl > +N flag clear or ``plus'' > +@item vs > +V flag set or signed overflow > +@item vc > +V flag clear > +@item hi > +unsigned greater than > +@item ls > +unsigned less than equal > +@item ge > +signed greater than equal > +@item lt > +signed less than > +@item gt > +signed greater than > +@item le > +signed less than equal > +@end table > + > @item x86 family > The flag output constraints for the x86 family are of the form > @samp{=@@cc@var{cond}} where @var{cond} is one of the standard > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ 2019-11-14 14:40 ` Richard Earnshaw (lists) @ 2019-11-14 15:09 ` Richard Henderson 2019-11-14 15:22 ` Richard Earnshaw (lists) 0 siblings, 1 reply; 26+ messages in thread From: Richard Henderson @ 2019-11-14 15:09 UTC (permalink / raw) To: Richard Earnshaw (lists), gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford On 11/14/19 3:39 PM, Richard Earnshaw (lists) wrote: > Not had a chance to look at this in detail, but I don't see any support for > > 1) Thumb1 where we do not expose the condition codes at all > 2) Thumb2 where we need IT instructions along-side the conditional instructions > themselves. > > How have you tested this for those targets? I tested aarch64-linux and arm-elf-eabi (I'm currently 8 time zones away from my arm-linux-eabihf box, so using sim). I didn't know about the thumb1 restriction. I had assumed somehow that we'd just use branch insns to form whatever cstore* is required. I suppose it's easy enough to generate an error/sorry for asm-flags in thumb1 mode. As for thumb2, correct behaviour comes from the existing cstore* patterns, and the testsuite need not check for IT specifically because unified asm syntax says that the insns that are conditional under the IT should still bear the conditions themselves. I presume I can test both of these cases with arm-elf-eabi + -mthumb{1,2}? r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ 2019-11-14 15:09 ` Richard Henderson @ 2019-11-14 15:22 ` Richard Earnshaw (lists) 0 siblings, 0 replies; 26+ messages in thread From: Richard Earnshaw (lists) @ 2019-11-14 15:22 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford On 14/11/2019 15:06, Richard Henderson wrote: > On 11/14/19 3:39 PM, Richard Earnshaw (lists) wrote: >> Not had a chance to look at this in detail, but I don't see any support for >> >> 1) Thumb1 where we do not expose the condition codes at all >> 2) Thumb2 where we need IT instructions along-side the conditional instructions >> themselves. >> >> How have you tested this for those targets? > > I tested aarch64-linux and arm-elf-eabi (I'm currently 8 time zones away from > my arm-linux-eabihf box, so using sim). > > I didn't know about the thumb1 restriction. I had assumed somehow that we'd > just use branch insns to form whatever cstore* is required. I suppose it's > easy enough to generate an error/sorry for asm-flags in thumb1 mode. I suggest we just suppress the __GCC_ASM_FLAG_OUTPUTS__ define if targetting thumb1. In the tests, we then just make the code PASS in that case. > > As for thumb2, correct behaviour comes from the existing cstore* patterns, and > the testsuite need not check for IT specifically because unified asm syntax > says that the insns that are conditional under the IT should still bear the > conditions themselves. > > I presume I can test both of these cases with arm-elf-eabi + -mthumb{1,2}? Not quite, selection of thumb/thumb1 is controlled by the architecture (or the cpu that causes the architecture chosen). There are several helpers in target-supports.exp to help with testing if the selected architecture has thumb/thumb2/neither as appropriate. R. > > > r~ > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ 2019-11-14 10:07 ` [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson 2019-11-14 14:40 ` Richard Earnshaw (lists) @ 2019-11-14 14:53 ` Richard Earnshaw (lists) 2019-11-14 15:14 ` Richard Henderson 1 sibling, 1 reply; 26+ messages in thread From: Richard Earnshaw (lists) @ 2019-11-14 14:53 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford On 14/11/2019 10:07, Richard Henderson wrote: > Since all but a couple of lines is shared between the two targets, > enable them both at once. > > * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare. > * config/arm/aarch-common.c (arm_md_asm_adjust): New. > * config/arm/arm-c.c (arm_cpu_builtins): Define > __GCC_ASM_FLAG_OUTPUTS__. > * config/arm/arm.c (TARGET_MD_ASM_ADJUST): New. > * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): > Define __GCC_ASM_FLAG_OUTPUTS__. > * config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New. > * doc/extend.texi (FlagOutputOperands): Add documentation > for ARM and AArch64. In AArch64 when SVE is enabled, there are some additional condition names which are more suited for describing the way conditions are set by the SVE instructions. Do you plan to support those as well? R. > --- > gcc/config/arm/aarch-common-protos.h | 6 ++ > gcc/config/aarch64/aarch64-c.c | 2 + > gcc/config/aarch64/aarch64.c | 3 + > gcc/config/arm/aarch-common.c | 136 +++++++++++++++++++++++++++ > gcc/config/arm/arm-c.c | 1 + > gcc/config/arm/arm.c | 3 + > gcc/doc/extend.texi | 39 ++++++++ > 7 files changed, 190 insertions(+) > > diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h > index 3bf38a104f6..f15cf336e9d 100644 > --- a/gcc/config/arm/aarch-common-protos.h > +++ b/gcc/config/arm/aarch-common-protos.h > @@ -23,6 +23,8 @@ > #ifndef GCC_AARCH_COMMON_PROTOS_H > #define GCC_AARCH_COMMON_PROTOS_H > > +#include "hard-reg-set.h" > + > extern int aarch_accumulator_forwarding (rtx_insn *, rtx_insn *); > extern bool aarch_rev16_p (rtx); > extern bool aarch_rev16_shleft_mask_imm_p (rtx, machine_mode); > @@ -141,5 +143,9 @@ struct cpu_cost_table > const struct vector_cost_table vect; > }; > > +rtx_insn * > +arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/, > + vec<const char *> &constraints, > + vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs); > > #endif /* GCC_AARCH_COMMON_PROTOS_H */ > diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c > index 7c322ca0813..0af859f1c14 100644 > --- a/gcc/config/aarch64/aarch64-c.c > +++ b/gcc/config/aarch64/aarch64-c.c > @@ -69,6 +69,8 @@ aarch64_define_unconditional_macros (cpp_reader *pfile) > builtin_define ("__ARM_FEATURE_UNALIGNED"); > builtin_define ("__ARM_PCS_AAPCS64"); > builtin_define_with_int_value ("__ARM_SIZEOF_WCHAR_T", WCHAR_TYPE_SIZE / 8); > + > + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); > } > > /* Undefine/redefine macros that depend on the current backend state and may > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c > index d2a3c7ef90a..9a5f27fea3a 100644 > --- a/gcc/config/aarch64/aarch64.c > +++ b/gcc/config/aarch64/aarch64.c > @@ -21933,6 +21933,9 @@ aarch64_libgcc_floating_mode_supported_p > #undef TARGET_STRICT_ARGUMENT_NAMING > #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true > > +#undef TARGET_MD_ASM_ADJUST > +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust > + > struct gcc_target targetm = TARGET_INITIALIZER; > > #include "gt-aarch64.h" > diff --git a/gcc/config/arm/aarch-common.c b/gcc/config/arm/aarch-common.c > index 965a07a43e3..760ef6c9c0a 100644 > --- a/gcc/config/arm/aarch-common.c > +++ b/gcc/config/arm/aarch-common.c > @@ -26,10 +26,16 @@ > #include "config.h" > #include "system.h" > #include "coretypes.h" > +#include "insn-modes.h" > #include "tm.h" > #include "rtl.h" > #include "rtl-iter.h" > #include "memmodel.h" > +#include "diagnostic.h" > +#include "tree.h" > +#include "expr.h" > +#include "function.h" > +#include "emit-rtl.h" > > /* Return TRUE if X is either an arithmetic shift left, or > is a multiplication by a power of two. */ > @@ -520,3 +526,133 @@ arm_mac_accumulator_is_mul_result (rtx producer, rtx consumer) > && !reg_overlap_mentioned_p (mul_result, mac_op0) > && !reg_overlap_mentioned_p (mul_result, mac_op1)); > } > + > +/* Worker function for TARGET_MD_ASM_ADJUST. > + We implement asm flag outputs. */ > + > +rtx_insn * > +arm_md_asm_adjust (vec<rtx> &outputs, vec<rtx> &/*inputs*/, > + vec<const char *> &constraints, > + vec<rtx> &/*clobbers*/, HARD_REG_SET &/*clobbered_regs*/) > +{ > + bool saw_asm_flag = false; > + > + start_sequence (); > + for (unsigned i = 0, n = outputs.length (); i < n; ++i) > + { > + const char *con = constraints[i]; > + if (strncmp (con, "=@cc", 4) != 0) > + continue; > + con += 4; > + if (strchr (con, ',') != NULL) > + { > + error ("alternatives not allowed in %<asm%> flag output"); > + continue; > + } > + > + machine_mode mode; > + rtx_code code; > + int con01 = 0; > + > +#define C(X, Y) (unsigned char)(X) * 256 + (unsigned char)(Y) > + > + /* All of the condition codes are two characters. */ > + if (con[0] != 0 && con[1] != 0 && con[2] == 0) > + con01 = C(con[0], con[1]); > + > + switch (con01) > + { > + case C('c', 'c'): > + case C('l', 'o'): > + mode = CC_Cmode, code = GEU; > + break; > + case C('c', 's'): > + case C('h', 's'): > + mode = CC_Cmode, code = LTU; > + break; > + case C('e', 'q'): > + mode = CC_NZmode, code = EQ; > + break; > + case C('g', 'e'): > + mode = CCmode, code = GE; > + break; > + case C('g', 't'): > + mode = CCmode, code = GT; > + break; > + case C('h', 'i'): > + mode = CCmode, code = GTU; > + break; > + case C('l', 'e'): > + mode = CCmode, code = LE; > + break; > + case C('l', 's'): > + mode = CCmode, code = LEU; > + break; > + case C('l', 't'): > + mode = CCmode, code = LT; > + break; > + case C('m', 'i'): > + mode = CC_NZmode, code = LT; > + break; > + case C('n', 'e'): > + mode = CC_NZmode, code = NE; > + break; > + case C('p', 'l'): > + mode = CC_NZmode, code = GE; > + break; > + case C('v', 'c'): > + mode = CC_Vmode, code = EQ; > + break; > + case C('v', 's'): > + mode = CC_Vmode, code = NE; > + break; > + default: > + error ("unknown %<asm%> flag output %qs", constraints[i]); > + continue; > + } > + > +#undef C > + > + rtx dest = outputs[i]; > + machine_mode dest_mode = GET_MODE (dest); > + if (!SCALAR_INT_MODE_P (dest_mode)) > + { > + error ("invalid type for %<asm%> flag output"); > + continue; > + } > + > + if (!saw_asm_flag) > + { > + /* This is the first asm flag output. Here we put the flags > + register in as the real output and adjust the condition to > + allow it. */ > + constraints[i] = "=c"; > + outputs[i] = gen_rtx_REG (CCmode, CC_REGNUM); > + saw_asm_flag = true; > + } > + else > + { > + /* We don't need the flags register as output twice. */ > + constraints[i] = "=X"; > + outputs[i] = gen_rtx_SCRATCH (word_mode); > + } > + > + rtx x = gen_rtx_REG (mode, CC_REGNUM); > + x = gen_rtx_fmt_ee (code, word_mode, x, const0_rtx); > + > + if (dest_mode == word_mode) > + emit_insn (gen_rtx_SET (dest, x)); > + else > + { > + rtx tmp = gen_reg_rtx (word_mode); > + emit_insn (gen_rtx_SET (tmp, x)); > + > + tmp = convert_modes (dest_mode, word_mode, tmp, true); > + emit_move_insn (dest, tmp); > + } > + } > + rtx_insn *seq = get_insns (); > + end_sequence (); > + > + return saw_asm_flag ? seq : NULL; > +} > diff --git a/gcc/config/arm/arm-c.c b/gcc/config/arm/arm-c.c > index 34695fa0112..c4485ce7af1 100644 > --- a/gcc/config/arm/arm-c.c > +++ b/gcc/config/arm/arm-c.c > @@ -122,6 +122,7 @@ arm_cpu_builtins (struct cpp_reader* pfile) > if (arm_arch_notm) > builtin_define ("__ARM_ARCH_ISA_ARM"); > builtin_define ("__APCS_32__"); > + builtin_define ("__GCC_ASM_FLAG_OUTPUTS__"); > > def_or_undef_macro (pfile, "__thumb__", TARGET_THUMB); > def_or_undef_macro (pfile, "__thumb2__", TARGET_THUMB2); > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index d996207853c..fea3882a2a6 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -816,6 +816,9 @@ static const struct attribute_spec arm_attribute_table[] = > > #undef TARGET_CONSTANT_ALIGNMENT > #define TARGET_CONSTANT_ALIGNMENT arm_constant_alignment > + > +#undef TARGET_MD_ASM_ADJUST > +#define TARGET_MD_ASM_ADJUST arm_md_asm_adjust > \f > /* Obstack for minipool constant handling. */ > static struct obstack minipool_obstack; > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi > index 9db4f9b1d29..1c8ae0d5cd3 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -9771,6 +9771,45 @@ referenced within the assembler template via @code{%0} etc, as there's > no corresponding text in the assembly language. > > @table @asis > +@item ARM > +@itemx AArch64 > +The flag output constraints for the ARM family are of the form > +@samp{=@@cc@var{cond}} where @var{cond} is one of the standard > +conditions defined in the ARM ARM for @code{ConditionHolds}. > + > +@table @code > +@item eq > +Z flag set, or equal > +@item ne > +Z flag clear or not equal > +@item cs > +@itemx hs > +C flag set or unsigned greater than equal > +@item cc > +@itemx lo > +C flag clear or unsigned less than > +@item mi > +N flag set or ``minus'' > +@item pl > +N flag clear or ``plus'' > +@item vs > +V flag set or signed overflow > +@item vc > +V flag clear > +@item hi > +unsigned greater than > +@item ls > +unsigned less than equal > +@item ge > +signed greater than equal > +@item lt > +signed less than > +@item gt > +signed greater than > +@item le > +signed less than equal > +@end table > + > @item x86 family > The flag output constraints for the x86 family are of the form > @samp{=@@cc@var{cond}} where @var{cond} is one of the standard > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ 2019-11-14 14:53 ` Richard Earnshaw (lists) @ 2019-11-14 15:14 ` Richard Henderson 0 siblings, 0 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-14 15:14 UTC (permalink / raw) To: Richard Earnshaw (lists), gcc-patches; +Cc: kyrylo.tkachov, richard.sandiford On 11/14/19 3:48 PM, Richard Earnshaw (lists) wrote: > On 14/11/2019 10:07, Richard Henderson wrote: >> Since all but a couple of lines is shared between the two targets, >> enable them both at once. >> >>     * config/arm/aarch-common-protos.h (arm_md_asm_adjust): Declare. >>     * config/arm/aarch-common.c (arm_md_asm_adjust): New. >>     * config/arm/arm-c.c (arm_cpu_builtins): Define >>     __GCC_ASM_FLAG_OUTPUTS__. >>     * config/arm/arm.c (TARGET_MD_ASM_ADJUST): New. >>     * config/aarch64/aarch64-c.c (aarch64_define_unconditional_macros): >>     Define __GCC_ASM_FLAG_OUTPUTS__. >>     * config/aarch64/aarch64.c (TARGET_MD_ASM_ADJUST): New. >>     * doc/extend.texi (FlagOutputOperands): Add documentation >>     for ARM and AArch64. > > In AArch64 when SVE is enabled, there are some additional condition names which > are more suited for describing the way conditions are set by the SVE > instructions. Do you plan to support those as well? I did not, no. I read the acle spec once at the beginning of the year, and vaguely recall that it already covers pretty much all one wants to do. I haven't given much thought to sve in inline asm since. I suppose I can add them if they're thought important. r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson ` (4 preceding siblings ...) 2019-11-14 10:07 ` [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson @ 2019-11-14 10:12 ` Richard Henderson 2019-11-18 12:35 ` Christophe Lyon 2019-11-14 13:13 ` [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Kyrill Tkachov 6 siblings, 1 reply; 26+ messages in thread From: Richard Henderson @ 2019-11-14 10:12 UTC (permalink / raw) To: gcc-patches; +Cc: richard.earnshaw, kyrylo.tkachov, richard.sandiford Inspired by the tests in gcc.target/i386. Testing code generation, diagnostics, and execution. * gcc.target/aarch64/asm-flag-1.c: New test. * gcc.target/aarch64/asm-flag-3.c: New test. * gcc.target/aarch64/asm-flag-5.c: New test. * gcc.target/aarch64/asm-flag-6.c: New test. --- gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 +++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++ gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 +++++++++++++++++++ 4 files changed, 165 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c new file mode 100644 index 00000000000..49901e59c38 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c @@ -0,0 +1,35 @@ +/* Test the valid @cc<cc> asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#ifndef __GCC_ASM_FLAG_OUTPUTS__ +#error "missing preprocessor define" +#endif + +void f(char *out) +{ + asm("" + : "=@ccne"(out[0]), "=@cceq"(out[1]), + "=@cccs"(out[2]), "=@cccc"(out[3]), + "=@ccmi"(out[4]), "=@ccpl"(out[5]), + "=@ccvs"(out[6]), "=@ccvc"(out[7]), + "=@cchi"(out[8]), "=@ccls"(out[9]), + "=@ccge"(out[10]), "=@cclt"(out[11]), + "=@ccgt"(out[12]), "=@ccle"(out[13]), + "=@cchs"(out[14]), "=@cclo"(out[15])); +} + +/* { dg-final { scan-assembler "cset.*, ne" } } */ +/* { dg-final { scan-assembler "cset.*, eq" } } */ +/* { dg-final { scan-assembler "cset.*, cs" } } */ +/* { dg-final { scan-assembler "cset.*, cc" } } */ +/* { dg-final { scan-assembler "cset.*, mi" } } */ +/* { dg-final { scan-assembler "cset.*, pl" } } */ +/* { dg-final { scan-assembler "cset.*, vs" } } */ +/* { dg-final { scan-assembler "cset.*, vc" } } */ +/* { dg-final { scan-assembler "cset.*, hi" } } */ +/* { dg-final { scan-assembler "cset.*, ls" } } */ +/* { dg-final { scan-assembler "cset.*, ge" } } */ +/* { dg-final { scan-assembler "cset.*, ls" } } */ +/* { dg-final { scan-assembler "cset.*, gt" } } */ +/* { dg-final { scan-assembler "cset.*, le" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c new file mode 100644 index 00000000000..e84e3431277 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c @@ -0,0 +1,38 @@ +/* Test some of the valid @cc<cc> asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "-O" } */ + +#define DO(C) \ +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } + +DO(ne) +DO(eq) +DO(cs) +DO(cc) +DO(hs) +DO(lo) +DO(mi) +DO(pl) +DO(vs) +DO(vc) +DO(hi) +DO(ls) +DO(ge) +DO(lt) +DO(gt) +DO(le) + +/* { dg-final { scan-assembler "bne" } } */ +/* { dg-final { scan-assembler "beq" } } */ +/* { dg-final { scan-assembler "bcs" } } */ +/* { dg-final { scan-assembler "bcc" } } */ +/* { dg-final { scan-assembler "bmi" } } */ +/* { dg-final { scan-assembler "bpl" } } */ +/* { dg-final { scan-assembler "bvs" } } */ +/* { dg-final { scan-assembler "bvc" } } */ +/* { dg-final { scan-assembler "bhi" } } */ +/* { dg-final { scan-assembler "bls" } } */ +/* { dg-final { scan-assembler "bge" } } */ +/* { dg-final { scan-assembler "blt" } } */ +/* { dg-final { scan-assembler "bgt" } } */ +/* { dg-final { scan-assembler "ble" } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c new file mode 100644 index 00000000000..4d4394e1478 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c @@ -0,0 +1,30 @@ +/* Test error conditions of asm flag outputs. */ +/* { dg-do compile } */ +/* { dg-options "" } */ + +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } +void f_c(void) { char x; asm("" : "=@cccc"(x)); } +void f_s(void) { short x; asm("" : "=@cccc"(x)); } +void f_i(void) { int x; asm("" : "=@cccc"(x)); } +void f_l(void) { long x; asm("" : "=@cccc"(x)); } +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } + +void f_f(void) +{ + float x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +void f_d(void) +{ + double x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} + +struct S { int x[3]; }; + +void f_S(void) +{ + struct S x; + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c new file mode 100644 index 00000000000..963b5a48c70 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c @@ -0,0 +1,62 @@ +/* Executable testcase for 'output flags.' */ +/* { dg-do run } */ + +int test_bits (long nzcv) +{ + long n, z, c, v; + + __asm__ ("msr nzcv, %[in]" + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) + : [in] "r"(nzcv << 28)); + + return n * 8 + z * 4 + c * 2 + v == nzcv; +} + +int test_cmps (long x, long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int test_cmpu (unsigned long x, unsigned long y) +{ + long gt, lt, ge, le; + + __asm__ ("cmp %[x], %[y]" + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) + : [x] "r"(x), [y] "r"(y)); + + return (gt == (x > y) + && lt == (x < y) + && ge == (x >= y) + && le == (x <= y)); +} + +int main () +{ + long i, j; + + for (i = 0; i < 16; ++i) + if (!test_bits (i)) + __builtin_abort (); + + for (i = -1; i <= 1; ++i) + for (j = -1; j <= 1; ++j) + if (!test_cmps (i, j)) + __builtin_abort (); + + for (i = 0; i <= 2; ++i) + for (j = 0; j <= 2; ++j) + if (!test_cmpu (i, j)) + __builtin_abort (); + + return 0; +} -- 2.17.1 ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-14 10:12 ` [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson @ 2019-11-18 12:35 ` Christophe Lyon 2019-11-18 20:06 ` Richard Henderson 0 siblings, 1 reply; 26+ messages in thread From: Christophe Lyon @ 2019-11-18 12:35 UTC (permalink / raw) To: Richard Henderson Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford On Thu, 14 Nov 2019 at 11:08, Richard Henderson <richard.henderson@linaro.org> wrote: > > Inspired by the tests in gcc.target/i386. Testing code generation, > diagnostics, and execution. > > * gcc.target/aarch64/asm-flag-1.c: New test. > * gcc.target/aarch64/asm-flag-3.c: New test. > * gcc.target/aarch64/asm-flag-5.c: New test. > * gcc.target/aarch64/asm-flag-6.c: New test. Hi Richard, I'm sorry to notice that the last test (asm-flag-6.c) fails to execute when compiling with -mabi=ilp32. I have less details than for Arm, because here I'm using the Foundation Model as simulator instead of Qemu. In addition, I'm using an old version of it, so maybe it's a simulator bug. Does it work on your side? Thanks, Christophe > --- > gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 +++++++++++ > gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++++++++++ > gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++++++++ > gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 +++++++++++++++++++ > 4 files changed, 165 insertions(+) > create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c > create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c > > diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c > new file mode 100644 > index 00000000000..49901e59c38 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-1.c > @@ -0,0 +1,35 @@ > +/* Test the valid @cc<cc> asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "-O" } */ > + > +#ifndef __GCC_ASM_FLAG_OUTPUTS__ > +#error "missing preprocessor define" > +#endif > + > +void f(char *out) > +{ > + asm("" > + : "=@ccne"(out[0]), "=@cceq"(out[1]), > + "=@cccs"(out[2]), "=@cccc"(out[3]), > + "=@ccmi"(out[4]), "=@ccpl"(out[5]), > + "=@ccvs"(out[6]), "=@ccvc"(out[7]), > + "=@cchi"(out[8]), "=@ccls"(out[9]), > + "=@ccge"(out[10]), "=@cclt"(out[11]), > + "=@ccgt"(out[12]), "=@ccle"(out[13]), > + "=@cchs"(out[14]), "=@cclo"(out[15])); > +} > + > +/* { dg-final { scan-assembler "cset.*, ne" } } */ > +/* { dg-final { scan-assembler "cset.*, eq" } } */ > +/* { dg-final { scan-assembler "cset.*, cs" } } */ > +/* { dg-final { scan-assembler "cset.*, cc" } } */ > +/* { dg-final { scan-assembler "cset.*, mi" } } */ > +/* { dg-final { scan-assembler "cset.*, pl" } } */ > +/* { dg-final { scan-assembler "cset.*, vs" } } */ > +/* { dg-final { scan-assembler "cset.*, vc" } } */ > +/* { dg-final { scan-assembler "cset.*, hi" } } */ > +/* { dg-final { scan-assembler "cset.*, ls" } } */ > +/* { dg-final { scan-assembler "cset.*, ge" } } */ > +/* { dg-final { scan-assembler "cset.*, ls" } } */ > +/* { dg-final { scan-assembler "cset.*, gt" } } */ > +/* { dg-final { scan-assembler "cset.*, le" } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c > new file mode 100644 > index 00000000000..e84e3431277 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-3.c > @@ -0,0 +1,38 @@ > +/* Test some of the valid @cc<cc> asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "-O" } */ > + > +#define DO(C) \ > +void f##C(void) { char x; asm("" : "=@cc"#C(x)); if (!x) asm(""); asm(""); } > + > +DO(ne) > +DO(eq) > +DO(cs) > +DO(cc) > +DO(hs) > +DO(lo) > +DO(mi) > +DO(pl) > +DO(vs) > +DO(vc) > +DO(hi) > +DO(ls) > +DO(ge) > +DO(lt) > +DO(gt) > +DO(le) > + > +/* { dg-final { scan-assembler "bne" } } */ > +/* { dg-final { scan-assembler "beq" } } */ > +/* { dg-final { scan-assembler "bcs" } } */ > +/* { dg-final { scan-assembler "bcc" } } */ > +/* { dg-final { scan-assembler "bmi" } } */ > +/* { dg-final { scan-assembler "bpl" } } */ > +/* { dg-final { scan-assembler "bvs" } } */ > +/* { dg-final { scan-assembler "bvc" } } */ > +/* { dg-final { scan-assembler "bhi" } } */ > +/* { dg-final { scan-assembler "bls" } } */ > +/* { dg-final { scan-assembler "bge" } } */ > +/* { dg-final { scan-assembler "blt" } } */ > +/* { dg-final { scan-assembler "bgt" } } */ > +/* { dg-final { scan-assembler "ble" } } */ > diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c > new file mode 100644 > index 00000000000..4d4394e1478 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-5.c > @@ -0,0 +1,30 @@ > +/* Test error conditions of asm flag outputs. */ > +/* { dg-do compile } */ > +/* { dg-options "" } */ > + > +void f_B(void) { _Bool x; asm("" : "=@cccc"(x)); } > +void f_c(void) { char x; asm("" : "=@cccc"(x)); } > +void f_s(void) { short x; asm("" : "=@cccc"(x)); } > +void f_i(void) { int x; asm("" : "=@cccc"(x)); } > +void f_l(void) { long x; asm("" : "=@cccc"(x)); } > +void f_ll(void) { long long x; asm("" : "=@cccc"(x)); } > + > +void f_f(void) > +{ > + float x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > + > +void f_d(void) > +{ > + double x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > + > +struct S { int x[3]; }; > + > +void f_S(void) > +{ > + struct S x; > + asm("" : "=@cccc"(x)); /* { dg-error invalid type } */ > +} > diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c > new file mode 100644 > index 00000000000..963b5a48c70 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c > @@ -0,0 +1,62 @@ > +/* Executable testcase for 'output flags.' */ > +/* { dg-do run } */ > + > +int test_bits (long nzcv) > +{ > + long n, z, c, v; > + > + __asm__ ("msr nzcv, %[in]" > + : "=@ccmi"(n), "=@cceq"(z), "=@cccs"(c), "=@ccvs"(v) > + : [in] "r"(nzcv << 28)); > + > + return n * 8 + z * 4 + c * 2 + v == nzcv; > +} > + > +int test_cmps (long x, long y) > +{ > + long gt, lt, ge, le; > + > + __asm__ ("cmp %[x], %[y]" > + : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) > + : [x] "r"(x), [y] "r"(y)); > + > + return (gt == (x > y) > + && lt == (x < y) > + && ge == (x >= y) > + && le == (x <= y)); > +} > + > +int test_cmpu (unsigned long x, unsigned long y) > +{ > + long gt, lt, ge, le; > + > + __asm__ ("cmp %[x], %[y]" > + : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) > + : [x] "r"(x), [y] "r"(y)); > + > + return (gt == (x > y) > + && lt == (x < y) > + && ge == (x >= y) > + && le == (x <= y)); > +} > + > +int main () > +{ > + long i, j; > + > + for (i = 0; i < 16; ++i) > + if (!test_bits (i)) > + __builtin_abort (); > + > + for (i = -1; i <= 1; ++i) > + for (j = -1; j <= 1; ++j) > + if (!test_cmps (i, j)) > + __builtin_abort (); > + > + for (i = 0; i <= 2; ++i) > + for (j = 0; j <= 2; ++j) > + if (!test_cmpu (i, j)) > + __builtin_abort (); > + > + return 0; > +} > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-18 12:35 ` Christophe Lyon @ 2019-11-18 20:06 ` Richard Henderson 2019-11-18 21:35 ` Andreas Schwab 2019-11-19 8:38 ` Christophe Lyon 0 siblings, 2 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-18 20:06 UTC (permalink / raw) To: Christophe Lyon Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford On 11/18/19 1:30 PM, Christophe Lyon wrote: > I'm sorry to notice that the last test (asm-flag-6.c) fails to execute > when compiling with -mabi=ilp32. I have less details than for Arm, > because here I'm using the Foundation Model as simulator instead of > Qemu. In addition, I'm using an old version of it, so maybe it's a > simulator bug. Does it work on your side? I don't know how to test ilp32 with qemu. Is there a distribution that uses this mode, and one tests in system mode? We don't have user-only support for ilp32. I think I have reproduced this with newlib and aarch64-elf. It could be solvable by using either unsigned long long, or by using %w constraints with the two cmp instructions. Except that I made that change and the failure didn't go away. I'm having trouble building a version of gdb that can debug this... r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-18 20:06 ` Richard Henderson @ 2019-11-18 21:35 ` Andreas Schwab 2019-11-19 8:38 ` Christophe Lyon 1 sibling, 0 replies; 26+ messages in thread From: Andreas Schwab @ 2019-11-18 21:35 UTC (permalink / raw) To: Richard Henderson Cc: Christophe Lyon, gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford On Nov 18 2019, Richard Henderson wrote: > Except that I made that change and the failure didn't go away. I'm having > trouble building a version of gdb that can debug this... https://build.opensuse.org/package/show/devel:ARM:Factory:Contrib:ILP32/gdb has a gdb package that has support for ILP32. Andreas. -- Andreas Schwab, schwab@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different." ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-18 20:06 ` Richard Henderson 2019-11-18 21:35 ` Andreas Schwab @ 2019-11-19 8:38 ` Christophe Lyon 2019-11-19 9:26 ` Richard Henderson 1 sibling, 1 reply; 26+ messages in thread From: Christophe Lyon @ 2019-11-19 8:38 UTC (permalink / raw) To: Richard Henderson Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford On Mon, 18 Nov 2019 at 20:54, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 11/18/19 1:30 PM, Christophe Lyon wrote: > > I'm sorry to notice that the last test (asm-flag-6.c) fails to execute > > when compiling with -mabi=ilp32. I have less details than for Arm, > > because here I'm using the Foundation Model as simulator instead of > > Qemu. In addition, I'm using an old version of it, so maybe it's a > > simulator bug. Does it work on your side? > > I don't know how to test ilp32 with qemu. Is there a distribution that uses > this mode, and one tests in system mode? We don't have user-only support for > ilp32. > Sorry I wasn't clear: I test aarch64-elf with -mabi=ilp32, using newlib. > I think I have reproduced this with newlib and aarch64-elf. It could be > solvable by using either unsigned long long, or by using %w constraints with > the two cmp instructions. > > Except that I made that change and the failure didn't go away. I'm having > trouble building a version of gdb that can debug this... > > > r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-19 8:38 ` Christophe Lyon @ 2019-11-19 9:26 ` Richard Henderson 2019-11-19 10:12 ` Christophe Lyon 0 siblings, 1 reply; 26+ messages in thread From: Richard Henderson @ 2019-11-19 9:26 UTC (permalink / raw) To: Christophe Lyon Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford [-- Attachment #1: Type: text/plain, Size: 840 bytes --] On 11/19/19 9:29 AM, Christophe Lyon wrote: > On Mon, 18 Nov 2019 at 20:54, Richard Henderson > <richard.henderson@linaro.org> wrote: >> >> On 11/18/19 1:30 PM, Christophe Lyon wrote: >>> I'm sorry to notice that the last test (asm-flag-6.c) fails to execute >>> when compiling with -mabi=ilp32. I have less details than for Arm, >>> because here I'm using the Foundation Model as simulator instead of >>> Qemu. In addition, I'm using an old version of it, so maybe it's a >>> simulator bug. Does it work on your side? >> >> I don't know how to test ilp32 with qemu. Is there a distribution that uses >> this mode, and one tests in system mode? We don't have user-only support for >> ilp32. >> > > Sorry I wasn't clear: I test aarch64-elf with -mabi=ilp32, using newlib. In the short term, can you please try this testsuite patch? r~ [-- Attachment #2: z --] [-- Type: text/plain, Size: 944 bytes --] diff --git a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c index 963b5a48c70..54d7fbf317d 100644 --- a/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c +++ b/gcc/testsuite/gcc.target/aarch64/asm-flag-6.c @@ -1,6 +1,12 @@ /* Executable testcase for 'output flags.' */ /* { dg-do run } */ +#ifdef __LP64__ +#define W "" +#else +#define W "w" +#endif + int test_bits (long nzcv) { long n, z, c, v; @@ -16,7 +22,7 @@ int test_cmps (long x, long y) { long gt, lt, ge, le; - __asm__ ("cmp %[x], %[y]" + __asm__ ("cmp %"W"[x], %"W"[y]" : "=@ccgt"(gt), "=@cclt"(lt), "=@ccge"(ge), "=@ccle"(le) : [x] "r"(x), [y] "r"(y)); @@ -30,7 +36,7 @@ int test_cmpu (unsigned long x, unsigned long y) { long gt, lt, ge, le; - __asm__ ("cmp %[x], %[y]" + __asm__ ("cmp %"W"[x], %"W"[y]" : "=@cchi"(gt), "=@cclo"(lt), "=@cchs"(ge), "=@ccls"(le) : [x] "r"(x), [y] "r"(y)); ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag 2019-11-19 9:26 ` Richard Henderson @ 2019-11-19 10:12 ` Christophe Lyon 0 siblings, 0 replies; 26+ messages in thread From: Christophe Lyon @ 2019-11-19 10:12 UTC (permalink / raw) To: Richard Henderson Cc: gcc Patches, Richard Earnshaw, Kyrylo Tkachov, Richard Sandiford On Tue, 19 Nov 2019 at 10:23, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 11/19/19 9:29 AM, Christophe Lyon wrote: > > On Mon, 18 Nov 2019 at 20:54, Richard Henderson > > <richard.henderson@linaro.org> wrote: > >> > >> On 11/18/19 1:30 PM, Christophe Lyon wrote: > >>> I'm sorry to notice that the last test (asm-flag-6.c) fails to execute > >>> when compiling with -mabi=ilp32. I have less details than for Arm, > >>> because here I'm using the Foundation Model as simulator instead of > >>> Qemu. In addition, I'm using an old version of it, so maybe it's a > >>> simulator bug. Does it work on your side? > >> > >> I don't know how to test ilp32 with qemu. Is there a distribution that uses > >> this mode, and one tests in system mode? We don't have user-only support for > >> ilp32. > >> > > > > Sorry I wasn't clear: I test aarch64-elf with -mabi=ilp32, using newlib. > > In the short term, can you please try this testsuite patch? > I confirm this patch makes the test pass. > > r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson ` (5 preceding siblings ...) 2019-11-14 10:12 ` [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson @ 2019-11-14 13:13 ` Kyrill Tkachov 2019-11-14 13:57 ` Richard Henderson 6 siblings, 1 reply; 26+ messages in thread From: Kyrill Tkachov @ 2019-11-14 13:13 UTC (permalink / raw) To: Richard Henderson, gcc-patches; +Cc: Richard Earnshaw, Richard Sandiford Hi Richard, On 11/14/19 10:07 AM, Richard Henderson wrote: > I've put the implementation into config/arm/aarch-common.c, so > that it can be shared between the two targets. This required > a little bit of cleanup to the CC modes and constraints to get > the two targets to match up. > > Changes for v2: >  * Document overflow flags. >  * Add "hs" and "lo" as aliases of "cs" and "cc". >  * Add unsigned cmp tests to asm-flag-6.c. > > Richard Sandiford has given his ack for the aarch64 side. > I'm still looking for an ack for the arm side. > The arm parts look good to me, there's not too much arm-specific stuff that's not shared with aarch64 thankfully. Thanks, Kyrill > > r~ > > > Richard Henderson (6): >  aarch64: Add "c" constraint >  arm: Fix the "c" constraint >  arm: Rename CC_NOOVmode to CC_NZmode >  arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ >  arm: Add testsuite checks for asm-flag >  aarch64: Add testsuite checks for asm-flag > >  gcc/config/arm/aarch-common-protos.h         |  6 + >  gcc/config/aarch64/aarch64-c.c               |  2 + >  gcc/config/aarch64/aarch64.c                 |  3 + >  gcc/config/arm/aarch-common.c                | 136 +++++++++++++ >  gcc/config/arm/arm-c.c                       |  1 + >  gcc/config/arm/arm.c                         | 15 +- >  gcc/testsuite/gcc.target/aarch64/asm-flag-1.c | 35 ++++ >  gcc/testsuite/gcc.target/aarch64/asm-flag-3.c | 38 ++++ >  gcc/testsuite/gcc.target/aarch64/asm-flag-5.c | 30 +++ >  gcc/testsuite/gcc.target/aarch64/asm-flag-6.c | 62 ++++++ >  gcc/testsuite/gcc.target/arm/asm-flag-1.c    | 36 ++++ >  gcc/testsuite/gcc.target/arm/asm-flag-3.c    | 38 ++++ >  gcc/testsuite/gcc.target/arm/asm-flag-5.c    | 30 +++ >  gcc/testsuite/gcc.target/arm/asm-flag-6.c    | 62 ++++++ >  gcc/config/aarch64/constraints.md            |  4 + >  gcc/config/arm/arm-modes.def                 |  4 +- >  gcc/config/arm/arm.md                        | 186 +++++++++--------- >  gcc/config/arm/constraints.md                |  5 +- >  gcc/config/arm/predicates.md                 |  2 +- >  gcc/config/arm/thumb1.md                     |  8 +- >  gcc/config/arm/thumb2.md                     | 34 ++-- >  gcc/doc/extend.texi                          | 39 ++++ >  22 files changed, 651 insertions(+), 125 deletions(-) >  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-1.c >  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-3.c >  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-5.c >  create mode 100644 gcc/testsuite/gcc.target/aarch64/asm-flag-6.c >  create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-1.c >  create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-3.c >  create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-5.c >  create mode 100644 gcc/testsuite/gcc.target/arm/asm-flag-6.c > > -- > 2.17.1 > ^ permalink raw reply [flat|nested] 26+ messages in thread
* Re: [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 2019-11-14 13:13 ` [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Kyrill Tkachov @ 2019-11-14 13:57 ` Richard Henderson 0 siblings, 0 replies; 26+ messages in thread From: Richard Henderson @ 2019-11-14 13:57 UTC (permalink / raw) To: Kyrill Tkachov, Richard Henderson, gcc-patches Cc: Richard Earnshaw, Richard Sandiford On 11/14/19 2:08 PM, Kyrill Tkachov wrote: > Hi Richard, > > On 11/14/19 10:07 AM, Richard Henderson wrote: >> I've put the implementation into config/arm/aarch-common.c, so >> that it can be shared between the two targets. This required >> a little bit of cleanup to the CC modes and constraints to get >> the two targets to match up. >> >> Changes for v2: >>  * Document overflow flags. >>  * Add "hs" and "lo" as aliases of "cs" and "cc". >>  * Add unsigned cmp tests to asm-flag-6.c. >> >> Richard Sandiford has given his ack for the aarch64 side. >> I'm still looking for an ack for the arm side. >> > The arm parts look good to me, there's not too much arm-specific stuff that's > not shared with aarch64 thankfully. Yes indeed. Committed series ending in r278228. Thanks, r~ ^ permalink raw reply [flat|nested] 26+ messages in thread
end of thread, other threads:[~2019-11-19 10:05 UTC | newest] Thread overview: 26+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-11-14 10:07 [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Richard Henderson 2019-11-14 10:07 ` [PATCH v2 1/6] aarch64: Add "c" constraint Richard Henderson 2019-11-14 10:07 ` [PATCH v2 3/6] arm: Rename CC_NOOVmode to CC_NZmode Richard Henderson 2019-11-14 14:42 ` Richard Earnshaw (lists) 2019-11-14 10:07 ` [PATCH v2 2/6] arm: Fix the "c" constraint Richard Henderson 2019-11-14 13:08 ` Kyrill Tkachov 2019-11-14 13:36 ` Richard Henderson 2019-11-14 10:07 ` [PATCH v2 5/6] arm: Add testsuite checks for asm-flag Richard Henderson 2019-11-14 14:48 ` Richard Earnshaw (lists) 2019-11-18 12:28 ` Christophe Lyon 2019-11-18 13:32 ` Richard Henderson 2019-11-14 10:07 ` [PATCH v2 4/6] arm, aarch64: Add support for __GCC_ASM_FLAG_OUTPUTS__ Richard Henderson 2019-11-14 14:40 ` Richard Earnshaw (lists) 2019-11-14 15:09 ` Richard Henderson 2019-11-14 15:22 ` Richard Earnshaw (lists) 2019-11-14 14:53 ` Richard Earnshaw (lists) 2019-11-14 15:14 ` Richard Henderson 2019-11-14 10:12 ` [PATCH v2 6/6] aarch64: Add testsuite checks for asm-flag Richard Henderson 2019-11-18 12:35 ` Christophe Lyon 2019-11-18 20:06 ` Richard Henderson 2019-11-18 21:35 ` Andreas Schwab 2019-11-19 8:38 ` Christophe Lyon 2019-11-19 9:26 ` Richard Henderson 2019-11-19 10:12 ` Christophe Lyon 2019-11-14 13:13 ` [PATCH v2 0/6] Implement asm flag outputs for arm + aarch64 Kyrill Tkachov 2019-11-14 13:57 ` Richard Henderson
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