From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 67074 invoked by alias); 21 Dec 2019 00:11:05 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 67061 invoked by uid 89); 21 Dec 2019 00:11:05 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.1 required=5.0 tests=AWL,BAYES_00,GIT_PATCH_2,GIT_PATCH_3,KAM_SHORT,RCVD_IN_DNSWL_LOW,SPF_PASS autolearn=ham version=3.3.1 spammy=prefixdsdqc, UD:prefix-ds-dq.c, prefix-ds-dq.c, HX-Languages-Length:4920 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Sat, 21 Dec 2019 00:11:03 +0000 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBKNuLxT168174; Fri, 20 Dec 2019 19:11:02 -0500 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 2x0wb21nbp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Dec 2019 19:11:01 -0500 Received: from m0187473.ppops.net (m0187473.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id xBKNug6I168944; Fri, 20 Dec 2019 19:11:01 -0500 Received: from ppma03wdc.us.ibm.com (ba.79.3fa9.ip4.static.sl-reverse.com [169.63.121.186]) by mx0a-001b2d01.pphosted.com with ESMTP id 2x0wb21nb1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 20 Dec 2019 19:11:01 -0500 Received: from pps.filterd (ppma03wdc.us.ibm.com [127.0.0.1]) by ppma03wdc.us.ibm.com (8.16.0.27/8.16.0.27) with SMTP id xBL059n0030855; Sat, 21 Dec 2019 00:11:00 GMT Received: from b03cxnp08025.gho.boulder.ibm.com (b03cxnp08025.gho.boulder.ibm.com [9.17.130.17]) by ppma03wdc.us.ibm.com with ESMTP id 2wvqc7bp0n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 21 Dec 2019 00:10:59 +0000 Received: from b03ledav005.gho.boulder.ibm.com (b03ledav005.gho.boulder.ibm.com [9.17.130.236]) by b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBL0AwH511927938 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sat, 21 Dec 2019 00:10:58 GMT Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B5670BE05B; Sat, 21 Dec 2019 00:10:58 +0000 (GMT) Received: from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5B567BE053; Sat, 21 Dec 2019 00:10:58 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.32.77.177]) by b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTPS; Sat, 21 Dec 2019 00:10:58 +0000 (GMT) Date: Sat, 21 Dec 2019 00:12:00 -0000 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn Subject: [PATCH] V11 patch #9 of 15, Add test to validate generating prefixed memory when the offset is invalid for DS/DQ insns Message-ID: <20191221001056.GI28993@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, Segher Boessenkool , David Edelsohn References: <20191220231507.GA18386@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20191220231507.GA18386@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) X-SW-Source: 2019-12/txt/msg01498.txt.bz2 This is V10 patch #11. This adds a new test to validate that for -mcpu=future, we generate a prefixed load/store if the offset would have been illegal for a non-prefixed DS or DQ instruction. https://gcc.gnu.org/ml/gcc-patches/2019-12/msg00845.html This test passes when I run the testsuite. Can I check it in? 2019-12-20 Michael Meissner * gcc.target/powerpc/prefix-ds-dq.c: New test to verify that we generate the prefix load/store instructions for traditional instructions with an offset that doesn't match DS/DQ requirements. Index: gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c =================================================================== --- gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c (revision 279256) +++ gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c (working copy) @@ -0,0 +1,156 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_prefixed_addr } */ +/* { dg-options "-O2 -mdejagnu-cpu=future" } */ + +/* Tests whether we generate a prefixed load/store operation for addresses that + don't meet DS/DQ offset constraints. */ + +unsigned long +load_uc_offset1 (unsigned char *p) +{ + return p[1]; /* should generate LBZ. */ +} + +long +load_sc_offset1 (signed char *p) +{ + return p[1]; /* should generate LBZ + EXTSB. */ +} + +unsigned long +load_us_offset1 (unsigned char *p) +{ + return *(unsigned short *)(p + 1); /* should generate LHZ. */ +} + +long +load_ss_offset1 (unsigned char *p) +{ + return *(short *)(p + 1); /* should generate LHA. */ +} + +unsigned long +load_ui_offset1 (unsigned char *p) +{ + return *(unsigned int *)(p + 1); /* should generate LWZ. */ +} + +long +load_si_offset1 (unsigned char *p) +{ + return *(int *)(p + 1); /* should generate PLWA. */ +} + +unsigned long +load_ul_offset1 (unsigned char *p) +{ + return *(unsigned long *)(p + 1); /* should generate PLD. */ +} + +long +load_sl_offset1 (unsigned char *p) +{ + return *(long *)(p + 1); /* should generate PLD. */ +} + +float +load_float_offset1 (unsigned char *p) +{ + return *(float *)(p + 1); /* should generate LFS. */ +} + +double +load_double_offset1 (unsigned char *p) +{ + return *(double *)(p + 1); /* should generate LFD. */ +} + +__float128 +load_float128_offset1 (unsigned char *p) +{ + return *(__float128 *)(p + 1); /* should generate PLXV. */ +} + +void +store_uc_offset1 (unsigned char uc, unsigned char *p) +{ + p[1] = uc; /* should generate STB. */ +} + +void +store_sc_offset1 (signed char sc, signed char *p) +{ + p[1] = sc; /* should generate STB. */ +} + +void +store_us_offset1 (unsigned short us, unsigned char *p) +{ + *(unsigned short *)(p + 1) = us; /* should generate STH. */ +} + +void +store_ss_offset1 (signed short ss, unsigned char *p) +{ + *(signed short *)(p + 1) = ss; /* should generate STH. */ +} + +void +store_ui_offset1 (unsigned int ui, unsigned char *p) +{ + *(unsigned int *)(p + 1) = ui; /* should generate STW. */ +} + +void +store_si_offset1 (signed int si, unsigned char *p) +{ + *(signed int *)(p + 1) = si; /* should generate STW. */ +} + +void +store_ul_offset1 (unsigned long ul, unsigned char *p) +{ + *(unsigned long *)(p + 1) = ul; /* should generate PSTD. */ +} + +void +store_sl_offset1 (signed long sl, unsigned char *p) +{ + *(signed long *)(p + 1) = sl; /* should generate PSTD. */ +} + +void +store_float_offset1 (float f, unsigned char *p) +{ + *(float *)(p + 1) = f; /* should generate STF. */ +} + +void +store_double_offset1 (double d, unsigned char *p) +{ + *(double *)(p + 1) = d; /* should generate STD. */ +} + +void +store_float128_offset1 (__float128 f128, unsigned char *p) +{ + *(__float128 *)(p + 1) = f128; /* should generate PSTXV. */ +} + +/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlbz\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mlfd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlfs\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlha\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlhz\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mlwz\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mpld\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mplwa\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mplxv\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mpstxv\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstb\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstfd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mstfs\M} 1 } } */ +/* { dg-final { scan-assembler-times {\msth\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mstw\M} 2 } } */ -- Michael Meissner, IBM IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA email: meissner@linux.ibm.com, phone: +1 (978) 899-4797