PowerPC -mcpu=future Version 12 patches

PowerPC -mcpu=future Version 12 patches

[Michael Meissner]

This is version 12 of my patches for PowerPC -mcpu=future.  There are currently
14 patches.  Note, the PCREL_OPT patches are not part of this series.  I want
to concentrate on getting the other patches checked in.

Patches #1-4 reflect changes that were asked for in the previous (V11) set of
patches for patches V11 #2-#5.

Patch #5 is the same patch as V11 patch #6 that switches the default for
-mpcrel when the user uses -mcpu=future.

Patch #6 is the same patch as V11 patch #7 that adds new options for the
target-supports testcases.

The remaining patches (#7-14) are the same tests that were in V11 as patches
#8-15.

I have built these patches on a little endian power8 system and there were no
regressions in the test suite.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #1 of 14, add gcc_asserts for rs6000_adjust_vec_address

[Michael Meissner]

In https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01530.html, Segher asked me to
do the gcc_asserts as early as possible.

This patch makes sure the base register temporary is not used in the other
arguments.

I have built and bootstrapped a compiler on a little endian power8 system, and
there were no regressions in the test.  In addition, I compiled both Spec 2006
and Spec 2017 benchmarks with this compiler and I saw new build failures.  Can
I check this into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
	gcc_asserts.

--- /tmp/kXfaUP_rs6000.c	2020-01-08 13:59:48.664454496 -0500
+++ gcc/config/rs6000/rs6000.c	2020-01-08 13:59:45.593410764 -0500
@@ -6772,6 +6772,9 @@ rs6000_adjust_vec_address (rtx scalar_re
   rtx new_addr;
   bool valid_addr_p;
 
+  gcc_assert (!reg_mentioned_p (base_tmp, addr));
+  gcc_assert (!reg_mentioned_p (base_tmp, element));
+
   /* Vector addresses should not have PRE_INC, PRE_DEC, or PRE_MODIFY.  */
   gcc_assert (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC);
 
@@ -6781,6 +6784,10 @@ rs6000_adjust_vec_address (rtx scalar_re
     element_offset = GEN_INT (INTVAL (element) * scalar_size);
   else
     {
+      /* All insns should use the 'Q' constraint (address is a single register)
+	 if the element number is not a constant.  */
+      gcc_assert (REG_P (addr) || SUBREG_P (addr));
+
       int byte_shift = exact_log2 (scalar_size);
       gcc_assert (byte_shift >= 0);
 

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #2 of 14, Refactor rs6000_adjust_vec_address & rs6000_split_vec_extract_var

[Michael Meissner]

In https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01530.html, Seghar had some
questions about that patch.

This patch addresses some of those concerns.

Instead of limiting the vector element number in rs6000_split_vec_extract_var
so that the memory access does not go out of bounds, I decided to move the
logic to rs6000_adjust_vec_address.  Rs6000_split_vec_extract_var is the only
caller of rs6000_adjust_vec_address that passes in a variable element number.

The function rs6000_adjust_vec_address has 3 parts:
  1) Calculation of the byte offset within the vector;
  2) Creation of the new vector address;
  3) Validating that the new address is valid for the register being loaded.

In this patch, I moved the code that calculates the byte offset to a separate
function, and moved in the AND that was originally done in
rs6000_split_vec_extract_var.

I have built and bootstrapped a compiler with this patch installed on a little
endian power8 system and there were no regressions in the test suite.  In
addition, I built -mcpu=future versions of Spec 2006 and Spec 2017, and there
were no additional failures.  Can I check this patch into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (get_vector_offset): New helper function
	to calculate the offset in memory from the start of a vector of a
	particular element.  Add code to keep the element number in
	bounces if the element number is variable.
	(rs6000_adjust_vec_address): Move calculation of offset of the
	vector element to get_vector_offset.
	(rs6000_split_vec_extract_var): Do not do the initial AND of
	element here, move the code to get_vector_offset.

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 280071)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -6753,6 +6753,43 @@ hard_reg_and_mode_to_addr_mask (rtx reg,
   return addr_mask;
 }
 
+/* Return the offset within a memory object (MEM) of a vector type to a given
+   element within the vector (ELEMENT) with an element size (SCALAR_SIZE).  If
+   the element is constant, we return a constant integer.  Otherwise, we use a
+   base register temporary to calculate the offset after making it to fit
+   within the vector and scaling it.  */
+
+static rtx
+get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
+{
+  if (CONST_INT_P (element))
+    return GEN_INT (INTVAL (element) * scalar_size);
+
+  /* All insns should use the 'Q' constraint (address is a single register) if
+     the element number is not a constant.  */
+  rtx addr = XEXP (mem, 0);
+  gcc_assert (REG_P (addr) || SUBREG_P (addr));
+
+  /* Mask the element to make sure the element number is between 0 and the
+     maximum number of elements - 1 so that we don't generate an address
+     outside the vector.  */
+  rtx num_ele_m1 = GEN_INT (GET_MODE_NUNITS (GET_MODE (mem)) - 1);
+  rtx and_op = gen_rtx_AND (Pmode, element, num_ele_m1);
+  emit_insn (gen_rtx_SET (base_tmp, and_op));
+
+  /* Shift the element to get the byte offset from the element number.  */
+  int shift = exact_log2 (scalar_size);
+  gcc_assert (shift >= 0);
+
+  if (shift > 0)
+    {
+      rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
+      emit_insn (gen_rtx_SET (base_tmp, shift_op));
+    }
+
+  return base_tmp;
+}
+
 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
    within the vector (ELEMENT) with a mode (SCALAR_MODE).  Use a base register
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
@@ -6767,7 +6804,6 @@ rs6000_adjust_vec_address (rtx scalar_re
 {
   unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
   rtx addr = XEXP (mem, 0);
-  rtx element_offset;
   rtx new_addr;
   bool valid_addr_p;
 
@@ -6779,30 +6815,7 @@ rs6000_adjust_vec_address (rtx scalar_re
 
   /* Calculate what we need to add to the address to get the element
      address.  */
-  if (CONST_INT_P (element))
-    element_offset = GEN_INT (INTVAL (element) * scalar_size);
-  else
-    {
-      /* All insns should use the 'Q' constraint (address is a single register)
-	 if the element number is not a constant.  */
-      gcc_assert (REG_P (addr) || SUBREG_P (addr));
-
-      int byte_shift = exact_log2 (scalar_size);
-      gcc_assert (byte_shift >= 0);
-
-      if (byte_shift == 0)
-	element_offset = element;
-
-      else
-	{
-	  if (TARGET_POWERPC64)
-	    emit_insn (gen_ashldi3 (base_tmp, element, GEN_INT (byte_shift)));
-	  else
-	    emit_insn (gen_ashlsi3 (base_tmp, element, GEN_INT (byte_shift)));
-
-	  element_offset = base_tmp;
-	}
-    }
+  rtx element_offset = get_vector_offset (mem, element, base_tmp, scalar_size);
 
   /* Create the new address pointing to the element within the vector.  If we
      are adding 0, we don't have to change the address.  */
@@ -6938,13 +6951,9 @@ rs6000_split_vec_extract_var (rtx dest,
      systems.  */
   if (MEM_P (src))
     {
-      int num_elements = GET_MODE_NUNITS (mode);
-      rtx num_ele_m1 = GEN_INT (num_elements - 1);
-
-      emit_insn (gen_anddi3 (element, element, num_ele_m1));
-      gcc_assert (REG_P (tmp_gpr));
-      emit_move_insn (dest, rs6000_adjust_vec_address (dest, src, element,
-						       tmp_gpr, scalar_mode));
+      emit_move_insn (dest,
+		      rs6000_adjust_vec_address (dest, src, element, tmp_gpr,
+						 scalar_mode));
       return;
     }
 
-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #3 of 14, Improve address validation in rs6000_adjust_vec_address

[Michael Meissner]

In the patches:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01530.html
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01533.html

Segher said the whole code was too complex.  This patch is my attempt to make
it somewhat easier to understand.

One part that is an issue was there was a section of code to tried to prevent
doing an ADDI if the register was GPR 0 (where the machine uses '0' instead of
the value in GPR 0).  I realized that if I changed the order of the adds, I
wouldn't have to worry about adding GPR 0.

For example consider:

	#include <altivec.h>

	double
	indexed_get1 (vector double *vp, unsigned long m)
	{
	  return vec_extract (vp[m], 1);
	}

Right now it generates:

        sldi 4,4,4
        addi 9,3,8
        lfdx 1,4,9

I.e. add the offset to the base register and then form a X-FORM load with the
base and index registers.

With this patch, it now generates:

        sldi 4,4,4
        add 9,4,3
        lfd 1,8(9)

I.e. add the base and index registers to the temporary, and a D-FORM load
(assuming the element number is constant) instead of a X-FORM load with the
offset as the index.

The second part of cleaning up the code was to eliminate the special purpose
code that checks the addr_masks for the register type along with the code that
assumed all 8-byte values needed a DS-FORM instruction.

Instead I now call address_to_insn_form, which is the general address
classification function added recently.  That function peers into the
addr_masks, etc. but it means this function at a higher abstraction layer
doens't have to worry about the details.

This patch does eliminate the hard_reg_and_mode_to_addr_mask function that I
added recently in anticipation of using to optimize PC-relative addresses as
well.  When I started looking at it, I figured it simplified things if I could
push all of the details to address_to_insn_form (which already knew about these
things).

As with the other patches, I have built and boostrapped a compiler on a little
endian power8 system, and there were no regressions in the tests.  Can I check
this patch into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
	reference.
	(hard_reg_and_mode_to_addr_mask): Delete, no longer used.
	(rs6000_adjust_vec_address): If the original vector address
	was REG+REG or REG+OFFSET and the element is not zero, do the add
	of the elements in the original address before adding the offset
	for the vector element.  Use address_to_insn_form to validate the
	address using the register being loaded, rather than guessing
	whether the address is a DS-FORM or DQ-FORM address.

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 280072)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -1172,6 +1172,7 @@ static bool rs6000_secondary_reload_move
 					  machine_mode,
 					  secondary_reload_info *,
 					  bool);
+static enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
 
 /* Hash table stuff for keeping track of TOC entries.  */
@@ -6729,30 +6730,6 @@ rs6000_expand_vector_extract (rtx target
     }
 }
 
-/* Helper function to return an address mask based on a physical register.  */
-
-static addr_mask_type
-hard_reg_and_mode_to_addr_mask (rtx reg, machine_mode mode)
-{
-  unsigned int r = reg_or_subregno (reg);
-  addr_mask_type addr_mask;
-
-  gcc_assert (HARD_REGISTER_NUM_P (r));
-  if (INT_REGNO_P (r))
-    addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_GPR];
-
-  else if (FP_REGNO_P (r))
-    addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_FPR];
-
-  else if (ALTIVEC_REGNO_P (r))
-    addr_mask = reg_addr[mode].addr_mask[RELOAD_REG_VMX];
-
-  else
-    gcc_unreachable ();
-
-  return addr_mask;
-}
-
 /* Return the offset within a memory object (MEM) of a vector type to a given
    element within the vector (ELEMENT) with an element size (SCALAR_SIZE).  If
    the element is constant, we return a constant integer.  Otherwise, we use a
@@ -6805,7 +6782,6 @@ rs6000_adjust_vec_address (rtx scalar_re
   unsigned scalar_size = GET_MODE_SIZE (scalar_mode);
   rtx addr = XEXP (mem, 0);
   rtx new_addr;
-  bool valid_addr_p;
 
   gcc_assert (!reg_mentioned_p (base_tmp, addr));
   gcc_assert (!reg_mentioned_p (base_tmp, element));
@@ -6833,68 +6809,30 @@ rs6000_adjust_vec_address (rtx scalar_re
     {
       rtx op0 = XEXP (addr, 0);
       rtx op1 = XEXP (addr, 1);
-      rtx insn;
 
       gcc_assert (REG_P (op0) || SUBREG_P (op0));
       if (CONST_INT_P (op1) && CONST_INT_P (element_offset))
 	{
+	  /* D-FORM address with constant element number.  */
 	  HOST_WIDE_INT offset = INTVAL (op1) + INTVAL (element_offset);
 	  rtx offset_rtx = GEN_INT (offset);
-
-	  /* 16-bit offset.  */
-	  if (SIGNED_INTEGER_16BIT_P (offset)
-	      && (scalar_size < 8 || (offset & 0x3) == 0))
-	    new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
-
-	  /* 34-bit offset if we have prefixed addresses.  */
-	  else if (TARGET_PREFIXED_ADDR && SIGNED_INTEGER_34BIT_P (offset))
-	    new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
-
-	  else
-	    {
-	      /* Offset overflowed, move offset to the temporary (which will
-		 likely be split), and do X-FORM addressing.  */
-	      emit_move_insn (base_tmp, offset_rtx);
-	      new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
-	    }
+	  new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
 	}
       else
 	{
-	  bool op1_reg_p = (REG_P (op1) || SUBREG_P (op1));
-	  bool ele_reg_p = (REG_P (element_offset) || SUBREG_P (element_offset));
+	  /* If we don't have a D-FORM address with a constant element number,
+	     add the two elements in the current address.  Then add the offset.
 
-	  /* Note, ADDI requires the register being added to be a base
-	     register.  If the register was R0, load it up into the temporary
-	     and do the add.  */
-	  if (op1_reg_p
-	      && (ele_reg_p || reg_or_subregno (op1) != FIRST_GPR_REGNO))
-	    {
-	      insn = gen_add3_insn (base_tmp, op1, element_offset);
-	      gcc_assert (insn != NULL_RTX);
-	      emit_insn (insn);
-	    }
-
-	  else if (ele_reg_p
-		   && reg_or_subregno (element_offset) != FIRST_GPR_REGNO)
-	    {
-	      insn = gen_add3_insn (base_tmp, element_offset, op1);
-	      gcc_assert (insn != NULL_RTX);
-	      emit_insn (insn);
-	    }
-
-	  /* Make sure we don't overwrite the temporary if the element being
-	     extracted is variable, and we've put the offset into base_tmp
-	     previously.  */
-	  else if (reg_mentioned_p (base_tmp, element_offset))
-	    emit_insn (gen_add2_insn (base_tmp, op1));
-
-	  else
-	    {
-	      emit_move_insn (base_tmp, op1);
-	      emit_insn (gen_add2_insn (base_tmp, element_offset));
-	    }
-
-	  new_addr = gen_rtx_PLUS (Pmode, op0, base_tmp);
+	     Previously, we tried to add the offset to OP1 and change the
+	     address to an X-FORM format adding OP0 and BASE_TMP, but it became
+	     complicated because we had to verify that op1 was not GPR0 and we
+	     had a constant element offset (due to the way ADDI is defined).
+	     By doing the add of OP0 and OP1 first, and then adding in the
+	     offset, it has the benefit that if D-FORM instructions are
+	     allowed, the offset is part of the memory access to the vector
+	     element. */
+	  emit_insn (gen_rtx_SET (base_tmp, gen_rtx_PLUS (Pmode, op0, op1)));
+	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
 	}
     }
 
@@ -6904,27 +6842,19 @@ rs6000_adjust_vec_address (rtx scalar_re
       new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
     }
 
-  /* If we have a PLUS, we need to see whether the particular register class
-     allows for D-FORM or X-FORM addressing.  */
-  if (GET_CODE (new_addr) == PLUS)
-    {
-      rtx op1 = XEXP (new_addr, 1);
-      addr_mask_type addr_mask
-	= hard_reg_and_mode_to_addr_mask (scalar_reg, scalar_mode);
-
-      if (REG_P (op1) || SUBREG_P (op1))
-	valid_addr_p = (addr_mask & RELOAD_REG_INDEXED) != 0;
-      else
-	valid_addr_p = (addr_mask & RELOAD_REG_OFFSET) != 0;
-    }
-
-  else if (REG_P (new_addr) || SUBREG_P (new_addr))
-    valid_addr_p = true;
+    /* If the address isn't valid, move the address into the temporary base
+       register.  Some reasons it could not be valid include:
 
-  else
-    valid_addr_p = false;
+       The address offset overflowed the 16 or 34 bit offset size;
+       We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
+       We need to use a DQ-FORM load, and the bottom 2 bits are non-zero;
+       Only X_FORM loads can be done, and the address is D_FORM.  */
+
+  enum insn_form iform
+    = address_to_insn_form (new_addr, scalar_mode,
+			    reg_to_non_prefixed (scalar_reg, scalar_mode));
 
-  if (!valid_addr_p)
+  if (iform == INSN_FORM_BAD)
     {
       emit_move_insn (base_tmp, new_addr);
       new_addr = base_tmp;

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #4 of 14, Optimize adjusting PC-relative vector addresses

[Michael Meissner]

This patch folds a PC-relative vector address that is adjusted with a constant
offset, to fold the constant into the PC-relative address.  I moved this code
to be a separate function to make it clearer what the steps were.  With patch
V12 #3, address_to_insn_form is now used to validate the address, so we don't
need any new special address validation.

I have build and bootstrapped a compiler on a little endian power8 system, and
there were no regressions in the test suite.  Can I check this in to the trunk.
Patch V12 #13 will contain new tests for this optimization.

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/rs6000.c (adjust_vec_address_pcrel): New helper
	function to adjust PC-relative vector addresses.
	(rs6000_adjust_vec_address): Call adjust_vec_address_pcrel to
	handle vectors with PC-relative addresses.

Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 280073)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -6767,6 +6767,60 @@ get_vector_offset (rtx mem, rtx element,
   return base_tmp;
 }
 
+/* Helper function update PC-relative addresses when we are adjusting a memory
+   address (ADDR) to a vector to point to a scalar field within the vector with
+   a constant offset (ELEMENT_OFFSET).  If the address is not valid, we can
+   use the base register temporary (BASE_TMP) to form the address.  */
+
+static rtx
+adjust_vec_address_pcrel (rtx addr, rtx element_offset, rtx base_tmp)
+{
+  rtx new_addr = NULL;
+
+  gcc_assert (CONST_INT_P (element_offset));
+
+  if (GET_CODE (addr) == CONST)
+    addr = XEXP (addr, 0);
+
+  if (GET_CODE (addr) == PLUS)
+    {
+      rtx op0 = XEXP (addr, 0);
+      rtx op1 = XEXP (addr, 1);
+
+      if (CONST_INT_P (op1))
+	{
+	  HOST_WIDE_INT offset
+	    = INTVAL (XEXP (addr, 1)) + INTVAL (element_offset);
+
+	  if (offset == 0)
+	    new_addr = op0;
+
+	  else
+	    {
+	      rtx plus = gen_rtx_PLUS (Pmode, op0, GEN_INT (offset));
+	      new_addr = gen_rtx_CONST (Pmode, plus);
+	    }
+	}
+
+      else
+	{
+	  emit_move_insn (base_tmp, addr);
+	  new_addr = gen_rtx_PLUS (Pmode, base_tmp, element_offset);
+	}
+    }
+
+  else if (SYMBOL_REF_P (addr) || LABEL_REF_P (addr))
+    {
+      rtx plus = gen_rtx_PLUS (Pmode, addr, element_offset);
+      new_addr = gen_rtx_CONST (Pmode, plus);
+    }
+
+  else
+    gcc_unreachable ();
+
+  return new_addr;
+}
+
 /* Adjust a memory address (MEM) of a vector type to point to a scalar field
    within the vector (ELEMENT) with a mode (SCALAR_MODE).  Use a base register
    temporary (BASE_TMP) to fixup the address.  Return the new memory address
@@ -6803,6 +6857,11 @@ rs6000_adjust_vec_address (rtx scalar_re
   else if (REG_P (addr) || SUBREG_P (addr))
     new_addr = gen_rtx_PLUS (Pmode, addr, element_offset);
 
+  /* For references to local static variables, fold a constant offset into the
+     address.  */
+  else if (pcrel_local_address (addr, Pmode) && CONST_INT_P (element_offset))
+    new_addr = adjust_vec_address_pcrel (addr, element_offset, base_tmp);
+
   /* Optimize D-FORM addresses with constant offset with a constant element, to
      include the element offset in the address directly.  */
   else if (GET_CODE (addr) == PLUS)


-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #5 of 14, Make -mpcrel default for -mcpu=future on little endian Linux 64-bit systems

[Michael Meissner]

This patch is the same as patch V11 #6:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01494.html

Assuming patches 1-4 are applied, it fixes all of the known codegen bugs with
the -mcpu=future support, and so it is time to make -mpcrel default on the one
system that will support PC-relative addressing on the future system.

I have built and bootstrapped a compiler with this patch on a little endian
power8 system, and there were no regressions in the testsuite.  I have built
Spec 2006 and Spec 2017 benchmarks with this patch, and there were no
regressions in building the benchmarks.  Can I check this patch into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* config/rs6000/linux64.h (PREFIXED_ADDR_SUPPORTED_BY_OS): Set to
	1 to enable prefixed addressing if -mcpu=future.
	(PCREL_SUPPORTED_BY_OS): Set to 1 to enable PC-relative addressing
	if -mcpu=future.
	* config/rs6000/rs6000-cpus.h (ISA_FUTURE_MASKS_SERVER): Do not
	enable -mprefixed-addr or -mpcrel by default.
	(ADDRESSING_FUTURE_MASKS): New macro.
	(OTHER_FUTURE_MASKS): Use ADDRESSING_FUTURE_MASKS.
	* config/rs6000/rs6000.c (PREFIXED_ADDR_SUPPORTED_BY_OS): Disable
	prefixed addressing unless the target OS tm.h says we should
	enable it.
	(PCREL_SUPPORTED_BY_OS): Disable PC-relative addressing unless the
	target OS tm.h says we should enable it.
	(rs6000_debug_reg_global): Print whether prefixed addressing and
	PC-relative addressing is enabled by default if -mcpu=future.
	(rs6000_option_override_internal): Move setting prefixed
	addressing and PC-relative addressing after the sub-target option
	handling is done.  Only enable prefixed addressing or PC-relative
	address on -mcpu=future system if the target OS says to enable
	it.  Disallow prefixed addressing on 32-bit systems or if the
	target object file is not ELF v2.

Index: gcc/config/rs6000/linux64.h
===================================================================
--- gcc/config/rs6000/linux64.h	(revision 280069)
+++ gcc/config/rs6000/linux64.h	(working copy)
@@ -640,3 +640,11 @@ extern int dot_symbols;
    enabling the __float128 keyword.  */
 #undef	TARGET_FLOAT128_ENABLE_TYPE
 #define TARGET_FLOAT128_ENABLE_TYPE 1
+
+/* Enable support for pc-relative and numeric prefixed addressing on the
+   'future' system.  */
+#undef  PREFIXED_ADDR_SUPPORTED_BY_OS
+#define PREFIXED_ADDR_SUPPORTED_BY_OS	1
+
+#undef  PCREL_SUPPORTED_BY_OS
+#define PCREL_SUPPORTED_BY_OS		1
Index: gcc/config/rs6000/rs6000-cpus.def
===================================================================
--- gcc/config/rs6000/rs6000-cpus.def	(revision 280069)
+++ gcc/config/rs6000/rs6000-cpus.def	(working copy)
@@ -75,15 +75,22 @@
 				 | OPTION_MASK_P8_VECTOR		\
 				 | OPTION_MASK_P9_VECTOR)
 
-/* Support for a future processor's features.  Do not enable -mpcrel until it
-   is fully functional.  */
+/* Support for a future processor's features.  The prefixed and pc-relative
+   addressing bits are not added here.  Instead, they are added if the target
+   OS tm.h says that it supports the addressing modes by default when
+   -mcpu=future is used.  */
 #define ISA_FUTURE_MASKS_SERVER	(ISA_3_0_MASKS_SERVER			\
-				 | OPTION_MASK_FUTURE			\
+				 | OPTION_MASK_FUTURE)
+
+/* Addressing related flags on a future processor.  These are options that need
+   to be cleared if the target OS is not capable of supporting prefixed
+   addressing at all (such as 32-bit mode or if the object file format is not
+   ELF v2).  */
+#define ADDRESSING_FUTURE_MASKS	(OPTION_MASK_PCREL			\
 				 | OPTION_MASK_PREFIXED_ADDR)
 
 /* Flags that need to be turned off if -mno-future.  */
-#define OTHER_FUTURE_MASKS	(OPTION_MASK_PCREL			\
-				 | OPTION_MASK_PREFIXED_ADDR)
+#define OTHER_FUTURE_MASKS	ADDRESSING_FUTURE_MASKS
 
 /* Flags that need to be turned off if -mno-power9-vector.  */
 #define OTHER_P9_VECTOR_MASKS	(OPTION_MASK_FLOAT128_HW		\
Index: gcc/config/rs6000/rs6000.c
===================================================================
--- gcc/config/rs6000/rs6000.c	(revision 280074)
+++ gcc/config/rs6000/rs6000.c	(working copy)
@@ -98,6 +98,16 @@
 #endif
 #endif
 
+/* Set up the defaults for whether prefixed addressing is used, and if it is
+   used, whether we want to turn on pc-relative support by default.  */
+#ifndef PREFIXED_ADDR_SUPPORTED_BY_OS
+#define PREFIXED_ADDR_SUPPORTED_BY_OS	0
+#endif
+
+#ifndef PCREL_SUPPORTED_BY_OS
+#define PCREL_SUPPORTED_BY_OS		0
+#endif
+
 /* Support targetm.vectorize.builtin_mask_for_load.  */
 GTY(()) tree altivec_builtin_mask_for_load;
 
@@ -2536,6 +2546,14 @@ rs6000_debug_reg_global (void)
   if (TARGET_DIRECT_MOVE_128)
     fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
 	     (int)VECTOR_ELEMENT_MFVSRLD_64BIT);
+
+  if (TARGET_FUTURE)
+    {
+      fprintf (stderr, DEBUG_FMT_D, "PREFIXED_ADDR_SUPPORTED_BY_OS",
+	       PREFIXED_ADDR_SUPPORTED_BY_OS);
+      fprintf (stderr, DEBUG_FMT_D, "PCREL_SUPPORTED_BY_OS",
+	       PCREL_SUPPORTED_BY_OS);
+    }
 }
 
 \f
@@ -4016,26 +4034,6 @@ rs6000_option_override_internal (bool gl
       rs6000_isa_flags &= ~OPTION_MASK_FLOAT128_HW;
     }
 
-  /* -mprefixed-addr (and hence -mpcrel) requires -mcpu=future.  */
-  if (TARGET_PREFIXED_ADDR && !TARGET_FUTURE)
-    {
-      if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
-	error ("%qs requires %qs", "-mpcrel", "-mcpu=future");
-      else if ((rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED_ADDR) != 0)
-	error ("%qs requires %qs", "-mprefixed-addr", "-mcpu=future");
-
-      rs6000_isa_flags &= ~(OPTION_MASK_PCREL | OPTION_MASK_PREFIXED_ADDR);
-    }
-
-  /* -mpcrel requires prefixed load/store addressing.  */
-  if (TARGET_PCREL && !TARGET_PREFIXED_ADDR)
-    {
-      if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
-	error ("%qs requires %qs", "-mpcrel", "-mprefixed-addr");
-
-      rs6000_isa_flags &= ~OPTION_MASK_PCREL;
-    }
-
   /* Print the options after updating the defaults.  */
   if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET)
     rs6000_print_isa_options (stderr, 0, "after defaults", rs6000_isa_flags);
@@ -4167,12 +4165,91 @@ rs6000_option_override_internal (bool gl
   SUB3TARGET_OVERRIDE_OPTIONS;
 #endif
 
-  /* -mpcrel requires -mcmodel=medium, but we can't check TARGET_CMODEL until
-      after the subtarget override options are done.  */
-  if (TARGET_PCREL && TARGET_CMODEL != CMODEL_MEDIUM)
+  /* Enable prefixed addressing and PC-relative addressing if the target OS
+     tm.h file says that it is supported and the user did not explicitly use
+     -mprefixed-addr or -mpcrel.  At the present time, only 64-bit Linux
+     enables this.
+
+     PC-relative support also requires the medium code model.
+
+     We can't check for ELFv2 or -mcmodel=medium until after the subtarget
+     macros are run.
+
+     If prefixed addressing is disabled by default, and the user does -mpcrel,
+     don't force them to also specify -mprefixed-addr.  */
+  if (TARGET_FUTURE)
+    {
+      bool explicit_prefixed = ((rs6000_isa_flags_explicit
+				 & OPTION_MASK_PREFIXED_ADDR) != 0);
+      bool explicit_pcrel = ((rs6000_isa_flags_explicit
+			      & OPTION_MASK_PCREL) != 0);
+
+      /* Prefixed addressing requires 64-bit registers.  */
+      if (!TARGET_POWERPC64)
+	{
+	  if (TARGET_PCREL && explicit_pcrel)
+	    error ("%qs requires %qs", "-mpcrel", "-m64");
+
+	  else if (TARGET_PREFIXED_ADDR && explicit_prefixed)
+	    error ("%qs requires %qs", "-mprefixed-addr", "-m64");
+
+	  rs6000_isa_flags &= ~ADDRESSING_FUTURE_MASKS;
+	}
+
+      /* Only ELFv2 currently supports prefixed/pcrel addressing.  */
+      else if (rs6000_current_abi != ABI_ELFv2)
+	{
+	  if (TARGET_PCREL && explicit_pcrel)
+	    error ("%qs requires %qs", "-mpcrel", "-mabi=elfv2");
+
+	  else if (TARGET_PREFIXED_ADDR && explicit_prefixed)
+	    error ("%qs requires %qs", "-mprefixed-addr", "-mabi=elfv2");
+
+	  rs6000_isa_flags &= ~ADDRESSING_FUTURE_MASKS;
+	}
+
+      /* Enable defaults if desired.  */
+      else
+	{
+	  if (!explicit_prefixed
+	      && (PREFIXED_ADDR_SUPPORTED_BY_OS
+		  || TARGET_PCREL
+		  || PCREL_SUPPORTED_BY_OS))
+	    rs6000_isa_flags |= OPTION_MASK_PREFIXED_ADDR;
+
+	  if (!explicit_pcrel && PCREL_SUPPORTED_BY_OS
+	      && TARGET_PREFIXED_ADDR
+	      && TARGET_CMODEL == CMODEL_MEDIUM)
+	    rs6000_isa_flags |= OPTION_MASK_PCREL;
+	}
+
+      /* PC-relative requires the medium code model.  */
+      if (TARGET_PCREL && TARGET_CMODEL != CMODEL_MEDIUM)
+	{
+	  if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
+	    error ("%qs requires %qs", "-mpcrel", "-mcmodel=medium");
+
+	  rs6000_isa_flags &= ~OPTION_MASK_PCREL;
+	}
+
+    }
+
+  /* -mprefixed-addr (and hence -mpcrel) requires -mcpu=future.  */
+  if (TARGET_PREFIXED_ADDR && !TARGET_FUTURE)
     {
       if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
-	error ("%qs requires %qs", "-mpcrel", "-mcmodel=medium");
+	error ("%qs requires %qs", "-mpcrel", "-mcpu=future");
+      else if ((rs6000_isa_flags_explicit & OPTION_MASK_PREFIXED_ADDR) != 0)
+	error ("%qs requires %qs", "-mprefixed-addr", "-mcpu=future");
+
+      rs6000_isa_flags &= ~(OPTION_MASK_PCREL | OPTION_MASK_PREFIXED_ADDR);
+    }
+
+  /* -mpcrel requires prefixed load/store addressing.  */
+  if (TARGET_PCREL && !TARGET_PREFIXED_ADDR)
+    {
+      if ((rs6000_isa_flags_explicit & OPTION_MASK_PCREL) != 0)
+	error ("%qs requires %qs", "-mpcrel", "-mprefixed-addr");
 
       rs6000_isa_flags &= ~OPTION_MASK_PCREL;
     }

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #6 of 14, Add -mcpu=future target-supports options

[Michael Meissner]

This patch is the same as V11, #7:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01495.html

This patch adds the necessary options to target-supports.exp to enable the
specific target supports for -mcpu=future.  It contains changes that you asked
for some time ago.  Can I check this into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* lib/target-supports.exp (check_effective_target_powerpc_pcrel):
	New target for PowerPC -mcpu=future support.
	(check_effective_target_powerpc_prefixed_addr): New target for
	PowerPC -mcpu=future support.

Index: gcc/testsuite/lib/target-supports.exp
===================================================================
--- gcc/testsuite/lib/target-supports.exp	(revision 280069)
+++ gcc/testsuite/lib/target-supports.exp	(working copy)
@@ -2161,6 +2161,23 @@ proc check_p9modulo_hw_available { } {
     }]
 }
 
+# Return 1 if the target generates PC-relative instructions automatically
+proc check_effective_target_powerpc_pcrel { } {
+    return [check_no_messages_and_pattern powerpc_pcrel \
+	{\mpld\M.*[@]pcrel} assembly {
+	    static long s;
+	    long *p = &s;
+	    long foo (void) { return s; }
+	} {-O2 -mcpu=future}]
+}
+
+# Return 1 if the target generates prefixed instructions automatically
+proc check_effective_target_powerpc_prefixed_addr { } {
+    return [check_no_messages_and_pattern powerpc_prefixed_addr \
+	{\mpld\M} assembly {
+	    long foo (long *p) { return p[0x12345]; }
+	} {-O2 -mcpu=future}]
+}
 
 # Return 1 if the target supports executing FUTURE instructions, 0 otherwise.
 # Cache the result.  It is assumed that if a simulator does not support the

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #7 of 14, Add PADDI/PLI tests

[Michael Meissner]

This patch adds new tests for the compiler generating PLI or PADDI with large
constants when -mcpu=future is used.  It renames the files as you requested
several patch generations ago so the -fident option doesn't give a false
positive result.  Can I check this patch into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-add.c: New test for -mcpu=future
	generating PADDI for large constant adds.
	* gcc.target/powerpc/prefix-di-constant.c: New test for
	-mcpu=future generating PLI to load up large DImode constants.
	* gcc.target/powerpc/prefix-si-constant.c: New test for
	-mcpu=future generating PLI to load up large SImode constants.

Index: gcc/testsuite/gcc.target/powerpc/prefix-add.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-add.c	(revision 280078)
+++ gcc/testsuite/gcc.target/powerpc/prefix-add.c	(working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PADDI is generated to add a large constant.  */
+unsigned long
+add (unsigned long a)
+{
+  return a + 0x12345678UL;
+}
+
+/* { dg-final { scan-assembler {\mpaddi\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c	(revision 280078)
+++ gcc/testsuite/gcc.target/powerpc/prefix-di-constant.c	(working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant.  */
+unsigned long
+large (void)
+{
+  return 0x12345678UL;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c	(revision 280078)
+++ gcc/testsuite/gcc.target/powerpc/prefix-si-constant.c	(working copy)
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test that PLI (PADDI) is generated to load a large constant for SImode.  */
+void
+large_si (unsigned int *p)
+{
+  *p = 0x12345U;
+}
+
+/* { dg-final { scan-assembler {\mpli\M} } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #8 of 14, Add test to verify prefixed instruction is generated for -mcpu=future for DS/DS illegal offsets

[Michael Meissner]

This patch is the same as:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01497.html

It adds a test to validate that the compiler will now generate a prefixed load
or store instead of loading up an offset that would be illegal for DS/DQ-FORM
instructions.  Can I check this into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-ds-dq.c: New test to verify that we
	generate the prefix load/store instructions for traditional
	instructions with an offset that doesn't match DS/DQ
	requirements.

Index: gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c	(revision 280080)
+++ gcc/testsuite/gcc.target/powerpc/prefix-ds-dq.c	(working copy)
@@ -0,0 +1,156 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests whether we generate a prefixed load/store operation for addresses that
+   don't meet DS/DQ offset constraints.  */
+
+unsigned long
+load_uc_offset1 (unsigned char *p)
+{
+  return p[1];				/* should generate LBZ.  */
+}
+
+long
+load_sc_offset1 (signed char *p)
+{
+  return p[1];				/* should generate LBZ + EXTSB.  */
+}
+
+unsigned long
+load_us_offset1 (unsigned char *p)
+{
+  return *(unsigned short *)(p + 1);	/* should generate LHZ.  */
+}
+
+long
+load_ss_offset1 (unsigned char *p)
+{
+  return *(short *)(p + 1);		/* should generate LHA.  */
+}
+
+unsigned long
+load_ui_offset1 (unsigned char *p)
+{
+  return *(unsigned int *)(p + 1);	/* should generate LWZ.  */
+}
+
+long
+load_si_offset1 (unsigned char *p)
+{
+  return *(int *)(p + 1);		/* should generate PLWA.  */
+}
+
+unsigned long
+load_ul_offset1 (unsigned char *p)
+{
+  return *(unsigned long *)(p + 1);	/* should generate PLD.  */
+}
+
+long
+load_sl_offset1 (unsigned char *p)
+{
+  return *(long *)(p + 1);		/* should generate PLD.  */
+}
+
+float
+load_float_offset1 (unsigned char *p)
+{
+  return *(float *)(p + 1);		/* should generate LFS.  */
+}
+
+double
+load_double_offset1 (unsigned char *p)
+{
+  return *(double *)(p + 1);		/* should generate LFD.  */
+}
+
+__float128
+load_float128_offset1 (unsigned char *p)
+{
+  return *(__float128 *)(p + 1);	/* should generate PLXV.  */
+}
+
+void
+store_uc_offset1 (unsigned char uc, unsigned char *p)
+{
+  p[1] = uc;				/* should generate STB.  */
+}
+
+void
+store_sc_offset1 (signed char sc, signed char *p)
+{
+  p[1] = sc;				/* should generate STB.  */
+}
+
+void
+store_us_offset1 (unsigned short us, unsigned char *p)
+{
+  *(unsigned short *)(p + 1) = us;	/* should generate STH.  */
+}
+
+void
+store_ss_offset1 (signed short ss, unsigned char *p)
+{
+  *(signed short *)(p + 1) = ss;	/* should generate STH.  */
+}
+
+void
+store_ui_offset1 (unsigned int ui, unsigned char *p)
+{
+  *(unsigned int *)(p + 1) = ui;	/* should generate STW.  */
+}
+
+void
+store_si_offset1 (signed int si, unsigned char *p)
+{
+  *(signed int *)(p + 1) = si;		/* should generate STW.  */
+}
+
+void
+store_ul_offset1 (unsigned long ul, unsigned char *p)
+{
+  *(unsigned long *)(p + 1) = ul;	/* should generate PSTD.  */
+}
+
+void
+store_sl_offset1 (signed long sl, unsigned char *p)
+{
+  *(signed long *)(p + 1) = sl;		/* should generate PSTD.  */
+}
+
+void
+store_float_offset1 (float f, unsigned char *p)
+{
+  *(float *)(p + 1) = f;		/* should generate STF.  */
+}
+
+void
+store_double_offset1 (double d, unsigned char *p)
+{
+  *(double *)(p + 1) = d;		/* should generate STD.  */
+}
+
+void
+store_float128_offset1 (__float128 f128, unsigned char *p)
+{
+  *(__float128 *)(p + 1) = f128;	/* should generate PSTXV.  */
+}
+
+/* { dg-final { scan-assembler-times {\mextsb\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlbz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mlfd\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlfs\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlha\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlhz\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mlwz\M}   1 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mplwa\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstb\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mstfd\M}  1 } } */
+/* { dg-final { scan-assembler-times {\mstfs\M}  1 } } */
+/* { dg-final { scan-assembler-times {\msth\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}   2 } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #9 of 14, Add test to validate we don't generate an illegal prefixed instruction

[Michael Meissner]

This patch is the same as:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01499.html

It adds a new test to make sure if we are using a prefixed load or store
instruction, the compiler does not try to use a load with update or store with
update version of the isntruction, since there are no prefixed version of those
instructions.  Can I check this into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-no-premodify.c: Make sure we do not
	generate the non-existent PLWZU instruction if -mcpu=future.

Index: gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	(revision 280082)
+++ gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	(working copy)
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Make sure that we don't generate a prefixed form of the load and store with
+   update instructions (i.e. instead of generating LWZU we have to generate
+   PLWZ plus a PADDI).  */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+  unsigned int field;
+  char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+  *q = (--p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+  (++p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+  (--p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mplwzu\M}    } } */
+/* { dg-final { scan-assembler-not   {\mpstwu\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddis\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddi\M}     } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #10 of 14, Add tests for generating prefixed load/store instructions with large numeric offsets

[Michael Meissner]

This patch is the same as:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01500.html

This patch adds one test per type validating that we generate the appropriate
prefixed instructions to load/store the type when the offset if large.  Can I
check this into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-large.h: New set of tests to test
	prefixed addressing on 'future' system with large numeric offsets
	for various types.
	* gcc.target/powerpc/prefix-large-dd.c: New test for prefixed
	loads/stores with large offsets for the _Decimal64 type.
	* gcc.target/powerpc/prefix-large-df.c: New test for prefixed
	loads/stores with large offsets for the double type.
	* gcc.target/powerpc/prefix-large-di.c: New test for prefixed
	loads/stores with large offsets for the long type.
	* gcc.target/powerpc/prefix-large-hi.c: New test for prefixed
	loads/stores with large offsets for the short type.
	* gcc.target/powerpc/prefix-large-kf.c: New test for prefixed
	loads/stores with large offsets for the __float128 type.
	* gcc.target/powerpc/prefix-large-qi.c: New test for prefixed
	loads/stores with large offsets for the signed char type.
	* gcc.target/powerpc/prefix-large-sd.c: New test for prefixed
	loads/stores with large offsets for the _Decimal32 type.
	* gcc.target/powerpc/prefix-large-sf.c: New test for prefixed
	loads/stores with large offsets for the float type.
	* gcc.target/powerpc/prefix-large-si.c: New test for prefixed
	loads/stores with large offsets for the int type.
	* gcc.target/powerpc/prefix-large-udi.c: New test for prefixed
	loads/stores with large offsets for the unsigned long type.
	* gcc.target/powerpc/prefix-large-uhi.c: New test for prefixed
	loads/stores with large offsets for the unsigned short type.
	* gcc.target/powerpc/prefix-large-uqi.c: New test for prefixed
	loads/stores with large offsets for the unsigned char type.
	* gcc.target/powerpc/prefix-large-usi.c: New test for prefixed
	loads/stores with large offsets for the unsigned int type.
	* gcc.target/powerpc/prefix-large-v2df.c: New test for prefixed
	loads/stores with large offsets for the vector double type.

Index: gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-dd.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for _Decimal64 objects.  */
+
+#define TYPE _Decimal64
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-df.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-df.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for double objects.  */
+
+#define TYPE double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-di.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-di.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-di.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for long objects.  */
+
+#define TYPE long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-hi.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for short objects.  */
+
+#define TYPE short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-kf.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for __float128 objects.  */
+
+#define TYPE __float128
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-qi.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for signed char objects.  */
+
+#define TYPE signed char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-sd.c	(working copy)
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for _Decimal32 objects.  */
+
+#define TYPE _Decimal32
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpaddi\M|\mpli|\mpla\M} 3 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M}              2 } } */
+/* { dg-final { scan-assembler-times {\mstfiwx\M}              2 } } */
+
+
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-sf.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for float objects.  */
+
+#define TYPE float
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-si.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-si.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-si.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for int objects.  */
+
+#define TYPE int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplw[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}     2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-udi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned long
+   objects.  */
+
+#define TYPE unsigned long
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-uhi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned short
+   objects.  */
+
+#define TYPE unsigned short
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplhz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-uqi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned char
+   objects.  */
+
+#define TYPE unsigned char
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-usi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for unsigned int
+   objects.  */
+
+#define TYPE unsigned int
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large-v2df.c	(working copy)
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether we can generate a prefixed
+   load/store instruction that has a 34-bit offset for vector objects.  */
+
+#define TYPE vector double
+
+#include "prefix-large.h"
+
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-large.h
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-large.h	(revision 280083)
+++ gcc/testsuite/gcc.target/powerpc/prefix-large.h	(working copy)
@@ -0,0 +1,59 @@
+/* Common tests for prefixed instructions testing whether we can generate a
+   34-bit offset using 1 instruction.  */
+
+typedef signed char	schar;
+typedef unsigned char	uchar;
+typedef unsigned short	ushort;
+typedef unsigned int	uint;
+typedef unsigned long	ulong;
+typedef long double	ldouble;
+typedef vector double	v2df;
+typedef vector long	v2di;
+typedef vector float	v4sf;
+typedef vector int	v4si;
+
+#ifndef TYPE
+#define TYPE ulong
+#endif
+
+#ifndef ITYPE
+#define ITYPE TYPE
+#endif
+
+#ifndef OTYPE
+#define OTYPE TYPE
+#endif
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD		1
+#define DO_VALUE	1
+#define DO_SET		1
+#endif
+
+#ifndef CONSTANT
+#define CONSTANT	0x123450UL
+#endif
+
+#if DO_ADD
+void
+add (TYPE *p, TYPE a)
+{
+  p[CONSTANT] += a;
+}
+#endif
+
+#if DO_VALUE
+OTYPE
+value (TYPE *p)
+{
+  return p[CONSTANT];
+}
+#endif
+
+#if DO_SET
+void
+set (TYPE *p, ITYPE a)
+{
+  p[CONSTANT] = a;
+}
+#endif
Index: gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	(revision 280082)
+++ gcc/testsuite/gcc.target/powerpc/prefix-no-premodify.c	(working copy)
@@ -0,0 +1,50 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Make sure that we don't generate a prefixed form of the load and store with
+   update instructions (i.e. instead of generating LWZU we have to generate
+   PLWZ plus a PADDI).  */
+
+#ifndef SIZE
+#define SIZE 50000
+#endif
+
+struct foo {
+  unsigned int field;
+  char pad[SIZE];
+};
+
+struct foo *inc_load (struct foo *p, unsigned int *q)
+{
+  *q = (++p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *dec_load (struct foo *p, unsigned int *q)
+{
+  *q = (--p)->field;	/* PLWZ, PADDI, STW.  */
+  return p;
+}
+
+struct foo *inc_store (struct foo *p, unsigned int *q)
+{
+  (++p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+struct foo *dec_store (struct foo *p, unsigned int *q)
+{
+  (--p)->field = *q;	/* LWZ, PADDI, PSTW.  */
+  return p;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mstw\M}    2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}   2 } } */
+/* { dg-final { scan-assembler-not   {\mplwzu\M}    } } */
+/* { dg-final { scan-assembler-not   {\mpstwu\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddis\M}    } } */
+/* { dg-final { scan-assembler-not   {\maddi\M}     } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #11 of 14, Add tests for using PC-relative instructions with -mcpu=future

[Michael Meissner]

This patch is the same as:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01501.html

This patch adds a set of tests for each type to verify that the appropriate
PC-relative instructions are generated when -mcpu=future is used.  Can I check
this patch into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-pcrel.h: New set of tests to test
	prefixed addressing on 'future' system with PC-relative addresses
	for various types.
	* gcc.target/powerpc/prefix-pcrel-dd.c: New test for prefixed
	loads/stores with PC-relative addresses for the _Decimal64 type.
	* gcc.target/powerpc/prefix-pcrel-df.c: New test for prefixed
	loads/stores with PC-relative addresses for the double type.
	* gcc.target/powerpc/prefix-pcrel-di.c: New test for prefixed
	loads/stores with PC-relative addresses for the long type.
	* gcc.target/powerpc/prefix-pcrel-hi.c: New test for prefixed
	loads/stores with PC-relative addresses for the short type.
	* gcc.target/powerpc/prefix-pcrel-kf.c: New test for prefixed
	loads/stores with PC-relative addresses for the __float128 type.
	* gcc.target/powerpc/prefix-pcrel-qi.c: New test for prefixed
	loads/stores with PC-relative addresses for the signed char type.
	* gcc.target/powerpc/prefix-pcrel-sd.c: New test for prefixed
	loads/stores with PC-relative addresses for the _Decimal32 type.
	* gcc.target/powerpc/prefix-pcrel-sf.c: New test for prefixed
	loads/stores with PC-relative addresses for the float type.
	* gcc.target/powerpc/prefix-pcrel-si.c: New test for prefixed
	loads/stores with PC-relative addresses for the int type.
	* gcc.target/powerpc/prefix-pcrel-udi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned long
	type.
	* gcc.target/powerpc/prefix-pcrel-uhi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned short
	type.
	* gcc.target/powerpc/prefix-pcrel-uqi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned char
	type.
	* gcc.target/powerpc/prefix-pcrel-usi.c: New test for prefixed
	loads/stores with PC-relative addresses for the unsigned int
	type.
	* gcc.target/powerpc/prefix-pcrel-v2df.c: New test for prefixed
	loads/stores with PC-relative addresses for the vector double
	type.

Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-dd.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the _Decimal64 type.  */
+
+#define TYPE _Decimal64
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-df.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the double type.  */
+
+#define TYPE double
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-di.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the long type.  */
+
+#define TYPE long
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel} 4 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-hi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the short type.  */
+
+#define TYPE short
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}     4 } } */
+/* { dg-final { scan-assembler-times {\mplh[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}     2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-kf.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the __float128 type.  */
+
+#define TYPE __float128
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-qi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the signed char type.  */
+
+#define TYPE signed char
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sd.c	(working copy)
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the _Decimal32 type.  Note, the _Decimal32
+   type will not generate any prefixed load or stores, because there is no
+   prefixed load/store instruction to load up a vector register as a zero
+   extended 32-bit integer.  So we count the number load addresses that are
+   generated.  */
+
+#define TYPE _Decimal32
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel} 3 } } */
+/* { dg-final { scan-assembler-times {\mpla\M}  3 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-sf.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the float type.  */
+
+#define TYPE float
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstfs\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-si.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the int type.  */
+
+#define TYPE int
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}     4 } } */
+/* { dg-final { scan-assembler-times {\mplw[az]\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}     2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-udi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for unsigned long type.  */
+
+#define TYPE unsigned long
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel} 4 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstd\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uhi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the unsigned short type.  */
+
+#define TYPE unsigned short
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplhz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpsth\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-uqi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the unsigned char type.  */
+
+#define TYPE unsigned char
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplbz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstb\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-usi.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for unsigned int type.  */
+
+#define TYPE unsigned int
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstw\M}  2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel-v2df.c	(working copy)
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for the vector double type.  */
+
+#define TYPE vector double
+
+#include "prefix-pcrel.h"
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  4 } } */
+/* { dg-final { scan-assembler-times {\mplxv\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpstxv\M} 2 } } */
Index: gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h	(revision 280086)
+++ gcc/testsuite/gcc.target/powerpc/prefix-pcrel.h	(working copy)
@@ -0,0 +1,58 @@
+/* Common tests for prefixed instructions testing whether pc-relative prefixed
+   instructions are generated for each type.  */
+
+typedef signed char	schar;
+typedef unsigned char	uchar;
+typedef unsigned short	ushort;
+typedef unsigned int	uint;
+typedef unsigned long	ulong;
+typedef long double	ldouble;
+typedef vector double	v2df;
+typedef vector long	v2di;
+typedef vector float	v4sf;
+typedef vector int	v4si;
+
+#ifndef TYPE
+#define TYPE ulong
+#endif
+
+#ifndef ITYPE
+#define ITYPE TYPE
+#endif
+
+#ifndef OTYPE
+#define OTYPE TYPE
+#endif
+
+static TYPE a;
+TYPE *p = &a;
+
+#if !defined(DO_ADD) && !defined(DO_VALUE) && !defined(DO_SET)
+#define DO_ADD		1
+#define DO_VALUE	1
+#define DO_SET		1
+#endif
+
+#if DO_ADD
+void
+add (TYPE b)
+{
+  a += b;
+}
+#endif
+
+#if DO_VALUE
+OTYPE
+value (void)
+{
+  return (OTYPE)a;
+}
+#endif
+
+#if DO_SET
+void
+set (ITYPE b)
+{
+  a = (TYPE)b;
+}
+#endif

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #12 of 14, Add test for -fstack-protect-strong with large stack sizes and -mcpu=future

[Michael Meissner]

This patch is the same as:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01503.html

This patch adds a new test to test that -fstack-protect-strong generates the
correct code when a large stack is used and the compiler option -mcpu=future is
also used.  Can I check this into the trunk?

This is a bug that we discovered when we attempted to build glibc using the
-mcpu=future option.

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/prefix-stack-protect.c: New test to make sure
	-fstack-protect-strong works with prefixed addressing.

Index: gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c	(revision 280088)
+++ gcc/testsuite/gcc.target/powerpc/prefix-stack-protect.c	(working copy)
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future -fstack-protector-strong" } */
+
+/* Test that we can handle large stack frames with -fstack-protector-strong and
+   prefixed addressing.  This was originally discovered in trying to build
+   glibc with -mcpu=future, and vfwprintf.c failed because it used
+   -fstack-protector-strong.  */
+
+extern long foo (char *);
+
+long
+bar (void)
+{
+  char buffer[0x20000];
+  return foo (buffer) + 1;
+}
+
+/* { dg-final { scan-assembler {\mpld\M}  } } */
+/* { dg-final { scan-assembler {\mpstd\M} } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #13 of 14, Add tests for vec_extract with PC-relative addresses

[Michael Meissner]

This patch is the same as:
https://gcc.gnu.org/ml/gcc-patches/2019-12/msg01504.html

This patch adds some tests to validate the work in patches V12 #1-4 generate
the correct code with vec_extract is used with a vector with a PC-relative
address and -mcpu=future is used.  Can I check this into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/vec-extract-pcrel-si.c: New test for
	vec_extract from a PC-relative address.
	* gcc.target/powerpc/vec-extract-pcrel-di.c: New test for
	vec_extract from a PC-relative address.
	* gcc.target/powerpc/vec-extract-pcrel-sf.c: New test for
	vec_extract from a PC-relative address.
	* gcc.target/powerpc/vec-extract-pcrel-df.c: New test for
	vec_extract from a PC-relative address.

Index: gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-df.c	(revision 280090)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-df.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V2DF vectors with a PC-relative
+   address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE double
+#endif
+
+static vector TYPE v;
+vector TYPE *p = &v;
+
+TYPE
+get0 (void)
+{
+  return vec_extract (v, 0);
+}
+
+TYPE
+get1 (void)
+{
+  return vec_extract (v, 1);
+}
+
+TYPE
+getn (unsigned long n)
+{
+  return vec_extract (v, n);
+}
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  3 } } */
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpla\M}   1 } } */
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-di.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-di.c	(revision 280090)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-di.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V2DI vectors with a PC-relative
+   address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE unsigned long
+#endif
+
+static vector TYPE v;
+vector TYPE *p = &v;
+
+TYPE
+get0 (void)
+{
+  return vec_extract (v, 0);
+}
+
+TYPE
+get1 (void)
+{
+  return vec_extract (v, 1);
+}
+
+TYPE
+getn (unsigned long n)
+{
+  return vec_extract (v, n);
+}
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  3 } } */
+/* { dg-final { scan-assembler-times {\mpld\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpla\M}   1 } } */
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-sf.c	(revision 280090)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-sf.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V4SF vectors with a PC-relative
+   address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE float
+#endif
+
+static vector TYPE v;
+vector TYPE *p = &v;
+
+TYPE
+get0 (void)
+{
+  return vec_extract (v, 0);
+}
+
+TYPE
+get1 (void)
+{
+  return vec_extract (v, 1);
+}
+
+TYPE
+getn (unsigned long n)
+{
+  return vec_extract (v, n);
+}
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  3 } } */
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpla\M}   1 } } */
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-si.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-si.c	(revision 280090)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-pcrel-si.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_pcrel } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V4SI vectors with a PC-relative
+   address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE unsigned int
+#endif
+
+static vector TYPE v;
+vector TYPE *p = &v;
+
+TYPE
+get0 (void)
+{
+  return vec_extract (v, 0);
+}
+
+TYPE
+get1 (void)
+{
+  return vec_extract (v, 1);
+}
+
+TYPE
+getn (unsigned long n)
+{
+  return vec_extract (v, n);
+}
+
+/* { dg-final { scan-assembler-times {[@]pcrel}  3 } } */
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpla\M}   1 } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

[PATCH] V12 patch #14 of 14, Add tests for generating prefixed instructions when using vec_extract with large offsets with -mcpu=future

[Michael Meissner]

While this patch is similar in spirit to V11 #15, I lost that patch, and I
re-implemented the check.  Can I check this test into the trunk?

2020-01-09  Michael Meissner  <meissner@linux.ibm.com>

	* gcc.target/powerpc/vec-extract-large-si.c: New test for
	vec_extract from a vector unsigned int in memory with a large
	offset.
	* gcc.target/powerpc/vec-extract-large-di.c: New test for
	vec_extract from a vector long in memory with a large offset.
	* gcc.target/powerpc/vec-extract-large-sf.c: New test for
	vec_extract from a vector float in memory with a large offset.
	* gcc.target/powerpc/vec-extract-large-df.c: New test for
	vec_extract from a vector double in memory with a large offset.

Index: gcc/testsuite/gcc.target/powerpc/vec-extract-large-df.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-large-df.c	(revision 280092)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-large-df.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V2DF vectors with a large numeric
+   offset address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE double
+#endif
+
+#ifndef OFFSET
+#define OFFSET 0x12345
+#endif
+
+TYPE
+get0 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 0);
+}
+
+TYPE
+get1 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 1);
+}
+
+TYPE
+getn (vector TYPE *p, unsigned long n)
+{
+  return vec_extract (p[OFFSET], n);
+}
+
+/* { dg-final { scan-assembler-times {\mplfd\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-large-di.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-large-di.c	(revision 280092)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-large-di.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V2DI vectors with a large numeric
+   offset address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE unsigned long long
+#endif
+
+#ifndef OFFSET
+#define OFFSET 0x12345
+#endif
+
+TYPE
+get0 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 0);
+}
+
+TYPE
+get1 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 1);
+}
+
+TYPE
+getn (vector TYPE *p, unsigned long n)
+{
+  return vec_extract (p[OFFSET], n);
+}
+
+/* { dg-final { scan-assembler-times {\mpld\M}   2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-large-sf.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-large-sf.c	(revision 280092)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-large-sf.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V4SF vectors with a large numeric
+   offset address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE float
+#endif
+
+#ifndef OFFSET
+#define OFFSET 0x12345
+#endif
+
+TYPE
+get0 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 0);
+}
+
+TYPE
+get1 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 1);
+}
+
+TYPE
+getn (vector TYPE *p, unsigned long n)
+{
+  return vec_extract (p[OFFSET], n);
+}
+
+/* { dg-final { scan-assembler-times {\mplfs\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */
Index: gcc/testsuite/gcc.target/powerpc/vec-extract-large-si.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/vec-extract-large-si.c	(revision 280092)
+++ gcc/testsuite/gcc.target/powerpc/vec-extract-large-si.c	(working copy)
@@ -0,0 +1,37 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=future" } */
+
+/* Test if we can support vec_extract on V4SI vectors with a large numeric
+   offset address.  */
+
+#include <altivec.h>
+
+#ifndef TYPE
+#define TYPE unsigned int
+#endif
+
+#ifndef OFFSET
+#define OFFSET 0x12345
+#endif
+
+TYPE
+get0 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 0);
+}
+
+TYPE
+get1 (vector TYPE *p)
+{
+  return vec_extract (p[OFFSET], 1);
+}
+
+TYPE
+getn (vector TYPE *p, unsigned long n)
+{
+  return vec_extract (p[OFFSET], n);
+}
+
+/* { dg-final { scan-assembler-times {\mplwz\M}  2 } } */
+/* { dg-final { scan-assembler-times {\mpaddi\M} 1 } } */

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] V12 patch #1 of 14, add gcc_asserts for rs6000_adjust_vec_address

[Segher Boessenkool]

Hi!

On Thu, Jan 09, 2020 at 06:52:05PM -0500, Michael Meissner wrote:
> 2020-01-09  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* config/rs6000/rs6000.c (rs6000_adjust_vec_address): Add some
> 	gcc_asserts.

> +      /* All insns should use the 'Q' constraint (address is a single register)
> +	 if the element number is not a constant.  */
> +      gcc_assert (REG_P (addr) || SUBREG_P (addr));

So maybe you should just more directly say

  gcc_assert (satisfies_constraint_Q (addr));

?  The Q constraint does not allow subregs, btw, is that an oversight?

Okay for trunk either way.  Thanks!


Segher

Re: [PATCH] V12 patch #2 of 14, Refactor rs6000_adjust_vec_address & rs6000_split_vec_extract_var

[Segher Boessenkool]

Hi!

On Thu, Jan 09, 2020 at 07:04:10PM -0500, Michael Meissner wrote:
> 2020-01-09  Michael Meissner  <meissner@linux.ibm.com>
> 
> 	* config/rs6000/rs6000.c (get_vector_offset): New helper function
> 	to calculate the offset in memory from the start of a vector of a
> 	particular element.  Add code to keep the element number in
> 	bounces if the element number is variable.

"within bounds"?

> +/* Return the offset within a memory object (MEM) of a vector type to a given
> +   element within the vector (ELEMENT) with an element size (SCALAR_SIZE).  If
> +   the element is constant, we return a constant integer.  Otherwise, we use a
> +   base register temporary to calculate the offset after making it to fit
> +   within the vector and scaling it.  */

"masking it"?

> +static rtx
> +get_vector_offset (rtx mem, rtx element, rtx base_tmp, unsigned scalar_size)
> +{
> +  if (CONST_INT_P (element))
> +    return GEN_INT (INTVAL (element) * scalar_size);
> +
> +  /* All insns should use the 'Q' constraint (address is a single register) if
> +     the element number is not a constant.  */
> +  rtx addr = XEXP (mem, 0);
> +  gcc_assert (REG_P (addr) || SUBREG_P (addr));

satisfies_constraint_Q (addr)

> +  /* Mask the element to make sure the element number is between 0 and the
> +     maximum number of elements - 1 so that we don't generate an address
> +     outside the vector.  */

But why is that the correct thing to do?  Garbage in, garbage out is
perfectly fine?  Or do we have (e.g.) builtins that specify this masking?
If so, please say that here.

> +  emit_insn (gen_rtx_SET (base_tmp, and_op));
> +
> +  /* Shift the element to get the byte offset from the element number.  */
> +  int shift = exact_log2 (scalar_size);
> +  gcc_assert (shift >= 0);
> +
> +  if (shift > 0)
> +    {
> +      rtx shift_op = gen_rtx_ASHIFT (Pmode, base_tmp, GEN_INT (shift));
> +      emit_insn (gen_rtx_SET (base_tmp, shift_op));
> +    }

This sets the same pseudo twice (or is it never a pseudo?), not a good
idea in general.

Okay for trunk, with comments improved please.  Thanks!


Segher

Re: [PATCH] V12 patch #5 of 14, Make -mpcrel default for -mcpu=future on little endian Linux 64-bit systems

[Segher Boessenkool]

Hi!

On Thu, Jan 09, 2020 at 07:40:08PM -0500, Michael Meissner wrote:
> 	* config/rs6000/linux64.h (PREFIXED_ADDR_SUPPORTED_BY_OS): Set to
> 	1 to enable prefixed addressing if -mcpu=future.
> 	(PCREL_SUPPORTED_BY_OS): Set to 1 to enable PC-relative addressing
> 	if -mcpu=future.
> 	* config/rs6000/rs6000-cpus.h (ISA_FUTURE_MASKS_SERVER): Do not
> 	enable -mprefixed-addr or -mpcrel by default.

I understand why this is needed for pcrel (or useful at least), but why
for prefixed addressing in general as well?  What OS support is needed
for that?

Put another way, is this just carefulness, or do you run into actual
problems without it?

> +/* Enable support for pc-relative and numeric prefixed addressing on the
> +   'future' system.  */
> +#undef  PREFIXED_ADDR_SUPPORTED_BY_OS
> +#define PREFIXED_ADDR_SUPPORTED_BY_OS	1
> +
> +#undef  PCREL_SUPPORTED_BY_OS
> +#define PCREL_SUPPORTED_BY_OS		1

"Numeric prefixed addressing"?  What's that?  Just "and other prefixed
addressing", maybe?

(Is it useful to have those two separate at all, btw?  Now, that is while
we are still developing the code, but also in the future?)

> +/* Addressing related flags on a future processor.  These are options that need
> +   to be cleared if the target OS is not capable of supporting prefixed
> +   addressing at all (such as 32-bit mode or if the object file format is not
> +   ELF v2).  */

Ah.  If we are missing the needed relocations (or other as/ld support).
So it is not about OS really, missing toolchain support instead?

> +      /* Only ELFv2 currently supports prefixed/pcrel addressing.  */
> +      else if (rs6000_current_abi != ABI_ELFv2)
> +	{
> +	  if (TARGET_PCREL && explicit_pcrel)
> +	    error ("%qs requires %qs", "-mpcrel", "-mabi=elfv2");
> +
> +	  else if (TARGET_PREFIXED_ADDR && explicit_prefixed)
> +	    error ("%qs requires %qs", "-mprefixed-addr", "-mabi=elfv2");

It would be good if the error messages also said "currently" somehow (it
is not an actual limitation, it's just a matter of code).  "Is only
supported with -mabi=elfv2", perhaps?


Segher

Re: [PATCH] V12 patch #5 of 14, Make -mpcrel default for -mcpu=future on little endian Linux 64-bit systems

[Michael Meissner]

On Fri, Jan 31, 2020 at 07:12:53PM -0600, Segher Boessenkool wrote:
> Hi!
> 
> On Thu, Jan 09, 2020 at 07:40:08PM -0500, Michael Meissner wrote:
> > 	* config/rs6000/linux64.h (PREFIXED_ADDR_SUPPORTED_BY_OS): Set to
> > 	1 to enable prefixed addressing if -mcpu=future.
> > 	(PCREL_SUPPORTED_BY_OS): Set to 1 to enable PC-relative addressing
> > 	if -mcpu=future.
> > 	* config/rs6000/rs6000-cpus.h (ISA_FUTURE_MASKS_SERVER): Do not
> > 	enable -mprefixed-addr or -mpcrel by default.
> 
> I understand why this is needed for pcrel (or useful at least), but why
> for prefixed addressing in general as well?  What OS support is needed
> for that?
> 
> Put another way, is this just carefulness, or do you run into actual
> problems without it?

Just caution.  I can just do the PCREL.

> > +/* Enable support for pc-relative and numeric prefixed addressing on the
> > +   'future' system.  */
> > +#undef  PREFIXED_ADDR_SUPPORTED_BY_OS
> > +#define PREFIXED_ADDR_SUPPORTED_BY_OS	1
> > +
> > +#undef  PCREL_SUPPORTED_BY_OS
> > +#define PCREL_SUPPORTED_BY_OS		1
> 
> "Numeric prefixed addressing"?  What's that?  Just "and other prefixed
> addressing", maybe?

Using a prefixed address with a large offset, or using a small offset because
the traditional instruction is a DS/DQ instruction and the bottom 2/4 bits are
non-zero.

> (Is it useful to have those two separate at all, btw?  Now, that is while
> we are still developing the code, but also in the future?)
> 
> > +/* Addressing related flags on a future processor.  These are options that need
> > +   to be cleared if the target OS is not capable of supporting prefixed
> > +   addressing at all (such as 32-bit mode or if the object file format is not
> > +   ELF v2).  */
> 
> Ah.  If we are missing the needed relocations (or other as/ld support).
> So it is not about OS really, missing toolchain support instead?

It also plays into the dynamic loader of the system.  If the dynamic loader
doesn't support the new relocations, you can't do PCREL.

> 
> > +      /* Only ELFv2 currently supports prefixed/pcrel addressing.  */
> > +      else if (rs6000_current_abi != ABI_ELFv2)
> > +	{
> > +	  if (TARGET_PCREL && explicit_pcrel)
> > +	    error ("%qs requires %qs", "-mpcrel", "-mabi=elfv2");
> > +
> > +	  else if (TARGET_PREFIXED_ADDR && explicit_prefixed)
> > +	    error ("%qs requires %qs", "-mprefixed-addr", "-mabi=elfv2");
> 
> It would be good if the error messages also said "currently" somehow (it
> is not an actual limitation, it's just a matter of code).  "Is only
> supported with -mabi=elfv2", perhaps?

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] V12 patch #2 of 14, Refactor rs6000_adjust_vec_address & rs6000_split_vec_extract_var

[Michael Meissner]

On Fri, Jan 31, 2020 at 11:30:22AM -0600, Segher Boessenkool wrote:
> But why is that the correct thing to do?  Garbage in, garbage out is
> perfectly fine?  Or do we have (e.g.) builtins that specify this masking?
> If so, please say that here.

It has been this way since I added these for power7 or power8, so I'm not
changing the semantics here.

Quoting from the LE abi:

VEC_EXTRACT (ARG1, ARG2)

This function uses modular arithmetic on ARG2 to determine the element number. For
example, if ARG2 is out of range, the compiler uses ARG2 modulo the number of elements
in the vector to determine the element position.

So if we were to remove the ANDing, we would have to change the ABI.

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] V12 patch #3 of 14, Improve address validation in rs6000_adjust_vec_address

[Michael Meissner]

On Fri, Jan 31, 2020 at 05:43:20PM -0600, Segher Boessenkool wrote:
> Hi!
> 
> On Thu, Jan 09, 2020 at 07:27:58PM -0500, Michael Meissner wrote:
> > 	* config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
> > 	reference.
> 
> FWIW, it is better to just reorder the code, in most cases.
> 
> > 	(hard_reg_and_mode_to_addr_mask): Delete, no longer used.
> 
> Just "Delete.".  Changelogs say what, not why; you have the commit
> message for that.
> 
> > +	  new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
> 
> So this depends on op0 not being r0 here.  Do we guarantee that somehow?
> It isn't obvious, so add an assert for this please?  (Or do I miss
> something obvious?  :-) )

That particular code is inside if CONST_INT_P (op1).  Therefore, op0 cannot be
r0, but I can add an assertion.

> > +    /* If the address isn't valid, move the address into the temporary base
> > +       register.  Some reasons it could not be valid include:
> > +       The address offset overflowed the 16 or 34 bit offset size;
> > +       We need to use a DS-FORM load, and the bottom 2 bits are non-zero;
> > +       We need to use a DQ-FORM load, and the bottom 2 bits are non-zero;
> > +       Only X_FORM loads can be done, and the address is D_FORM.  */
> 
> 4 bits for DQ-form?
> 
> Okay for trunk with those tweaks.  Thanks!
> 
> 
> Segher

-- 
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.ibm.com, phone: +1 (978) 899-4797

Re: [PATCH] V12 patch #5 of 14, Make -mpcrel default for -mcpu=future on little endian Linux 64-bit systems

[Segher Boessenkool]

On Mon, Feb 03, 2020 at 04:52:42PM -0500, Michael Meissner wrote:
> > I understand why this is needed for pcrel (or useful at least), but why
> > for prefixed addressing in general as well?  What OS support is needed
> > for that?
> > 
> > Put another way, is this just carefulness, or do you run into actual
> > problems without it?
> 
> Just caution.  I can just do the PCREL.

See below...  It really isn't "OS support", so maybe a better name will
help.

> > > +/* Enable support for pc-relative and numeric prefixed addressing on the
> > > +   'future' system.  */
> > > +#undef  PREFIXED_ADDR_SUPPORTED_BY_OS
> > > +#define PREFIXED_ADDR_SUPPORTED_BY_OS	1
> > > +
> > > +#undef  PCREL_SUPPORTED_BY_OS
> > > +#define PCREL_SUPPORTED_BY_OS		1
> > 
> > "Numeric prefixed addressing"?  What's that?  Just "and other prefixed
> > addressing", maybe?
> 
> Using a prefixed address with a large offset, or using a small offset because
> the traditional instruction is a DS/DQ instruction and the bottom 2/4 bits are
> non-zero.

Okay.  So pretty much any prefixed load/store instruction.  "Support for
pc-relative and other prefixed addressing".  It's fine to point out pcrel
specifically, but just don't try to detail the rest here :-)

> > > +/* Addressing related flags on a future processor.  These are options that need
> > > +   to be cleared if the target OS is not capable of supporting prefixed
> > > +   addressing at all (such as 32-bit mode or if the object file format is not
> > > +   ELF v2).  */
> > 
> > Ah.  If we are missing the needed relocations (or other as/ld support).
> > So it is not about OS really, missing toolchain support instead?
> 
> It also plays into the dynamic loader of the system.  If the dynamic loader
> doesn't support the new relocations, you can't do PCREL.

If you are building shared stuff at all.  Right.

So toolchain support and dl support (i.e. binutils and glibc)?
Anything else?

We'll be best off if you separate those out now, because those
restrictions are independent.  Also handled by different people on
different projects ;-)

Thanks,


Segher

Re: [PATCH] V12 patch #2 of 14, Refactor rs6000_adjust_vec_address & rs6000_split_vec_extract_var

[Segher Boessenkool]

On Mon, Feb 03, 2020 at 05:02:25PM -0500, Michael Meissner wrote:
> On Fri, Jan 31, 2020 at 11:30:22AM -0600, Segher Boessenkool wrote:
> > But why is that the correct thing to do?  Garbage in, garbage out is
> > perfectly fine?  Or do we have (e.g.) builtins that specify this masking?
> > If so, please say that here.
> 
> It has been this way since I added these for power7 or power8, so I'm not
> changing the semantics here.

Please don't cut away too much context.

> +  /* Mask the element to make sure the element number is between 0 and the
> +     maximum number of elements - 1 so that we don't generate an address
> +     outside the vector.  */

But why is that the correct thing to do?  Garbage in, garbage out is
perfectly fine?  Or do we have (e.g.) builtins that specify this masking?
If so, please say that here.

The comment should not just say it is masking thigs; that does not help
the reader much, that isn't too hard to see.  But *why* is it masking
things?  Is that a requirement, is that for better performance, is there
no reason?  If there is no reason, and it could be better not to do this,
a FIXME comment would help.

> Quoting from the LE abi:
> 
> VEC_EXTRACT (ARG1, ARG2)
> 
> This function uses modular arithmetic on ARG2 to determine the element number. For
> example, if ARG2 is out of range, the compiler uses ARG2 modulo the number of elements
> in the vector to determine the element position.

Right.  So it is *not* "so that we don't generate an address outside the
vector" -- it is simply because the API definition says we do, so we
should.


Segher

Re: [PATCH] V12 patch #3 of 14, Improve address validation in rs6000_adjust_vec_address

[Segher Boessenkool]

On Mon, Feb 03, 2020 at 06:19:07PM -0500, Michael Meissner wrote:
> On Fri, Jan 31, 2020 at 05:43:20PM -0600, Segher Boessenkool wrote:
> > On Thu, Jan 09, 2020 at 07:27:58PM -0500, Michael Meissner wrote:
> > > 	* config/rs6000/rs6000.c (reg_to_non_prefixed): Add forward
> > > 	reference.
> > 
> > FWIW, it is better to just reorder the code, in most cases.
> > 
> > > 	(hard_reg_and_mode_to_addr_mask): Delete, no longer used.
> > 
> > Just "Delete.".  Changelogs say what, not why; you have the commit
> > message for that.
> > 
> > > +	  new_addr = gen_rtx_PLUS (Pmode, op0, offset_rtx);
> > 
> > So this depends on op0 not being r0 here.  Do we guarantee that somehow?
> > It isn't obvious, so add an assert for this please?  (Or do I miss
> > something obvious?  :-) )
> 
> That particular code is inside if CONST_INT_P (op1).  Therefore, op0 cannot be
> r0, but I can add an assertion.

Please do (unless you think I'm just totally silly for not seeing this --
it's not always as obvious in a patch as it will be in the final code).


Segher