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From: Jakub Jelinek <jakub@redhat.com>
To: Richard Biener <richard.guenther@gmail.com>
Cc: Uros Bizjak <ubizjak@gmail.com>, GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [PATCH] i386: Fix -mavx -mno-mavx2 ICE with VEC_COND_EXPR [PR93637]
Date: Mon, 10 Feb 2020 14:47:00 -0000	[thread overview]
Message-ID: <20200210144707.GR17695@tucnak> (raw)
In-Reply-To: <CAFiYyc3Y3As91cT6wFsnjgs-vB4hK5EUbavjmwvn=cD=R5Hdsg@mail.gmail.com>

On Mon, Feb 10, 2020 at 03:40:18PM +0100, Richard Biener wrote:
> Hmm.  Maybe with FP operands we can also try to implement the mask
> as != 0.0 FP condition?  Not sure if -1 (or 1) is enough non-NaNish to
> not cause problems of course.

Well, by the time we reach expansion, we have just the VECTOR_CST integral
operand, and we use right now:
      gcc_assert (VECTOR_BOOLEAN_TYPE_P (TREE_TYPE (op0)));
      if (get_vcond_mask_icode (mode, TYPE_MODE (TREE_TYPE (op0)))
          != CODE_FOR_nothing)
        return expand_vec_cond_mask_expr (vec_cond_type, op0, op1,
                                          op2, target);
      /* Fake op0 < 0.  */
      else
        {
          gcc_assert (GET_MODE_CLASS (TYPE_MODE (TREE_TYPE (op0)))
                      == MODE_VECTOR_INT);
          op0a = op0;
          op0b = build_zero_cst (TREE_TYPE (op0));
          tcode = LT_EXPR;
        }
so we'd need to try that op0 < 0 case and if that fails, try to find some
floating point (or other?) mode that has the same element size and precision
and change the condition back to comparison of two floating point constants
and then hope combine will fold it back to vcond_mask* again.

	Jakub

  reply	other threads:[~2020-02-10 14:47 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-10 14:33 Jakub Jelinek
2020-02-10 14:40 ` Richard Biener
2020-02-10 14:47   ` Jakub Jelinek [this message]
2020-02-10 20:16 ` Uros Bizjak

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