From: Richard Henderson <richard.henderson@linaro.org>
To: gcc-patches@gcc.gnu.org
Cc: richard.earnshaw@arm.com, richard.sandiford@arm.com,
marcus.shawcroft@arm.com, kyrylo.tkachov@arm.com
Subject: [PATCH 1/6] aarch64: Add ucmp_*_carryinC patterns for all usub_*_carryinC
Date: Wed, 18 Mar 2020 23:48:00 -0700 [thread overview]
Message-ID: <20200319064805.17739-2-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200319064805.17739-1-richard.henderson@linaro.org>
Use xzr for the output when we only require the flags output.
This will be used shortly for TImode comparisons.
* config/aarch64/aarch64.md (ucmp<GPI>3_carryinC): New.
(*ucmp<GPI>3_carryinC_z1): New.
(*ucmp<GPI>3_carryinC_z2): New.
(*ucmp<GPI>3_carryinC): New.
---
gcc/config/aarch64/aarch64.md | 50 +++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index c7c4d1dd519..fcc1ddafaec 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -3439,6 +3439,18 @@
""
)
+(define_expand "ucmp<GPI:mode>3_carryinC"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (zero_extend:<DWI>
+ (match_operand:GPI 0 "register_operand"))
+ (plus:<DWI>
+ (zero_extend:<DWI>
+ (match_operand:GPI 1 "register_operand"))
+ (ltu:<DWI> (reg:CC CC_REGNUM) (const_int 0)))))]
+ ""
+)
+
(define_insn "*usub<GPI:mode>3_carryinC_z1"
[(set (reg:CC CC_REGNUM)
(compare:CC
@@ -3456,6 +3468,19 @@
[(set_attr "type" "adc_reg")]
)
+(define_insn "*ucmp<GPI:mode>3_carryinC_z1"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (const_int 0)
+ (plus:<DWI>
+ (zero_extend:<DWI>
+ (match_operand:GPI 0 "register_operand" "r"))
+ (match_operand:<DWI> 1 "aarch64_borrow_operation" ""))))]
+ ""
+ "sbcs\\t<w>zr, <w>zr, %<w>0"
+ [(set_attr "type" "adc_reg")]
+)
+
(define_insn "*usub<GPI:mode>3_carryinC_z2"
[(set (reg:CC CC_REGNUM)
(compare:CC
@@ -3471,6 +3496,17 @@
[(set_attr "type" "adc_reg")]
)
+(define_insn "*ucmp<GPI:mode>3_carryinC_z2"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (zero_extend:<DWI>
+ (match_operand:GPI 0 "register_operand" "r"))
+ (match_operand:<DWI> 1 "aarch64_borrow_operation" "")))]
+ ""
+ "sbcs\\t<w>zr, %<w>0, <w>zr"
+ [(set_attr "type" "adc_reg")]
+)
+
(define_insn "*usub<GPI:mode>3_carryinC"
[(set (reg:CC CC_REGNUM)
(compare:CC
@@ -3489,6 +3525,20 @@
[(set_attr "type" "adc_reg")]
)
+(define_insn "*ucmp<GPI:mode>3_carryinC"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC
+ (zero_extend:<DWI>
+ (match_operand:GPI 0 "register_operand" "r"))
+ (plus:<DWI>
+ (zero_extend:<DWI>
+ (match_operand:GPI 1 "register_operand" "r"))
+ (match_operand:<DWI> 2 "aarch64_borrow_operation" ""))))]
+ ""
+ "sbcs\\t<w>zr, %<w>0, %<w>1"
+ [(set_attr "type" "adc_reg")]
+)
+
(define_expand "sub<GPI:mode>3_carryinV"
[(parallel
[(set (reg:CC_V CC_REGNUM)
--
2.20.1
next prev parent reply other threads:[~2020-03-19 6:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-19 6:47 [PATCH 0/6] aarch64: Implement TImode comparisons Richard Henderson
2020-03-19 6:48 ` Richard Henderson [this message]
2020-03-19 6:48 ` [PATCH 2/6] aarch64: Adjust result of aarch64_gen_compare_reg Richard Henderson
2020-03-19 6:48 ` [PATCH 3/6] aarch64: Accept 0 as first argument to compares Richard Henderson
2020-03-19 6:48 ` [PATCH 4/6] aarch64: Simplify @ccmp<cc_mode><mode> operands Richard Henderson
2020-03-19 6:48 ` [PATCH 5/6] aarch64: Improve nzcv argument to ccmp Richard Henderson
2020-03-19 6:48 ` [PATCH 6/6] aarch64: Implement TImode comparisons Richard Henderson
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