From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) by sourceware.org (Postfix) with ESMTPS id E62B6385E00D for ; Thu, 2 Apr 2020 07:24:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org E62B6385E00D Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 0327482X033002 for ; Thu, 2 Apr 2020 03:24:27 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 304mcc41jm-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 02 Apr 2020 03:24:27 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 2 Apr 2020 08:24:21 +0100 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 0327OMBO54001806 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 2 Apr 2020 07:24:23 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D4BC711C05B for ; Thu, 2 Apr 2020 07:24:22 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FA7411C052 for ; Thu, 2 Apr 2020 07:24:22 +0000 (GMT) Received: from bart.boeblingen.de.ibm.com (unknown [9.145.4.152]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP for ; Thu, 2 Apr 2020 07:24:22 +0000 (GMT) From: Andreas Krebbel To: gcc-patches@gcc.gnu.org Subject: [Committed] S/390: Remove superfluous commutative constraint modifiers Date: Thu, 2 Apr 2020 09:24:22 +0200 X-Mailer: git-send-email 2.17.1 X-TM-AS-GCONF: 00 x-cbid: 20040207-0028-0000-0000-000003F079EF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20040207-0029-0000-0000-000024B602C6 Message-Id: <20200402072422.19638-1-krebbel@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.138, 18.0.676 definitions=2020-04-01_04:2020-03-31, 2020-04-01 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=1 bulkscore=0 mlxscore=0 adultscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 malwarescore=0 phishscore=0 mlxlogscore=999 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2003020000 definitions=main-2004020060 X-Spam-Status: No, score=-18.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_DMARC_STATUS, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Apr 2020 07:24:31 -0000 For operands with an identical set of alternatives there is no point in marking them commutative. This patch removes the superfluous constraint modifiers in vector.md and vx-builtins.md since it might slow down reload without buying us anything. There were even two patterns where the constraint modifier was plain wrong: "sub3" and "ior_not3". Fortunately it never had any effect. Bootstrapped and regression tested on s390x. SPEC binaries built with and without the patch are identical. gcc/ChangeLog: 2020-04-02 Andreas Krebbel * config/s390/vector.md ("add3", "mul3") ("and3", "notand3", "ior3", "ior_not3") ("xor3", "notxor3", "smin3", "smax3") ("umin3", "umax3", "vec_widen_smult_even_") ("vec_widen_umult_even_", "vec_widen_smult_odd_") ("vec_widen_umult_odd_", "add3", "sub3") ("mul3", "fma4", "fms4", "neg_fma4") ("neg_fms4", "*smax3_vxe", "*smaxv2df3_vx") ("*smin3_vxe", "*sminv2df3_vx"): Remove % constraint modifier. ("vec_widen_umult_lo_", "vec_widen_umult_hi_") ("vec_widen_smult_lo_", "vec_widen_smult_hi_"): Remove constraints from expander. * config/s390/vx-builtins.md ("vacc_", "vacq") ("vacccq", "vec_avg", "vec_avgu", "vec_vmal") ("vec_vmah", "vec_vmalh", "vec_vmae") ("vec_vmale", "vec_vmao", "vec_vmalo") ("vec_smulh", "vec_umulh", "vec_nor3") ("vfmin", "vfmax"): Remove % constraint modifier. --- gcc/ChangeLog | 22 ++++++++++ gcc/config/s390/vector.md | 80 +++++++++++++++++----------------- gcc/config/s390/vx-builtins.md | 78 ++++++++++++++++----------------- 3 files changed, 101 insertions(+), 79 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 66a118b6f5f..5a8a2c525c9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,25 @@ +2020-04-02 Andreas Krebbel + + * config/s390/vector.md ("add3", "mul3") + ("and3", "notand3", "ior3", "ior_not3") + ("xor3", "notxor3", "smin3", "smax3") + ("umin3", "umax3", "vec_widen_smult_even_") + ("vec_widen_umult_even_", "vec_widen_smult_odd_") + ("vec_widen_umult_odd_", "add3", "sub3") + ("mul3", "fma4", "fms4", "neg_fma4") + ("neg_fms4", "*smax3_vxe", "*smaxv2df3_vx") + ("*smin3_vxe", "*sminv2df3_vx"): Remove % constraint + modifier. + ("vec_widen_umult_lo_", "vec_widen_umult_hi_") + ("vec_widen_smult_lo_", "vec_widen_smult_hi_"): + Remove constraints from expander. + * config/s390/vx-builtins.md ("vacc_", "vacq") + ("vacccq", "vec_avg", "vec_avgu", "vec_vmal") + ("vec_vmah", "vec_vmalh", "vec_vmae") + ("vec_vmale", "vec_vmao", "vec_vmalo") + ("vec_smulh", "vec_umulh", "vec_nor3") + ("vfmin", "vfmax"): Remove % constraint modifier. + 2020-04-01 Peter Bergner PR rtl-optimization/94123 diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 378c9e3c7fb..9d3df9813c9 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -694,7 +694,7 @@ ; operation into two DImode ADDs. (define_insn "add3" [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") - (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "%v") + (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") (match_operand:VIT 2 "general_operand" "v")))] "TARGET_VX" "va\t%v0,%v1,%v2" @@ -704,7 +704,7 @@ (define_insn "sub3" [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") (minus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") - (match_operand:VIT 2 "general_operand" "v")))] + (match_operand:VIT 2 "general_operand" "v")))] "TARGET_VX" "vs\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) @@ -712,7 +712,7 @@ ; vmlb, vmlhw, vmlf (define_insn "mul3" [(set (match_operand:VI_QHS 0 "register_operand" "=v") - (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "%v") + (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "v") (match_operand:VI_QHS 2 "register_operand" "v")))] "TARGET_VX" "vml\t%v0,%v1,%v2" @@ -767,7 +767,7 @@ (define_insn "and3" [(set (match_operand:VT 0 "register_operand" "=v") - (and:VT (match_operand:VT 1 "register_operand" "%v") + (and:VT (match_operand:VT 1 "register_operand" "v") (match_operand:VT 2 "register_operand" "v")))] "TARGET_VX" "vn\t%v0,%v1,%v2" @@ -777,7 +777,7 @@ (define_insn "notand3" [(set (match_operand:VT 0 "register_operand" "=v") - (ior:VT (not:VT (match_operand:VT 1 "register_operand" "%v")) + (ior:VT (not:VT (match_operand:VT 1 "register_operand" "v")) (not:VT (match_operand:VT 2 "register_operand" "v"))))] "TARGET_VXE" "vnn\t%v0,%v1,%v2" @@ -787,7 +787,7 @@ (define_insn "ior3" [(set (match_operand:VT 0 "register_operand" "=v") - (ior:VT (match_operand:VT 1 "register_operand" "%v") + (ior:VT (match_operand:VT 1 "register_operand" "v") (match_operand:VT 2 "register_operand" "v")))] "TARGET_VX" "vo\t%v0,%v1,%v2" @@ -798,7 +798,7 @@ (define_insn "ior_not3" [(set (match_operand:VT 0 "register_operand" "=v") (ior:VT (not:VT (match_operand:VT 2 "register_operand" "v")) - (match_operand:VT 1 "register_operand" "%v")))] + (match_operand:VT 1 "register_operand" "v")))] "TARGET_VXE" "voc\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) @@ -807,7 +807,7 @@ (define_insn "xor3" [(set (match_operand:VT 0 "register_operand" "=v") - (xor:VT (match_operand:VT 1 "register_operand" "%v") + (xor:VT (match_operand:VT 1 "register_operand" "v") (match_operand:VT 2 "register_operand" "v")))] "TARGET_VX" "vx\t%v0,%v1,%v2" @@ -817,7 +817,7 @@ (define_insn "notxor3" [(set (match_operand:VT 0 "register_operand" "=v") - (not:VT (xor:VT (match_operand:VT 1 "register_operand" "%v") + (not:VT (xor:VT (match_operand:VT 1 "register_operand" "v") (match_operand:VT 2 "register_operand" "v"))))] "TARGET_VXE" "vnx\t%v0,%v1,%v2" @@ -1075,7 +1075,7 @@ ; vmnb, vmnh, vmnf, vmng (define_insn "smin3" [(set (match_operand:VI 0 "register_operand" "=v") - (smin:VI (match_operand:VI 1 "register_operand" "%v") + (smin:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmn\t%v0,%v1,%v2" @@ -1084,7 +1084,7 @@ ; vmxb, vmxh, vmxf, vmxg (define_insn "smax3" [(set (match_operand:VI 0 "register_operand" "=v") - (smax:VI (match_operand:VI 1 "register_operand" "%v") + (smax:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmx\t%v0,%v1,%v2" @@ -1093,7 +1093,7 @@ ; vmnlb, vmnlh, vmnlf, vmnlg (define_insn "umin3" [(set (match_operand:VI 0 "register_operand" "=v") - (umin:VI (match_operand:VI 1 "register_operand" "%v") + (umin:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmnl\t%v0,%v1,%v2" @@ -1102,7 +1102,7 @@ ; vmxlb, vmxlh, vmxlf, vmxlg (define_insn "umax3" [(set (match_operand:VI 0 "register_operand" "=v") - (umax:VI (match_operand:VI 1 "register_operand" "%v") + (umax:VI (match_operand:VI 1 "register_operand" "v") (match_operand:VI 2 "register_operand" "v")))] "TARGET_VX" "vmxl\t%v0,%v1,%v2" @@ -1111,7 +1111,7 @@ ; vmeb, vmeh, vmef (define_insn "vec_widen_smult_even_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_SMULT_EVEN))] "TARGET_VX" @@ -1121,7 +1121,7 @@ ; vmleb, vmleh, vmlef (define_insn "vec_widen_umult_even_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_UMULT_EVEN))] "TARGET_VX" @@ -1131,7 +1131,7 @@ ; vmob, vmoh, vmof (define_insn "vec_widen_smult_odd_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_SMULT_ODD))] "TARGET_VX" @@ -1141,7 +1141,7 @@ ; vmlob, vmloh, vmlof (define_insn "vec_widen_umult_odd_" [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") + (unspec: [(match_operand:VI_QHS 1 "register_operand" "v") (match_operand:VI_QHS 2 "register_operand" "v")] UNSPEC_VEC_UMULT_ODD))] "TARGET_VX" @@ -1162,13 +1162,13 @@ (define_expand "vec_widen_umult_lo_" [(set (match_dup 3) - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") - (match_operand:VI_QHS 2 "register_operand" "v")] + (unspec: [(match_operand:VI_QHS 1 "register_operand" "") + (match_operand:VI_QHS 2 "register_operand" "")] UNSPEC_VEC_UMULT_EVEN)) (set (match_dup 4) (unspec: [(match_dup 1) (match_dup 2)] UNSPEC_VEC_UMULT_ODD)) - (set (match_operand: 0 "register_operand" "=v") + (set (match_operand: 0 "register_operand" "") (unspec: [(match_dup 3) (match_dup 4)] UNSPEC_VEC_MERGEL))] "TARGET_VX" @@ -1179,13 +1179,13 @@ (define_expand "vec_widen_umult_hi_" [(set (match_dup 3) - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") - (match_operand:VI_QHS 2 "register_operand" "v")] + (unspec: [(match_operand:VI_QHS 1 "register_operand" "") + (match_operand:VI_QHS 2 "register_operand" "")] UNSPEC_VEC_UMULT_EVEN)) (set (match_dup 4) (unspec: [(match_dup 1) (match_dup 2)] UNSPEC_VEC_UMULT_ODD)) - (set (match_operand: 0 "register_operand" "=v") + (set (match_operand: 0 "register_operand" "") (unspec: [(match_dup 3) (match_dup 4)] UNSPEC_VEC_MERGEH))] "TARGET_VX" @@ -1196,13 +1196,13 @@ (define_expand "vec_widen_smult_lo_" [(set (match_dup 3) - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") - (match_operand:VI_QHS 2 "register_operand" "v")] + (unspec: [(match_operand:VI_QHS 1 "register_operand" "") + (match_operand:VI_QHS 2 "register_operand" "")] UNSPEC_VEC_SMULT_EVEN)) (set (match_dup 4) (unspec: [(match_dup 1) (match_dup 2)] UNSPEC_VEC_SMULT_ODD)) - (set (match_operand: 0 "register_operand" "=v") + (set (match_operand: 0 "register_operand" "") (unspec: [(match_dup 3) (match_dup 4)] UNSPEC_VEC_MERGEL))] "TARGET_VX" @@ -1213,13 +1213,13 @@ (define_expand "vec_widen_smult_hi_" [(set (match_dup 3) - (unspec: [(match_operand:VI_QHS 1 "register_operand" "%v") - (match_operand:VI_QHS 2 "register_operand" "v")] + (unspec: [(match_operand:VI_QHS 1 "register_operand" "") + (match_operand:VI_QHS 2 "register_operand" "")] UNSPEC_VEC_SMULT_EVEN)) (set (match_dup 4) (unspec: [(match_dup 1) (match_dup 2)] UNSPEC_VEC_SMULT_ODD)) - (set (match_operand: 0 "register_operand" "=v") + (set (match_operand: 0 "register_operand" "") (unspec: [(match_dup 3) (match_dup 4)] UNSPEC_VEC_MERGEH))] "TARGET_VX" @@ -1240,7 +1240,7 @@ ; vfasb, vfadb, wfasb, wfadb, wfaxb (define_insn "add3" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (plus:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (plus:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VX" "fab\t%v0,%v1,%v2" @@ -1249,7 +1249,7 @@ ; vfssb, vfsdb, wfssb, wfsdb, wfsxb (define_insn "sub3" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (minus:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (minus:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VX" "fsb\t%v0,%v1,%v2" @@ -1258,7 +1258,7 @@ ; vfmsb, vfmdb, wfmsb, wfmdb, wfmxb (define_insn "mul3" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (mult:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (mult:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VX" "fmb\t%v0,%v1,%v2" @@ -1284,7 +1284,7 @@ ; vfmasb, vfmadb, wfmasb, wfmadb, wfmaxb (define_insn "fma4" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v") (match_operand:VF_HW 3 "register_operand" "v")))] "TARGET_VX" @@ -1294,7 +1294,7 @@ ; vfmssb, vfmsdb, wfmssb, wfmsdb, wfmsxb (define_insn "fms4" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v") (neg:VF_HW (match_operand:VF_HW 3 "register_operand" "v"))))] "TARGET_VX" @@ -1305,7 +1305,7 @@ (define_insn "neg_fma4" [(set (match_operand:VF_HW 0 "register_operand" "=v") (neg:VF_HW - (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v") (match_operand:VF_HW 3 "register_operand" "v"))))] "TARGET_VXE" @@ -1316,7 +1316,7 @@ (define_insn "neg_fms4" [(set (match_operand:VF_HW 0 "register_operand" "=v") (neg:VF_HW - (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v") (neg:VF_HW (match_operand:VF_HW 3 "register_operand" "v")))))] "TARGET_VXE" @@ -1356,7 +1356,7 @@ ; vfmaxsb, vfmaxdb, wfmaxsb, wfmaxdb, wfmaxxb (define_insn "*smax3_vxe" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (smax:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (smax:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VXE" "fmaxb\t%v0,%v1,%v2,4" @@ -1365,7 +1365,7 @@ ; Emulate with compare + select (define_insn_and_split "*smaxv2df3_vx" [(set (match_operand:V2DF 0 "register_operand" "=v") - (smax:V2DF (match_operand:V2DF 1 "register_operand" "%v") + (smax:V2DF (match_operand:V2DF 1 "register_operand" "v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX && !TARGET_VXE" "#" @@ -1392,7 +1392,7 @@ ; vfminsb, vfmindb, wfminsb, wfmindb, wfminxb (define_insn "*smin3_vxe" [(set (match_operand:VF_HW 0 "register_operand" "=v") - (smin:VF_HW (match_operand:VF_HW 1 "register_operand" "%v") + (smin:VF_HW (match_operand:VF_HW 1 "register_operand" "v") (match_operand:VF_HW 2 "register_operand" "v")))] "TARGET_VXE" "fminb\t%v0,%v1,%v2,4" @@ -1401,7 +1401,7 @@ ; Emulate with compare + select (define_insn_and_split "*sminv2df3_vx" [(set (match_operand:V2DF 0 "register_operand" "=v") - (smin:V2DF (match_operand:V2DF 1 "register_operand" "%v") + (smin:V2DF (match_operand:V2DF 1 "register_operand" "v") (match_operand:V2DF 2 "register_operand" "v")))] "TARGET_VX && !TARGET_VXE" "#" diff --git a/gcc/config/s390/vx-builtins.md b/gcc/config/s390/vx-builtins.md index f13984de954..9a7f3dae1df 100644 --- a/gcc/config/s390/vx-builtins.md +++ b/gcc/config/s390/vx-builtins.md @@ -619,7 +619,7 @@ ; vaccb, vacch, vaccf, vaccg, vaccq (define_insn "vacc_" [(set (match_operand:VIT_HW 0 "register_operand" "=v") - (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "%v") + (unspec:VIT_HW [(match_operand:VIT_HW 1 "register_operand" "v") (match_operand:VIT_HW 2 "register_operand" "v")] UNSPEC_VEC_ADDC))] "TARGET_VX" @@ -630,7 +630,7 @@ (define_insn "vacq" [(set (match_operand:TI 0 "register_operand" "=v") - (unspec:TI [(match_operand:TI 1 "register_operand" "%v") + (unspec:TI [(match_operand:TI 1 "register_operand" "v") (match_operand:TI 2 "register_operand" "v") (match_operand:TI 3 "register_operand" "v")] UNSPEC_VEC_ADDE_U128))] @@ -643,7 +643,7 @@ (define_insn "vacccq" [(set (match_operand:TI 0 "register_operand" "=v") - (unspec:TI [(match_operand:TI 1 "register_operand" "%v") + (unspec:TI [(match_operand:TI 1 "register_operand" "v") (match_operand:TI 2 "register_operand" "v") (match_operand:TI 3 "register_operand" "v")] UNSPEC_VEC_ADDEC_U128))] @@ -671,7 +671,7 @@ ; vavgb, vavgh, vavgf, vavgg (define_insn "vec_avg" [(set (match_operand:VI_HW 0 "register_operand" "=v") - (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") (match_operand:VI_HW 2 "register_operand" "v")] UNSPEC_VEC_AVG))] "TARGET_VX" @@ -683,7 +683,7 @@ ; vavglb, vavglh, vavglf, vavglg (define_insn "vec_avgu" [(set (match_operand:VI_HW 0 "register_operand" "=v") - (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "%v") + (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v") (match_operand:VI_HW 2 "register_operand" "v")] UNSPEC_VEC_AVGU))] "TARGET_VX" @@ -855,9 +855,9 @@ ; vmalb, vmalh, vmalf, vmalg (define_insn "vec_vmal" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") - (match_operand:VI_HW_QHS 3 "register_operand" "v")] + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v")] UNSPEC_VEC_VMAL))] "TARGET_VX" "vmal\t%v0,%v1,%v2,%v3" @@ -868,9 +868,9 @@ ; vmahb; vmahh, vmahf, vmahg (define_insn "vec_vmah" [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") - (match_operand:VI_HW_QHS 3 "register_operand" "v")] + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v")] UNSPEC_VEC_VMAH))] "TARGET_VX" "vmah\t%v0,%v1,%v2,%v3" @@ -878,10 +878,10 @@ ; vmalhb; vmalhh, vmalhf, vmalhg (define_insn "vec_vmalh" - [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") - (match_operand:VI_HW_QHS 3 "register_operand" "v")] + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") + (match_operand:VI_HW_QHS 3 "register_operand" "v")] UNSPEC_VEC_VMALH))] "TARGET_VX" "vmalh\t%v0,%v1,%v2,%v3" @@ -891,8 +891,8 @@ ; vmaeb; vmaeh, vmaef, vmaeg (define_insn "vec_vmae" - [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMAE))] @@ -902,9 +902,9 @@ ; vmaleb; vmaleh, vmalef, vmaleg (define_insn "vec_vmale" - [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "%v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMALE))] "TARGET_VX" @@ -915,9 +915,9 @@ ; vmaob; vmaoh, vmaof, vmaog (define_insn "vec_vmao" - [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "%v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMAO))] "TARGET_VX" @@ -926,9 +926,9 @@ ; vmalob; vmaloh, vmalof, vmalog (define_insn "vec_vmalo" - [(set (match_operand: 0 "register_operand" "=v") - (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") - (match_operand:VI_HW_QHS 2 "register_operand" "v") + [(set (match_operand: 0 "register_operand" "=v") + (unspec: [(match_operand:VI_HW_QHS 1 "register_operand" "v") + (match_operand:VI_HW_QHS 2 "register_operand" "v") (match_operand: 3 "register_operand" "v")] UNSPEC_VEC_VMALO))] "TARGET_VX" @@ -942,8 +942,8 @@ ; vmhb, vmhh, vmhf (define_insn "vec_smulh" - [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") (match_operand:VI_HW_QHS 2 "register_operand" "v")] UNSPEC_VEC_SMULT_HI))] "TARGET_VX" @@ -952,8 +952,8 @@ ; vmlhb, vmlhh, vmlhf (define_insn "vec_umulh" - [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") - (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "%v") + [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") + (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") (match_operand:VI_HW_QHS 2 "register_operand" "v")] UNSPEC_VEC_UMULT_HI))] "TARGET_VX" @@ -970,9 +970,9 @@ ; Vector nor (define_insn "vec_nor3" - [(set (match_operand:VT_HW 0 "register_operand" "=v") + [(set (match_operand:VT_HW 0 "register_operand" "=v") (not:VT_HW - (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "%v") + (ior:VT_HW (match_operand:VT_HW 1 "register_operand" "v") (match_operand:VT_HW 2 "register_operand" "v"))))] "TARGET_VX" "vno\t%v0,%v1,%v2" @@ -2120,7 +2120,7 @@ [(set (reg:CCVFHE CC_REGNUM) (compare:CCVFHE (match_operand:VF_HW 0 "register_operand" "v") (match_operand:VF_HW 1 "register_operand" "v"))) - (set (match_operand: 2 "register_operand" "=v") + (set (match_operand: 2 "register_operand" "=v") (ge: (match_dup 0) (match_dup 1)))] "TARGET_VX" "fchebs\t%v2,%v0,%v1" @@ -2128,9 +2128,9 @@ (define_insn "vfmin" - [(set (match_operand:VF_HW 0 "register_operand" "=v") - (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v") - (match_operand:VF_HW 2 "register_operand" "v") + [(set (match_operand:VF_HW 0 "register_operand" "=v") + (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "v") + (match_operand:VF_HW 2 "register_operand" "v") (match_operand:QI 3 "const_mask_operand" "C")] UNSPEC_VEC_VFMIN))] "TARGET_VXE" @@ -2138,9 +2138,9 @@ [(set_attr "op_type" "VRR")]) (define_insn "vfmax" - [(set (match_operand:VF_HW 0 "register_operand" "=v") - (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "%v") - (match_operand:VF_HW 2 "register_operand" "v") + [(set (match_operand:VF_HW 0 "register_operand" "=v") + (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "v") + (match_operand:VF_HW 2 "register_operand" "v") (match_operand:QI 3 "const_mask_operand" "C")] UNSPEC_VEC_VFMAX))] "TARGET_VXE" -- 2.17.1