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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id r64sm4216973pjb.15.2020.04.02.11.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Apr 2020 11:54:02 -0700 (PDT) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: richard.sandiford@arm.com, segher@kernel.crashing.org, richard.earnshaw@arm.com, Wilco.Dijkstra@arm.com, marcus.shawcroft@arm.com, kyrylo.tkachov@arm.com Subject: [PATCH v2 06/11] aarch64: Use UNSPEC_ADCS for add-with-carry + output flags Date: Thu, 2 Apr 2020 11:53:48 -0700 Message-Id: <20200402185353.11047-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200402185353.11047-1-richard.henderson@linaro.org> References: <20200402185353.11047-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-22.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 02 Apr 2020 18:54:06 -0000 Similar to UNSPEC_SBCS, we can unify the signed/unsigned overflow paths by using an unspec. Accept -1 for the second input by using SBCS. * config/aarch64/aarch64.md (UNSPEC_ADCS): New. (addvti4, uaddvti4): Use adddi_carryin_cmp. (add3_carryinC): Remove. (*add3_carryinC_zero): Remove. (*add3_carryinC): Remove. (add3_carryinV): Remove. (*add3_carryinV_zero): Remove. (*add3_carryinV): Remove. (add3_carryin_cmp): New expander. (*add3_carryin_cmp): New pattern. (*add3_carryin_cmp_0): New pattern. (*cmn3_carryin): New pattern. (*cmn3_carryin_0): New pattern. --- gcc/config/aarch64/aarch64.md | 206 +++++++++++++++------------------- 1 file changed, 89 insertions(+), 117 deletions(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 564dea390be..99023494fa1 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -281,6 +281,7 @@ UNSPEC_GEN_TAG_RND ; Generate a random 4-bit MTE tag. UNSPEC_TAG_SPACE ; Translate address to MTE tag address space. UNSPEC_LD1RO + UNSPEC_ADCS UNSPEC_SBCS ]) @@ -2062,7 +2063,7 @@ aarch64_expand_addsubti (operands[0], operands[1], operands[2], CODE_FOR_adddi3_compareV, CODE_FOR_adddi3_compareC, - CODE_FOR_adddi3_carryinV); + CODE_FOR_adddi3_carryin_cmp); aarch64_gen_unlikely_cbranch (NE, CC_Vmode, operands[3]); DONE; }) @@ -2077,7 +2078,7 @@ aarch64_expand_addsubti (operands[0], operands[1], operands[2], CODE_FOR_adddi3_compareC, CODE_FOR_adddi3_compareC, - CODE_FOR_adddi3_carryinC); + CODE_FOR_adddi3_carryin_cmp); aarch64_gen_unlikely_cbranch (GEU, CC_ADCmode, operands[3]); DONE; }) @@ -2579,133 +2580,104 @@ [(set_attr "type" "adc_reg")] ) -(define_expand "add3_carryinC" +(define_expand "add3_carryin_cmp" [(parallel - [(set (match_dup 3) - (compare:CC_ADC - (plus: - (plus: - (match_dup 4) - (zero_extend: - (match_operand:GPI 1 "register_operand"))) - (zero_extend: - (match_operand:GPI 2 "register_operand"))) - (match_dup 6))) - (set (match_operand:GPI 0 "register_operand") - (plus:GPI - (plus:GPI (match_dup 5) (match_dup 1)) - (match_dup 2)))])] + [(set (match_dup 3) + (unspec:CC + [(match_operand:GPI 1 "aarch64_reg_or_zero") + (match_operand:GPI 2 "aarch64_reg_zero_minus1") + (match_dup 4)] + UNSPEC_ADCS)) + (set (match_operand:GPI 0 "register_operand") + (unspec:GPI + [(match_dup 1) (match_dup 2) (match_dup 4)] + UNSPEC_ADCS))])] "" -{ - operands[3] = gen_rtx_REG (CC_ADCmode, CC_REGNUM); - rtx ccin = gen_rtx_REG (CC_Cmode, CC_REGNUM); - operands[4] = gen_rtx_LTU (mode, ccin, const0_rtx); - operands[5] = gen_rtx_LTU (mode, ccin, const0_rtx); - operands[6] = immed_wide_int_const (wi::shwi (1, mode) - << GET_MODE_BITSIZE (mode), - TImode); -}) + { + operands[3] = gen_rtx_REG (CCmode, CC_REGNUM); + operands[4] = gen_rtx_GEU (mode, operands[3], const0_rtx); + } +) -(define_insn "*add3_carryinC_zero" - [(set (reg:CC_ADC CC_REGNUM) - (compare:CC_ADC - (plus: - (match_operand: 2 "aarch64_carry_operation" "") - (zero_extend: (match_operand:GPI 1 "register_operand" "r"))) - (match_operand 4 "const_scalar_int_operand" ""))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (match_operand:GPI 3 "aarch64_carry_operation" "") - (match_dup 1)))] - "rtx_mode_t (operands[4], mode) - == (wi::shwi (1, mode) << (unsigned) GET_MODE_BITSIZE (mode))" - "adcs\\t%0, %1, zr" +(define_insn "*add3_carryin_cmp" + [(set (reg:CC CC_REGNUM) + (unspec:CC + [(match_operand:GPI 1 "aarch64_reg_or_zero" "%rZ,rZ") + (match_operand:GPI 2 "aarch64_reg_zero_minus1" "rZ,UsM") + (match_operand:GPI 3 "aarch64_carry_operation" "")] + UNSPEC_ADCS)) + (set (match_operand:GPI 0 "register_operand" "=r,r") + (unspec:GPI + [(match_dup 1) (match_dup 2) (match_dup 3)] + UNSPEC_ADCS))] + "" + "@ + adcs\\t%0, %1, %2 + sbcs\\t%0, %1, zr" [(set_attr "type" "adc_reg")] ) -(define_insn "*add3_carryinC" - [(set (reg:CC_ADC CC_REGNUM) - (compare:CC_ADC - (plus: - (plus: - (match_operand: 3 "aarch64_carry_operation" "") - (zero_extend: (match_operand:GPI 1 "register_operand" "r"))) - (zero_extend: (match_operand:GPI 2 "register_operand" "r"))) - (match_operand 5 "const_scalar_int_operand" ""))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI - (plus:GPI (match_operand:GPI 4 "aarch64_carry_operation" "") - (match_dup 1)) - (match_dup 2)))] - "rtx_mode_t (operands[5], mode) - == (wi::shwi (1, mode) << (unsigned) GET_MODE_BITSIZE (mode))" - "adcs\\t%0, %1, %2" +(define_insn "*cmn3_carryin" + [(set (reg:CC CC_REGNUM) + (unspec:CC + [(match_operand:GPI 0 "aarch64_reg_or_zero" "%rZ,rZ") + (match_operand:GPI 1 "aarch64_reg_zero_minus1" "rZ,UsM") + (match_operand:GPI 2 "aarch64_carry_operation" "")] + UNSPEC_ADCS))] + "" + "@ + adcs\\tzr, %0, %1 + sbcs\\tzr, %0, zr" [(set_attr "type" "adc_reg")] ) -(define_expand "add3_carryinV" - [(parallel - [(set (reg:CC_V CC_REGNUM) - (compare:CC_V - (plus: - (plus: - (match_dup 3) - (sign_extend: - (match_operand:GPI 1 "register_operand"))) - (sign_extend: - (match_operand:GPI 2 "register_operand"))) - (sign_extend: - (plus:GPI - (plus:GPI (match_dup 4) (match_dup 1)) - (match_dup 2))))) - (set (match_operand:GPI 0 "register_operand") - (plus:GPI - (plus:GPI (match_dup 4) (match_dup 1)) - (match_dup 2)))])] - "" -{ - rtx cc = gen_rtx_REG (CC_Cmode, CC_REGNUM); - operands[3] = gen_rtx_LTU (mode, cc, const0_rtx); - operands[4] = gen_rtx_LTU (mode, cc, const0_rtx); -}) - -(define_insn "*add3_carryinV_zero" - [(set (reg:CC_V CC_REGNUM) - (compare:CC_V - (plus: - (match_operand: 2 "aarch64_carry_operation" "") - (sign_extend: (match_operand:GPI 1 "register_operand" "r"))) - (sign_extend: - (plus:GPI - (match_operand:GPI 3 "aarch64_carry_operation" "") - (match_dup 1))))) +;; If combine can show that the borrow is 0, fold ADCS to ADDS. +(define_insn_and_split "*add3_carryin_cmp_0" + [(set (reg:CC CC_REGNUM) + (unspec:CC + [(match_operand:GPI 1 "aarch64_reg_or_zero" "%rk") + (match_operand:GPI 2 "aarch64_plus_immediate" "rIJ") + (const_int 0)] + UNSPEC_ADCS)) (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI (match_dup 3) (match_dup 1)))] - "" - "adcs\\t%0, %1, zr" - [(set_attr "type" "adc_reg")] + (unspec:GPI + [(match_dup 1) (match_dup 2) (const_int 0)] + UNSPEC_ADCS))] + "" + "#" + "" + [(scratch)] + { + if (CONST_INT_P (operands[1])) + { + /* If operand2 is also constant, this must be before reload. + Expanding this to an explicit plus of two constants would + result in invalid rtl. */ + if (CONST_INT_P (operands[2])) + FAIL; + std::swap (operands[1], operands[2]); + } + emit_insn (gen_add3_compare0 (operands[0], operands[1], + operands[2])); + DONE; + } ) -(define_insn "*add3_carryinV" - [(set (reg:CC_V CC_REGNUM) - (compare:CC_V - (plus: - (plus: - (match_operand: 3 "aarch64_carry_operation" "") - (sign_extend: (match_operand:GPI 1 "register_operand" "r"))) - (sign_extend: (match_operand:GPI 2 "register_operand" "r"))) - (sign_extend: - (plus:GPI - (plus:GPI - (match_operand:GPI 4 "aarch64_carry_operation" "") - (match_dup 1)) - (match_dup 2))))) - (set (match_operand:GPI 0 "register_operand" "=r") - (plus:GPI - (plus:GPI (match_dup 4) (match_dup 1)) - (match_dup 2)))] - "" - "adcs\\t%0, %1, %2" - [(set_attr "type" "adc_reg")] +;; ??? There's no one add*compare*cconly pattern that covers both C and V +;; into which this can be split. Leave it whole for now. +(define_insn "*cmn3_carryin_0" + [(set (reg:CC CC_REGNUM) + (unspec:CC + [(match_operand:GPI 0 "aarch64_reg_or_zero" "%rk,rk,rZ") + (match_operand:GPI 1 "aarch64_plus_operand" "I,J,rZ") + (const_int 0)] + UNSPEC_ADCS))] + "" + "@ + cmn\\t%0, %1 + cmp\\t%0, #%n1 + cmn\\t%0, %1" + [(set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) (define_insn "*add_uxt_shift2" -- 2.20.1