Re: [PATCH] rs6000: Don't split constant oprator when add, move to temp register for future optimization

[Segher Boessenkool <segher@kernel.crashing.org>]

Hi!

On Mon, Mar 30, 2020 at 11:59:57AM +0800, luoxhu wrote:
> > Do we want something later in the RTL pipeline to make "addi"s etc. again?

(This would be a good thing to consider -- maybe a define_insn_and_split
will work.  But see below).

> [PATCH] rs6000: Don't split constant operator add before reload, move to temp register for future optimization
> 
> Don't split code from add<mode>3 for SDI to allow a later pass to split.
> This allows later logic to hoist out constant load in add instructions.
> In loop, lis+ori could be hoisted out to improve performance compared with
> previous addis+addi (About 15% on typical case), weak point is
> one more register is used and one more instruction is generated.  i.e.:
> 
> addis 3,3,0x8765
> addi 3,3,0x4321
> 
> =>
> 
> lis 9,0x8765
> ori 9,9,0x4321
> add 3,3,9

(This patch will of course have to wait for stage 1).

Such a define_insn_and_split could be for an add of a (signed) 32-bit
immediate.  combine will try to combine the three insns (lis;ori;add),
and match the new pattern.

This also links in with Alan's work on big immediates, and with paddi
insns, etc.


Segher